Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm

   1 What:           /sys/bus/coresight/devices/<tpdm-name>/integration_test
   2 Date:           January 2023
   3 KernelVersion   6.2
   4 Contact:        Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
   5 Description:
   6                 (Write) Run integration test for tpdm. Integration test
   7                 will generate test data for tpdm. It can help to make
   8                 sure that the trace path is enabled and the link configurations
   9                 are fine.
  10
  11                 Accepts only one of the 2 values -  1 or 2.
  12                 1 : Generate 64 bits data
  13                 2 : Generate 32 bits data
  14
  15 What:           /sys/bus/coresight/devices/<tpdm-name>/reset_dataset
  16 Date:           March 2023
  17 KernelVersion   6.7
  18 Contact:        Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
  19 Description:
  20                 (Write) Reset the dataset of the tpdm.
  21
  22                 Accepts only one value -  1.
  23                 1 : Reset the dataset of the tpdm
  24
  25 What:           /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_type
  26 Date:           March 2023
  27 KernelVersion   6.7
  28 Contact:        Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
  29 Description:
  30                 (RW) Set/Get the trigger type of the DSB for tpdm.
  31
  32                 Accepts only one of the 2 values -  0 or 1.
  33                 0 : Set the DSB trigger type to false
  34                 1 : Set the DSB trigger type to true
  35
  36 What:           /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_ts
  37 Date:           March 2023
  38 KernelVersion   6.7
  39 Contact:        Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
  40 Description:
  41                 (RW) Set/Get the trigger timestamp of the DSB for tpdm.
  42
  43                 Accepts only one of the 2 values -  0 or 1.
  44                 0 : Set the DSB trigger type to false
  45                 1 : Set the DSB trigger type to true
  46
  47 What:           /sys/bus/coresight/devices/<tpdm-name>/dsb_mode
  48 Date:           March 2023
  49 KernelVersion   6.7
  50 Contact:        Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
  51 Description:
  52                 (RW) Set/Get the programming mode of the DSB for tpdm.
  53
  54                 Accepts the value needs to be greater than 0. What data
  55                 bits do is listed below.
  56                 Bit[0:1] : Test mode control bit for choosing the inputs.
  57                 Bit[3] : Set to 0 for low performance mode. Set to 1 for high
  58                 performance mode.
  59                 Bit[4:8] : Select byte lane for high performance mode.
  60
  61 What:           /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_idx
  62 Date:           March 2023
  63 KernelVersion   6.7
  64 Contact:        Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
  65 Description:
  66                 (RW) Set/Get the index number of the edge detection for the DSB
  67                 subunit TPDM. Since there are at most 256 edge detections, this
  68                 value ranges from 0 to 255.
  69
  70 What:           /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_val
  71 Date:           March 2023
  72 KernelVersion   6.7
  73 Contact:        Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
  74 Description:
  75                 Write a data to control the edge detection corresponding to
  76                 the index number. Before writing data to this sysfs file,
  77                 "ctrl_idx" should be written first to configure the index
  78                 number of the edge detection which needs to be controlled.
  79
  80                 Accepts only one of the following values.
  81                 0 - Rising edge detection
  82                 1 - Falling edge detection
  83                 2 - Rising and falling edge detection (toggle detection)
  84
  85
  86 What:           /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_mask
  87 Date:           March 2023
  88 KernelVersion   6.7
  89 Contact:        Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
  90 Description:
  91                 Write a data to mask the edge detection corresponding to the index
  92                 number. Before writing data to this sysfs file, "ctrl_idx" should
  93                 be written first to configure the index number of the edge detection
  94                 which needs to be masked.
  95
  96                 Accepts only one of the 2 values -  0 or 1.
  97
  98 What:           /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcr[0:15]
  99 Date:           March 2023
 100 KernelVersion   6.7
 101 Contact:        Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
 102 Description:
 103                 Read a set of the edge control value of the DSB in TPDM.
 104
 105 What:           /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcmr[0:7]
 106 Date:           March 2023
 107 KernelVersion   6.7
 108 Contact:        Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
 109 Description:
 110                 Read a set of the edge control mask of the DSB in TPDM.
 111
 112 What:           /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpr[0:7]
 113 Date:           March 2023
 114 KernelVersion   6.7
 115 Contact:        Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
 116 Description:
 117                 (RW) Set/Get the value of the trigger pattern for the DSB
 118                 subunit TPDM.
 119
 120 What:           /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpmr[0:7]
 121 Date:           March 2023
 122 KernelVersion   6.7
 123 Contact:        Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
 124 Description:
 125                 (RW) Set/Get the mask of the trigger pattern for the DSB
 126                 subunit TPDM.
 127
 128 What:           /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:7]
 129 Date:           March 2023
 130 KernelVersion   6.7
 131 Contact:        Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
 132 Description:
 133                 (RW) Set/Get the value of the pattern for the DSB subunit TPDM.
 134
 135 What:           /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:7]
 136 Date:           March 2023
 137 KernelVersion   6.7
 138 Contact:        Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
 139 Description:
 140                 (RW) Set/Get the mask of the pattern for the DSB subunit TPDM.
 141
 142 What:           /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/enable_ts
 143 Date:           March 2023
 144 KernelVersion   6.7
 145 Contact:        Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
 146 Description:
 147                 (Write) Set the pattern timestamp of DSB tpdm. Read
 148                 the pattern timestamp of DSB tpdm.
 149
 150                 Accepts only one of the 2 values -  0 or 1.
 151                 0 : Disable DSB pattern timestamp.
 152                 1 : Enable DSB pattern timestamp.
 153
 154 What:           /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/set_type
 155 Date:           March 2023
 156 KernelVersion   6.7
 157 Contact:        Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
 158 Description:
 159                 (Write) Set the pattern type of DSB tpdm. Read
 160                 the pattern type of DSB tpdm.
 161
 162                 Accepts only one of the 2 values -  0 or 1.
 163                 0 : Set the DSB pattern type to value.
 164                 1 : Set the DSB pattern type to toggle.
 165
 166 What:           /sys/bus/coresight/devices/<tpdm-name>/dsb_msr/msr[0:31]
 167 Date:           March 2023
 168 KernelVersion   6.7
 169 Contact:        Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
 170 Description:
 171                 (RW) Set/Get the MSR(mux select register) for the DSB subunit
 172                 TPDM.