cifs: fix creating sockets when using sfu mount options
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / nvidia / tegra20-paz00.dts
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
6
7 #include "tegra20.dtsi"
8 #include "tegra20-cpu-opp.dtsi"
9 #include "tegra20-cpu-opp-microvolt.dtsi"
10
11 / {
12         model = "Toshiba AC100 / Dynabook AZ";
13         compatible = "compal,paz00", "nvidia,tegra20";
14
15         aliases {
16                 mmc0 = &sdmmc4; /* eMMC */
17                 mmc1 = &sdmmc1; /* MicroSD */
18                 rtc0 = "/i2c@7000d000/tps6586x@34";
19                 rtc1 = "/rtc@7000e000";
20                 serial0 = &uarta;
21                 serial1 = &uartc;
22         };
23
24         chosen {
25                 stdout-path = "serial0:115200n8";
26         };
27
28         memory@0 {
29                 reg = <0x00000000 0x20000000>;
30         };
31
32         host1x@50000000 {
33                 dc@54200000 {
34                         rgb {
35                                 status = "okay";
36
37                                 nvidia,panel = <&panel>;
38                         };
39                 };
40
41                 hdmi@54280000 {
42                         status = "okay";
43
44                         vdd-supply = <&hdmi_vdd_reg>;
45                         pll-supply = <&hdmi_pll_reg>;
46
47                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
48                         nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
49                                 GPIO_ACTIVE_HIGH>;
50                 };
51         };
52
53         pinmux@70000014 {
54                 pinctrl-names = "default";
55                 pinctrl-0 = <&state_default>;
56
57                 state_default: pinmux {
58                         ata {
59                                 nvidia,pins = "ata", "atc", "atd", "ate",
60                                         "dap2", "gmb", "gmc", "gmd", "spia",
61                                         "spib", "spic", "spid", "spie";
62                                 nvidia,function = "gmi";
63                         };
64                         atb {
65                                 nvidia,pins = "atb", "gma", "gme";
66                                 nvidia,function = "sdio4";
67                         };
68                         cdev1 {
69                                 nvidia,pins = "cdev1";
70                                 nvidia,function = "plla_out";
71                         };
72                         cdev2 {
73                                 nvidia,pins = "cdev2";
74                                 nvidia,function = "pllp_out4";
75                         };
76                         crtp {
77                                 nvidia,pins = "crtp";
78                                 nvidia,function = "crt";
79                         };
80                         csus {
81                                 nvidia,pins = "csus";
82                                 nvidia,function = "pllc_out1";
83                         };
84                         dap1 {
85                                 nvidia,pins = "dap1";
86                                 nvidia,function = "dap1";
87                         };
88                         dap3 {
89                                 nvidia,pins = "dap3";
90                                 nvidia,function = "dap3";
91                         };
92                         dap4 {
93                                 nvidia,pins = "dap4";
94                                 nvidia,function = "dap4";
95                         };
96                         ddc {
97                                 nvidia,pins = "ddc";
98                                 nvidia,function = "i2c2";
99                         };
100                         dta {
101                                 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
102                                 nvidia,function = "rsvd1";
103                         };
104                         dtf {
105                                 nvidia,pins = "dtf";
106                                 nvidia,function = "i2c3";
107                         };
108                         gpu {
109                                 nvidia,pins = "gpu", "sdb", "sdd";
110                                 nvidia,function = "pwm";
111                         };
112                         gpu7 {
113                                 nvidia,pins = "gpu7";
114                                 nvidia,function = "rtck";
115                         };
116                         gpv {
117                                 nvidia,pins = "gpv", "slxa", "slxk";
118                                 nvidia,function = "pcie";
119                         };
120                         hdint {
121                                 nvidia,pins = "hdint", "pta";
122                                 nvidia,function = "hdmi";
123                         };
124                         i2cp {
125                                 nvidia,pins = "i2cp";
126                                 nvidia,function = "i2cp";
127                         };
128                         irrx {
129                                 nvidia,pins = "irrx", "irtx";
130                                 nvidia,function = "uarta";
131                         };
132                         kbca {
133                                 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
134                                 nvidia,function = "kbc";
135                         };
136                         kbcb {
137                                 nvidia,pins = "kbcb", "kbcd";
138                                 nvidia,function = "sdio2";
139                         };
140                         lcsn {
141                                 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
142                                         "ld3", "ld4", "ld5", "ld6", "ld7",
143                                         "ld8", "ld9", "ld10", "ld11", "ld12",
144                                         "ld13", "ld14", "ld15", "ld16", "ld17",
145                                         "ldc", "ldi", "lhp0", "lhp1", "lhp2",
146                                         "lhs", "lm0", "lm1", "lpp", "lpw0",
147                                         "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
148                                         "lsda", "lsdi", "lspi", "lvp0", "lvp1",
149                                         "lvs";
150                                 nvidia,function = "displaya";
151                         };
152                         owc {
153                                 nvidia,pins = "owc";
154                                 nvidia,function = "owr";
155                         };
156                         pmc {
157                                 nvidia,pins = "pmc";
158                                 nvidia,function = "pwr_on";
159                         };
160                         rm {
161                                 nvidia,pins = "rm";
162                                 nvidia,function = "i2c1";
163                         };
164                         sdc {
165                                 nvidia,pins = "sdc";
166                                 nvidia,function = "twc";
167                         };
168                         sdio1 {
169                                 nvidia,pins = "sdio1";
170                                 nvidia,function = "sdio1";
171                         };
172                         slxc {
173                                 nvidia,pins = "slxc", "slxd";
174                                 nvidia,function = "spi4";
175                         };
176                         spdi {
177                                 nvidia,pins = "spdi", "spdo";
178                                 nvidia,function = "rsvd2";
179                         };
180                         spif {
181                                 nvidia,pins = "spif", "uac";
182                                 nvidia,function = "rsvd4";
183                         };
184                         spig {
185                                 nvidia,pins = "spig", "spih";
186                                 nvidia,function = "spi2_alt";
187                         };
188                         uaa {
189                                 nvidia,pins = "uaa", "uab", "uda";
190                                 nvidia,function = "ulpi";
191                         };
192                         uad {
193                                 nvidia,pins = "uad";
194                                 nvidia,function = "spdif";
195                         };
196                         uca {
197                                 nvidia,pins = "uca", "ucb";
198                                 nvidia,function = "uartc";
199                         };
200                         conf_ata {
201                                 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
202                                         "cdev1", "cdev2", "dap1", "dap2", "dtf",
203                                         "gma", "gmb", "gmc", "gmd", "gme",
204                                         "gpu", "gpu7", "gpv", "i2cp", "pta",
205                                         "rm", "sdio1", "slxk", "spdo", "uac",
206                                         "uda";
207                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
208                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
209                         };
210                         conf_ck32 {
211                                 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
212                                         "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
213                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
214                         };
215                         conf_crtp {
216                                 nvidia,pins = "crtp", "dap3", "dap4", "dtb",
217                                         "dtc", "dte", "slxa", "slxc", "slxd",
218                                         "spdi";
219                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
220                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
221                         };
222                         conf_csus {
223                                 nvidia,pins = "csus", "spia", "spib", "spid",
224                                         "spif";
225                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
226                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
227                         };
228                         conf_ddc {
229                                 nvidia,pins = "ddc", "irrx", "irtx", "kbca",
230                                         "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
231                                         "spic", "spig", "uaa", "uab";
232                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
233                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
234                         };
235                         conf_dta {
236                                 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
237                                         "spie", "spih", "uad", "uca", "ucb";
238                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
239                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
240                         };
241                         conf_hdint {
242                                 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
243                                         "ld3", "ld4", "ld5", "ld6", "ld7",
244                                         "ld8", "ld9", "ld10", "ld11", "ld12",
245                                         "ld13", "ld14", "ld15", "ld16", "ld17",
246                                         "ldc", "ldi", "lhs", "lsc0", "lspi",
247                                         "lvs", "pmc";
248                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
249                         };
250                         conf_lc {
251                                 nvidia,pins = "lc", "ls";
252                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
253                         };
254                         conf_lcsn {
255                                 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
256                                         "lm0", "lm1", "lpp", "lpw0", "lpw1",
257                                         "lpw2", "lsc1", "lsck", "lsda", "lsdi",
258                                         "lvp0", "lvp1", "sdb";
259                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
260                         };
261                         conf_ld17_0 {
262                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
263                                         "ld23_22";
264                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
265                         };
266                 };
267         };
268
269         spdif@70002400 {
270                 status = "okay";
271
272                 nvidia,fixed-parent-rate;
273         };
274
275         i2s@70002800 {
276                 status = "okay";
277
278                 nvidia,fixed-parent-rate;
279         };
280
281         serial@70006000 {
282                 /delete-property/ dmas;
283                 /delete-property/ dma-names;
284                 status = "okay";
285         };
286
287         serial@70006200 {
288                 /delete-property/ dmas;
289                 /delete-property/ dma-names;
290                 status = "okay";
291         };
292
293         pwm: pwm@7000a000 {
294                 status = "okay";
295         };
296
297         lvds_ddc: i2c@7000c000 {
298                 status = "okay";
299                 clock-frequency = <400000>;
300
301                 alc5632: alc5632@1e {
302                         compatible = "realtek,alc5632";
303                         reg = <0x1e>;
304                         gpio-controller;
305                         #gpio-cells = <2>;
306                 };
307         };
308
309         hdmi_ddc: i2c@7000c400 {
310                 status = "okay";
311                 clock-frequency = <100000>;
312         };
313
314         i2c@7000c500 {
315                 compatible = "nvidia,nvec";
316
317                 /delete-property/ #address-cells;
318                 /delete-property/ #size-cells;
319                 /delete-property/ dmas;
320                 /delete-property/ dma-names;
321
322                 clock-frequency = <80000>;
323                 request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
324                 slave-addr = <138>;
325
326                 status = "okay";
327         };
328
329         i2c@7000d000 {
330                 status = "okay";
331                 clock-frequency = <400000>;
332
333                 pmic: tps6586x@34 {
334                         compatible = "ti,tps6586x";
335                         reg = <0x34>;
336                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
337
338                         #gpio-cells = <2>;
339                         gpio-controller;
340
341                         sys-supply = <&p5valw_reg>;
342                         vin-sm0-supply = <&sys_reg>;
343                         vin-sm1-supply = <&sys_reg>;
344                         vin-sm2-supply = <&sys_reg>;
345                         vinldo01-supply = <&sm2_reg>;
346                         vinldo23-supply = <&sm2_reg>;
347                         vinldo4-supply = <&sm2_reg>;
348                         vinldo678-supply = <&sm2_reg>;
349                         vinldo9-supply = <&sm2_reg>;
350
351                         regulators {
352                                 sys_reg: sys {
353                                         regulator-name = "vdd_sys";
354                                         regulator-always-on;
355                                 };
356
357                                 core_vdd_reg: sm0 {
358                                         regulator-name = "+1.2vs_sm0,vdd_core";
359                                         regulator-min-microvolt = <950000>;
360                                         regulator-max-microvolt = <1300000>;
361                                         regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>;
362                                         regulator-coupled-max-spread = <170000 550000>;
363                                         regulator-always-on;
364
365                                         nvidia,tegra-core-regulator;
366                                 };
367
368                                 cpu_vdd_reg: sm1 {
369                                         regulator-name = "+1.0vs_sm1,vdd_cpu";
370                                         regulator-min-microvolt = <750000>;
371                                         regulator-max-microvolt = <1100000>;
372                                         regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>;
373                                         regulator-coupled-max-spread = <550000 550000>;
374                                         regulator-always-on;
375
376                                         nvidia,tegra-cpu-regulator;
377                                 };
378
379                                 sm2_reg: sm2 {
380                                         regulator-name = "+3.7vs_sm2,vin_ldo*";
381                                         regulator-min-microvolt = <3700000>;
382                                         regulator-max-microvolt = <3700000>;
383                                         regulator-always-on;
384                                 };
385
386                                 /* LDO0 is not connected to anything */
387
388                                 ldo1 {
389                                         regulator-name = "+1.1vs_ldo1,avdd_pll*";
390                                         regulator-min-microvolt = <1100000>;
391                                         regulator-max-microvolt = <1100000>;
392                                         regulator-always-on;
393                                 };
394
395                                 rtc_vdd_reg: ldo2 {
396                                         regulator-name = "+1.2vs_ldo2,vdd_rtc";
397                                         regulator-min-microvolt = <950000>;
398                                         regulator-max-microvolt = <1300000>;
399                                         regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>;
400                                         regulator-coupled-max-spread = <170000 550000>;
401                                         regulator-always-on;
402
403                                         nvidia,tegra-rtc-regulator;
404                                 };
405
406                                 ldo3 {
407                                         regulator-name = "+3.3vs_ldo3,avdd_usb*";
408                                         regulator-min-microvolt = <3300000>;
409                                         regulator-max-microvolt = <3300000>;
410                                         regulator-always-on;
411                                 };
412
413                                 ldo4 {
414                                         regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
415                                         regulator-min-microvolt = <1800000>;
416                                         regulator-max-microvolt = <1800000>;
417                                         regulator-always-on;
418                                 };
419
420                                 ldo5 {
421                                         regulator-name = "+2.85vs_ldo5,vcore_mmc";
422                                         regulator-min-microvolt = <2850000>;
423                                         regulator-max-microvolt = <2850000>;
424                                         regulator-always-on;
425                                 };
426
427                                 ldo6 {
428                                         /*
429                                          * Research indicates this should be
430                                          * 1.8v; other boards that use this
431                                          * rail for the same purpose need it
432                                          * set to 1.8v. The schematic signal
433                                          * name is incorrect; perhaps copied
434                                          * from an incorrect NVIDIA reference.
435                                          */
436                                         regulator-name = "+2.85vs_ldo6,avdd_vdac";
437                                         regulator-min-microvolt = <1800000>;
438                                         regulator-max-microvolt = <1800000>;
439                                 };
440
441                                 hdmi_vdd_reg: ldo7 {
442                                         regulator-name = "+3.3vs_ldo7,avdd_hdmi";
443                                         regulator-min-microvolt = <3300000>;
444                                         regulator-max-microvolt = <3300000>;
445                                 };
446
447                                 hdmi_pll_reg: ldo8 {
448                                         regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
449                                         regulator-min-microvolt = <1800000>;
450                                         regulator-max-microvolt = <1800000>;
451                                 };
452
453                                 ldo9 {
454                                         regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
455                                         regulator-min-microvolt = <2850000>;
456                                         regulator-max-microvolt = <2850000>;
457                                         regulator-always-on;
458                                 };
459
460                                 ldo_rtc {
461                                         regulator-name = "+3.3vs_rtc";
462                                         regulator-min-microvolt = <3300000>;
463                                         regulator-max-microvolt = <3300000>;
464                                         regulator-always-on;
465                                 };
466                         };
467                 };
468
469                 adt7461: temperature-sensor@4c {
470                         compatible = "adi,adt7461";
471                         reg = <0x4c>;
472
473                         interrupt-parent = <&gpio>;
474                         interrupts = <TEGRA_GPIO(N, 6) IRQ_TYPE_EDGE_FALLING>;
475
476                         #thermal-sensor-cells = <1>;
477                 };
478         };
479
480         pmc@7000e400 {
481                 nvidia,invert-interrupt;
482                 nvidia,suspend-mode = <1>;
483                 nvidia,cpu-pwr-good-time = <2000>;
484                 nvidia,cpu-pwr-off-time = <0>;
485                 nvidia,core-pwr-good-time = <3845 3845>;
486                 nvidia,core-pwr-off-time = <0>;
487                 nvidia,sys-clock-req-active-high;
488                 core-supply = <&core_vdd_reg>;
489         };
490
491         memory-controller@7000f400 {
492                 nvidia,use-ram-code;
493
494                 emc-tables@0 {
495                         nvidia,ram-code = <0x0>;
496                         #address-cells = <1>;
497                         #size-cells = <0>;
498                         reg = <0>;
499
500                         emc-table@166500 {
501                                 reg = <166500>;
502                                 compatible = "nvidia,tegra20-emc-table";
503                                 clock-frequency = <166500>;
504                                 nvidia,emc-registers = <0x0000000a 0x00000016
505                                         0x00000008 0x00000003 0x00000004 0x00000004
506                                         0x00000002 0x0000000c 0x00000003 0x00000003
507                                         0x00000002 0x00000001 0x00000004 0x00000005
508                                         0x00000004 0x00000009 0x0000000d 0x000004df
509                                         0x00000000 0x00000003 0x00000003 0x00000003
510                                         0x00000003 0x00000001 0x0000000a 0x000000c8
511                                         0x00000003 0x00000006 0x00000004 0x00000008
512                                         0x00000002 0x00000000 0x00000000 0x00000002
513                                         0x00000000 0x00000000 0x00000083 0xe03b0323
514                                         0x007fe010 0x00001414 0x00000000 0x00000000
515                                         0x00000000 0x00000000 0x00000000 0x00000000>;
516                         };
517
518                         emc-table@333000 {
519                                 reg = <333000>;
520                                 compatible = "nvidia,tegra20-emc-table";
521                                 clock-frequency = <333000>;
522                                 nvidia,emc-registers = <0x00000018 0x00000033
523                                         0x00000012 0x00000004 0x00000004 0x00000005
524                                         0x00000003 0x0000000c 0x00000006 0x00000006
525                                         0x00000003 0x00000001 0x00000004 0x00000005
526                                         0x00000004 0x00000009 0x0000000d 0x00000bff
527                                         0x00000000 0x00000003 0x00000003 0x00000006
528                                         0x00000006 0x00000001 0x00000011 0x000000c8
529                                         0x00000003 0x0000000e 0x00000007 0x00000008
530                                         0x00000002 0x00000000 0x00000000 0x00000002
531                                         0x00000000 0x00000000 0x00000083 0xf0440303
532                                         0x007fe010 0x00001414 0x00000000 0x00000000
533                                         0x00000000 0x00000000 0x00000000 0x00000000>;
534                         };
535                 };
536
537                 emc-tables@1 {
538                         nvidia,ram-code = <0x1>;
539                         #address-cells = <1>;
540                         #size-cells = <0>;
541                         reg = <1>;
542
543                         emc-table@166500 {
544                                 reg = <166500>;
545                                 compatible = "nvidia,tegra20-emc-table";
546                                 clock-frequency = <166500>;
547                                 nvidia,emc-registers = <0x0000000a 0x00000016
548                                         0x00000008 0x00000003 0x00000004 0x00000004
549                                         0x00000002 0x0000000c 0x00000003 0x00000003
550                                         0x00000002 0x00000001 0x00000004 0x00000005
551                                         0x00000004 0x00000009 0x0000000d 0x000004df
552                                         0x00000000 0x00000003 0x00000003 0x00000003
553                                         0x00000003 0x00000001 0x0000000a 0x000000c8
554                                         0x00000003 0x00000006 0x00000004 0x00000008
555                                         0x00000002 0x00000000 0x00000000 0x00000002
556                                         0x00000000 0x00000000 0x00000083 0xe03b0323
557                                         0x007fe010 0x00001414 0x00000000 0x00000000
558                                         0x00000000 0x00000000 0x00000000 0x00000000>;
559                         };
560
561                         emc-table@333000 {
562                                 reg = <333000>;
563                                 compatible = "nvidia,tegra20-emc-table";
564                                 clock-frequency = <333000>;
565                                 nvidia,emc-registers = <0x00000018 0x00000033
566                                         0x00000012 0x00000004 0x00000004 0x00000005
567                                         0x00000003 0x0000000c 0x00000006 0x00000006
568                                         0x00000003 0x00000001 0x00000004 0x00000005
569                                         0x00000004 0x00000009 0x0000000d 0x00000bff
570                                         0x00000000 0x00000003 0x00000003 0x00000006
571                                         0x00000006 0x00000001 0x00000011 0x000000c8
572                                         0x00000003 0x0000000e 0x00000007 0x00000008
573                                         0x00000002 0x00000000 0x00000000 0x00000002
574                                         0x00000000 0x00000000 0x00000083 0xf0440303
575                                         0x007fe010 0x00001414 0x00000000 0x00000000
576                                         0x00000000 0x00000000 0x00000000 0x00000000>;
577                         };
578                 };
579         };
580
581         usb@c5000000 {
582                 compatible = "nvidia,tegra20-udc";
583                 status = "okay";
584                 dr_mode = "peripheral";
585         };
586
587         usb-phy@c5000000 {
588                 status = "okay";
589         };
590
591         usb@c5004000 {
592                 status = "okay";
593         };
594
595         usb-phy@c5004000 {
596                 status = "okay";
597                 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
598                         GPIO_ACTIVE_LOW>;
599         };
600
601         usb@c5008000 {
602                 status = "okay";
603         };
604
605         usb-phy@c5008000 {
606                 status = "okay";
607         };
608
609         sdmmc1: mmc@c8000000 {
610                 status = "okay";
611                 cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
612                 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
613                 power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
614                 bus-width = <4>;
615         };
616
617         sdmmc4: mmc@c8000600 {
618                 status = "okay";
619                 bus-width = <8>;
620                 non-removable;
621         };
622
623         backlight: backlight {
624                 compatible = "pwm-backlight";
625
626                 enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
627                 pwms = <&pwm 0 5000000>;
628
629                 brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
630                 default-brightness-level = <10>;
631
632                 /* close enough */
633                 power-supply = <&vdd_pnl_reg>;
634         };
635
636         clk32k_in: clock-32k {
637                 compatible = "fixed-clock";
638                 clock-frequency = <32768>;
639                 #clock-cells = <0>;
640         };
641
642         cpus {
643                 cpu0: cpu@0 {
644                         cpu-supply = <&cpu_vdd_reg>;
645                         operating-points-v2 = <&cpu0_opp_table>;
646                         #cooling-cells = <2>;
647                 };
648
649                 cpu1: cpu@1 {
650                         cpu-supply = <&cpu_vdd_reg>;
651                         operating-points-v2 = <&cpu0_opp_table>;
652                         #cooling-cells = <2>;
653                 };
654         };
655
656         gpio-keys {
657                 compatible = "gpio-keys";
658
659                 key-wakeup {
660                         label = "Wakeup";
661                         gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
662                         linux,code = <KEY_WAKEUP>;
663                         wakeup-source;
664                 };
665         };
666
667         gpio-leds {
668                 compatible = "gpio-leds";
669
670                 led-0 {
671                         label = "wifi-led";
672                         gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
673                         linux,default-trigger = "rfkill0";
674                 };
675         };
676
677         opp-table-emc {
678                 /delete-node/ opp-760000000;
679         };
680
681         panel: panel {
682                 compatible = "samsung,ltn101nt05";
683
684                 ddc-i2c-bus = <&lvds_ddc>;
685                 power-supply = <&vdd_pnl_reg>;
686                 enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>;
687
688                 backlight = <&backlight>;
689         };
690
691         p5valw_reg: regulator-5v0alw {
692                 compatible = "regulator-fixed";
693                 regulator-name = "+5valw";
694                 regulator-min-microvolt = <5000000>;
695                 regulator-max-microvolt = <5000000>;
696                 regulator-always-on;
697         };
698
699         vdd_pnl_reg: regulator-3v0 {
700                 compatible = "regulator-fixed";
701                 regulator-name = "+3VS,vdd_pnl";
702                 regulator-min-microvolt = <3300000>;
703                 regulator-max-microvolt = <3300000>;
704                 regulator-boot-on;
705                 gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
706                 enable-active-high;
707         };
708
709         sound {
710                 compatible = "nvidia,tegra-audio-alc5632-paz00",
711                         "nvidia,tegra-audio-alc5632";
712
713                 nvidia,model = "Compal PAZ00";
714
715                 nvidia,audio-routing =
716                         "Int Spk", "SPKOUT",
717                         "Int Spk", "SPKOUTN",
718                         "Headset Mic", "MICBIAS1",
719                         "MIC1", "Headset Mic",
720                         "Headset Stereophone", "HPR",
721                         "Headset Stereophone", "HPL",
722                         "DMICDAT", "Digital Mic";
723
724                 nvidia,audio-codec = <&alc5632>;
725                 nvidia,i2s-controller = <&tegra_i2s1>;
726                 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
727                         GPIO_ACTIVE_HIGH>;
728
729                 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
730                          <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
731                          <&tegra_car TEGRA20_CLK_CDEV1>;
732                 clock-names = "pll_a", "pll_a_out0", "mclk";
733         };
734
735         thermal-zones {
736                 cpu-thermal {
737                         polling-delay-passive = <500>; /* milliseconds */
738                         polling-delay = <1500>; /* milliseconds */
739
740                         thermal-sensors = <&adt7461 1>;
741
742                         trips {
743                                 trip0: cpu-alert0 {
744                                         /* start throttling at 80C */
745                                         temperature = <80000>;
746                                         hysteresis = <200>;
747                                         type = "passive";
748                                 };
749
750                                 trip1: cpu-crit {
751                                         /* shut down at 85C */
752                                         temperature = <85000>;
753                                         hysteresis = <2000>;
754                                         type = "critical";
755                                 };
756                         };
757
758                         cooling-maps {
759                                 map0 {
760                                         trip = <&trip0>;
761                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
762                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
763                                 };
764                         };
765                 };
766         };
767 };