arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 //
   3 // Copyright (C) 2018 emtrion GmbH
   4 //
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/pwm/pwm.h>
   8 #include <dt-bindings/input/input.h>
   9
  10 / {
  11
  12         model = "emtrion SoM emCON-MX6";
  13         compatible = "emtrion,emcon-mx6";
  14
  15         aliases {
  16                 mmc0 = &usdhc3;
  17                 mmc1 = &usdhc2;
  18                 mmc2 = &usdhc1;
  19                 rtc0 = &ds1307;
  20         };
  21
  22         chosen {
  23                 stdout-path = &uart1;
  24         };
  25
  26         memory@10000000 {
  27                 device_type = "memory";
  28                 reg = <0x10000000 0x40000000>;
  29         };
  30
  31         gpio-keys {
  32                 compatible = "gpio-keys";
  33                 pinctrl-names = "default";
  34                 pinctrl-0 = <&pinctrl_emcon_wake>;
  35
  36                 wake {
  37                         label = "Wake";
  38                         linux,code = <KEY_WAKEUP>;
  39                         gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
  40                         wakeup-source;
  41                 };
  42         };
  43
  44         som_leds: leds {
  45                 compatible = "gpio-leds";
  46                 pinctrl-names = "default";
  47                 pinctrl-0 = <&pinctrl_som_leds>;
  48
  49                 led-green {
  50                         label = "som:green";
  51                         gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
  52                         linux,default-trigger = "heartbeat";
  53                         default-state = "on";
  54                 };
  55
  56                 led-red {
  57                         label = "som:red";
  58                         gpios = <&gpio3 1 GPIO_ACTIVE_LOW>;
  59                         default-state = "keep";
  60                 };
  61
  62         };
  63
  64         lvds_backlight: lvds-backlight {
  65                 compatible = "pwm-backlight";
  66                 pinctrl-names = "default";
  67                 pinctrl-0 = <&pinctrl_lvds_bl>;
  68                 enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;
  69                 pwms = <&pwm1 0 50000>;
  70                 brightness-levels = <
  71                         0 4 8 16 32 64 80 96 112
  72                         128 144 160 176 250
  73                 >;
  74                 default-brightness-level = <13>;
  75                 status = "okay";
  76         };
  77
  78         pwm_fan: pwm-fan {
  79                 compatible = "pwm-fan";
  80                 #cooling-cells = <2>;
  81                 pwms = <&pwm4 0 50000>;
  82                 cooling-levels = <0 64 127 191 255>;
  83                 status = "disabled";
  84         };
  85
  86
  87         rgb_encoder: display {
  88                 compatible = "fsl,imx-parallel-display";
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91                 pinctrl-names = "default";
  92                 pinctrl-0 = <&pinctrl_rgb24_display>;
  93                 status = "disabled";
  94
  95                 port@0 {
  96                         reg = <0>;
  97
  98                         rgb_encoder_in: endpoint {
  99                                 remote-endpoint = <&ipu1_di0_disp0>;
 100                         };
 101                 };
 102
 103                 port@1 {
 104                         reg = <1>;
 105
 106                         rgb_encoder_out: endpoint {
 107                                 remote-endpoint = <&rgb_panel_in>;
 108                         };
 109                 };
 110         };
 111
 112         rgb_panel: lcd {
 113                 backlight = <&rgb_backlight>;
 114                 power-supply = <&reg_parallel_disp>;
 115
 116                 port {
 117                         rgb_panel_in: endpoint {
 118                                 remote-endpoint = <&rgb_encoder_out>;
 119                         };
 120                 };
 121         };
 122
 123         reg_parallel_disp: reg-parallel-display {
 124                 compatible = "regulator-fixed";
 125                 pinctrl-names = "default";
 126                 pinctrl-0 = <&pinctrl_rgb_bl_en>;
 127                 regulator-name = "LCD-Supply";
 128                 regulator-min-microvolt = <5000000>;
 129                 regulator-max-microvolt = <5000000>;
 130                 gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>;
 131                 enable-active-high;
 132         };
 133
 134         reg_lvds_disp: reg-lvds-display {
 135                 compatible = "regulator-fixed";
 136                 regulator-name = "LVDS-Supply";
 137                 regulator-min-microvolt = <5000000>;
 138                 regulator-max-microvolt = <5000000>;
 139                 gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>;
 140                 enable-active-high;
 141         };
 142
 143         rgb_backlight: rgb-backlight {
 144                 compatible = "pwm-backlight";
 145                 pinctrl-names = "default";
 146                 pinctrl-0 = <&pinctrl_rgb_bl>;
 147                 enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
 148                 pwms = <&pwm3 0 5000000>;
 149                 brightness-levels = <
 150                         250 176 160 144 128 112
 151                         96 80 64 48 32 16 8 1
 152                 >;
 153                 default-brightness-level = <13>;
 154                 status = "okay";
 155         };
 156 };
 157
 158 &can1 {
 159         pinctrl-names = "default";
 160         pinctrl-0 = <&pinctrl_can1>;
 161 };
 162
 163 &can2 {
 164         pinctrl-names = "default";
 165         pinctrl-0 = <&pinctrl_can2>;
 166 };
 167
 168 &ecspi2 {
 169         pinctrl-names = "default";
 170         pinctrl-0 = <&pinctrl_ecspi2>;
 171         cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>,
 172                 <&gpio2 27 GPIO_ACTIVE_LOW>;
 173 };
 174
 175 &ecspi4 {
 176         pinctrl-names = "default";
 177         pinctrl-0 = <&pinctrl_nor_flash>;
 178 };
 179
 180 &fec {
 181         pinctrl-names = "default";
 182         pinctrl-0 = <&pinctrl_enet>;
 183         phy-mode = "rgmii";
 184         phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
 185         phy-reset-duration = <50>;
 186         phy-supply = <&vdd_1V8_reg>;
 187         phy-handle = <&ksz9031>;
 188         status = "okay";
 189
 190         mdio {
 191                 #address-cells = <1>;
 192                 #size-cells = <0>;
 193
 194                 ksz9031: phy@0 {
 195                         compatible = "ethernet-phy-ieee802.3-c22";
 196                         reg = <0>;
 197                         interrupt-parent = <&gpio1>;
 198                         interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
 199                         rxdv-skew-ps = <480>;
 200                         txen-skew-ps = <480>;
 201                         rxd0-skew-ps = <480>;
 202                         rxd1-skew-ps = <480>;
 203                         rxd2-skew-ps = <480>;
 204                         rxd3-skew-ps = <480>;
 205                         txd0-skew-ps = <420>;
 206                         txd1-skew-ps = <420>;
 207                         txd2-skew-ps = <360>;
 208                         txd3-skew-ps = <360>;
 209                         txc-skew-ps = <1020>;
 210                         rxc-skew-ps = <960>;
 211                 };
 212         };
 213 };
 214
 215 &i2c1 {
 216         clock-frequency = <100000>;
 217         pinctrl-names = "default";
 218         pinctrl-0 = <&pinctrl_i2c1>;
 219         status = "okay";
 220
 221         da9063: pmic@58 {
 222                 compatible = "dlg,da9063";
 223                 reg = <0x58>;
 224                 pinctrl-names = "default";
 225                 pinctrl-0 = <&pinctrl_pmic>;
 226                 interrupt-parent = <&gpio2>;
 227                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 228
 229                 onkey {
 230                         compatible = "dlg,da9063-onkey";
 231                         wakeup-source;
 232                 };
 233
 234                 watchdog {
 235                         compatible = "dlg,da9063-watchdog";
 236                         timeout-sec = <0>;
 237                 };
 238
 239                 regulators {
 240                         vddcore_reg: bcore1 {
 241                                 regulator-min-microvolt = <1100000>;
 242                                 regulator-max-microvolt = <1450000>;
 243                                 regulator-ramp-delay = <2>;
 244                                 regulator-name = "DA9063_CORE";
 245                                 regulator-always-on;
 246                         };
 247
 248                         vddsoc_reg: bcore2 {
 249                                 regulator-min-microvolt = <1100000>;
 250                                 regulator-max-microvolt = <1450000>;
 251                                 regulator-ramp-delay = <2>;
 252                                 regulator-name = "DA9063_SOC";
 253                                 regulator-always-on;
 254                         };
 255
 256                         vdd_ddr3_reg: bpro {
 257                                 regulator-min-microvolt = <1500000>;
 258                                 regulator-max-microvolt = <1500000>;
 259                                 regulator-ramp-delay = <2>;
 260                                 regulator-always-on;
 261                         };
 262
 263                         vdd_3v3_reg: bperi {
 264                                 regulator-min-microvolt = <3300000>;
 265                                 regulator-max-microvolt = <3300000>;
 266                                 regulator-ramp-delay = <2>;
 267                                 regulator-always-on;
 268                         };
 269
 270                         vdd_sata_reg: ldo3 {
 271                                 regulator-min-microvolt = <2500000>;
 272                                 regulator-max-microvolt = <2500000>;
 273                                 regulator-always-on;
 274                         };
 275                         vdd_mipi_reg: ldo4 {
 276                                 regulator-min-microvolt = <2500000>;
 277                                 regulator-max-microvolt = <2500000>;
 278                                 regulator-always-on;
 279                         };
 280
 281                         vdd_mx6_snvs_reg: ldo5 {
 282                                 regulator-min-microvolt = <3300000>;
 283                                 regulator-max-microvolt = <3300000>;
 284                                 regulator-always-on;
 285                         };
 286
 287                         vdd_hdmi_reg: ldo6 {
 288                                 regulator-min-microvolt = <2500000>;
 289                                 regulator-max-microvolt = <2500000>;
 290                                 regulator-always-on;
 291                                 regulator-boot-on;
 292                         };
 293
 294                         vdd_pcie_reg: ldo7 {
 295                                 regulator-min-microvolt = <2500000>;
 296                                 regulator-max-microvolt = <2500000>;
 297                                 regulator-always-on;
 298                         };
 299
 300                         vdd_1V8_reg: ldo8 {
 301                                 regulator-min-microvolt = <1800000>;
 302                                 regulator-max-microvolt = <1800000>;
 303                                 regulator-always-on;
 304                         };
 305
 306                         vdd_3V3_sdc_reg: ldo9 {
 307                                 regulator-min-microvolt = <1800000>;
 308                                 regulator-max-microvolt = <3300000>;
 309                                 regulator-always-on;
 310                         };
 311
 312                         vdd_1V2_reg: ldo10 {
 313                                 regulator-min-microvolt = <1200000>;
 314                                 regulator-max-microvolt = <1200000>;
 315                                 regulator-always-on;
 316                         };
 317                 };
 318         };
 319
 320         ds1307: rtc@68 {
 321                 compatible = "dallas,ds1307";
 322                 reg = <0x68>;
 323         };
 324 };
 325
 326 &i2c2 {
 327         clock-frequency = <100000>;
 328         pinctrl-names = "default";
 329         pinctrl-0 = <&pinctrl_i2c2>;
 330 };
 331
 332 &iomuxc {
 333
 334         pinctrl_audmux: audmuxgrp {
 335                 fsl,pins = <
 336                         MX6QDL_PAD_CSI0_DAT7__AUD3_RXD                  0x130b0
 337                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC                  0x1b060
 338                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD                  0x130B0
 339                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS                 0x1b060
 340                 >;
 341         };
 342
 343         pinctrl_can1: can1grp {
 344                 fsl,pins = <
 345                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX                0x1b0b1
 346                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX                0x1b0b1
 347                 >;
 348         };
 349
 350         pinctrl_can2: can2grp {
 351                 fsl,pins = <
 352                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX                0x1b0b1
 353                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX                0x1b0b1
 354                 >;
 355         };
 356
 357         pinctrl_cpi1: csi0grp {
 358                 fsl,pins = <
 359                         MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
 360                         MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC   0x1b0b1
 361                         MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC  0x1b0b1
 362                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1
 363                         MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1
 364                         MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1
 365                         MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1
 366                         MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1
 367                         MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1
 368                         MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1
 369                         MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1
 370                 >;
 371         };
 372
 373         /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/
 374
 375         pinctrl_ecspi2: ecspi2grp {
 376                 fsl,pins = <
 377                         MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK                 0x100b1
 378                         MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI                 0x100b1
 379                         MX6QDL_PAD_EIM_OE__ECSPI2_MISO                  0x100b1
 380                         MX6QDL_PAD_EIM_LBA__GPIO2_IO27                  0x100b1
 381                         MX6QDL_PAD_EIM_RW__GPIO2_IO26                   0x100b1
 382                 >;
 383         };
 384
 385         pinctrl_emcon_gpio1: emcongpio1 {
 386                 fsl,pins = <
 387                         MX6QDL_PAD_NANDF_D0__GPIO2_IO00                 0x0b0b1
 388                 >;
 389         };
 390
 391         pinctrl_emcon_gpio2: emcongpio2 {
 392                 fsl,pins = <
 393                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01                 0x0b0b1
 394                 >;
 395         };
 396
 397         pinctrl_emcon_gpio3: emcongpio3 {
 398                 fsl,pins = <
 399                         MX6QDL_PAD_NANDF_D2__GPIO2_IO02                 0x0b0b1
 400                 >;
 401         };
 402
 403         pinctrl_emcon_gpio4: emcongpio4 {
 404                 fsl,pins = <
 405                         MX6QDL_PAD_NANDF_D3__GPIO2_IO03                 0x0b0b1
 406                 >;
 407         };
 408
 409         pinctrl_emcon_gpio5: emcongpio5 {
 410                 fsl,pins = <
 411                         MX6QDL_PAD_NANDF_D4__GPIO2_IO04                 0x0b0b1
 412                 >;
 413         };
 414
 415         pinctrl_emcon_gpio6: emcongpio6 {
 416                 fsl,pins = <
 417                         MX6QDL_PAD_NANDF_D5__GPIO2_IO05                 0x0b0b1
 418                 >;
 419         };
 420
 421         pinctrl_emcon_gpio7: emcongpio7 {
 422                 fsl,pins = <
 423                         MX6QDL_PAD_NANDF_D6__GPIO2_IO06                 0x0b0b1
 424                 >;
 425         };
 426
 427         pinctrl_emcon_gpio8: emcongpio8 {
 428                 fsl,pins = <
 429                         MX6QDL_PAD_NANDF_D7__GPIO2_IO07                 0x0b0b1
 430                 >;
 431         };
 432
 433         pinctrl_emcon_irq_a: emconirqa {
 434                 fsl,pins = <
 435                         MX6QDL_PAD_NANDF_CLE__GPIO6_IO07                0x0b0b1
 436                 >;
 437         };
 438
 439         pinctrl_emcon_irq_b: emconirqb {
 440                 fsl,pins = <
 441                         MX6QDL_PAD_NANDF_CS2__GPIO6_IO15                0x0b0b1
 442                 >;
 443         };
 444
 445         pinctrl_emcon_irq_c: emconirqc {
 446                 fsl,pins = <
 447                         MX6QDL_PAD_NANDF_CS3__GPIO6_IO16                0x0b0b1
 448                 >;
 449         };
 450
 451         pinctrl_emcon_irq_pwr: emconirqpwr {
 452                 fsl,pins = <
 453                         MX6QDL_PAD_EIM_D23__GPIO3_IO23                  0x0b0b1
 454                 >;
 455         };
 456
 457         pinctrl_emcon_wake: emconwake {
 458                 fsl,pins = <
 459                         MX6QDL_PAD_EIM_DA2__GPIO3_IO02                  0x1b0b1
 460                 >;
 461         };
 462
 463         pinctrl_enet: enetgrp {
 464                 fsl,pins = <
 465                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO                 0x1b030
 466                         MX6QDL_PAD_ENET_MDC__ENET_MDC                   0x1b030
 467                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC                 0x1b030
 468                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0                 0x1b030
 469                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1                 0x1b030
 470                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2                 0x1b030
 471                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3                 0x1b030
 472                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 473                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x4001a0b1
 474                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC                 0x1b030
 475                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0                 0x1b030
 476                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1                 0x1b030
 477                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2                 0x1b030
 478                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3                 0x1b030
 479                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 480                         MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20             0x1b058
 481                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30                0x1b0b0
 482                  >;
 483         };
 484
 485         pinctrl_i2c1: i2c1grp {
 486                 fsl,pins = <
 487                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 488                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 489                 >;
 490         };
 491
 492         pinctrl_i2c2: i2c2grp {
 493                 fsl,pins = <
 494                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 495                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 496                 >;
 497         };
 498
 499         pinctrl_i2c3: i2c3grp {
 500                 fsl,pins = <
 501                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4000b070
 502                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b870
 503                 >;
 504         };
 505
 506         pinctrl_irq_touch1: irqtouch1 {
 507                 fsl,pins = <
 508                         MX6QDL_PAD_GPIO_5__GPIO1_IO05                   0x0b0b1
 509                 >;
 510         };
 511
 512         pinctrl_irq_touch2: irqtouch2 {
 513                 fsl,pins = <
 514                         MX6QDL_PAD_EIM_BCLK__GPIO6_IO31                 0x0b0b1
 515                 >;
 516         };
 517
 518         pinctrl_lvds_bl: lvdsbacklightgrp {
 519                 fsl,pins = <
 520                         MX6QDL_PAD_GPIO_9__PWM1_OUT                     0x0b0b1
 521                         MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09               0x0b0b1
 522                 >;
 523         };
 524
 525         pinctrl_lvds_reg: lvdsreggrp {
 526                 fsl,pins = <
 527                         MX6QDL_PAD_SD4_CLK__GPIO7_IO10                  0x0b0b1
 528                 >;
 529         };
 530
 531
 532         pinctrl_nor_flash: norflashgrp {
 533                 fsl,pins = <
 534                         MX6QDL_PAD_NANDF_CS0__GPIO6_IO11                0x1b0b1
 535                         MX6QDL_PAD_EIM_D21__ECSPI4_SCLK                 0x100b1
 536                         MX6QDL_PAD_EIM_D28__ECSPI4_MOSI                 0x100b1
 537                         MX6QDL_PAD_EIM_D22__ECSPI4_MISO                 0x100b1
 538                         MX6QDL_PAD_EIM_A25__GPIO5_IO02                  0x100b1
 539                 >;
 540         };
 541
 542         pinctrl_pcie_ctrl: pciegrp {
 543                 fsl,pins = <
 544                         MX6QDL_PAD_EIM_A16__GPIO2_IO22                  0x1b0b1
 545                         MX6QDL_PAD_GPIO_17__GPIO7_IO12                  0x1b0b1
 546                 >;
 547         };
 548
 549         pinctrl_pmic: pmicgrp {
 550                 fsl,pins = <
 551                         MX6QDL_PAD_SD4_DAT0__GPIO2_IO08                 0x0b0b1
 552                 >;
 553         };
 554
 555         pinctrl_pwm_fan: pwmfan {
 556                 fsl,pins = <
 557                         MX6QDL_PAD_SD4_DAT2__PWM4_OUT                   0x0b0b1
 558                 >;
 559         };
 560
 561         pinctrl_rgb_bl: rgbbacklightgrp {
 562                 fsl,pins = <
 563                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT                   0x0b0b1
 564                         MX6QDL_PAD_NANDF_ALE__GPIO6_IO08                0x0b0b1
 565                 >;
 566         };
 567
 568         pinctrl_rgb_bl_en: rgbenable {
 569                 fsl,pins = <
 570                         MX6QDL_PAD_SD4_CMD__GPIO7_IO09                  0x0b0b1
 571                 >;
 572         };
 573
 574         pinctrl_rgb24_display: rgbgrp {
 575                 fsl,pins = <
 576                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 577                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 578                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 579                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 580                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
 581                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 582                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 583                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 584                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 585                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 586                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 587                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 588                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 589                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 590                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 591                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 592                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 593                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 594                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 595                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 596                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 597                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 598                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 599                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 600                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 601                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 602                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 603                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 604                 >;
 605         };
 606
 607         pinctrl_secure: securegrp {
 608                 fsl,pins = <
 609                         MX6QDL_PAD_GPIO_18__GPIO7_IO13                  0x1b0b1
 610                 >;
 611         };
 612
 613         pinctrl_som_leds: somledgrp {
 614                 fsl,pins = <
 615                         MX6QDL_PAD_EIM_DA0__GPIO3_IO00                  0x0b0b1
 616                         MX6QDL_PAD_EIM_DA1__GPIO3_IO01                  0x0b0b1
 617                 >;
 618         };
 619
 620         pinctrl_spdif_in: spdifin {
 621                 fsl,pins = <
 622                         MX6QDL_PAD_GPIO_16__SPDIF_IN                    0x1b0b0
 623                 >;
 624         };
 625
 626         pinctrl_spdif_out: spdifout {
 627                 fsl,pins = <
 628                         MX6QDL_PAD_GPIO_19__SPDIF_OUT                   0x13091
 629                 >;
 630         };
 631
 632         pinctrl_uart1: uart1grp {
 633                 fsl,pins = <
 634                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 635                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 636                 >;
 637         };
 638
 639         pinctrl_uart2: uart2grp {
 640                 fsl,pins = <
 641                         MX6QDL_PAD_SD4_DAT5__UART2_RTS_B                0x1b0b1
 642                         MX6QDL_PAD_SD4_DAT6__UART2_CTS_B                0x1b0b1
 643                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA              0x1b0b1
 644                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA              0x1b0b1
 645                 >;
 646         };
 647
 648         pinctrl_uart3: uart3grp {
 649                 fsl,pins = <
 650                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA               0x1b0b1
 651                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA               0x1b0b1
 652                 >;
 653         };
 654
 655         pinctrl_uart4: uart4grp {
 656                 fsl,pins = <
 657                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA              0x1b0b1
 658                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA              0x1b0b1
 659                 >;
 660         };
 661
 662         pinctrl_uart5: uart5grp {
 663                 fsl,pins = <
 664                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA              0x1b0b1
 665                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA              0x1b0b1
 666                 >;
 667         };
 668
 669         pinctrl_usb_host1: usbhgrp {
 670                 fsl,pins = <
 671                         MX6QDL_PAD_EIM_D31__USB_H1_PWR                  0x1B058
 672                         MX6QDL_PAD_EIM_D30__USB_H1_OC                   0x1B058
 673                 >;
 674         };
 675
 676         pinctrl_usb_otg: usbotggrp {
 677                 fsl,pins = <
 678                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID               0x17059
 679                         MX6QDL_PAD_GPIO_7__GPIO1_IO07                   0x17059
 680                         MX6QDL_PAD_GPIO_8__GPIO1_IO08                   0x17059
 681                 >;
 682         };
 683
 684         pinctrl_usdhc1: usdhc1grp {
 685                 fsl,pins = <
 686                         MX6QDL_PAD_SD1_CMD__SD1_CMD                     0x17059
 687                         MX6QDL_PAD_SD1_CLK__SD1_CLK                     0x10059
 688                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0                  0x17059
 689                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1                  0x17059
 690                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2                  0x17059
 691                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3                  0x17059
 692                         MX6QDL_PAD_GPIO_1__SD1_CD_B                     0x1b0b1
 693                         MX6QDL_PAD_DI0_PIN4__SD1_WP                     0x1b0b1
 694                 >;
 695         };
 696
 697         pinctrl_usdhc2: usdhc2grp {
 698                 fsl,pins = <
 699                         MX6QDL_PAD_SD2_CMD__SD2_CMD                     0x17059
 700                         MX6QDL_PAD_SD2_CLK__SD2_CLK                     0x10059
 701                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0                  0x17059
 702                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1                  0x17059
 703                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2                  0x17059
 704                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3                  0x17059
 705                         MX6QDL_PAD_GPIO_4__SD2_CD_B                     0x1b0b1
 706                         MX6QDL_PAD_GPIO_2__SD2_WP                       0x1b0b1
 707                 >;
 708         };
 709
 710         pinctrl_usdhc3: usdhc3grp {
 711                 fsl,pins = <
 712                         MX6QDL_PAD_SD3_CMD__SD3_CMD                     0x17059
 713                         MX6QDL_PAD_SD3_CLK__SD3_CLK                     0x10059
 714                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0                  0x17059
 715                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1                  0x17059
 716                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2                  0x17059
 717                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3                  0x17059
 718                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4                  0x17059
 719                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5                  0x17059
 720                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6                  0x17059
 721                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7                  0x17059
 722                         MX6QDL_PAD_SD3_RST__SD3_RESET                   0x1b0b1
 723                 >;
 724         };
 725 };
 726
 727 &ipu1_di0_disp0 {
 728         remote-endpoint = <&rgb_encoder_in>;
 729 };
 730
 731 &pcie {
 732         pinctrl-names = "default";
 733         pinctrl-0 = <&pinctrl_pcie_ctrl>;
 734         reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
 735         disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>;
 736 };
 737
 738 &pwm1 {
 739         #pwm-cells = <2>;
 740         status = "okay";
 741 };
 742
 743 &pwm3 {
 744         #pwm-cells = <2>;
 745         status = "okay";
 746 };
 747
 748 &pwm4 {
 749         #pwm-cells = <2>;
 750         status = "okay";
 751 };
 752
 753 &uart1 {
 754         pinctrl-names = "default";
 755         pinctrl-0 = <&pinctrl_uart1>;
 756         status = "okay";
 757 };
 758
 759 &uart2 {
 760         pinctrl-names = "default";
 761         pinctrl-0 = <&pinctrl_uart2>;
 762 };
 763
 764 &uart3 {
 765         pinctrl-names = "default";
 766         pinctrl-0 = <&pinctrl_uart3>;
 767 };
 768
 769 &uart4 {
 770         pinctrl-names = "default";
 771         pinctrl-0 = <&pinctrl_uart4>;
 772 };
 773
 774 &uart5 {
 775         pinctrl-names = "default";
 776         pinctrl-0 = <&pinctrl_uart5>;
 777 };
 778
 779 &usbh1 {
 780         pinctrl-names = "default";
 781         pinctrl-0 = <&pinctrl_usb_host1>;
 782 };
 783
 784 &usbotg {
 785         pinctrl-names = "default";
 786         pinctrl-0 = <&pinctrl_usb_otg>;
 787         vbus-supply = <&reg_usb_otg>;
 788         dr_mode = "peripheral";
 789 };
 790
 791 &usdhc1 {
 792         pinctrl-names = "default";
 793         pinctrl-0 = <&pinctrl_usdhc1>;
 794         fsl,wp-controller;
 795 };
 796
 797 &usdhc2 {
 798         pinctrl-names = "default";
 799         pinctrl-0 = <&pinctrl_usdhc2>;
 800         fsl,wp-controller;
 801 };
 802
 803 &usdhc3 {
 804         pinctrl-names = "default";
 805         pinctrl-0 = <&pinctrl_usdhc3>;
 806         non-removable;
 807         bus-width = <8>;
 808         status = "okay";
 809 };
 810
 811 /******device power Management*********/
 812
 813 &cpu0 {
 814         voltage-tolerance = <2>;
 815 };
 816
 817 &reg_arm {
 818         vin-supply = <&vddcore_reg>;
 819 };
 820
 821 &reg_soc {
 822         vin-supply = <&vddsoc_reg>;
 823 };
 824
 825 &reg_pu {
 826         vin-supply = <&vddsoc_reg>;
 827 };
 828
 829 /*******Disabled HW following***********/
 830
 831 &snvs_rtc {
 832         status = "disabled";
 833 };