arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright 2013 Sascha Hauer, Pengutronix
   4  *
   5  * Copyright 2013-2021 TQ-Systems GmbH
   6  * Author: Markus Niebel <Markus.Niebel@tq-group.com>
   7  */
   8
   9 #include <dt-bindings/clock/imx6qdl-clock.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/input/input.h>
  12 #include <dt-bindings/sound/fsl-imx-audmux.h>
  13
  14 / {
  15         aliases {
  16                 mmc0 = &usdhc3;
  17                 mmc1 = &usdhc2;
  18                 /delete-property/ mmc2;
  19                 /delete-property/ mmc3;
  20                 rtc0 = &rtc0;
  21         };
  22
  23         chosen {
  24                 stdout-path = &uart2;
  25         };
  26
  27         beeper: gpio-beeper {
  28                 compatible = "gpio-beeper";
  29                 pinctrl-names = "default";
  30                 pinctrl-0 = <&pinctrl_gpiobeeper>;
  31                 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
  32         };
  33
  34         gpio_buttons: gpio-buttons {
  35                 compatible = "gpio-keys";
  36                 pinctrl-names = "default";
  37                 pinctrl-0 = <&pinctrl_gpiobuttons>;
  38
  39                 button-1 {
  40                         label = "s6";
  41                         linux,code = <KEY_F6>;
  42                         gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
  43                         wakeup-source;
  44                 };
  45
  46                 button-2 {
  47                         label = "s7";
  48                         linux,code = <KEY_F7>;
  49                         gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
  50                         wakeup-source;
  51                 };
  52
  53                 button-3 {
  54                         label = "s8";
  55                         linux,code = <KEY_F8>;
  56                         gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
  57                         wakeup-source;
  58                 };
  59         };
  60
  61         gpio-leds {
  62                 compatible = "gpio-leds";
  63                 pinctrl-names = "default";
  64                 pinctrl-0 = <&pinctrl_gpioled>;
  65
  66                 led1 {
  67                         label = "led1";
  68                         gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
  69                         linux,default-trigger = "default-on";
  70                 };
  71
  72                 led2 {
  73                         label = "led2";
  74                         gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>;
  75                         linux,default-trigger = "heartbeat";
  76                 };
  77         };
  78
  79         reg_mba6_3p3v: regulator-mba6-3p3v {
  80                 compatible = "regulator-fixed";
  81                 regulator-name = "supply-mba6-3p3v";
  82                 regulator-min-microvolt = <3300000>;
  83                 regulator-max-microvolt = <3300000>;
  84                 regulator-always-on;
  85         };
  86
  87         reg_pcie: regulator-pcie {
  88                 compatible = "regulator-fixed";
  89                 pinctrl-names = "default";
  90                 pinctrl-0 = <&pinctrl_regpcie>;
  91                 regulator-name = "supply-pcie";
  92                 regulator-min-microvolt = <3300000>;
  93                 regulator-max-microvolt = <3300000>;
  94                 /* PCIE.PWR_EN */
  95                 gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
  96                 enable-active-high;
  97                 regulator-always-on;
  98                 vin-supply = <&reg_mba6_3p3v>;
  99         };
 100
 101         reg_vcc3v3_audio: regulator-vcc3v3-audio {
 102                 compatible = "regulator-fixed";
 103                 regulator-name = "vcc3v3-audio";
 104                 regulator-min-microvolt = <3300000>;
 105                 regulator-max-microvolt = <3300000>;
 106                 vin-supply = <&reg_mba6_3p3v>;
 107         };
 108
 109         sound {
 110                 compatible = "fsl,imx-audio-tlv320aic32x4";
 111                 pinctrl-names = "default";
 112                 pinctrl-0 = <&pinctrl_audmux>;
 113                 model = "imx-audio-tlv320aic32x4";
 114                 ssi-controller = <&ssi1>;
 115                 audio-codec = <&tlv320aic32x4>;
 116                 audio-asrc = <&asrc>;
 117                 audio-routing =
 118                         "IN3_L", "Mic Jack",
 119                         "Mic Jack", "Mic Bias",
 120                         "IN1_L", "Line In Jack",
 121                         "IN1_R", "Line In Jack",
 122                         "Line Out Jack", "LOL",
 123                         "Line Out Jack", "LOR";
 124                 mux-int-port = <1>;
 125                 mux-ext-port = <3>;
 126         };
 127 };
 128
 129 &audmux {
 130         status = "okay";
 131
 132         mux-ssi0 {
 133                 fsl,audmux-port = <MX31_AUDMUX_PORT1_SSI0>;
 134                 fsl,port-config = <
 135                         (IMX_AUDMUX_V2_PTCR_SYN |
 136                                 IMX_AUDMUX_V2_PTCR_TFSDIR |
 137                                 IMX_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) |
 138                                 IMX_AUDMUX_V2_PTCR_TCLKDIR |
 139                                 IMX_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT3_SSI_PINS_3))
 140                         IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT3_SSI_PINS_3)
 141                 >;
 142         };
 143
 144         mux-aud3 {
 145                 fsl,audmux-port = <MX31_AUDMUX_PORT3_SSI_PINS_3>;
 146                 fsl,port-config = <
 147                         IMX_AUDMUX_V2_PTCR_SYN
 148                         IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0)
 149                 >;
 150         };
 151 };
 152
 153 &can1 {
 154         pinctrl-names = "default";
 155         pinctrl-0 = <&pinctrl_can1>;
 156         status = "okay";
 157 };
 158
 159 &can2 {
 160         pinctrl-names = "default";
 161         pinctrl-0 = <&pinctrl_can2>;
 162         status = "okay";
 163 };
 164
 165 &ecspi1 {
 166         pinctrl-names = "default";
 167         pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_mba6>;
 168         cs-gpios = <&gpio3 19 0>, <&gpio3 24 0>;
 169 };
 170
 171 &fec {
 172         phy-mode = "rgmii-id";
 173         phy-handle = <&ethphy>;
 174         mac-address = [00 00 00 00 00 00];
 175         status = "okay";
 176
 177         mdio {
 178                 #address-cells = <1>;
 179                 #size-cells = <0>;
 180
 181                 ethphy: ethernet-phy@3 {
 182                         compatible = "ethernet-phy-ieee802.3-c22";
 183                         reg = <3>;
 184                         interrupt-parent = <&gpio1>;
 185                         interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
 186                         reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
 187                         reset-assert-us = <1000>;
 188                         reset-deassert-us = <100000>;
 189                         micrel,force-master;
 190                         max-speed = <1000>;
 191                 };
 192         };
 193 };
 194
 195 &hdmi {
 196         pinctrl-names = "default";
 197         pinctrl-0 = <&pinctrl_hdmi>;
 198         ddc-i2c-bus = <&i2c2>;
 199         status = "okay";
 200 };
 201
 202 &i2c1 {
 203         tlv320aic32x4: audio-codec@18 {
 204                 compatible = "ti,tlv320aic32x4";
 205                 reg = <0x18>;
 206                 clocks = <&clks IMX6QDL_CLK_CKO>;
 207                 clock-names = "mclk";
 208                 pinctrl-names = "default";
 209                 pinctrl-0 = <&pinctrl_codec>;
 210                 ldoin-supply = <&reg_vcc3v3_audio>;
 211                 iov-supply = <&reg_mba6_3p3v>;
 212         };
 213 };
 214
 215 /* DDC */
 216 &i2c2 {
 217         clock-frequency = <100000>;
 218         pinctrl-names = "default", "gpio";
 219         pinctrl-0 = <&pinctrl_i2c2>;
 220         pinctrl-1 = <&pinctrl_i2c2_recovery>;
 221         scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 222         sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 223         status = "okay";
 224 };
 225
 226 &pcie {
 227         pinctrl-names = "default";
 228         pinctrl-0 = <&pinctrl_pcie>;
 229         reset-gpio = <&gpio6 7 GPIO_ACTIVE_LOW>;
 230         vpcie-supply = <&reg_pcie>;
 231         status = "okay";
 232 };
 233
 234 &pwm1 {
 235         pinctrl-names = "default";
 236         pinctrl-0 = <&pinctrl_pwm1>;
 237         status = "okay";
 238 };
 239
 240 &pwm3 {
 241         pinctrl-names = "default";
 242         pinctrl-0 = <&pinctrl_pwm3>;
 243         status = "okay";
 244 };
 245
 246 &pwm4 {
 247         pinctrl-names = "default";
 248         pinctrl-0 = <&pinctrl_pwm4>;
 249         status = "okay";
 250 };
 251
 252 &snvs_poweroff {
 253         status = "okay";
 254 };
 255
 256 &ssi1 {
 257         status = "okay";
 258 };
 259
 260 &uart2 {
 261         pinctrl-names = "default";
 262         pinctrl-0 = <&pinctrl_uart2>;
 263         status = "okay";
 264 };
 265
 266 &uart3 {
 267         pinctrl-names = "default";
 268         pinctrl-0 = <&pinctrl_uart3>;
 269         uart-has-rtscts;
 270         status = "okay";
 271 };
 272
 273 &uart4 {
 274         pinctrl-names = "default";
 275         pinctrl-0 = <&pinctrl_uart4>;
 276         uart-has-rtscts;
 277         linux,rs485-enabled-at-boot-time;
 278         rs485-rts-active-low;
 279         rs485-rx-during-tx;
 280         status = "okay";
 281 };
 282
 283 &uart5 {
 284         pinctrl-names = "default";
 285         pinctrl-0 = <&pinctrl_uart5>;
 286         uart-has-rtscts;
 287         status = "okay";
 288 };
 289
 290 &usbh1 {
 291         disable-over-current;
 292         status = "okay";
 293         #address-cells = <1>;
 294         #size-cells = <0>;
 295
 296         hub@1 {
 297                 compatible = "usb424,2517";
 298                 reg = <1>;
 299                 #address-cells = <1>;
 300                 #size-cells = <0>;
 301
 302                 ethernet@1 {
 303                         compatible = "usb424,9e00";
 304                         reg = <1>;
 305                         nvmem-cells = <&mba_mac_address>;
 306                         nvmem-cell-names = "mac-address";
 307                 };
 308         };
 309 };
 310
 311 &usbotg {
 312         pinctrl-names = "default";
 313         pinctrl-0 = <&pinctrl_usbotg>;
 314         power-active-high;
 315         over-current-active-low;
 316         srp-disable;
 317         hnp-disable;
 318         adp-disable;
 319         dr_mode = "otg";
 320         status = "okay";
 321 };
 322
 323 /* SD card slot */
 324 &usdhc2 {
 325         pinctrl-names = "default";
 326         pinctrl-0 = <&pinctrl_usdhc2>;
 327         vmmc-supply = <&reg_mba6_3p3v>;
 328         bus-width = <4>;
 329         no-1-8-v;
 330         no-mmc;
 331         no-sdio;
 332         cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 333         wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 334         status = "okay";
 335 };
 336
 337 &wdog1 {
 338         pinctrl-names = "default";
 339         pinctrl-0 = <&pinctrl_wdog1>;
 340         /* does not work on unmodified starter kit */
 341         /* fsl,ext-reset-output; */
 342         status = "okay";
 343 };
 344
 345 &iomuxc {
 346         pinctrl-names = "default";
 347         pinctrl-0 = <&pinctrl_hog>;
 348
 349         pinctrl_audmux: audmuxgrp {
 350                 fsl,pins = <
 351                         MX6QDL_PAD_CSI0_DAT7__AUD3_RXD  0x1b0b0
 352                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC  0x1b0b0
 353                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD  0x1b0b0
 354                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
 355                 >;
 356         };
 357
 358         pinctrl_can1: can1grp {
 359                 fsl,pins = <
 360                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0xb099
 361                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0xb099
 362                 >;
 363         };
 364
 365         pinctrl_can2: can2grp {
 366                 fsl,pins = <
 367                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0xb099
 368                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0xb099
 369                 >;
 370         };
 371
 372         pinctrl_codec: codecgrp {
 373                 fsl,pins = <
 374                         MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0xb0 /* CLK */
 375                 >;
 376         };
 377
 378         pinctrl_ecspi1_mba6: ecspimba6grp {
 379                 fsl,pins = <
 380                         MX6QDL_PAD_EIM_D24__GPIO3_IO24 0xb099 /* eCSPI1 SS2 */
 381                 >;
 382         };
 383
 384         pinctrl_enet: enetgrp {
 385                 fsl,pins = <
 386                         /* FEC phy IRQ */
 387                         MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28     0x00011008
 388                         /* FEC phy reset */
 389                         MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25   0x1b099
 390                         /* DSE = 100, 100k up, SPEED = MED */
 391                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0xb0a0
 392                         MX6QDL_PAD_ENET_MDC__ENET_MDC         0xb0a0
 393                         /* DSE = 111, pull 100k up */
 394                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0xb038
 395                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0xb038
 396                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0xb038
 397                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0xb038
 398                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0xb038
 399                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038
 400                         /* DSE = 111, pull external */
 401                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x0038
 402                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x0038
 403                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x0038
 404                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x0038
 405                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x0038
 406                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038
 407                         /* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */
 408                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0f0
 409                 >;
 410         };
 411
 412         pinctrl_gpiobeeper: gpiobeepergrp {
 413                 fsl,pins = <
 414                         MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0xb099
 415                 >;
 416         };
 417
 418         pinctrl_gpiobuttons: gpiobuttongrp {
 419                 fsl,pins = <
 420                         MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b099
 421                         MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b099
 422                         MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b099
 423                 >;
 424         };
 425
 426         pinctrl_gpioled: gpioledgrp {
 427                 fsl,pins = <
 428                         MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0xb099 /* LED V15 */
 429                         MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb099 /* LED V16 */
 430                 >;
 431         };
 432
 433         pinctrl_hdmi: hdmigrp {
 434                 /* NOTE: DDC is done via I2C2, so DON'T
 435                  * configure DDC pins for HDMI!
 436                  */
 437                 fsl,pins = <
 438                         MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
 439                 >;
 440         };
 441
 442         pinctrl_hog: hoggrp {
 443                 fsl,pins = <
 444                         MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099
 445
 446                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099
 447                         MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099
 448                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099
 449
 450                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099
 451                         MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099
 452                         MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099
 453                         MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099
 454                         MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099
 455                         MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099
 456                         MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099
 457
 458                         MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099
 459                         MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099
 460                         MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099
 461                         MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099
 462                         MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099
 463
 464                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099
 465                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099
 466                         MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099
 467                         MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099
 468
 469                         MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099
 470                         MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099
 471                         MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099
 472
 473                         MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099
 474                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099
 475                 >;
 476         };
 477
 478         pinctrl_i2c2: i2c2grp {
 479                 fsl,pins = <
 480                         MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899
 481                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899
 482                 >;
 483         };
 484
 485         pinctrl_i2c2_recovery: i2c2recoverygrp {
 486                 fsl,pins = <
 487                         MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b899
 488                         MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b899
 489                 >;
 490         };
 491
 492         pinctrl_pcie: pciegrp {
 493                 fsl,pins = <
 494                         /* HYS = 1, DSE = 110, 100k up, SPEED = HIGH (11)*/
 495                         MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x001b0f0 /* #PCIE.WAKE */
 496                         MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x001b0f0 /* #PCIE.RST */
 497                         MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x001b0f0 /* #PCIE.DIS */
 498                 >;
 499         };
 500
 501         pinctrl_pwm1: pwm1grp {
 502                 fsl,pins = <
 503                         /* 100 k PD, DSE 120 OHM, SPEED LO */
 504                         MX6QDL_PAD_GPIO_9__PWM1_OUT 0x00003050
 505                 >;
 506         };
 507
 508         pinctrl_pwm3: pwm3grp {
 509                 fsl,pins = <
 510                         /* 100 k PD, DSE 120 OHM, SPEED LO */
 511                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x00003050
 512                 >;
 513         };
 514
 515         pinctrl_pwm4: pwm4grp {
 516                 fsl,pins = <
 517                         /* 100 k PD, DSE 120 OHM, SPEED LO */
 518                         MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x00003050
 519                 >;
 520         };
 521
 522         pinctrl_regpcie: regpciegrp {
 523                 fsl,pins = <
 524                         /* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/
 525                         MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */
 526                 >;
 527         };
 528
 529         pinctrl_uart2: uart2grp {
 530                 fsl,pins = <
 531                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099
 532                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099
 533                 >;
 534         };
 535
 536         pinctrl_uart3: uart3grp {
 537                 fsl,pins = <
 538                         MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
 539                         MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
 540                         MX6QDL_PAD_EIM_D30__UART3_CTS_B   0x1b0b1
 541                         MX6QDL_PAD_EIM_D31__UART3_RTS_B   0x1b0b1
 542                 >;
 543         };
 544
 545         pinctrl_uart4: uart4grp {
 546                 fsl,pins = <
 547                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
 548                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
 549                         MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
 550                         MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
 551                 >;
 552         };
 553
 554         pinctrl_uart5: uart5grp {
 555                 fsl,pins = <
 556                         MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
 557                         MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
 558                         MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1
 559                         MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1
 560                 >;
 561         };
 562
 563         pinctrl_usdhc2: usdhc2grp {
 564                 fsl,pins = <
 565                         /* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */
 566                         MX6QDL_PAD_SD2_CLK__SD2_CLK    0x00017071
 567                         /* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */
 568                         MX6QDL_PAD_SD2_CMD__SD2_CMD    0x00017059
 569                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059
 570                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059
 571                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059
 572                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059
 573
 574                         MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x0001b099 /* usdhc2 CD */
 575                         MX6QDL_PAD_GPIO_2__GPIO1_IO02  0x0001b099 /* usdhc2 WP */
 576                 >;
 577         };
 578
 579         pinctrl_usbotg: usbotggrp {
 580                 fsl,pins = <
 581                         MX6QDL_PAD_EIM_D21__USB_OTG_OC  0x0001b0b0
 582                         MX6QDL_PAD_GPIO_1__USB_OTG_ID   0x00017059
 583                         MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0001b099
 584                 >;
 585         };
 586
 587         pinctrl_wdog1: wdog1grp {
 588                 fsl,pins = <
 589                          /* Watchdog out */
 590                         MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x0000b099
 591                 >;
 592         };
 593 };