arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11
  12 / {
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15
  16         model = "Qualcomm Technologies, Inc. IPQ4019";
  17         compatible = "qcom,ipq4019";
  18         interrupt-parent = <&intc>;
  19
  20         reserved-memory {
  21                 #address-cells = <0x1>;
  22                 #size-cells = <0x1>;
  23                 ranges;
  24
  25                 smem_region: smem@87e00000 {
  26                         reg = <0x87e00000 0x080000>;
  27                         no-map;
  28                 };
  29
  30                 tz@87e80000 {
  31                         reg = <0x87e80000 0x180000>;
  32                         no-map;
  33                 };
  34         };
  35
  36         aliases {
  37                 spi0 = &blsp1_spi1;
  38                 spi1 = &blsp1_spi2;
  39                 i2c0 = &blsp1_i2c3;
  40                 i2c1 = &blsp1_i2c4;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46                 cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a7";
  49                         enable-method = "qcom,kpss-acc-v2";
  50                         next-level-cache = <&L2>;
  51                         qcom,acc = <&acc0>;
  52                         qcom,saw = <&saw0>;
  53                         reg = <0x0>;
  54                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  55                         clock-frequency = <0>;
  56                         clock-latency = <256000>;
  57                         operating-points-v2 = <&cpu0_opp_table>;
  58                 };
  59
  60                 cpu@1 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a7";
  63                         enable-method = "qcom,kpss-acc-v2";
  64                         next-level-cache = <&L2>;
  65                         qcom,acc = <&acc1>;
  66                         qcom,saw = <&saw1>;
  67                         reg = <0x1>;
  68                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  69                         clock-frequency = <0>;
  70                         clock-latency = <256000>;
  71                         operating-points-v2 = <&cpu0_opp_table>;
  72                 };
  73
  74                 cpu@2 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a7";
  77                         enable-method = "qcom,kpss-acc-v2";
  78                         next-level-cache = <&L2>;
  79                         qcom,acc = <&acc2>;
  80                         qcom,saw = <&saw2>;
  81                         reg = <0x2>;
  82                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  83                         clock-frequency = <0>;
  84                         clock-latency = <256000>;
  85                         operating-points-v2 = <&cpu0_opp_table>;
  86                 };
  87
  88                 cpu@3 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a7";
  91                         enable-method = "qcom,kpss-acc-v2";
  92                         next-level-cache = <&L2>;
  93                         qcom,acc = <&acc3>;
  94                         qcom,saw = <&saw3>;
  95                         reg = <0x3>;
  96                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  97                         clock-frequency = <0>;
  98                         clock-latency = <256000>;
  99                         operating-points-v2 = <&cpu0_opp_table>;
 100                 };
 101
 102                 L2: l2-cache {
 103                         compatible = "cache";
 104                         cache-level = <2>;
 105                         cache-unified;
 106                         qcom,saw = <&saw_l2>;
 107                 };
 108         };
 109
 110         cpu0_opp_table: opp-table {
 111                 compatible = "operating-points-v2";
 112                 opp-shared;
 113
 114                 opp-48000000 {
 115                         opp-hz = /bits/ 64 <48000000>;
 116                         clock-latency-ns = <256000>;
 117                 };
 118                 opp-200000000 {
 119                         opp-hz = /bits/ 64 <200000000>;
 120                         clock-latency-ns = <256000>;
 121                 };
 122                 opp-500000000 {
 123                         opp-hz = /bits/ 64 <500000000>;
 124                         clock-latency-ns = <256000>;
 125                 };
 126                 opp-716000000 {
 127                         opp-hz = /bits/ 64 <716000000>;
 128                         clock-latency-ns = <256000>;
 129                 };
 130         };
 131
 132         memory {
 133                 device_type = "memory";
 134                 reg = <0x0 0x0>;
 135         };
 136
 137         pmu {
 138                 compatible = "arm,cortex-a7-pmu";
 139                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
 140                                          IRQ_TYPE_LEVEL_HIGH)>;
 141         };
 142
 143         clocks {
 144                 sleep_clk: sleep_clk {
 145                         compatible = "fixed-clock";
 146                         clock-frequency = <32000>;
 147                         #clock-cells = <0>;
 148                 };
 149
 150                 xo: xo {
 151                         compatible = "fixed-clock";
 152                         clock-frequency = <48000000>;
 153                         #clock-cells = <0>;
 154                 };
 155         };
 156
 157         firmware {
 158                 scm {
 159                         compatible = "qcom,scm-ipq4019", "qcom,scm";
 160                 };
 161         };
 162
 163         timer {
 164                 compatible = "arm,armv7-timer";
 165                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 166                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 167                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 168                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 169                 clock-frequency = <48000000>;
 170                 always-on;
 171         };
 172
 173         soc {
 174                 #address-cells = <1>;
 175                 #size-cells = <1>;
 176                 ranges;
 177                 compatible = "simple-bus";
 178
 179                 intc: interrupt-controller@b000000 {
 180                         compatible = "qcom,msm-qgic2";
 181                         interrupt-controller;
 182                         #interrupt-cells = <3>;
 183                         reg = <0x0b000000 0x1000>,
 184                         <0x0b002000 0x1000>;
 185                 };
 186
 187                 gcc: clock-controller@1800000 {
 188                         compatible = "qcom,gcc-ipq4019";
 189                         #clock-cells = <1>;
 190                         #power-domain-cells = <1>;
 191                         #reset-cells = <1>;
 192                         reg = <0x1800000 0x60000>;
 193                         clocks = <&xo>, <&sleep_clk>;
 194                         clock-names = "xo", "sleep_clk";
 195                 };
 196
 197                 prng: rng@22000 {
 198                         compatible = "qcom,prng";
 199                         reg = <0x22000 0x140>;
 200                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 201                         clock-names = "core";
 202                         status = "disabled";
 203                 };
 204
 205                 tlmm: pinctrl@1000000 {
 206                         compatible = "qcom,ipq4019-pinctrl";
 207                         reg = <0x01000000 0x300000>;
 208                         gpio-controller;
 209                         gpio-ranges = <&tlmm 0 0 100>;
 210                         #gpio-cells = <2>;
 211                         interrupt-controller;
 212                         #interrupt-cells = <2>;
 213                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 214                 };
 215
 216                 vqmmc: regulator@1948000 {
 217                         compatible = "qcom,vqmmc-ipq4019-regulator";
 218                         reg = <0x01948000 0x4>;
 219                         regulator-name = "vqmmc";
 220                         regulator-min-microvolt = <1500000>;
 221                         regulator-max-microvolt = <3000000>;
 222                         regulator-always-on;
 223                         status = "disabled";
 224                 };
 225
 226                 sdhci: mmc@7824900 {
 227                         compatible = "qcom,ipq4019-sdhci", "qcom,sdhci-msm-v4";
 228                         reg = <0x7824900 0x11c>, <0x7824000 0x800>;
 229                         reg-names = "hc", "core";
 230                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 231                         interrupt-names = "hc_irq", "pwr_irq";
 232                         bus-width = <8>;
 233                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 234                                  <&gcc GCC_SDCC1_APPS_CLK>,
 235                                  <&xo>;
 236                         clock-names = "iface",
 237                                       "core",
 238                                       "xo";
 239                         status = "disabled";
 240                 };
 241
 242                 blsp_dma: dma-controller@7884000 {
 243                         compatible = "qcom,bam-v1.7.0";
 244                         reg = <0x07884000 0x23000>;
 245                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 246                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 247                         clock-names = "bam_clk";
 248                         #dma-cells = <1>;
 249                         qcom,ee = <0>;
 250                         status = "disabled";
 251                 };
 252
 253                 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
 254                         compatible = "qcom,spi-qup-v2.2.1";
 255                         reg = <0x78b5000 0x600>;
 256                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 257                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 258                                  <&gcc GCC_BLSP1_AHB_CLK>;
 259                         clock-names = "core", "iface";
 260                         #address-cells = <1>;
 261                         #size-cells = <0>;
 262                         dmas = <&blsp_dma 4>, <&blsp_dma 5>;
 263                         dma-names = "tx", "rx";
 264                         status = "disabled";
 265                 };
 266
 267                 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
 268                         compatible = "qcom,spi-qup-v2.2.1";
 269                         reg = <0x78b6000 0x600>;
 270                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 271                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 272                                 <&gcc GCC_BLSP1_AHB_CLK>;
 273                         clock-names = "core", "iface";
 274                         #address-cells = <1>;
 275                         #size-cells = <0>;
 276                         dmas = <&blsp_dma 6>, <&blsp_dma 7>;
 277                         dma-names = "tx", "rx";
 278                         status = "disabled";
 279                 };
 280
 281                 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
 282                         compatible = "qcom,i2c-qup-v2.2.1";
 283                         reg = <0x78b7000 0x600>;
 284                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 285                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
 286                                  <&gcc GCC_BLSP1_AHB_CLK>;
 287                         clock-names = "core", "iface";
 288                         #address-cells = <1>;
 289                         #size-cells = <0>;
 290                         dmas = <&blsp_dma 8>, <&blsp_dma 9>;
 291                         dma-names = "tx", "rx";
 292                         status = "disabled";
 293                 };
 294
 295                 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
 296                         compatible = "qcom,i2c-qup-v2.2.1";
 297                         reg = <0x78b8000 0x600>;
 298                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 299                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
 300                                  <&gcc GCC_BLSP1_AHB_CLK>;
 301                         clock-names = "core", "iface";
 302                         #address-cells = <1>;
 303                         #size-cells = <0>;
 304                         dmas = <&blsp_dma 10>, <&blsp_dma 11>;
 305                         dma-names = "tx", "rx";
 306                         status = "disabled";
 307                 };
 308
 309                 cryptobam: dma-controller@8e04000 {
 310                         compatible = "qcom,bam-v1.7.0";
 311                         reg = <0x08e04000 0x20000>;
 312                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 313                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
 314                         clock-names = "bam_clk";
 315                         #dma-cells = <1>;
 316                         qcom,ee = <1>;
 317                         qcom,controlled-remotely;
 318                         status = "disabled";
 319                 };
 320
 321                 crypto: crypto@8e3a000 {
 322                         compatible = "qcom,crypto-v5.1";
 323                         reg = <0x08e3a000 0x6000>;
 324                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
 325                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 326                                  <&gcc GCC_CRYPTO_CLK>;
 327                         clock-names = "iface", "bus", "core";
 328                         dmas = <&cryptobam 2>, <&cryptobam 3>;
 329                         dma-names = "rx", "tx";
 330                         status = "disabled";
 331                 };
 332
 333                 acc0: power-manager@b088000 {
 334                         compatible = "qcom,kpss-acc-v2";
 335                         reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
 336                 };
 337
 338                 acc1: power-manager@b098000 {
 339                         compatible = "qcom,kpss-acc-v2";
 340                         reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
 341                 };
 342
 343                 acc2: power-manager@b0a8000 {
 344                         compatible = "qcom,kpss-acc-v2";
 345                         reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
 346                 };
 347
 348                 acc3: power-manager@b0b8000 {
 349                         compatible = "qcom,kpss-acc-v2";
 350                         reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
 351                 };
 352
 353                 saw0: power-manager@b089000 {
 354                         compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
 355                         reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
 356                 };
 357
 358                 saw1: power-manager@b099000 {
 359                         compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
 360                         reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
 361                 };
 362
 363                 saw2: power-manager@b0a9000 {
 364                         compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
 365                         reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
 366                 };
 367
 368                 saw3: power-manager@b0b9000 {
 369                         compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
 370                         reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
 371                 };
 372
 373                 saw_l2: power-manager@b012000 {
 374                         compatible = "qcom,ipq4019-saw2-l2", "qcom,saw2";
 375                         reg = <0xb012000 0x1000>;
 376                 };
 377
 378                 blsp1_uart1: serial@78af000 {
 379                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 380                         reg = <0x78af000 0x200>;
 381                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 382                         status = "disabled";
 383                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 384                                 <&gcc GCC_BLSP1_AHB_CLK>;
 385                         clock-names = "core", "iface";
 386                         dmas = <&blsp_dma 0>, <&blsp_dma 1>;
 387                         dma-names = "tx", "rx";
 388                 };
 389
 390                 blsp1_uart2: serial@78b0000 {
 391                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 392                         reg = <0x78b0000 0x200>;
 393                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 394                         status = "disabled";
 395                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
 396                                 <&gcc GCC_BLSP1_AHB_CLK>;
 397                         clock-names = "core", "iface";
 398                         dmas = <&blsp_dma 2>, <&blsp_dma 3>;
 399                         dma-names = "tx", "rx";
 400                 };
 401
 402                 watchdog: watchdog@b017000 {
 403                         compatible = "qcom,kpss-wdt-ipq4019", "qcom,kpss-wdt";
 404                         reg = <0xb017000 0x40>;
 405                         clocks = <&sleep_clk>;
 406                         timeout-sec = <10>;
 407                         status = "disabled";
 408                 };
 409
 410                 restart@4ab000 {
 411                         compatible = "qcom,pshold";
 412                         reg = <0x4ab000 0x4>;
 413                 };
 414
 415                 pcie0: pcie@40000000 {
 416                         compatible = "qcom,pcie-ipq4019";
 417                         reg = <0x40000000 0xf1d>,
 418                               <0x40000f20 0xa8>,
 419                               <0x80000 0x2000>,
 420                               <0x40100000 0x1000>;
 421                         reg-names = "dbi", "elbi", "parf", "config";
 422                         device_type = "pci";
 423                         linux,pci-domain = <0>;
 424                         bus-range = <0x00 0xff>;
 425                         num-lanes = <1>;
 426                         #address-cells = <3>;
 427                         #size-cells = <2>;
 428
 429                         ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>,
 430                                  <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>;
 431
 432                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 433                         interrupt-names = "msi";
 434                         #interrupt-cells = <1>;
 435                         interrupt-map-mask = <0 0 0 0x7>;
 436                         interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 437                                         <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 438                                         <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 439                                         <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 440                         clocks = <&gcc GCC_PCIE_AHB_CLK>,
 441                                  <&gcc GCC_PCIE_AXI_M_CLK>,
 442                                  <&gcc GCC_PCIE_AXI_S_CLK>;
 443                         clock-names = "aux",
 444                                       "master_bus",
 445                                       "slave_bus";
 446
 447                         resets = <&gcc PCIE_AXI_M_ARES>,
 448                                  <&gcc PCIE_AXI_S_ARES>,
 449                                  <&gcc PCIE_PIPE_ARES>,
 450                                  <&gcc PCIE_AXI_M_VMIDMT_ARES>,
 451                                  <&gcc PCIE_AXI_S_XPU_ARES>,
 452                                  <&gcc PCIE_PARF_XPU_ARES>,
 453                                  <&gcc PCIE_PHY_ARES>,
 454                                  <&gcc PCIE_AXI_M_STICKY_ARES>,
 455                                  <&gcc PCIE_PIPE_STICKY_ARES>,
 456                                  <&gcc PCIE_PWR_ARES>,
 457                                  <&gcc PCIE_AHB_ARES>,
 458                                  <&gcc PCIE_PHY_AHB_ARES>;
 459                         reset-names = "axi_m",
 460                                       "axi_s",
 461                                       "pipe",
 462                                       "axi_m_vmid",
 463                                       "axi_s_xpu",
 464                                       "parf",
 465                                       "phy",
 466                                       "axi_m_sticky",
 467                                       "pipe_sticky",
 468                                       "pwr",
 469                                       "ahb",
 470                                       "phy_ahb";
 471
 472                         status = "disabled";
 473                 };
 474
 475                 qpic_bam: dma-controller@7984000 {
 476                         compatible = "qcom,bam-v1.7.0";
 477                         reg = <0x7984000 0x1a000>;
 478                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 479                         clocks = <&gcc GCC_QPIC_CLK>;
 480                         clock-names = "bam_clk";
 481                         #dma-cells = <1>;
 482                         qcom,ee = <0>;
 483                         status = "disabled";
 484                 };
 485
 486                 nand: nand-controller@79b0000 {
 487                         compatible = "qcom,ipq4019-nand";
 488                         reg = <0x79b0000 0x1000>;
 489                         #address-cells = <1>;
 490                         #size-cells = <0>;
 491                         clocks = <&gcc GCC_QPIC_CLK>,
 492                                  <&gcc GCC_QPIC_AHB_CLK>;
 493                         clock-names = "core", "aon";
 494
 495                         dmas = <&qpic_bam 0>,
 496                                <&qpic_bam 1>,
 497                                <&qpic_bam 2>;
 498                         dma-names = "tx", "rx", "cmd";
 499                         status = "disabled";
 500
 501                         nand@0 {
 502                                 reg = <0>;
 503
 504                                 nand-ecc-strength = <4>;
 505                                 nand-ecc-step-size = <512>;
 506                                 nand-bus-width = <8>;
 507                         };
 508                 };
 509
 510                 wifi0: wifi@a000000 {
 511                         compatible = "qcom,ipq4019-wifi";
 512                         reg = <0xa000000 0x200000>;
 513                         resets = <&gcc WIFI0_CPU_INIT_RESET>,
 514                                  <&gcc WIFI0_RADIO_SRIF_RESET>,
 515                                  <&gcc WIFI0_RADIO_WARM_RESET>,
 516                                  <&gcc WIFI0_RADIO_COLD_RESET>,
 517                                  <&gcc WIFI0_CORE_WARM_RESET>,
 518                                  <&gcc WIFI0_CORE_COLD_RESET>;
 519                         reset-names = "wifi_cpu_init", "wifi_radio_srif",
 520                                       "wifi_radio_warm", "wifi_radio_cold",
 521                                       "wifi_core_warm", "wifi_core_cold";
 522                         clocks = <&gcc GCC_WCSS2G_CLK>,
 523                                  <&gcc GCC_WCSS2G_REF_CLK>,
 524                                  <&gcc GCC_WCSS2G_RTC_CLK>;
 525                         clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
 526                                       "wifi_wcss_rtc";
 527                         interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
 528                                      <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
 529                                      <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
 530                                      <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
 531                                      <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
 532                                      <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
 533                                      <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
 534                                      <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
 535                                      <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
 536                                      <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
 537                                      <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
 538                                      <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
 539                                      <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
 540                                      <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
 541                                      <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
 542                                      <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
 543                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 544                         interrupt-names = "msi0",  "msi1",  "msi2",  "msi3",
 545                                           "msi4",  "msi5",  "msi6",  "msi7",
 546                                           "msi8",  "msi9", "msi10", "msi11",
 547                                           "msi12", "msi13", "msi14", "msi15",
 548                                           "legacy";
 549                         status = "disabled";
 550                 };
 551
 552                 wifi1: wifi@a800000 {
 553                         compatible = "qcom,ipq4019-wifi";
 554                         reg = <0xa800000 0x200000>;
 555                         resets = <&gcc WIFI1_CPU_INIT_RESET>,
 556                                  <&gcc WIFI1_RADIO_SRIF_RESET>,
 557                                  <&gcc WIFI1_RADIO_WARM_RESET>,
 558                                  <&gcc WIFI1_RADIO_COLD_RESET>,
 559                                  <&gcc WIFI1_CORE_WARM_RESET>,
 560                                  <&gcc WIFI1_CORE_COLD_RESET>;
 561                         reset-names = "wifi_cpu_init", "wifi_radio_srif",
 562                                       "wifi_radio_warm", "wifi_radio_cold",
 563                                       "wifi_core_warm", "wifi_core_cold";
 564                         clocks = <&gcc GCC_WCSS5G_CLK>,
 565                                  <&gcc GCC_WCSS5G_REF_CLK>,
 566                                  <&gcc GCC_WCSS5G_RTC_CLK>;
 567                         clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
 568                                       "wifi_wcss_rtc";
 569                         interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
 570                                      <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
 571                                      <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
 572                                      <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
 573                                      <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
 574                                      <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
 575                                      <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
 576                                      <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
 577                                      <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
 578                                      <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
 579                                      <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
 580                                      <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
 581                                      <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
 582                                      <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
 583                                      <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
 584                                      <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
 585                                      <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 586                         interrupt-names = "msi0",  "msi1",  "msi2",  "msi3",
 587                                           "msi4",  "msi5",  "msi6",  "msi7",
 588                                           "msi8",  "msi9", "msi10", "msi11",
 589                                           "msi12", "msi13", "msi14", "msi15",
 590                                           "legacy";
 591                         status = "disabled";
 592                 };
 593
 594                 mdio: mdio@90000 {
 595                         #address-cells = <1>;
 596                         #size-cells = <0>;
 597                         compatible = "qcom,ipq4019-mdio";
 598                         reg = <0x90000 0x64>;
 599                         status = "disabled";
 600
 601                         ethphy0: ethernet-phy@0 {
 602                                 reg = <0>;
 603                         };
 604
 605                         ethphy1: ethernet-phy@1 {
 606                                 reg = <1>;
 607                         };
 608
 609                         ethphy2: ethernet-phy@2 {
 610                                 reg = <2>;
 611                         };
 612
 613                         ethphy3: ethernet-phy@3 {
 614                                 reg = <3>;
 615                         };
 616
 617                         ethphy4: ethernet-phy@4 {
 618                                 reg = <4>;
 619                         };
 620                 };
 621
 622                 usb3_ss_phy: usb-phy@9a000 {
 623                         compatible = "qcom,usb-ss-ipq4019-phy";
 624                         #phy-cells = <0>;
 625                         reg = <0x9a000 0x800>;
 626                         reg-names = "phy_base";
 627                         resets = <&gcc USB3_UNIPHY_PHY_ARES>;
 628                         reset-names = "por_rst";
 629                         status = "disabled";
 630                 };
 631
 632                 usb3_hs_phy: usb-phy@a6000 {
 633                         compatible = "qcom,usb-hs-ipq4019-phy";
 634                         #phy-cells = <0>;
 635                         reg = <0xa6000 0x40>;
 636                         reg-names = "phy_base";
 637                         resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
 638                         reset-names = "por_rst", "srif_rst";
 639                         status = "disabled";
 640                 };
 641
 642                 usb3: usb@8af8800 {
 643                         compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
 644                         reg = <0x8af8800 0x100>;
 645                         #address-cells = <1>;
 646                         #size-cells = <1>;
 647                         clocks = <&gcc GCC_USB3_MASTER_CLK>,
 648                                  <&gcc GCC_USB3_SLEEP_CLK>,
 649                                  <&gcc GCC_USB3_MOCK_UTMI_CLK>;
 650                         clock-names = "core", "sleep", "mock_utmi";
 651                         ranges;
 652                         status = "disabled";
 653
 654                         usb3_dwc: usb@8a00000 {
 655                                 compatible = "snps,dwc3";
 656                                 reg = <0x8a00000 0xf8000>;
 657                                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 658                                 phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
 659                                 phy-names = "usb2-phy", "usb3-phy";
 660                                 dr_mode = "host";
 661                         };
 662                 };
 663
 664                 usb2_hs_phy: usb-phy@a8000 {
 665                         compatible = "qcom,usb-hs-ipq4019-phy";
 666                         #phy-cells = <0>;
 667                         reg = <0xa8000 0x40>;
 668                         reg-names = "phy_base";
 669                         resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
 670                         reset-names = "por_rst", "srif_rst";
 671                         status = "disabled";
 672                 };
 673
 674                 usb2: usb@60f8800 {
 675                         compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
 676                         reg = <0x60f8800 0x100>;
 677                         #address-cells = <1>;
 678                         #size-cells = <1>;
 679                         clocks = <&gcc GCC_USB2_MASTER_CLK>,
 680                                  <&gcc GCC_USB2_SLEEP_CLK>,
 681                                  <&gcc GCC_USB2_MOCK_UTMI_CLK>;
 682                         clock-names = "core", "sleep", "mock_utmi";
 683                         ranges;
 684                         status = "disabled";
 685
 686                         usb@6000000 {
 687                                 compatible = "snps,dwc3";
 688                                 reg = <0x6000000 0xf8000>;
 689                                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 690                                 phys = <&usb2_hs_phy>;
 691                                 phy-names = "usb2-phy";
 692                                 dr_mode = "host";
 693                         };
 694                 };
 695         };
 696 };