arch/arm/boot/dts/st/stm32mp131.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
   4  * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
   5  */
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/stm32mp13-clks.h>
   8 #include <dt-bindings/reset/stm32mp13-resets.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a7";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                 };
  23         };
  24
  25         arm-pmu {
  26                 compatible = "arm,cortex-a7-pmu";
  27                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
  28                 interrupt-affinity = <&cpu0>;
  29                 interrupt-parent = <&intc>;
  30         };
  31
  32         firmware {
  33                 optee {
  34                         method = "smc";
  35                         compatible = "linaro,optee-tz";
  36                         interrupt-parent = <&intc>;
  37                         interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
  38                 };
  39
  40                 scmi: scmi {
  41                         compatible = "linaro,scmi-optee";
  42                         #address-cells = <1>;
  43                         #size-cells = <0>;
  44                         linaro,optee-channel-id = <0>;
  45
  46                         scmi_clk: protocol@14 {
  47                                 reg = <0x14>;
  48                                 #clock-cells = <1>;
  49                         };
  50
  51                         scmi_reset: protocol@16 {
  52                                 reg = <0x16>;
  53                                 #reset-cells = <1>;
  54                         };
  55
  56                         scmi_voltd: protocol@17 {
  57                                 reg = <0x17>;
  58
  59                                 scmi_regu: regulators {
  60                                         #address-cells = <1>;
  61                                         #size-cells = <0>;
  62
  63                                         scmi_reg11: regulator@0 {
  64                                                 reg = <VOLTD_SCMI_REG11>;
  65                                                 regulator-name = "reg11";
  66                                         };
  67                                         scmi_reg18: regulator@1 {
  68                                                 reg = <VOLTD_SCMI_REG18>;
  69                                                 regulator-name = "reg18";
  70                                         };
  71                                         scmi_usb33: regulator@2 {
  72                                                 reg = <VOLTD_SCMI_USB33>;
  73                                                 regulator-name = "usb33";
  74                                         };
  75                                 };
  76                         };
  77                 };
  78         };
  79
  80         intc: interrupt-controller@a0021000 {
  81                 compatible = "arm,cortex-a7-gic";
  82                 #interrupt-cells = <3>;
  83                 interrupt-controller;
  84                 reg = <0xa0021000 0x1000>,
  85                       <0xa0022000 0x2000>;
  86         };
  87
  88         psci {
  89                 compatible = "arm,psci-1.0";
  90                 method = "smc";
  91         };
  92
  93         timer {
  94                 compatible = "arm,armv7-timer";
  95                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  96                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  97                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  98                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
  99                 interrupt-parent = <&intc>;
 100                 always-on;
 101         };
 102
 103         soc {
 104                 compatible = "simple-bus";
 105                 #address-cells = <1>;
 106                 #size-cells = <1>;
 107                 interrupt-parent = <&intc>;
 108                 ranges;
 109
 110                 timers2: timer@40000000 {
 111                         #address-cells = <1>;
 112                         #size-cells = <0>;
 113                         compatible = "st,stm32-timers";
 114                         reg = <0x40000000 0x400>;
 115                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 116                         interrupt-names = "global";
 117                         clocks = <&rcc TIM2_K>;
 118                         clock-names = "int";
 119                         dmas = <&dmamux1 18 0x400 0x1>,
 120                                <&dmamux1 19 0x400 0x1>,
 121                                <&dmamux1 20 0x400 0x1>,
 122                                <&dmamux1 21 0x400 0x1>,
 123                                <&dmamux1 22 0x400 0x1>;
 124                         dma-names = "ch1", "ch2", "ch3", "ch4", "up";
 125                         status = "disabled";
 126
 127                         pwm {
 128                                 compatible = "st,stm32-pwm";
 129                                 #pwm-cells = <3>;
 130                                 status = "disabled";
 131                         };
 132
 133                         timer@1 {
 134                                 compatible = "st,stm32h7-timer-trigger";
 135                                 reg = <1>;
 136                                 status = "disabled";
 137                         };
 138
 139                         counter {
 140                                 compatible = "st,stm32-timer-counter";
 141                                 status = "disabled";
 142                         };
 143                 };
 144
 145                 timers3: timer@40001000 {
 146                         #address-cells = <1>;
 147                         #size-cells = <0>;
 148                         compatible = "st,stm32-timers";
 149                         reg = <0x40001000 0x400>;
 150                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 151                         interrupt-names = "global";
 152                         clocks = <&rcc TIM3_K>;
 153                         clock-names = "int";
 154                         dmas = <&dmamux1 23 0x400 0x1>,
 155                                <&dmamux1 24 0x400 0x1>,
 156                                <&dmamux1 25 0x400 0x1>,
 157                                <&dmamux1 26 0x400 0x1>,
 158                                <&dmamux1 27 0x400 0x1>,
 159                                <&dmamux1 28 0x400 0x1>;
 160                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 161                         status = "disabled";
 162
 163                         pwm {
 164                                 compatible = "st,stm32-pwm";
 165                                 #pwm-cells = <3>;
 166                                 status = "disabled";
 167                         };
 168
 169                         timer@2 {
 170                                 compatible = "st,stm32h7-timer-trigger";
 171                                 reg = <2>;
 172                                 status = "disabled";
 173                         };
 174
 175                         counter {
 176                                 compatible = "st,stm32-timer-counter";
 177                                 status = "disabled";
 178                         };
 179                 };
 180
 181                 timers4: timer@40002000 {
 182                         #address-cells = <1>;
 183                         #size-cells = <0>;
 184                         compatible = "st,stm32-timers";
 185                         reg = <0x40002000 0x400>;
 186                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 187                         interrupt-names = "global";
 188                         clocks = <&rcc TIM4_K>;
 189                         clock-names = "int";
 190                         dmas = <&dmamux1 29 0x400 0x1>,
 191                                <&dmamux1 30 0x400 0x1>,
 192                                <&dmamux1 31 0x400 0x1>,
 193                                <&dmamux1 32 0x400 0x1>;
 194                         dma-names = "ch1", "ch2", "ch3", "up";
 195                         status = "disabled";
 196
 197                         pwm {
 198                                 compatible = "st,stm32-pwm";
 199                                 #pwm-cells = <3>;
 200                                 status = "disabled";
 201                         };
 202
 203                         timer@3 {
 204                                 compatible = "st,stm32h7-timer-trigger";
 205                                 reg = <3>;
 206                                 status = "disabled";
 207                         };
 208
 209                         counter {
 210                                 compatible = "st,stm32-timer-counter";
 211                                 status = "disabled";
 212                         };
 213                 };
 214
 215                 timers5: timer@40003000 {
 216                         #address-cells = <1>;
 217                         #size-cells = <0>;
 218                         compatible = "st,stm32-timers";
 219                         reg = <0x40003000 0x400>;
 220                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 221                         interrupt-names = "global";
 222                         clocks = <&rcc TIM5_K>;
 223                         clock-names = "int";
 224                         dmas = <&dmamux1 55 0x400 0x1>,
 225                                <&dmamux1 56 0x400 0x1>,
 226                                <&dmamux1 57 0x400 0x1>,
 227                                <&dmamux1 58 0x400 0x1>,
 228                                <&dmamux1 59 0x400 0x1>,
 229                                <&dmamux1 60 0x400 0x1>;
 230                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 231                         status = "disabled";
 232
 233                         pwm {
 234                                 compatible = "st,stm32-pwm";
 235                                 #pwm-cells = <3>;
 236                                 status = "disabled";
 237                         };
 238
 239                         timer@4 {
 240                                 compatible = "st,stm32h7-timer-trigger";
 241                                 reg = <4>;
 242                                 status = "disabled";
 243                         };
 244
 245                         counter {
 246                                 compatible = "st,stm32-timer-counter";
 247                                 status = "disabled";
 248                         };
 249                 };
 250
 251                 timers6: timer@40004000 {
 252                         #address-cells = <1>;
 253                         #size-cells = <0>;
 254                         compatible = "st,stm32-timers";
 255                         reg = <0x40004000 0x400>;
 256                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 257                         interrupt-names = "global";
 258                         clocks = <&rcc TIM6_K>;
 259                         clock-names = "int";
 260                         dmas = <&dmamux1 69 0x400 0x1>;
 261                         dma-names = "up";
 262                         status = "disabled";
 263
 264                         timer@5 {
 265                                 compatible = "st,stm32h7-timer-trigger";
 266                                 reg = <5>;
 267                                 status = "disabled";
 268                         };
 269                 };
 270
 271                 timers7: timer@40005000 {
 272                         #address-cells = <1>;
 273                         #size-cells = <0>;
 274                         compatible = "st,stm32-timers";
 275                         reg = <0x40005000 0x400>;
 276                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 277                         interrupt-names = "global";
 278                         clocks = <&rcc TIM7_K>;
 279                         clock-names = "int";
 280                         dmas = <&dmamux1 70 0x400 0x1>;
 281                         dma-names = "up";
 282                         status = "disabled";
 283
 284                         timer@6 {
 285                                 compatible = "st,stm32h7-timer-trigger";
 286                                 reg = <6>;
 287                                 status = "disabled";
 288                         };
 289                 };
 290
 291                 lptimer1: timer@40009000 {
 292                         #address-cells = <1>;
 293                         #size-cells = <0>;
 294                         compatible = "st,stm32-lptimer";
 295                         reg = <0x40009000 0x400>;
 296                         interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
 297                         clocks = <&rcc LPTIM1_K>;
 298                         clock-names = "mux";
 299                         wakeup-source;
 300                         status = "disabled";
 301
 302                         pwm {
 303                                 compatible = "st,stm32-pwm-lp";
 304                                 #pwm-cells = <3>;
 305                                 status = "disabled";
 306                         };
 307
 308                         trigger@0 {
 309                                 compatible = "st,stm32-lptimer-trigger";
 310                                 reg = <0>;
 311                                 status = "disabled";
 312                         };
 313
 314                         counter {
 315                                 compatible = "st,stm32-lptimer-counter";
 316                                 status = "disabled";
 317                         };
 318
 319                         timer {
 320                                 compatible = "st,stm32-lptimer-timer";
 321                                 status = "disabled";
 322                         };
 323                 };
 324
 325                 i2s2: audio-controller@4000b000 {
 326                         compatible = "st,stm32h7-i2s";
 327                         reg = <0x4000b000 0x400>;
 328                         #sound-dai-cells = <0>;
 329                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 330                         dmas = <&dmamux1 39 0x400 0x01>,
 331                                <&dmamux1 40 0x400 0x01>;
 332                         dma-names = "rx", "tx";
 333                         status = "disabled";
 334                 };
 335
 336                 spi2: spi@4000b000 {
 337                         compatible = "st,stm32h7-spi";
 338                         reg = <0x4000b000 0x400>;
 339                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 340                         clocks = <&rcc SPI2_K>;
 341                         resets = <&rcc SPI2_R>;
 342                         #address-cells = <1>;
 343                         #size-cells = <0>;
 344                         dmas = <&dmamux1 39 0x400 0x01>,
 345                                <&dmamux1 40 0x400 0x01>;
 346                         dma-names = "rx", "tx";
 347                         status = "disabled";
 348                 };
 349
 350                 i2s3: audio-controller@4000c000 {
 351                         compatible = "st,stm32h7-i2s";
 352                         reg = <0x4000c000 0x400>;
 353                         #sound-dai-cells = <0>;
 354                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 355                         dmas = <&dmamux1 61 0x400 0x01>,
 356                                <&dmamux1 62 0x400 0x01>;
 357                         dma-names = "rx", "tx";
 358                         status = "disabled";
 359                 };
 360
 361                 spi3: spi@4000c000 {
 362                         compatible = "st,stm32h7-spi";
 363                         reg = <0x4000c000 0x400>;
 364                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 365                         clocks = <&rcc SPI3_K>;
 366                         resets = <&rcc SPI3_R>;
 367                         #address-cells = <1>;
 368                         #size-cells = <0>;
 369                         dmas = <&dmamux1 61 0x400 0x01>,
 370                                <&dmamux1 62 0x400 0x01>;
 371                         dma-names = "rx", "tx";
 372                         status = "disabled";
 373                 };
 374
 375                 spdifrx: audio-controller@4000d000 {
 376                         compatible = "st,stm32h7-spdifrx";
 377                         reg = <0x4000d000 0x400>;
 378                         #sound-dai-cells = <0>;
 379                         clocks = <&rcc SPDIF_K>;
 380                         clock-names = "kclk";
 381                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 382                         dmas = <&dmamux1 93 0x400 0x01>,
 383                                <&dmamux1 94 0x400 0x01>;
 384                         dma-names = "rx", "rx-ctrl";
 385                         status = "disabled";
 386                 };
 387
 388                 usart3: serial@4000f000 {
 389                         compatible = "st,stm32h7-uart";
 390                         reg = <0x4000f000 0x400>;
 391                         interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
 392                         clocks = <&rcc USART3_K>;
 393                         resets = <&rcc USART3_R>;
 394                         wakeup-source;
 395                         dmas = <&dmamux1 45 0x400 0x5>,
 396                                <&dmamux1 46 0x400 0x1>;
 397                         dma-names = "rx", "tx";
 398                         status = "disabled";
 399                 };
 400
 401                 uart4: serial@40010000 {
 402                         compatible = "st,stm32h7-uart";
 403                         reg = <0x40010000 0x400>;
 404                         interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
 405                         clocks = <&rcc UART4_K>;
 406                         resets = <&rcc UART4_R>;
 407                         wakeup-source;
 408                         dmas = <&dmamux1 63 0x400 0x5>,
 409                                <&dmamux1 64 0x400 0x1>;
 410                         dma-names = "rx", "tx";
 411                         status = "disabled";
 412                 };
 413
 414                 uart5: serial@40011000 {
 415                         compatible = "st,stm32h7-uart";
 416                         reg = <0x40011000 0x400>;
 417                         interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
 418                         clocks = <&rcc UART5_K>;
 419                         resets = <&rcc UART5_R>;
 420                         wakeup-source;
 421                         dmas = <&dmamux1 65 0x400 0x5>,
 422                                <&dmamux1 66 0x400 0x1>;
 423                         dma-names = "rx", "tx";
 424                         status = "disabled";
 425                 };
 426
 427                 i2c1: i2c@40012000 {
 428                         compatible = "st,stm32mp13-i2c";
 429                         reg = <0x40012000 0x400>;
 430                         interrupt-names = "event", "error";
 431                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 432                                      <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 433                         clocks = <&rcc I2C1_K>;
 434                         resets = <&rcc I2C1_R>;
 435                         #address-cells = <1>;
 436                         #size-cells = <0>;
 437                         dmas = <&dmamux1 33 0x400 0x1>,
 438                                <&dmamux1 34 0x400 0x1>;
 439                         dma-names = "rx", "tx";
 440                         st,syscfg-fmp = <&syscfg 0x4 0x1>;
 441                         i2c-analog-filter;
 442                         status = "disabled";
 443                 };
 444
 445                 i2c2: i2c@40013000 {
 446                         compatible = "st,stm32mp13-i2c";
 447                         reg = <0x40013000 0x400>;
 448                         interrupt-names = "event", "error";
 449                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 450                                      <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 451                         clocks = <&rcc I2C2_K>;
 452                         resets = <&rcc I2C2_R>;
 453                         #address-cells = <1>;
 454                         #size-cells = <0>;
 455                         dmas = <&dmamux1 35 0x400 0x1>,
 456                                <&dmamux1 36 0x400 0x1>;
 457                         dma-names = "rx", "tx";
 458                         st,syscfg-fmp = <&syscfg 0x4 0x2>;
 459                         i2c-analog-filter;
 460                         status = "disabled";
 461                 };
 462
 463                 uart7: serial@40018000 {
 464                         compatible = "st,stm32h7-uart";
 465                         reg = <0x40018000 0x400>;
 466                         interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
 467                         clocks = <&rcc UART7_K>;
 468                         resets = <&rcc UART7_R>;
 469                         wakeup-source;
 470                         dmas = <&dmamux1 79 0x400 0x5>,
 471                                <&dmamux1 80 0x400 0x1>;
 472                         dma-names = "rx", "tx";
 473                         status = "disabled";
 474                 };
 475
 476                 uart8: serial@40019000 {
 477                         compatible = "st,stm32h7-uart";
 478                         reg = <0x40019000 0x400>;
 479                         interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
 480                         clocks = <&rcc UART8_K>;
 481                         resets = <&rcc UART8_R>;
 482                         wakeup-source;
 483                         dmas = <&dmamux1 81 0x400 0x5>,
 484                                <&dmamux1 82 0x400 0x1>;
 485                         dma-names = "rx", "tx";
 486                         status = "disabled";
 487                 };
 488
 489                 timers1: timer@44000000 {
 490                         #address-cells = <1>;
 491                         #size-cells = <0>;
 492                         compatible = "st,stm32-timers";
 493                         reg = <0x44000000 0x400>;
 494                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
 495                                      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 496                                      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 497                                      <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 498                         interrupt-names = "brk", "up", "trg-com", "cc";
 499                         clocks = <&rcc TIM1_K>;
 500                         clock-names = "int";
 501                         dmas = <&dmamux1 11 0x400 0x1>,
 502                                <&dmamux1 12 0x400 0x1>,
 503                                <&dmamux1 13 0x400 0x1>,
 504                                <&dmamux1 14 0x400 0x1>,
 505                                <&dmamux1 15 0x400 0x1>,
 506                                <&dmamux1 16 0x400 0x1>,
 507                                <&dmamux1 17 0x400 0x1>;
 508                         dma-names = "ch1", "ch2", "ch3", "ch4",
 509                                     "up", "trig", "com";
 510                         status = "disabled";
 511
 512                         pwm {
 513                                 compatible = "st,stm32-pwm";
 514                                 #pwm-cells = <3>;
 515                                 status = "disabled";
 516                         };
 517
 518                         timer@0 {
 519                                 compatible = "st,stm32h7-timer-trigger";
 520                                 reg = <0>;
 521                                 status = "disabled";
 522                         };
 523
 524                         counter {
 525                                 compatible = "st,stm32-timer-counter";
 526                                 status = "disabled";
 527                         };
 528                 };
 529
 530                 timers8: timer@44001000 {
 531                         #address-cells = <1>;
 532                         #size-cells = <0>;
 533                         compatible = "st,stm32-timers";
 534                         reg = <0x44001000 0x400>;
 535                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 536                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 537                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 538                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 539                         interrupt-names = "brk", "up", "trg-com", "cc";
 540                         clocks = <&rcc TIM8_K>;
 541                         clock-names = "int";
 542                         dmas = <&dmamux1 47 0x400 0x1>,
 543                                <&dmamux1 48 0x400 0x1>,
 544                                <&dmamux1 49 0x400 0x1>,
 545                                <&dmamux1 50 0x400 0x1>,
 546                                <&dmamux1 51 0x400 0x1>,
 547                                <&dmamux1 52 0x400 0x1>,
 548                                <&dmamux1 53 0x400 0x1>;
 549                         dma-names = "ch1", "ch2", "ch3", "ch4",
 550                                     "up", "trig", "com";
 551                         status = "disabled";
 552
 553                         pwm {
 554                                 compatible = "st,stm32-pwm";
 555                                 #pwm-cells = <3>;
 556                                 status = "disabled";
 557                         };
 558
 559                         timer@7 {
 560                                 compatible = "st,stm32h7-timer-trigger";
 561                                 reg = <7>;
 562                                 status = "disabled";
 563                         };
 564
 565                         counter {
 566                                 compatible = "st,stm32-timer-counter";
 567                                 status = "disabled";
 568                         };
 569                 };
 570
 571                 usart6: serial@44003000 {
 572                         compatible = "st,stm32h7-uart";
 573                         reg = <0x44003000 0x400>;
 574                         interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
 575                         clocks = <&rcc USART6_K>;
 576                         resets = <&rcc USART6_R>;
 577                         wakeup-source;
 578                         dmas = <&dmamux1 71 0x400 0x5>,
 579                                <&dmamux1 72 0x400 0x1>;
 580                         dma-names = "rx", "tx";
 581                         status = "disabled";
 582                 };
 583
 584                 i2s1: audio-controller@44004000 {
 585                         compatible = "st,stm32h7-i2s";
 586                         reg = <0x44004000 0x400>;
 587                         #sound-dai-cells = <0>;
 588                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 589                         dmas = <&dmamux1 37 0x400 0x01>,
 590                                <&dmamux1 38 0x400 0x01>;
 591                         dma-names = "rx", "tx";
 592                         status = "disabled";
 593                 };
 594
 595                 spi1: spi@44004000 {
 596                         compatible = "st,stm32h7-spi";
 597                         reg = <0x44004000 0x400>;
 598                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 599                         clocks = <&rcc SPI1_K>;
 600                         resets = <&rcc SPI1_R>;
 601                         #address-cells = <1>;
 602                         #size-cells = <0>;
 603                         dmas = <&dmamux1 37 0x400 0x01>,
 604                                <&dmamux1 38 0x400 0x01>;
 605                         dma-names = "rx", "tx";
 606                         status = "disabled";
 607                 };
 608
 609                 sai1: sai@4400a000 {
 610                         compatible = "st,stm32h7-sai";
 611                         reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
 612                         ranges = <0 0x4400a000 0x400>;
 613                         #address-cells = <1>;
 614                         #size-cells = <1>;
 615                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 616                         resets = <&rcc SAI1_R>;
 617                         status = "disabled";
 618
 619                         sai1a: audio-controller@4400a004 {
 620                                 compatible = "st,stm32-sai-sub-a";
 621                                 reg = <0x4 0x20>;
 622                                 #sound-dai-cells = <0>;
 623                                 clocks = <&rcc SAI1_K>;
 624                                 clock-names = "sai_ck";
 625                                 dmas = <&dmamux1 87 0x400 0x01>;
 626                                 status = "disabled";
 627                         };
 628
 629                         sai1b: audio-controller@4400a024 {
 630                                 compatible = "st,stm32-sai-sub-b";
 631                                 reg = <0x24 0x20>;
 632                                 #sound-dai-cells = <0>;
 633                                 clocks = <&rcc SAI1_K>;
 634                                 clock-names = "sai_ck";
 635                                 dmas = <&dmamux1 88 0x400 0x01>;
 636                                 status = "disabled";
 637                         };
 638                 };
 639
 640                 sai2: sai@4400b000 {
 641                         compatible = "st,stm32h7-sai";
 642                         reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
 643                         ranges = <0 0x4400b000 0x400>;
 644                         #address-cells = <1>;
 645                         #size-cells = <1>;
 646                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 647                         resets = <&rcc SAI2_R>;
 648                         status = "disabled";
 649
 650                         sai2a: audio-controller@4400b004 {
 651                                 compatible = "st,stm32-sai-sub-a";
 652                                 reg = <0x4 0x20>;
 653                                 #sound-dai-cells = <0>;
 654                                 clocks = <&rcc SAI2_K>;
 655                                 clock-names = "sai_ck";
 656                                 dmas = <&dmamux1 89 0x400 0x01>;
 657                                 status = "disabled";
 658                         };
 659
 660                         sai2b: audio-controller@4400b024 {
 661                                 compatible = "st,stm32-sai-sub-b";
 662                                 reg = <0x24 0x20>;
 663                                 #sound-dai-cells = <0>;
 664                                 clocks = <&rcc SAI2_K>;
 665                                 clock-names = "sai_ck";
 666                                 dmas = <&dmamux1 90 0x400 0x01>;
 667                                 status = "disabled";
 668                         };
 669                 };
 670
 671                 dfsdm: dfsdm@4400d000 {
 672                         compatible = "st,stm32mp1-dfsdm";
 673                         reg = <0x4400d000 0x800>;
 674                         clocks = <&rcc DFSDM_K>;
 675                         clock-names = "dfsdm";
 676                         #address-cells = <1>;
 677                         #size-cells = <0>;
 678                         status = "disabled";
 679
 680                         dfsdm0: filter@0 {
 681                                 compatible = "st,stm32-dfsdm-adc";
 682                                 reg = <0>;
 683                                 #io-channel-cells = <1>;
 684                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 685                                 dmas = <&dmamux1 101 0x400 0x01>;
 686                                 dma-names = "rx";
 687                                 status = "disabled";
 688                         };
 689
 690                         dfsdm1: filter@1 {
 691                                 compatible = "st,stm32-dfsdm-adc";
 692                                 reg = <1>;
 693                                 #io-channel-cells = <1>;
 694                                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 695                                 dmas = <&dmamux1 102 0x400 0x01>;
 696                                 dma-names = "rx";
 697                                 status = "disabled";
 698                         };
 699                 };
 700
 701                 dma1: dma-controller@48000000 {
 702                         compatible = "st,stm32-dma";
 703                         reg = <0x48000000 0x400>;
 704                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 705                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 706                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 707                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 708                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 709                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 710                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 711                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 712                         clocks = <&rcc DMA1>;
 713                         resets = <&rcc DMA1_R>;
 714                         #dma-cells = <4>;
 715                         st,mem2mem;
 716                         dma-requests = <8>;
 717                 };
 718
 719                 dma2: dma-controller@48001000 {
 720                         compatible = "st,stm32-dma";
 721                         reg = <0x48001000 0x400>;
 722                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 723                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 724                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 725                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 726                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 727                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 728                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 729                                      <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 730                         clocks = <&rcc DMA2>;
 731                         resets = <&rcc DMA2_R>;
 732                         #dma-cells = <4>;
 733                         st,mem2mem;
 734                         dma-requests = <8>;
 735                 };
 736
 737                 dmamux1: dma-router@48002000 {
 738                         compatible = "st,stm32h7-dmamux";
 739                         reg = <0x48002000 0x40>;
 740                         clocks = <&rcc DMAMUX1>;
 741                         resets = <&rcc DMAMUX1_R>;
 742                         #dma-cells = <3>;
 743                         dma-masters = <&dma1 &dma2>;
 744                         dma-requests = <128>;
 745                         dma-channels = <16>;
 746                 };
 747
 748                 adc_2: adc@48004000 {
 749                         compatible = "st,stm32mp13-adc-core";
 750                         reg = <0x48004000 0x400>;
 751                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 752                         clocks = <&rcc ADC2>, <&rcc ADC2_K>;
 753                         clock-names = "bus", "adc";
 754                         interrupt-controller;
 755                         #interrupt-cells = <1>;
 756                         #address-cells = <1>;
 757                         #size-cells = <0>;
 758                         status = "disabled";
 759
 760                         adc2: adc@0 {
 761                                 compatible = "st,stm32mp13-adc";
 762                                 #io-channel-cells = <1>;
 763                                 #address-cells = <1>;
 764                                 #size-cells = <0>;
 765                                 reg = <0x0>;
 766                                 interrupt-parent = <&adc_2>;
 767                                 interrupts = <0>;
 768                                 dmas = <&dmamux1 10 0x400 0x80000001>;
 769                                 dma-names = "rx";
 770                                 status = "disabled";
 771
 772                                 channel@13 {
 773                                         reg = <13>;
 774                                         label = "vrefint";
 775                                 };
 776                                 channel@14 {
 777                                         reg = <14>;
 778                                         label = "vddcore";
 779                                 };
 780                                 channel@16 {
 781                                         reg = <16>;
 782                                         label = "vddcpu";
 783                                 };
 784                                 channel@17 {
 785                                         reg = <17>;
 786                                         label = "vddq_ddr";
 787                                 };
 788                         };
 789                 };
 790
 791                 usbotg_hs: usb@49000000 {
 792                         compatible = "st,stm32mp15-hsotg", "snps,dwc2";
 793                         reg = <0x49000000 0x40000>;
 794                         clocks = <&rcc USBO_K>;
 795                         clock-names = "otg";
 796                         resets = <&rcc USBO_R>;
 797                         reset-names = "dwc2";
 798                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 799                         g-rx-fifo-size = <512>;
 800                         g-np-tx-fifo-size = <32>;
 801                         g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
 802                         dr_mode = "otg";
 803                         otg-rev = <0x200>;
 804                         usb33d-supply = <&scmi_usb33>;
 805                         status = "disabled";
 806                 };
 807
 808                 usart1: serial@4c000000 {
 809                         compatible = "st,stm32h7-uart";
 810                         reg = <0x4c000000 0x400>;
 811                         interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
 812                         clocks = <&rcc USART1_K>;
 813                         resets = <&rcc USART1_R>;
 814                         wakeup-source;
 815                         dmas = <&dmamux1 41 0x400 0x5>,
 816                                <&dmamux1 42 0x400 0x1>;
 817                         dma-names = "rx", "tx";
 818                         status = "disabled";
 819                 };
 820
 821                 usart2: serial@4c001000 {
 822                         compatible = "st,stm32h7-uart";
 823                         reg = <0x4c001000 0x400>;
 824                         interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
 825                         clocks = <&rcc USART2_K>;
 826                         resets = <&rcc USART2_R>;
 827                         wakeup-source;
 828                         dmas = <&dmamux1 43 0x400 0x5>,
 829                                <&dmamux1 44 0x400 0x1>;
 830                         dma-names = "rx", "tx";
 831                         status = "disabled";
 832                 };
 833
 834                 i2s4: audio-controller@4c002000 {
 835                         compatible = "st,stm32h7-i2s";
 836                         reg = <0x4c002000 0x400>;
 837                         #sound-dai-cells = <0>;
 838                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 839                         dmas = <&dmamux1 83 0x400 0x01>,
 840                                <&dmamux1 84 0x400 0x01>;
 841                         dma-names = "rx", "tx";
 842                         status = "disabled";
 843                 };
 844
 845                 spi4: spi@4c002000 {
 846                         compatible = "st,stm32h7-spi";
 847                         reg = <0x4c002000 0x400>;
 848                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 849                         clocks = <&rcc SPI4_K>;
 850                         resets = <&rcc SPI4_R>;
 851                         #address-cells = <1>;
 852                         #size-cells = <0>;
 853                         dmas = <&dmamux1 83 0x400 0x01>,
 854                                <&dmamux1 84 0x400 0x01>;
 855                         dma-names = "rx", "tx";
 856                         status = "disabled";
 857                 };
 858
 859                 spi5: spi@4c003000 {
 860                         compatible = "st,stm32h7-spi";
 861                         reg = <0x4c003000 0x400>;
 862                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 863                         clocks = <&rcc SPI5_K>;
 864                         resets = <&rcc SPI5_R>;
 865                         #address-cells = <1>;
 866                         #size-cells = <0>;
 867                         dmas = <&dmamux1 85 0x400 0x01>,
 868                                <&dmamux1 86 0x400 0x01>;
 869                         dma-names = "rx", "tx";
 870                         status = "disabled";
 871                 };
 872
 873                 i2c3: i2c@4c004000 {
 874                         compatible = "st,stm32mp13-i2c";
 875                         reg = <0x4c004000 0x400>;
 876                         interrupt-names = "event", "error";
 877                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 878                                      <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 879                         clocks = <&rcc I2C3_K>;
 880                         resets = <&rcc I2C3_R>;
 881                         #address-cells = <1>;
 882                         #size-cells = <0>;
 883                         dmas = <&dmamux1 73 0x400 0x1>,
 884                                <&dmamux1 74 0x400 0x1>;
 885                         dma-names = "rx", "tx";
 886                         st,syscfg-fmp = <&syscfg 0x4 0x4>;
 887                         i2c-analog-filter;
 888                         status = "disabled";
 889                 };
 890
 891                 i2c4: i2c@4c005000 {
 892                         compatible = "st,stm32mp13-i2c";
 893                         reg = <0x4c005000 0x400>;
 894                         interrupt-names = "event", "error";
 895                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 896                                      <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 897                         clocks = <&rcc I2C4_K>;
 898                         resets = <&rcc I2C4_R>;
 899                         #address-cells = <1>;
 900                         #size-cells = <0>;
 901                         dmas = <&dmamux1 75 0x400 0x1>,
 902                                <&dmamux1 76 0x400 0x1>;
 903                         dma-names = "rx", "tx";
 904                         st,syscfg-fmp = <&syscfg 0x4 0x8>;
 905                         i2c-analog-filter;
 906                         status = "disabled";
 907                 };
 908
 909                 i2c5: i2c@4c006000 {
 910                         compatible = "st,stm32mp13-i2c";
 911                         reg = <0x4c006000 0x400>;
 912                         interrupt-names = "event", "error";
 913                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 914                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 915                         clocks = <&rcc I2C5_K>;
 916                         resets = <&rcc I2C5_R>;
 917                         #address-cells = <1>;
 918                         #size-cells = <0>;
 919                         dmas = <&dmamux1 115 0x400 0x1>,
 920                                <&dmamux1 116 0x400 0x1>;
 921                         dma-names = "rx", "tx";
 922                         st,syscfg-fmp = <&syscfg 0x4 0x10>;
 923                         i2c-analog-filter;
 924                         status = "disabled";
 925                 };
 926
 927                 timers12: timer@4c007000 {
 928                         #address-cells = <1>;
 929                         #size-cells = <0>;
 930                         compatible = "st,stm32-timers";
 931                         reg = <0x4c007000 0x400>;
 932                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 933                         interrupt-names = "global";
 934                         clocks = <&rcc TIM12_K>;
 935                         clock-names = "int";
 936                         status = "disabled";
 937
 938                         pwm {
 939                                 compatible = "st,stm32-pwm";
 940                                 #pwm-cells = <3>;
 941                                 status = "disabled";
 942                         };
 943
 944                         timer@11 {
 945                                 compatible = "st,stm32h7-timer-trigger";
 946                                 reg = <11>;
 947                                 status = "disabled";
 948                         };
 949                 };
 950
 951                 timers13: timer@4c008000 {
 952                         #address-cells = <1>;
 953                         #size-cells = <0>;
 954                         compatible = "st,stm32-timers";
 955                         reg = <0x4c008000 0x400>;
 956                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 957                         interrupt-names = "global";
 958                         clocks = <&rcc TIM13_K>;
 959                         clock-names = "int";
 960                         status = "disabled";
 961
 962                         pwm {
 963                                 compatible = "st,stm32-pwm";
 964                                 #pwm-cells = <3>;
 965                                 status = "disabled";
 966                         };
 967
 968                         timer@12 {
 969                                 compatible = "st,stm32h7-timer-trigger";
 970                                 reg = <12>;
 971                                 status = "disabled";
 972                         };
 973                 };
 974
 975                 timers14: timer@4c009000 {
 976                         #address-cells = <1>;
 977                         #size-cells = <0>;
 978                         compatible = "st,stm32-timers";
 979                         reg = <0x4c009000 0x400>;
 980                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 981                         interrupt-names = "global";
 982                         clocks = <&rcc TIM14_K>;
 983                         clock-names = "int";
 984                         status = "disabled";
 985
 986                         pwm {
 987                                 compatible = "st,stm32-pwm";
 988                                 #pwm-cells = <3>;
 989                                 status = "disabled";
 990                         };
 991
 992                         timer@13 {
 993                                 compatible = "st,stm32h7-timer-trigger";
 994                                 reg = <13>;
 995                                 status = "disabled";
 996                         };
 997                 };
 998
 999                 timers15: timer@4c00a000 {
1000                         #address-cells = <1>;
1001                         #size-cells = <0>;
1002                         compatible = "st,stm32-timers";
1003                         reg = <0x4c00a000 0x400>;
1004                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1005                         interrupt-names = "global";
1006                         clocks = <&rcc TIM15_K>;
1007                         clock-names = "int";
1008                         dmas = <&dmamux1 105 0x400 0x1>,
1009                                <&dmamux1 106 0x400 0x1>,
1010                                <&dmamux1 107 0x400 0x1>,
1011                                <&dmamux1 108 0x400 0x1>;
1012                         dma-names = "ch1", "up", "trig", "com";
1013                         status = "disabled";
1014
1015                         pwm {
1016                                 compatible = "st,stm32-pwm";
1017                                 #pwm-cells = <3>;
1018                                 status = "disabled";
1019                         };
1020
1021                         timer@14 {
1022                                 compatible = "st,stm32h7-timer-trigger";
1023                                 reg = <14>;
1024                                 status = "disabled";
1025                         };
1026                 };
1027
1028                 timers16: timer@4c00b000 {
1029                         #address-cells = <1>;
1030                         #size-cells = <0>;
1031                         compatible = "st,stm32-timers";
1032                         reg = <0x4c00b000 0x400>;
1033                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1034                         interrupt-names = "global";
1035                         clocks = <&rcc TIM16_K>;
1036                         clock-names = "int";
1037                         dmas = <&dmamux1 109 0x400 0x1>,
1038                                <&dmamux1 110 0x400 0x1>;
1039                         dma-names = "ch1", "up";
1040                         status = "disabled";
1041
1042                         pwm {
1043                                 compatible = "st,stm32-pwm";
1044                                 #pwm-cells = <3>;
1045                                 status = "disabled";
1046                         };
1047
1048                         timer@15 {
1049                                 compatible = "st,stm32h7-timer-trigger";
1050                                 reg = <15>;
1051                                 status = "disabled";
1052                         };
1053                 };
1054
1055                 timers17: timer@4c00c000 {
1056                         #address-cells = <1>;
1057                         #size-cells = <0>;
1058                         compatible = "st,stm32-timers";
1059                         reg = <0x4c00c000 0x400>;
1060                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1061                         interrupt-names = "global";
1062                         clocks = <&rcc TIM17_K>;
1063                         clock-names = "int";
1064                         dmas = <&dmamux1 111 0x400 0x1>,
1065                                <&dmamux1 112 0x400 0x1>;
1066                         dma-names = "ch1", "up";
1067                         status = "disabled";
1068
1069                         pwm {
1070                                 compatible = "st,stm32-pwm";
1071                                 #pwm-cells = <3>;
1072                                 status = "disabled";
1073                         };
1074
1075                         timer@16 {
1076                                 compatible = "st,stm32h7-timer-trigger";
1077                                 reg = <16>;
1078                                 status = "disabled";
1079                         };
1080                 };
1081
1082                 rcc: rcc@50000000 {
1083                         compatible = "st,stm32mp13-rcc", "syscon";
1084                         reg = <0x50000000 0x1000>;
1085                         #clock-cells = <1>;
1086                         #reset-cells = <1>;
1087                         clock-names = "hse", "hsi", "csi", "lse", "lsi";
1088                         clocks = <&scmi_clk CK_SCMI_HSE>,
1089                                  <&scmi_clk CK_SCMI_HSI>,
1090                                  <&scmi_clk CK_SCMI_CSI>,
1091                                  <&scmi_clk CK_SCMI_LSE>,
1092                                  <&scmi_clk CK_SCMI_LSI>;
1093                 };
1094
1095                 exti: interrupt-controller@5000d000 {
1096                         compatible = "st,stm32mp13-exti", "syscon";
1097                         interrupt-controller;
1098                         #interrupt-cells = <2>;
1099                         reg = <0x5000d000 0x400>;
1100                 };
1101
1102                 syscfg: syscon@50020000 {
1103                         compatible = "st,stm32mp157-syscfg", "syscon";
1104                         reg = <0x50020000 0x400>;
1105                         clocks = <&rcc SYSCFG>;
1106                 };
1107
1108                 lptimer2: timer@50021000 {
1109                         #address-cells = <1>;
1110                         #size-cells = <0>;
1111                         compatible = "st,stm32-lptimer";
1112                         reg = <0x50021000 0x400>;
1113                         interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
1114                         clocks = <&rcc LPTIM2_K>;
1115                         clock-names = "mux";
1116                         wakeup-source;
1117                         status = "disabled";
1118
1119                         pwm {
1120                                 compatible = "st,stm32-pwm-lp";
1121                                 #pwm-cells = <3>;
1122                                 status = "disabled";
1123                         };
1124
1125                         trigger@1 {
1126                                 compatible = "st,stm32-lptimer-trigger";
1127                                 reg = <1>;
1128                                 status = "disabled";
1129                         };
1130
1131                         counter {
1132                                 compatible = "st,stm32-lptimer-counter";
1133                                 status = "disabled";
1134                         };
1135
1136                         timer {
1137                                 compatible = "st,stm32-lptimer-timer";
1138                                 status = "disabled";
1139                         };
1140                 };
1141
1142                 lptimer3: timer@50022000 {
1143                         #address-cells = <1>;
1144                         #size-cells = <0>;
1145                         compatible = "st,stm32-lptimer";
1146                         reg = <0x50022000 0x400>;
1147                         interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
1148                         clocks = <&rcc LPTIM3_K>;
1149                         clock-names = "mux";
1150                         wakeup-source;
1151                         status = "disabled";
1152
1153                         pwm {
1154                                 compatible = "st,stm32-pwm-lp";
1155                                 #pwm-cells = <3>;
1156                                 status = "disabled";
1157                         };
1158
1159                         trigger@2 {
1160                                 compatible = "st,stm32-lptimer-trigger";
1161                                 reg = <2>;
1162                                 status = "disabled";
1163                         };
1164
1165                         timer {
1166                                 compatible = "st,stm32-lptimer-timer";
1167                                 status = "disabled";
1168                         };
1169                 };
1170
1171                 lptimer4: timer@50023000 {
1172                         compatible = "st,stm32-lptimer";
1173                         reg = <0x50023000 0x400>;
1174                         interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
1175                         clocks = <&rcc LPTIM4_K>;
1176                         clock-names = "mux";
1177                         wakeup-source;
1178                         status = "disabled";
1179
1180                         pwm {
1181                                 compatible = "st,stm32-pwm-lp";
1182                                 #pwm-cells = <3>;
1183                                 status = "disabled";
1184                         };
1185
1186                         timer {
1187                                 compatible = "st,stm32-lptimer-timer";
1188                                 status = "disabled";
1189                         };
1190                 };
1191
1192                 lptimer5: timer@50024000 {
1193                         compatible = "st,stm32-lptimer";
1194                         reg = <0x50024000 0x400>;
1195                         interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
1196                         clocks = <&rcc LPTIM5_K>;
1197                         clock-names = "mux";
1198                         wakeup-source;
1199                         status = "disabled";
1200
1201                         pwm {
1202                                 compatible = "st,stm32-pwm-lp";
1203                                 #pwm-cells = <3>;
1204                                 status = "disabled";
1205                         };
1206
1207                         timer {
1208                                 compatible = "st,stm32-lptimer-timer";
1209                                 status = "disabled";
1210                         };
1211                 };
1212
1213                 hash: hash@54003000 {
1214                         compatible = "st,stm32mp13-hash";
1215                         reg = <0x54003000 0x400>;
1216                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1217                         clocks = <&rcc HASH1>;
1218                         resets = <&rcc HASH1_R>;
1219                         dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>;
1220                         dma-names = "in";
1221                         status = "disabled";
1222                 };
1223
1224                 rng: rng@54004000 {
1225                         compatible = "st,stm32mp13-rng";
1226                         reg = <0x54004000 0x400>;
1227                         clocks = <&rcc RNG1_K>;
1228                         resets = <&rcc RNG1_R>;
1229                         status = "disabled";
1230                 };
1231
1232                 mdma: dma-controller@58000000 {
1233                         compatible = "st,stm32h7-mdma";
1234                         reg = <0x58000000 0x1000>;
1235                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1236                         clocks = <&rcc MDMA>;
1237                         #dma-cells = <5>;
1238                         dma-channels = <32>;
1239                         dma-requests = <48>;
1240                 };
1241
1242                 fmc: memory-controller@58002000 {
1243                         compatible = "st,stm32mp1-fmc2-ebi";
1244                         reg = <0x58002000 0x1000>;
1245                         ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1246                                  <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1247                                  <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1248                                  <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1249                                  <4 0 0x80000000 0x10000000>; /* NAND */
1250                         #address-cells = <2>;
1251                         #size-cells = <1>;
1252                         clocks = <&rcc FMC_K>;
1253                         resets = <&rcc FMC_R>;
1254                         status = "disabled";
1255
1256                         nand-controller@4,0 {
1257                                 compatible = "st,stm32mp1-fmc2-nfc";
1258                                 reg = <4 0x00000000 0x1000>,
1259                                       <4 0x08010000 0x1000>,
1260                                       <4 0x08020000 0x1000>,
1261                                       <4 0x01000000 0x1000>,
1262                                       <4 0x09010000 0x1000>,
1263                                       <4 0x09020000 0x1000>;
1264                                 #address-cells = <1>;
1265                                 #size-cells = <0>;
1266                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1267                                 dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>,
1268                                        <&mdma 24 0x2 0x12000a08 0x0 0x0>,
1269                                        <&mdma 25 0x2 0x12000a0a 0x0 0x0>;
1270                                 dma-names = "tx", "rx", "ecc";
1271                                 status = "disabled";
1272                         };
1273                 };
1274
1275                 qspi: spi@58003000 {
1276                         compatible = "st,stm32f469-qspi";
1277                         reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1278                         reg-names = "qspi", "qspi_mm";
1279                         #address-cells = <1>;
1280                         #size-cells = <0>;
1281                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1282                         dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>,
1283                                <&mdma 26 0x2 0x10100008 0x0 0x0>;
1284                         dma-names = "tx", "rx";
1285                         clocks = <&rcc QSPI_K>;
1286                         resets = <&rcc QSPI_R>;
1287                         status = "disabled";
1288                 };
1289
1290                 sdmmc1: mmc@58005000 {
1291                         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1292                         arm,primecell-periphid = <0x20253180>;
1293                         reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
1294                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1295                         clocks = <&rcc SDMMC1_K>;
1296                         clock-names = "apb_pclk";
1297                         resets = <&rcc SDMMC1_R>;
1298                         cap-sd-highspeed;
1299                         cap-mmc-highspeed;
1300                         max-frequency = <130000000>;
1301                         status = "disabled";
1302                 };
1303
1304                 sdmmc2: mmc@58007000 {
1305                         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1306                         arm,primecell-periphid = <0x20253180>;
1307                         reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
1308                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1309                         clocks = <&rcc SDMMC2_K>;
1310                         clock-names = "apb_pclk";
1311                         resets = <&rcc SDMMC2_R>;
1312                         cap-sd-highspeed;
1313                         cap-mmc-highspeed;
1314                         max-frequency = <130000000>;
1315                         status = "disabled";
1316                 };
1317
1318                 crc1: crc@58009000 {
1319                         compatible = "st,stm32f7-crc";
1320                         reg = <0x58009000 0x400>;
1321                         clocks = <&rcc CRC1>;
1322                         status = "disabled";
1323                 };
1324
1325                 usbh_ohci: usb@5800c000 {
1326                         compatible = "generic-ohci";
1327                         reg = <0x5800c000 0x1000>;
1328                         clocks = <&usbphyc>, <&rcc USBH>;
1329                         resets = <&rcc USBH_R>;
1330                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1331                         status = "disabled";
1332                 };
1333
1334                 usbh_ehci: usb@5800d000 {
1335                         compatible = "generic-ehci";
1336                         reg = <0x5800d000 0x1000>;
1337                         clocks = <&usbphyc>, <&rcc USBH>;
1338                         resets = <&rcc USBH_R>;
1339                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1340                         companion = <&usbh_ohci>;
1341                         status = "disabled";
1342                 };
1343
1344                 iwdg2: watchdog@5a002000 {
1345                         compatible = "st,stm32mp1-iwdg";
1346                         reg = <0x5a002000 0x400>;
1347                         clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
1348                         clock-names = "pclk", "lsi";
1349                         status = "disabled";
1350                 };
1351
1352                 usbphyc: usbphyc@5a006000 {
1353                         #address-cells = <1>;
1354                         #size-cells = <0>;
1355                         #clock-cells = <0>;
1356                         compatible = "st,stm32mp1-usbphyc";
1357                         reg = <0x5a006000 0x1000>;
1358                         clocks = <&rcc USBPHY_K>;
1359                         resets = <&rcc USBPHY_R>;
1360                         vdda1v1-supply = <&scmi_reg11>;
1361                         vdda1v8-supply = <&scmi_reg18>;
1362                         status = "disabled";
1363
1364                         usbphyc_port0: usb-phy@0 {
1365                                 #phy-cells = <0>;
1366                                 reg = <0>;
1367                         };
1368
1369                         usbphyc_port1: usb-phy@1 {
1370                                 #phy-cells = <1>;
1371                                 reg = <1>;
1372                         };
1373                 };
1374
1375                 rtc: rtc@5c004000 {
1376                         compatible = "st,stm32mp1-rtc";
1377                         reg = <0x5c004000 0x400>;
1378                         interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
1379                         clocks = <&scmi_clk CK_SCMI_RTCAPB>,
1380                                  <&scmi_clk CK_SCMI_RTC>;
1381                         clock-names = "pclk", "rtc_ck";
1382                         status = "disabled";
1383                 };
1384
1385                 bsec: efuse@5c005000 {
1386                         compatible = "st,stm32mp13-bsec";
1387                         reg = <0x5c005000 0x400>;
1388                         #address-cells = <1>;
1389                         #size-cells = <1>;
1390
1391                         part_number_otp: part_number_otp@4 {
1392                                 reg = <0x4 0x2>;
1393                                 bits = <0 12>;
1394                         };
1395                         ts_cal1: calib@5c {
1396                                 reg = <0x5c 0x2>;
1397                         };
1398                         ts_cal2: calib@5e {
1399                                 reg = <0x5e 0x2>;
1400                         };
1401                 };
1402
1403                 /*
1404                  * Break node order to solve dependency probe issue between
1405                  * pinctrl and exti.
1406                  */
1407                 pinctrl: pinctrl@50002000 {
1408                         #address-cells = <1>;
1409                         #size-cells = <1>;
1410                         compatible = "st,stm32mp135-pinctrl";
1411                         ranges = <0 0x50002000 0x8400>;
1412                         interrupt-parent = <&exti>;
1413                         st,syscfg = <&exti 0x60 0xff>;
1414
1415                         gpioa: gpio@50002000 {
1416                                 gpio-controller;
1417                                 #gpio-cells = <2>;
1418                                 interrupt-controller;
1419                                 #interrupt-cells = <2>;
1420                                 reg = <0x0 0x400>;
1421                                 clocks = <&rcc GPIOA>;
1422                                 st,bank-name = "GPIOA";
1423                                 ngpios = <16>;
1424                                 gpio-ranges = <&pinctrl 0 0 16>;
1425                         };
1426
1427                         gpiob: gpio@50003000 {
1428                                 gpio-controller;
1429                                 #gpio-cells = <2>;
1430                                 interrupt-controller;
1431                                 #interrupt-cells = <2>;
1432                                 reg = <0x1000 0x400>;
1433                                 clocks = <&rcc GPIOB>;
1434                                 st,bank-name = "GPIOB";
1435                                 ngpios = <16>;
1436                                 gpio-ranges = <&pinctrl 0 16 16>;
1437                         };
1438
1439                         gpioc: gpio@50004000 {
1440                                 gpio-controller;
1441                                 #gpio-cells = <2>;
1442                                 interrupt-controller;
1443                                 #interrupt-cells = <2>;
1444                                 reg = <0x2000 0x400>;
1445                                 clocks = <&rcc GPIOC>;
1446                                 st,bank-name = "GPIOC";
1447                                 ngpios = <16>;
1448                                 gpio-ranges = <&pinctrl 0 32 16>;
1449                         };
1450
1451                         gpiod: gpio@50005000 {
1452                                 gpio-controller;
1453                                 #gpio-cells = <2>;
1454                                 interrupt-controller;
1455                                 #interrupt-cells = <2>;
1456                                 reg = <0x3000 0x400>;
1457                                 clocks = <&rcc GPIOD>;
1458                                 st,bank-name = "GPIOD";
1459                                 ngpios = <16>;
1460                                 gpio-ranges = <&pinctrl 0 48 16>;
1461                         };
1462
1463                         gpioe: gpio@50006000 {
1464                                 gpio-controller;
1465                                 #gpio-cells = <2>;
1466                                 interrupt-controller;
1467                                 #interrupt-cells = <2>;
1468                                 reg = <0x4000 0x400>;
1469                                 clocks = <&rcc GPIOE>;
1470                                 st,bank-name = "GPIOE";
1471                                 ngpios = <16>;
1472                                 gpio-ranges = <&pinctrl 0 64 16>;
1473                         };
1474
1475                         gpiof: gpio@50007000 {
1476                                 gpio-controller;
1477                                 #gpio-cells = <2>;
1478                                 interrupt-controller;
1479                                 #interrupt-cells = <2>;
1480                                 reg = <0x5000 0x400>;
1481                                 clocks = <&rcc GPIOF>;
1482                                 st,bank-name = "GPIOF";
1483                                 ngpios = <16>;
1484                                 gpio-ranges = <&pinctrl 0 80 16>;
1485                         };
1486
1487                         gpiog: gpio@50008000 {
1488                                 gpio-controller;
1489                                 #gpio-cells = <2>;
1490                                 interrupt-controller;
1491                                 #interrupt-cells = <2>;
1492                                 reg = <0x6000 0x400>;
1493                                 clocks = <&rcc GPIOG>;
1494                                 st,bank-name = "GPIOG";
1495                                 ngpios = <16>;
1496                                 gpio-ranges = <&pinctrl 0 96 16>;
1497                         };
1498
1499                         gpioh: gpio@50009000 {
1500                                 gpio-controller;
1501                                 #gpio-cells = <2>;
1502                                 interrupt-controller;
1503                                 #interrupt-cells = <2>;
1504                                 reg = <0x7000 0x400>;
1505                                 clocks = <&rcc GPIOH>;
1506                                 st,bank-name = "GPIOH";
1507                                 ngpios = <15>;
1508                                 gpio-ranges = <&pinctrl 0 112 15>;
1509                         };
1510
1511                         gpioi: gpio@5000a000 {
1512                                 gpio-controller;
1513                                 #gpio-cells = <2>;
1514                                 interrupt-controller;
1515                                 #interrupt-cells = <2>;
1516                                 reg = <0x8000 0x400>;
1517                                 clocks = <&rcc GPIOI>;
1518                                 st,bank-name = "GPIOI";
1519                                 ngpios = <8>;
1520                                 gpio-ranges = <&pinctrl 0 128 8>;
1521                         };
1522                 };
1523         };
1524 };