arch/arm64/boot/dts/apm/apm-storm.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * dts file for AppliedMicro (APM) X-Gene Storm SOC
   4  *
   5  * Copyright (C) 2013, Applied Micro Circuits Corporation
   6  */
   7
   8 / {
   9         compatible = "apm,xgene-storm";
  10         interrupt-parent = <&gic>;
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13
  14         cpus {
  15                 #address-cells = <2>;
  16                 #size-cells = <0>;
  17
  18                 cpu@0 {
  19                         device_type = "cpu";
  20                         compatible = "apm,potenza";
  21                         reg = <0x0 0x000>;
  22                         enable-method = "spin-table";
  23                         cpu-release-addr = <0x1 0x0000fff8>;
  24                         next-level-cache = <&xgene_L2_0>;
  25                 };
  26                 cpu@1 {
  27                         device_type = "cpu";
  28                         compatible = "apm,potenza";
  29                         reg = <0x0 0x001>;
  30                         enable-method = "spin-table";
  31                         cpu-release-addr = <0x1 0x0000fff8>;
  32                         next-level-cache = <&xgene_L2_0>;
  33                 };
  34                 cpu@100 {
  35                         device_type = "cpu";
  36                         compatible = "apm,potenza";
  37                         reg = <0x0 0x100>;
  38                         enable-method = "spin-table";
  39                         cpu-release-addr = <0x1 0x0000fff8>;
  40                         next-level-cache = <&xgene_L2_1>;
  41                 };
  42                 cpu@101 {
  43                         device_type = "cpu";
  44                         compatible = "apm,potenza";
  45                         reg = <0x0 0x101>;
  46                         enable-method = "spin-table";
  47                         cpu-release-addr = <0x1 0x0000fff8>;
  48                         next-level-cache = <&xgene_L2_1>;
  49                 };
  50                 cpu@200 {
  51                         device_type = "cpu";
  52                         compatible = "apm,potenza";
  53                         reg = <0x0 0x200>;
  54                         enable-method = "spin-table";
  55                         cpu-release-addr = <0x1 0x0000fff8>;
  56                         next-level-cache = <&xgene_L2_2>;
  57                 };
  58                 cpu@201 {
  59                         device_type = "cpu";
  60                         compatible = "apm,potenza";
  61                         reg = <0x0 0x201>;
  62                         enable-method = "spin-table";
  63                         cpu-release-addr = <0x1 0x0000fff8>;
  64                         next-level-cache = <&xgene_L2_2>;
  65                 };
  66                 cpu@300 {
  67                         device_type = "cpu";
  68                         compatible = "apm,potenza";
  69                         reg = <0x0 0x300>;
  70                         enable-method = "spin-table";
  71                         cpu-release-addr = <0x1 0x0000fff8>;
  72                         next-level-cache = <&xgene_L2_3>;
  73                 };
  74                 cpu@301 {
  75                         device_type = "cpu";
  76                         compatible = "apm,potenza";
  77                         reg = <0x0 0x301>;
  78                         enable-method = "spin-table";
  79                         cpu-release-addr = <0x1 0x0000fff8>;
  80                         next-level-cache = <&xgene_L2_3>;
  81                 };
  82                 xgene_L2_0: l2-cache-0 {
  83                         compatible = "cache";
  84                         cache-level = <2>;
  85                         cache-unified;
  86                 };
  87                 xgene_L2_1: l2-cache-1 {
  88                         compatible = "cache";
  89                         cache-level = <2>;
  90                         cache-unified;
  91                 };
  92                 xgene_L2_2: l2-cache-2 {
  93                         compatible = "cache";
  94                         cache-level = <2>;
  95                         cache-unified;
  96                 };
  97                 xgene_L2_3: l2-cache-3 {
  98                         compatible = "cache";
  99                         cache-level = <2>;
 100                         cache-unified;
 101                 };
 102         };
 103
 104         gic: interrupt-controller@78010000 {
 105                 compatible = "arm,cortex-a15-gic";
 106                 #interrupt-cells = <3>;
 107                 interrupt-controller;
 108                 reg = <0x0 0x78010000 0x0 0x1000>,      /* GIC Dist */
 109                       <0x0 0x78020000 0x0 0x1000>,      /* GIC CPU */
 110                       <0x0 0x78040000 0x0 0x2000>,      /* GIC VCPU Control */
 111                       <0x0 0x78060000 0x0 0x2000>;      /* GIC VCPU */
 112                 interrupts = <1 9 0xf04>;       /* GIC Maintenence IRQ */
 113         };
 114
 115         refclk: refclk {
 116                 compatible = "fixed-clock";
 117                 #clock-cells = <1>;
 118                 clock-frequency = <100000000>;
 119                 clock-output-names = "refclk";
 120         };
 121
 122         timer {
 123                 compatible = "arm,armv8-timer";
 124                 interrupts = <1 0 0xff08>,      /* Secure Phys IRQ */
 125                              <1 13 0xff08>,     /* Non-secure Phys IRQ */
 126                              <1 14 0xff08>,     /* Virt IRQ */
 127                              <1 15 0xff08>;     /* Hyp IRQ */
 128                 clock-frequency = <50000000>;
 129         };
 130
 131         pmu {
 132                 compatible = "apm,potenza-pmu";
 133                 interrupts = <1 12 0xff04>;
 134         };
 135
 136         soc {
 137                 compatible = "simple-bus";
 138                 #address-cells = <2>;
 139                 #size-cells = <2>;
 140                 ranges;
 141                 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
 142
 143                 clocks {
 144                         #address-cells = <2>;
 145                         #size-cells = <2>;
 146                         ranges;
 147
 148                         pcppll: pcppll@17000100 {
 149                                 compatible = "apm,xgene-pcppll-clock";
 150                                 #clock-cells = <1>;
 151                                 clocks = <&refclk 0>;
 152                                 clock-names = "pcppll";
 153                                 reg = <0x0 0x17000100 0x0 0x1000>;
 154                                 clock-output-names = "pcppll";
 155                                 type = <0>;
 156                         };
 157
 158                         socpll: socpll@17000120 {
 159                                 compatible = "apm,xgene-socpll-clock";
 160                                 #clock-cells = <1>;
 161                                 clocks = <&refclk 0>;
 162                                 clock-names = "socpll";
 163                                 reg = <0x0 0x17000120 0x0 0x1000>;
 164                                 clock-output-names = "socpll";
 165                                 type = <1>;
 166                         };
 167
 168                         socplldiv2: socplldiv2  {
 169                                 compatible = "fixed-factor-clock";
 170                                 #clock-cells = <1>;
 171                                 clocks = <&socpll 0>;
 172                                 clock-names = "socplldiv2";
 173                                 clock-mult = <1>;
 174                                 clock-div = <2>;
 175                                 clock-output-names = "socplldiv2";
 176                         };
 177
 178                         ahbclk: ahbclk@17000000 {
 179                                 compatible = "apm,xgene-device-clock";
 180                                 #clock-cells = <1>;
 181                                 clocks = <&socplldiv2 0>;
 182                                 reg = <0x0 0x17000000 0x0 0x2000>;
 183                                 reg-names = "div-reg";
 184                                 divider-offset = <0x164>;
 185                                 divider-width = <0x5>;
 186                                 divider-shift = <0x0>;
 187                                 clock-output-names = "ahbclk";
 188                         };
 189
 190                         sdioclk: sdioclk@1f2ac000 {
 191                                 compatible = "apm,xgene-device-clock";
 192                                 #clock-cells = <1>;
 193                                 clocks = <&socplldiv2 0>;
 194                                 reg = <0x0 0x1f2ac000 0x0 0x1000
 195                                         0x0 0x17000000 0x0 0x2000>;
 196                                 reg-names = "csr-reg", "div-reg";
 197                                 csr-offset = <0x0>;
 198                                 csr-mask = <0x2>;
 199                                 enable-offset = <0x8>;
 200                                 enable-mask = <0x2>;
 201                                 divider-offset = <0x178>;
 202                                 divider-width = <0x8>;
 203                                 divider-shift = <0x0>;
 204                                 clock-output-names = "sdioclk";
 205                         };
 206
 207                         ethclk: ethclk {
 208                                 compatible = "apm,xgene-device-clock";
 209                                 #clock-cells = <1>;
 210                                 clocks = <&socplldiv2 0>;
 211                                 clock-names = "ethclk";
 212                                 reg = <0x0 0x17000000 0x0 0x1000>;
 213                                 reg-names = "div-reg";
 214                                 divider-offset = <0x238>;
 215                                 divider-width = <0x9>;
 216                                 divider-shift = <0x0>;
 217                                 clock-output-names = "ethclk";
 218                         };
 219
 220                         menetclk: menetclk {
 221                                 compatible = "apm,xgene-device-clock";
 222                                 #clock-cells = <1>;
 223                                 clocks = <&ethclk 0>;
 224                                 reg = <0x0 0x1702c000 0x0 0x1000>;
 225                                 reg-names = "csr-reg";
 226                                 clock-output-names = "menetclk";
 227                         };
 228
 229                         sge0clk: sge0clk@1f21c000 {
 230                                 compatible = "apm,xgene-device-clock";
 231                                 #clock-cells = <1>;
 232                                 clocks = <&socplldiv2 0>;
 233                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 234                                 reg-names = "csr-reg";
 235                                 csr-mask = <0xa>;
 236                                 enable-mask = <0xf>;
 237                                 clock-output-names = "sge0clk";
 238                         };
 239
 240                         xge0clk: xge0clk@1f61c000 {
 241                                 compatible = "apm,xgene-device-clock";
 242                                 #clock-cells = <1>;
 243                                 clocks = <&socplldiv2 0>;
 244                                 reg = <0x0 0x1f61c000 0x0 0x1000>;
 245                                 reg-names = "csr-reg";
 246                                 csr-mask = <0x3>;
 247                                 clock-output-names = "xge0clk";
 248                         };
 249
 250                         xge1clk: xge1clk@1f62c000 {
 251                                 compatible = "apm,xgene-device-clock";
 252                                 status = "disabled";
 253                                 #clock-cells = <1>;
 254                                 clocks = <&socplldiv2 0>;
 255                                 reg = <0x0 0x1f62c000 0x0 0x1000>;
 256                                 reg-names = "csr-reg";
 257                                 csr-mask = <0x3>;
 258                                 clock-output-names = "xge1clk";
 259                         };
 260
 261                         sataphy1clk: sataphy1clk@1f21c000 {
 262                                 compatible = "apm,xgene-device-clock";
 263                                 #clock-cells = <1>;
 264                                 clocks = <&socplldiv2 0>;
 265                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 266                                 reg-names = "csr-reg";
 267                                 clock-output-names = "sataphy1clk";
 268                                 status = "disabled";
 269                                 csr-offset = <0x4>;
 270                                 csr-mask = <0x00>;
 271                                 enable-offset = <0x0>;
 272                                 enable-mask = <0x06>;
 273                         };
 274
 275                         sataphy2clk: sataphy1clk@1f22c000 {
 276                                 compatible = "apm,xgene-device-clock";
 277                                 #clock-cells = <1>;
 278                                 clocks = <&socplldiv2 0>;
 279                                 reg = <0x0 0x1f22c000 0x0 0x1000>;
 280                                 reg-names = "csr-reg";
 281                                 clock-output-names = "sataphy2clk";
 282                                 status = "okay";
 283                                 csr-offset = <0x4>;
 284                                 csr-mask = <0x3a>;
 285                                 enable-offset = <0x0>;
 286                                 enable-mask = <0x06>;
 287                         };
 288
 289                         sataphy3clk: sataphy1clk@1f23c000 {
 290                                 compatible = "apm,xgene-device-clock";
 291                                 #clock-cells = <1>;
 292                                 clocks = <&socplldiv2 0>;
 293                                 reg = <0x0 0x1f23c000 0x0 0x1000>;
 294                                 reg-names = "csr-reg";
 295                                 clock-output-names = "sataphy3clk";
 296                                 status = "okay";
 297                                 csr-offset = <0x4>;
 298                                 csr-mask = <0x3a>;
 299                                 enable-offset = <0x0>;
 300                                 enable-mask = <0x06>;
 301                         };
 302
 303                         sata01clk: sata01clk@1f21c000 {
 304                                 compatible = "apm,xgene-device-clock";
 305                                 #clock-cells = <1>;
 306                                 clocks = <&socplldiv2 0>;
 307                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 308                                 reg-names = "csr-reg";
 309                                 clock-output-names = "sata01clk";
 310                                 csr-offset = <0x4>;
 311                                 csr-mask = <0x05>;
 312                                 enable-offset = <0x0>;
 313                                 enable-mask = <0x39>;
 314                         };
 315
 316                         sata23clk: sata23clk@1f22c000 {
 317                                 compatible = "apm,xgene-device-clock";
 318                                 #clock-cells = <1>;
 319                                 clocks = <&socplldiv2 0>;
 320                                 reg = <0x0 0x1f22c000 0x0 0x1000>;
 321                                 reg-names = "csr-reg";
 322                                 clock-output-names = "sata23clk";
 323                                 csr-offset = <0x4>;
 324                                 csr-mask = <0x05>;
 325                                 enable-offset = <0x0>;
 326                                 enable-mask = <0x39>;
 327                         };
 328
 329                         sata45clk: sata45clk@1f23c000 {
 330                                 compatible = "apm,xgene-device-clock";
 331                                 #clock-cells = <1>;
 332                                 clocks = <&socplldiv2 0>;
 333                                 reg = <0x0 0x1f23c000 0x0 0x1000>;
 334                                 reg-names = "csr-reg";
 335                                 clock-output-names = "sata45clk";
 336                                 csr-offset = <0x4>;
 337                                 csr-mask = <0x05>;
 338                                 enable-offset = <0x0>;
 339                                 enable-mask = <0x39>;
 340                         };
 341
 342                         rtcclk: rtcclk@17000000 {
 343                                 compatible = "apm,xgene-device-clock";
 344                                 #clock-cells = <1>;
 345                                 clocks = <&socplldiv2 0>;
 346                                 reg = <0x0 0x17000000 0x0 0x2000>;
 347                                 reg-names = "csr-reg";
 348                                 csr-offset = <0xc>;
 349                                 csr-mask = <0x2>;
 350                                 enable-offset = <0x10>;
 351                                 enable-mask = <0x2>;
 352                                 clock-output-names = "rtcclk";
 353                         };
 354
 355                         rngpkaclk: rngpkaclk@17000000 {
 356                                 compatible = "apm,xgene-device-clock";
 357                                 #clock-cells = <1>;
 358                                 clocks = <&socplldiv2 0>;
 359                                 reg = <0x0 0x17000000 0x0 0x2000>;
 360                                 reg-names = "csr-reg";
 361                                 csr-offset = <0xc>;
 362                                 csr-mask = <0x10>;
 363                                 enable-offset = <0x10>;
 364                                 enable-mask = <0x10>;
 365                                 clock-output-names = "rngpkaclk";
 366                         };
 367
 368                         pcie0clk: pcie0clk@1f2bc000 {
 369                                 status = "disabled";
 370                                 compatible = "apm,xgene-device-clock";
 371                                 #clock-cells = <1>;
 372                                 clocks = <&socplldiv2 0>;
 373                                 reg = <0x0 0x1f2bc000 0x0 0x1000>;
 374                                 reg-names = "csr-reg";
 375                                 clock-output-names = "pcie0clk";
 376                         };
 377
 378                         pcie1clk: pcie1clk@1f2cc000 {
 379                                 status = "disabled";
 380                                 compatible = "apm,xgene-device-clock";
 381                                 #clock-cells = <1>;
 382                                 clocks = <&socplldiv2 0>;
 383                                 reg = <0x0 0x1f2cc000 0x0 0x1000>;
 384                                 reg-names = "csr-reg";
 385                                 clock-output-names = "pcie1clk";
 386                         };
 387
 388                         pcie2clk: pcie2clk@1f2dc000 {
 389                                 status = "disabled";
 390                                 compatible = "apm,xgene-device-clock";
 391                                 #clock-cells = <1>;
 392                                 clocks = <&socplldiv2 0>;
 393                                 reg = <0x0 0x1f2dc000 0x0 0x1000>;
 394                                 reg-names = "csr-reg";
 395                                 clock-output-names = "pcie2clk";
 396                         };
 397
 398                         pcie3clk: pcie3clk@1f50c000 {
 399                                 status = "disabled";
 400                                 compatible = "apm,xgene-device-clock";
 401                                 #clock-cells = <1>;
 402                                 clocks = <&socplldiv2 0>;
 403                                 reg = <0x0 0x1f50c000 0x0 0x1000>;
 404                                 reg-names = "csr-reg";
 405                                 clock-output-names = "pcie3clk";
 406                         };
 407
 408                         pcie4clk: pcie4clk@1f51c000 {
 409                                 status = "disabled";
 410                                 compatible = "apm,xgene-device-clock";
 411                                 #clock-cells = <1>;
 412                                 clocks = <&socplldiv2 0>;
 413                                 reg = <0x0 0x1f51c000 0x0 0x1000>;
 414                                 reg-names = "csr-reg";
 415                                 clock-output-names = "pcie4clk";
 416                         };
 417
 418                         dmaclk: dmaclk@1f27c000 {
 419                                 compatible = "apm,xgene-device-clock";
 420                                 #clock-cells = <1>;
 421                                 clocks = <&socplldiv2 0>;
 422                                 reg = <0x0 0x1f27c000 0x0 0x1000>;
 423                                 reg-names = "csr-reg";
 424                                 clock-output-names = "dmaclk";
 425                         };
 426                 };
 427
 428                 msi: msi@79000000 {
 429                         compatible = "apm,xgene1-msi";
 430                         msi-controller;
 431                         reg = <0x00 0x79000000 0x0 0x900000>;
 432                         interrupts = <  0x0 0x10 0x4
 433                                         0x0 0x11 0x4
 434                                         0x0 0x12 0x4
 435                                         0x0 0x13 0x4
 436                                         0x0 0x14 0x4
 437                                         0x0 0x15 0x4
 438                                         0x0 0x16 0x4
 439                                         0x0 0x17 0x4
 440                                         0x0 0x18 0x4
 441                                         0x0 0x19 0x4
 442                                         0x0 0x1a 0x4
 443                                         0x0 0x1b 0x4
 444                                         0x0 0x1c 0x4
 445                                         0x0 0x1d 0x4
 446                                         0x0 0x1e 0x4
 447                                         0x0 0x1f 0x4>;
 448                 };
 449
 450                 scu: system-clk-controller@17000000 {
 451                         compatible = "apm,xgene-scu","syscon";
 452                         reg = <0x0 0x17000000 0x0 0x400>;
 453                 };
 454
 455                 reboot: reboot@17000014 {
 456                         compatible = "syscon-reboot";
 457                         regmap = <&scu>;
 458                         offset = <0x14>;
 459                         mask = <0x1>;
 460                 };
 461
 462                 csw: csw@7e200000 {
 463                         compatible = "apm,xgene-csw", "syscon";
 464                         reg = <0x0 0x7e200000 0x0 0x1000>;
 465                 };
 466
 467                 mcba: mcba@7e700000 {
 468                         compatible = "apm,xgene-mcb", "syscon";
 469                         reg = <0x0 0x7e700000 0x0 0x1000>;
 470                 };
 471
 472                 mcbb: mcbb@7e720000 {
 473                         compatible = "apm,xgene-mcb", "syscon";
 474                         reg = <0x0 0x7e720000 0x0 0x1000>;
 475                 };
 476
 477                 efuse: efuse@1054a000 {
 478                         compatible = "apm,xgene-efuse", "syscon";
 479                         reg = <0x0 0x1054a000 0x0 0x20>;
 480                 };
 481
 482                 rb: rb@7e000000 {
 483                         compatible = "apm,xgene-rb", "syscon";
 484                         reg = <0x0 0x7e000000 0x0 0x10>;
 485                 };
 486
 487                 edac@78800000 {
 488                         compatible = "apm,xgene-edac";
 489                         #address-cells = <2>;
 490                         #size-cells = <2>;
 491                         ranges;
 492                         regmap-csw = <&csw>;
 493                         regmap-mcba = <&mcba>;
 494                         regmap-mcbb = <&mcbb>;
 495                         regmap-efuse = <&efuse>;
 496                         regmap-rb = <&rb>;
 497                         reg = <0x0 0x78800000 0x0 0x100>;
 498                         interrupts = <0x0 0x20 0x4>,
 499                                      <0x0 0x21 0x4>,
 500                                      <0x0 0x27 0x4>;
 501
 502                         edacmc@7e800000 {
 503                                 compatible = "apm,xgene-edac-mc";
 504                                 reg = <0x0 0x7e800000 0x0 0x1000>;
 505                                 memory-controller = <0>;
 506                         };
 507
 508                         edacmc@7e840000 {
 509                                 compatible = "apm,xgene-edac-mc";
 510                                 reg = <0x0 0x7e840000 0x0 0x1000>;
 511                                 memory-controller = <1>;
 512                         };
 513
 514                         edacmc@7e880000 {
 515                                 compatible = "apm,xgene-edac-mc";
 516                                 reg = <0x0 0x7e880000 0x0 0x1000>;
 517                                 memory-controller = <2>;
 518                         };
 519
 520                         edacmc@7e8c0000 {
 521                                 compatible = "apm,xgene-edac-mc";
 522                                 reg = <0x0 0x7e8c0000 0x0 0x1000>;
 523                                 memory-controller = <3>;
 524                         };
 525
 526                         edacpmd@7c000000 {
 527                                 compatible = "apm,xgene-edac-pmd";
 528                                 reg = <0x0 0x7c000000 0x0 0x200000>;
 529                                 pmd-controller = <0>;
 530                         };
 531
 532                         edacpmd@7c200000 {
 533                                 compatible = "apm,xgene-edac-pmd";
 534                                 reg = <0x0 0x7c200000 0x0 0x200000>;
 535                                 pmd-controller = <1>;
 536                         };
 537
 538                         edacpmd@7c400000 {
 539                                 compatible = "apm,xgene-edac-pmd";
 540                                 reg = <0x0 0x7c400000 0x0 0x200000>;
 541                                 pmd-controller = <2>;
 542                         };
 543
 544                         edacpmd@7c600000 {
 545                                 compatible = "apm,xgene-edac-pmd";
 546                                 reg = <0x0 0x7c600000 0x0 0x200000>;
 547                                 pmd-controller = <3>;
 548                         };
 549
 550                         edacl3@7e600000 {
 551                                 compatible = "apm,xgene-edac-l3";
 552                                 reg = <0x0 0x7e600000 0x0 0x1000>;
 553                         };
 554
 555                         edacsoc@7e930000 {
 556                                 compatible = "apm,xgene-edac-soc-v1";
 557                                 reg = <0x0 0x7e930000 0x0 0x1000>;
 558                         };
 559                 };
 560
 561                 pmu: pmu@78810000 {
 562                         compatible = "apm,xgene-pmu-v2";
 563                         #address-cells = <2>;
 564                         #size-cells = <2>;
 565                         ranges;
 566                         regmap-csw = <&csw>;
 567                         regmap-mcba = <&mcba>;
 568                         regmap-mcbb = <&mcbb>;
 569                         reg = <0x0 0x78810000 0x0 0x1000>;
 570                         interrupts = <0x0 0x22 0x4>;
 571
 572                         pmul3c@7e610000 {
 573                                 compatible = "apm,xgene-pmu-l3c";
 574                                 reg = <0x0 0x7e610000 0x0 0x1000>;
 575                         };
 576
 577                         pmuiob@7e940000 {
 578                                 compatible = "apm,xgene-pmu-iob";
 579                                 reg = <0x0 0x7e940000 0x0 0x1000>;
 580                         };
 581
 582                         pmucmcb@7e710000 {
 583                                 compatible = "apm,xgene-pmu-mcb";
 584                                 reg = <0x0 0x7e710000 0x0 0x1000>;
 585                                 enable-bit-index = <0>;
 586                         };
 587
 588                         pmucmcb@7e730000 {
 589                                 compatible = "apm,xgene-pmu-mcb";
 590                                 reg = <0x0 0x7e730000 0x0 0x1000>;
 591                                 enable-bit-index = <1>;
 592                         };
 593
 594                         pmucmc@7e810000 {
 595                                 compatible = "apm,xgene-pmu-mc";
 596                                 reg = <0x0 0x7e810000 0x0 0x1000>;
 597                                 enable-bit-index = <0>;
 598                         };
 599
 600                         pmucmc@7e850000 {
 601                                 compatible = "apm,xgene-pmu-mc";
 602                                 reg = <0x0 0x7e850000 0x0 0x1000>;
 603                                 enable-bit-index = <1>;
 604                         };
 605
 606                         pmucmc@7e890000 {
 607                                 compatible = "apm,xgene-pmu-mc";
 608                                 reg = <0x0 0x7e890000 0x0 0x1000>;
 609                                 enable-bit-index = <2>;
 610                         };
 611
 612                         pmucmc@7e8d0000 {
 613                                 compatible = "apm,xgene-pmu-mc";
 614                                 reg = <0x0 0x7e8d0000 0x0 0x1000>;
 615                                 enable-bit-index = <3>;
 616                         };
 617                 };
 618
 619                 pcie0: pcie@1f2b0000 {
 620                         status = "disabled";
 621                         device_type = "pci";
 622                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 623                         #interrupt-cells = <1>;
 624                         #size-cells = <2>;
 625                         #address-cells = <3>;
 626                         reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
 627                                 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 628                         reg-names = "csr", "cfg";
 629                         ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
 630                                   0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000   /* mem */
 631                                   0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
 632                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 633                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 634                         bus-range = <0x00 0xff>;
 635                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 636                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4
 637                                          0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4
 638                                          0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4
 639                                          0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>;
 640                         dma-coherent;
 641                         clocks = <&pcie0clk 0>;
 642                         msi-parent = <&msi>;
 643                 };
 644
 645                 pcie1: pcie@1f2c0000 {
 646                         status = "disabled";
 647                         device_type = "pci";
 648                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 649                         #interrupt-cells = <1>;
 650                         #size-cells = <2>;
 651                         #address-cells = <3>;
 652                         reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
 653                                 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 654                         reg-names = "csr", "cfg";
 655                         ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */
 656                                   0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000   /* mem */
 657                                   0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
 658                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 659                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 660                         bus-range = <0x00 0xff>;
 661                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 662                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4
 663                                          0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4
 664                                          0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4
 665                                          0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>;
 666                         dma-coherent;
 667                         clocks = <&pcie1clk 0>;
 668                         msi-parent = <&msi>;
 669                 };
 670
 671                 pcie2: pcie@1f2d0000 {
 672                         status = "disabled";
 673                         device_type = "pci";
 674                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 675                         #interrupt-cells = <1>;
 676                         #size-cells = <2>;
 677                         #address-cells = <3>;
 678                         reg =  < 0x00 0x1f2d0000 0x0 0x00010000   /* Controller registers */
 679                                  0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
 680                         reg-names = "csr", "cfg";
 681                         ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000   /* io  */
 682                                   0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000   /* mem */
 683                                   0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
 684                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 685                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 686                         bus-range = <0x00 0xff>;
 687                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 688                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4
 689                                          0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4
 690                                          0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4
 691                                          0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>;
 692                         dma-coherent;
 693                         clocks = <&pcie2clk 0>;
 694                         msi-parent = <&msi>;
 695                 };
 696
 697                 pcie3: pcie@1f500000 {
 698                         status = "disabled";
 699                         device_type = "pci";
 700                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 701                         #interrupt-cells = <1>;
 702                         #size-cells = <2>;
 703                         #address-cells = <3>;
 704                         reg = < 0x00 0x1f500000 0x0 0x00010000   /* Controller registers */
 705                                 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 706                         reg-names = "csr", "cfg";
 707                         ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000   /* io  */
 708                                   0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000   /* mem */
 709                                   0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
 710                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 711                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 712                         bus-range = <0x00 0xff>;
 713                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 714                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4
 715                                          0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4
 716                                          0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4
 717                                          0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>;
 718                         dma-coherent;
 719                         clocks = <&pcie3clk 0>;
 720                         msi-parent = <&msi>;
 721                 };
 722
 723                 pcie4: pcie@1f510000 {
 724                         status = "disabled";
 725                         device_type = "pci";
 726                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 727                         #interrupt-cells = <1>;
 728                         #size-cells = <2>;
 729                         #address-cells = <3>;
 730                         reg = < 0x00 0x1f510000 0x0 0x00010000   /* Controller registers */
 731                                 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
 732                         reg-names = "csr", "cfg";
 733                         ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000   /* io  */
 734                                   0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000   /* mem */
 735                                   0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
 736                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 737                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 738                         bus-range = <0x00 0xff>;
 739                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 740                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4
 741                                          0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4
 742                                          0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4
 743                                          0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>;
 744                         dma-coherent;
 745                         clocks = <&pcie4clk 0>;
 746                         msi-parent = <&msi>;
 747                 };
 748
 749                 mailbox: mailbox@10540000 {
 750                         compatible = "apm,xgene-slimpro-mbox";
 751                         reg = <0x0 0x10540000 0x0 0xa000>;
 752                         #mbox-cells = <1>;
 753                         interrupts =    <0x0 0x0 0x4>,
 754                                         <0x0 0x1 0x4>,
 755                                         <0x0 0x2 0x4>,
 756                                         <0x0 0x3 0x4>,
 757                                         <0x0 0x4 0x4>,
 758                                         <0x0 0x5 0x4>,
 759                                         <0x0 0x6 0x4>,
 760                                         <0x0 0x7 0x4>;
 761                 };
 762
 763                 i2cslimpro {
 764                         compatible = "apm,xgene-slimpro-i2c";
 765                         mboxes = <&mailbox 0>;
 766                 };
 767
 768                 hwmonslimpro {
 769                         compatible = "apm,xgene-slimpro-hwmon";
 770                         mboxes = <&mailbox 7>;
 771                 };
 772
 773                 serial0: serial@1c020000 {
 774                         status = "disabled";
 775                         compatible = "ns16550a";
 776                         reg = <0 0x1c020000 0x0 0x1000>;
 777                         reg-shift = <2>;
 778                         clock-frequency = <10000000>; /* Updated by bootloader */
 779                         interrupt-parent = <&gic>;
 780                         interrupts = <0x0 0x4c 0x4>;
 781                 };
 782
 783                 serial1: serial@1c021000 {
 784                         status = "disabled";
 785                         compatible = "ns16550a";
 786                         reg = <0 0x1c021000 0x0 0x1000>;
 787                         reg-shift = <2>;
 788                         clock-frequency = <10000000>; /* Updated by bootloader */
 789                         interrupt-parent = <&gic>;
 790                         interrupts = <0x0 0x4d 0x4>;
 791                 };
 792
 793                 serial2: serial@1c022000 {
 794                         status = "disabled";
 795                         compatible = "ns16550a";
 796                         reg = <0 0x1c022000 0x0 0x1000>;
 797                         reg-shift = <2>;
 798                         clock-frequency = <10000000>; /* Updated by bootloader */
 799                         interrupt-parent = <&gic>;
 800                         interrupts = <0x0 0x4e 0x4>;
 801                 };
 802
 803                 serial3: serial@1c023000 {
 804                         status = "disabled";
 805                         compatible = "ns16550a";
 806                         reg = <0 0x1c023000 0x0 0x1000>;
 807                         reg-shift = <2>;
 808                         clock-frequency = <10000000>; /* Updated by bootloader */
 809                         interrupt-parent = <&gic>;
 810                         interrupts = <0x0 0x4f 0x4>;
 811                 };
 812
 813                 mmc0: mmc@1c000000 {
 814                         compatible = "arasan,sdhci-4.9a";
 815                         reg = <0x0 0x1c000000 0x0 0x100>;
 816                         interrupts = <0x0 0x49 0x4>;
 817                         dma-coherent;
 818                         no-1-8-v;
 819                         clock-names = "clk_xin", "clk_ahb";
 820                         clocks = <&sdioclk 0>, <&ahbclk 0>;
 821                 };
 822
 823                 gfcgpio: gpio0@1701c000 {
 824                         compatible = "apm,xgene-gpio";
 825                         reg = <0x0 0x1701c000 0x0 0x40>;
 826                         gpio-controller;
 827                         #gpio-cells = <2>;
 828                 };
 829
 830                 dwgpio: gpio@1c024000 {
 831                         compatible = "snps,dw-apb-gpio";
 832                         reg = <0x0 0x1c024000 0x0 0x1000>;
 833                         #address-cells = <1>;
 834                         #size-cells = <0>;
 835
 836                         porta: gpio-controller@0 {
 837                                 compatible = "snps,dw-apb-gpio-port";
 838                                 gpio-controller;
 839                                 #gpio-cells = <2>;
 840                                 snps,nr-gpios = <32>;
 841                                 reg = <0>;
 842                         };
 843                 };
 844
 845                 i2c0: i2c@10512000 {
 846                         status = "disabled";
 847                         #address-cells = <1>;
 848                         #size-cells = <0>;
 849                         compatible = "snps,designware-i2c";
 850                         reg = <0x0 0x10512000 0x0 0x1000>;
 851                         interrupts = <0 0x44 0x4>;
 852                         #clock-cells = <1>;
 853                         clocks = <&ahbclk 0>;
 854                         bus_num = <0>;
 855                 };
 856
 857                 phy1: phy@1f21a000 {
 858                         compatible = "apm,xgene-phy";
 859                         reg = <0x0 0x1f21a000 0x0 0x100>;
 860                         #phy-cells = <1>;
 861                         clocks = <&sataphy1clk 0>;
 862                         status = "disabled";
 863                         apm,tx-boost-gain = <30 30 30 30 30 30>;
 864                         apm,tx-eye-tuning = <2 10 10 2 10 10>;
 865                 };
 866
 867                 phy2: phy@1f22a000 {
 868                         compatible = "apm,xgene-phy";
 869                         reg = <0x0 0x1f22a000 0x0 0x100>;
 870                         #phy-cells = <1>;
 871                         clocks = <&sataphy2clk 0>;
 872                         status = "okay";
 873                         apm,tx-boost-gain = <30 30 30 30 30 30>;
 874                         apm,tx-eye-tuning = <1 10 10 2 10 10>;
 875                 };
 876
 877                 phy3: phy@1f23a000 {
 878                         compatible = "apm,xgene-phy";
 879                         reg = <0x0 0x1f23a000 0x0 0x100>;
 880                         #phy-cells = <1>;
 881                         clocks = <&sataphy3clk 0>;
 882                         status = "okay";
 883                         apm,tx-boost-gain = <31 31 31 31 31 31>;
 884                         apm,tx-eye-tuning = <2 10 10 2 10 10>;
 885                 };
 886
 887                 sata1: sata@1a000000 {
 888                         compatible = "apm,xgene-ahci";
 889                         reg = <0x0 0x1a000000 0x0 0x1000>,
 890                               <0x0 0x1f210000 0x0 0x1000>,
 891                               <0x0 0x1f21d000 0x0 0x1000>,
 892                               <0x0 0x1f21e000 0x0 0x1000>,
 893                               <0x0 0x1f217000 0x0 0x1000>;
 894                         interrupts = <0x0 0x86 0x4>;
 895                         dma-coherent;
 896                         status = "disabled";
 897                         clocks = <&sata01clk 0>;
 898                         phys = <&phy1 0>;
 899                         phy-names = "sata-phy";
 900                 };
 901
 902                 sata2: sata@1a400000 {
 903                         compatible = "apm,xgene-ahci";
 904                         reg = <0x0 0x1a400000 0x0 0x1000>,
 905                               <0x0 0x1f220000 0x0 0x1000>,
 906                               <0x0 0x1f22d000 0x0 0x1000>,
 907                               <0x0 0x1f22e000 0x0 0x1000>,
 908                               <0x0 0x1f227000 0x0 0x1000>;
 909                         interrupts = <0x0 0x87 0x4>;
 910                         dma-coherent;
 911                         status = "okay";
 912                         clocks = <&sata23clk 0>;
 913                         phys = <&phy2 0>;
 914                         phy-names = "sata-phy";
 915                 };
 916
 917                 sata3: sata@1a800000 {
 918                         compatible = "apm,xgene-ahci";
 919                         reg = <0x0 0x1a800000 0x0 0x1000>,
 920                               <0x0 0x1f230000 0x0 0x1000>,
 921                               <0x0 0x1f23d000 0x0 0x1000>,
 922                               <0x0 0x1f23e000 0x0 0x1000>;
 923                         interrupts = <0x0 0x88 0x4>;
 924                         dma-coherent;
 925                         status = "okay";
 926                         clocks = <&sata45clk 0>;
 927                         phys = <&phy3 0>;
 928                         phy-names = "sata-phy";
 929                 };
 930
 931                 /* Node-name might need to be coded as dwusb for backward compatibility */
 932                 usb0: usb@19000000 {
 933                         status = "disabled";
 934                         compatible = "snps,dwc3";
 935                         reg = <0x0 0x19000000 0x0 0x100000>;
 936                         interrupts = <0x0 0x89 0x4>;
 937                         dma-coherent;
 938                         dr_mode = "host";
 939                 };
 940
 941                 usb1: usb@19800000 {
 942                         status = "disabled";
 943                         compatible = "snps,dwc3";
 944                         reg = <0x0 0x19800000 0x0 0x100000>;
 945                         interrupts = <0x0 0x8a 0x4>;
 946                         dma-coherent;
 947                         dr_mode = "host";
 948                 };
 949
 950                 sbgpio: gpio@17001000 {
 951                         compatible = "apm,xgene-gpio-sb";
 952                         reg = <0x0 0x17001000 0x0 0x400>;
 953                         #gpio-cells = <2>;
 954                         gpio-controller;
 955                         interrupts =    <0x0 0x28 0x1>,
 956                                         <0x0 0x29 0x1>,
 957                                         <0x0 0x2a 0x1>,
 958                                         <0x0 0x2b 0x1>,
 959                                         <0x0 0x2c 0x1>,
 960                                         <0x0 0x2d 0x1>;
 961                         interrupt-parent = <&gic>;
 962                         #interrupt-cells = <2>;
 963                         interrupt-controller;
 964                 };
 965
 966                 rtc: rtc@10510000 {
 967                         compatible = "apm,xgene-rtc";
 968                         reg = <0x0 0x10510000 0x0 0x400>;
 969                         interrupts = <0x0 0x46 0x4>;
 970                         #clock-cells = <1>;
 971                         clocks = <&rtcclk 0>;
 972                 };
 973
 974                 mdio: mdio@17020000 {
 975                         compatible = "apm,xgene-mdio-rgmii";
 976                         #address-cells = <1>;
 977                         #size-cells = <0>;
 978                         reg = <0x0 0x17020000 0x0 0xd100>;
 979                         clocks = <&menetclk 0>;
 980                 };
 981
 982                 menet: ethernet@17020000 {
 983                         compatible = "apm,xgene-enet";
 984                         status = "disabled";
 985                         reg = <0x0 0x17020000 0x0 0xd100>,
 986                               <0x0 0x17030000 0x0 0xc300>,
 987                               <0x0 0x10000000 0x0 0x200>;
 988                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 989                         interrupts = <0x0 0x3c 0x4>;
 990                         dma-coherent;
 991                         clocks = <&menetclk 0>;
 992                         /* mac address will be overwritten by the bootloader */
 993                         local-mac-address = [00 00 00 00 00 00];
 994                         phy-connection-type = "rgmii";
 995                         phy-handle = <&menetphy>,<&menet0phy>;
 996                         mdio {
 997                                 compatible = "apm,xgene-mdio";
 998                                 #address-cells = <1>;
 999                                 #size-cells = <0>;
1000                                 menetphy: menetphy@3 {
1001                                         compatible = "ethernet-phy-id001c.c915";
1002                                         reg = <0x3>;
1003                                 };
1004
1005                         };
1006                 };
1007
1008                 sgenet0: ethernet@1f210000 {
1009                         compatible = "apm,xgene1-sgenet";
1010                         status = "disabled";
1011                         reg = <0x0 0x1f210000 0x0 0xd100>,
1012                               <0x0 0x1f200000 0x0 0xc300>,
1013                               <0x0 0x1b000000 0x0 0x200>;
1014                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
1015                         interrupts = <0x0 0xa0 0x4>,
1016                                      <0x0 0xa1 0x4>;
1017                         dma-coherent;
1018                         clocks = <&sge0clk 0>;
1019                         local-mac-address = [00 00 00 00 00 00];
1020                         phy-connection-type = "sgmii";
1021                         phy-handle = <&sgenet0phy>;
1022                 };
1023
1024                 sgenet1: ethernet@1f210030 {
1025                         compatible = "apm,xgene1-sgenet";
1026                         status = "disabled";
1027                         reg = <0x0 0x1f210030 0x0 0xd100>,
1028                               <0x0 0x1f200000 0x0 0xc300>,
1029                               <0x0 0x1b000000 0x0 0x8000>;
1030                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
1031                         interrupts = <0x0 0xac 0x4>,
1032                                      <0x0 0xad 0x4>;
1033                         port-id = <1>;
1034                         dma-coherent;
1035                         local-mac-address = [00 00 00 00 00 00];
1036                         phy-connection-type = "sgmii";
1037                         phy-handle = <&sgenet1phy>;
1038                 };
1039
1040                 xgenet: ethernet@1f610000 {
1041                         compatible = "apm,xgene1-xgenet";
1042                         status = "disabled";
1043                         reg = <0x0 0x1f610000 0x0 0xd100>,
1044                               <0x0 0x1f600000 0x0 0xc300>,
1045                               <0x0 0x18000000 0x0 0x200>;
1046                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
1047                         interrupts = <0x0 0x60 0x4>,
1048                                      <0x0 0x61 0x4>,
1049                                      <0x0 0x62 0x4>,
1050                                      <0x0 0x63 0x4>,
1051                                      <0x0 0x64 0x4>,
1052                                      <0x0 0x65 0x4>,
1053                                      <0x0 0x66 0x4>,
1054                                      <0x0 0x67 0x4>;
1055                         channel = <0>;
1056                         dma-coherent;
1057                         clocks = <&xge0clk 0>;
1058                         /* mac address will be overwritten by the bootloader */
1059                         local-mac-address = [00 00 00 00 00 00];
1060                         phy-connection-type = "xgmii";
1061                 };
1062
1063                 xgenet1: ethernet@1f620000 {
1064                         compatible = "apm,xgene1-xgenet";
1065                         status = "disabled";
1066                         reg = <0x0 0x1f620000 0x0 0xd100>,
1067                               <0x0 0x1f600000 0x0 0xc300>,
1068                               <0x0 0x18000000 0x0 0x8000>;
1069                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
1070                         interrupts = <0x0 0x6c 0x4>,
1071                                      <0x0 0x6d 0x4>;
1072                         port-id = <1>;
1073                         dma-coherent;
1074                         clocks = <&xge1clk 0>;
1075                         /* mac address will be overwritten by the bootloader */
1076                         local-mac-address = [00 00 00 00 00 00];
1077                         phy-connection-type = "xgmii";
1078                 };
1079
1080                 rng: rng@10520000 {
1081                         compatible = "apm,xgene-rng";
1082                         reg = <0x0 0x10520000 0x0 0x100>;
1083                         interrupts = <0x0 0x41 0x4>;
1084                         clocks = <&rngpkaclk 0>;
1085                 };
1086
1087                 dma: dma@1f270000 {
1088                         compatible = "apm,xgene-storm-dma";
1089                         device_type = "dma";
1090                         reg = <0x0 0x1f270000 0x0 0x10000>,
1091                               <0x0 0x1f200000 0x0 0x10000>,
1092                               <0x0 0x1b000000 0x0 0x400000>,
1093                               <0x0 0x1054a000 0x0 0x100>;
1094                         interrupts = <0x0 0x82 0x4>,
1095                                      <0x0 0xb8 0x4>,
1096                                      <0x0 0xb9 0x4>,
1097                                      <0x0 0xba 0x4>,
1098                                      <0x0 0xbb 0x4>;
1099                         dma-coherent;
1100                         clocks = <&dmaclk 0>;
1101                 };
1102         };
1103 };