arch/arm64/boot/dts/exynos/exynos850.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung Exynos850 SoC device tree source
   4  *
   5  * Copyright (C) 2018 Samsung Electronics Co., Ltd.
   6  * Copyright (C) 2021 Linaro Ltd.
   7  *
   8  * Samsung Exynos850 SoC device nodes are listed in this file.
   9  * Exynos850 based board files can include this file and provide
  10  * values for board specific bindings.
  11  */
  12
  13 #include <dt-bindings/clock/exynos850.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/soc/samsung,exynos-usi.h>
  16
  17 / {
  18         /* Also known under engineering name Exynos3830 */
  19         compatible = "samsung,exynos850";
  20         #address-cells = <2>;
  21         #size-cells = <1>;
  22
  23         interrupt-parent = <&gic>;
  24
  25         aliases {
  26                 pinctrl0 = &pinctrl_alive;
  27                 pinctrl1 = &pinctrl_cmgp;
  28                 pinctrl2 = &pinctrl_aud;
  29                 pinctrl3 = &pinctrl_hsi;
  30                 pinctrl4 = &pinctrl_core;
  31                 pinctrl5 = &pinctrl_peri;
  32         };
  33
  34         arm-pmu {
  35                 compatible = "arm,cortex-a55-pmu";
  36                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
  37                              <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
  38                              <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
  39                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
  40                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
  41                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
  42                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
  43                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
  44                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
  45                                      <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
  46         };
  47
  48         /* Main system clock (XTCXO); external, must be 26 MHz */
  49         oscclk: clock-oscclk {
  50                 compatible = "fixed-clock";
  51                 clock-output-names = "oscclk";
  52                 #clock-cells = <0>;
  53         };
  54
  55         cpus {
  56                 #address-cells = <1>;
  57                 #size-cells = <0>;
  58
  59                 cpu-map {
  60                         cluster0 {
  61                                 core0 {
  62                                         cpu = <&cpu0>;
  63                                 };
  64                                 core1 {
  65                                         cpu = <&cpu1>;
  66                                 };
  67                                 core2 {
  68                                         cpu = <&cpu2>;
  69                                 };
  70                                 core3 {
  71                                         cpu = <&cpu3>;
  72                                 };
  73                         };
  74
  75                         cluster1 {
  76                                 core0 {
  77                                         cpu = <&cpu4>;
  78                                 };
  79                                 core1 {
  80                                         cpu = <&cpu5>;
  81                                 };
  82                                 core2 {
  83                                         cpu = <&cpu6>;
  84                                 };
  85                                 core3 {
  86                                         cpu = <&cpu7>;
  87                                 };
  88                         };
  89                 };
  90
  91                 cpu0: cpu@0 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a55";
  94                         reg = <0x0>;
  95                         enable-method = "psci";
  96                         clocks = <&cmu_cpucl0 CLK_CLUSTER0_SCLK>;
  97                         clock-names = "cluster0_clk";
  98                 };
  99                 cpu1: cpu@1 {
 100                         device_type = "cpu";
 101                         compatible = "arm,cortex-a55";
 102                         reg = <0x1>;
 103                         enable-method = "psci";
 104                 };
 105                 cpu2: cpu@2 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a55";
 108                         reg = <0x2>;
 109                         enable-method = "psci";
 110                 };
 111                 cpu3: cpu@3 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a55";
 114                         reg = <0x3>;
 115                         enable-method = "psci";
 116                 };
 117                 cpu4: cpu@100 {
 118                         device_type = "cpu";
 119                         compatible = "arm,cortex-a55";
 120                         reg = <0x100>;
 121                         enable-method = "psci";
 122                         clocks = <&cmu_cpucl1 CLK_CLUSTER1_SCLK>;
 123                         clock-names = "cluster1_clk";
 124                 };
 125                 cpu5: cpu@101 {
 126                         device_type = "cpu";
 127                         compatible = "arm,cortex-a55";
 128                         reg = <0x101>;
 129                         enable-method = "psci";
 130                 };
 131                 cpu6: cpu@102 {
 132                         device_type = "cpu";
 133                         compatible = "arm,cortex-a55";
 134                         reg = <0x102>;
 135                         enable-method = "psci";
 136                 };
 137                 cpu7: cpu@103 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a55";
 140                         reg = <0x103>;
 141                         enable-method = "psci";
 142                 };
 143         };
 144
 145         psci {
 146                 compatible = "arm,psci-1.0";
 147                 method = "smc";
 148         };
 149
 150         timer {
 151                 compatible = "arm,armv8-timer";
 152                 /* Hypervisor Virtual Timer interrupt is not wired to GIC */
 153                 interrupts =
 154                      <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 155                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 156                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 157                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 158         };
 159
 160         soc: soc@0 {
 161                 compatible = "simple-bus";
 162                 #address-cells = <1>;
 163                 #size-cells = <1>;
 164                 ranges = <0x0 0x0 0x0 0x20000000>;
 165
 166                 chipid@10000000 {
 167                         compatible = "samsung,exynos850-chipid";
 168                         reg = <0x10000000 0x100>;
 169                 };
 170
 171                 timer@10040000 {
 172                         compatible = "samsung,exynos850-mct",
 173                                      "samsung,exynos4210-mct";
 174                         reg = <0x10040000 0x800>;
 175                         interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
 176                                      <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
 177                                      <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
 178                                      <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
 179                                      <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
 180                                      <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 181                                      <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
 182                                      <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 183                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 184                                      <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 185                                      <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 186                                      <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 187                         clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>;
 188                         clock-names = "fin_pll", "mct";
 189                 };
 190
 191                 pdma0: dma-controller@120c0000 {
 192                         compatible = "arm,pl330", "arm,primecell";
 193                         reg = <0x120c0000 0x1000>;
 194                         clocks = <&cmu_core CLK_GOUT_PDMA_CORE_ACLK>;
 195                         clock-names = "apb_pclk";
 196                         #dma-cells = <1>;
 197                         interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
 198                         arm,pl330-broken-no-flushp;
 199                 };
 200
 201                 gic: interrupt-controller@12a01000 {
 202                         compatible = "arm,gic-400";
 203                         #interrupt-cells = <3>;
 204                         #address-cells = <0>;
 205                         reg = <0x12a01000 0x1000>,
 206                               <0x12a02000 0x2000>,
 207                               <0x12a04000 0x2000>,
 208                               <0x12a06000 0x2000>;
 209                         interrupt-controller;
 210                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
 211                                                  IRQ_TYPE_LEVEL_HIGH)>;
 212                 };
 213
 214                 pmu_system_controller: system-controller@11860000 {
 215                         compatible = "samsung,exynos850-pmu", "syscon";
 216                         reg = <0x11860000 0x10000>;
 217
 218                         reboot: syscon-reboot {
 219                                 compatible = "syscon-reboot";
 220                                 regmap = <&pmu_system_controller>;
 221                                 offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
 222                                 mask = <0x2>; /* SWRESET_SYSTEM */
 223                                 value = <0x2>; /* reset value */
 224                         };
 225                 };
 226
 227                 watchdog_cl0: watchdog@10050000 {
 228                         compatible = "samsung,exynos850-wdt";
 229                         reg = <0x10050000 0x100>;
 230                         interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
 231                         clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>;
 232                         clock-names = "watchdog", "watchdog_src";
 233                         samsung,syscon-phandle = <&pmu_system_controller>;
 234                         samsung,cluster-index = <0>;
 235                         status = "disabled";
 236                 };
 237
 238                 watchdog_cl1: watchdog@10060000 {
 239                         compatible = "samsung,exynos850-wdt";
 240                         reg = <0x10060000 0x100>;
 241                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 242                         clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>;
 243                         clock-names = "watchdog", "watchdog_src";
 244                         samsung,syscon-phandle = <&pmu_system_controller>;
 245                         samsung,cluster-index = <1>;
 246                         status = "disabled";
 247                 };
 248
 249                 cmu_peri: clock-controller@10030000 {
 250                         compatible = "samsung,exynos850-cmu-peri";
 251                         reg = <0x10030000 0x8000>;
 252                         #clock-cells = <1>;
 253
 254                         clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
 255                                  <&cmu_top CLK_DOUT_PERI_UART>,
 256                                  <&cmu_top CLK_DOUT_PERI_IP>;
 257                         clock-names = "oscclk", "dout_peri_bus",
 258                                       "dout_peri_uart", "dout_peri_ip";
 259                 };
 260
 261                 cmu_cpucl1: clock-controller@10800000 {
 262                         compatible = "samsung,exynos850-cmu-cpucl1";
 263                         reg = <0x10800000 0x8000>;
 264                         #clock-cells = <1>;
 265
 266                         clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL1_SWITCH>,
 267                                  <&cmu_top CLK_DOUT_CPUCL1_DBG>;
 268                         clock-names = "oscclk", "dout_cpucl1_switch",
 269                                       "dout_cpucl1_dbg";
 270                 };
 271
 272                 cmu_cpucl0: clock-controller@10900000 {
 273                         compatible = "samsung,exynos850-cmu-cpucl0";
 274                         reg = <0x10900000 0x8000>;
 275                         #clock-cells = <1>;
 276
 277                         clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL0_SWITCH>,
 278                                  <&cmu_top CLK_DOUT_CPUCL0_DBG>;
 279                         clock-names = "oscclk", "dout_cpucl0_switch",
 280                                       "dout_cpucl0_dbg";
 281                 };
 282
 283                 cmu_g3d: clock-controller@11400000 {
 284                         compatible = "samsung,exynos850-cmu-g3d";
 285                         reg = <0x11400000 0x8000>;
 286                         #clock-cells = <1>;
 287
 288                         clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>;
 289                         clock-names = "oscclk", "dout_g3d_switch";
 290                 };
 291
 292                 cmu_apm: clock-controller@11800000 {
 293                         compatible = "samsung,exynos850-cmu-apm";
 294                         reg = <0x11800000 0x8000>;
 295                         #clock-cells = <1>;
 296
 297                         clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>;
 298                         clock-names = "oscclk", "dout_clkcmu_apm_bus";
 299                 };
 300
 301                 cmu_cmgp: clock-controller@11c00000 {
 302                         compatible = "samsung,exynos850-cmu-cmgp";
 303                         reg = <0x11c00000 0x8000>;
 304                         #clock-cells = <1>;
 305
 306                         clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>;
 307                         clock-names = "oscclk", "gout_clkcmu_cmgp_bus";
 308                 };
 309
 310                 cmu_core: clock-controller@12000000 {
 311                         compatible = "samsung,exynos850-cmu-core";
 312                         reg = <0x12000000 0x8000>;
 313                         #clock-cells = <1>;
 314
 315                         clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>,
 316                                  <&cmu_top CLK_DOUT_CORE_CCI>,
 317                                  <&cmu_top CLK_DOUT_CORE_MMC_EMBD>,
 318                                  <&cmu_top CLK_DOUT_CORE_SSS>;
 319                         clock-names = "oscclk", "dout_core_bus",
 320                                       "dout_core_cci", "dout_core_mmc_embd",
 321                                       "dout_core_sss";
 322                 };
 323
 324                 cmu_top: clock-controller@120e0000 {
 325                         compatible = "samsung,exynos850-cmu-top";
 326                         reg = <0x120e0000 0x8000>;
 327                         #clock-cells = <1>;
 328
 329                         clocks = <&oscclk>;
 330                         clock-names = "oscclk";
 331                 };
 332
 333                 cmu_mfcmscl: clock-controller@12c00000 {
 334                         compatible = "samsung,exynos850-cmu-mfcmscl";
 335                         reg = <0x12c00000 0x8000>;
 336                         #clock-cells = <1>;
 337
 338                         clocks = <&oscclk>,
 339                                  <&cmu_top CLK_DOUT_MFCMSCL_MFC>,
 340                                  <&cmu_top CLK_DOUT_MFCMSCL_M2M>,
 341                                  <&cmu_top CLK_DOUT_MFCMSCL_MCSC>,
 342                                  <&cmu_top CLK_DOUT_MFCMSCL_JPEG>;
 343                         clock-names = "oscclk", "dout_mfcmscl_mfc",
 344                                       "dout_mfcmscl_m2m", "dout_mfcmscl_mcsc",
 345                                       "dout_mfcmscl_jpeg";
 346                 };
 347
 348                 cmu_dpu: clock-controller@13000000 {
 349                         compatible = "samsung,exynos850-cmu-dpu";
 350                         reg = <0x13000000 0x8000>;
 351                         #clock-cells = <1>;
 352
 353                         clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>;
 354                         clock-names = "oscclk", "dout_dpu";
 355                 };
 356
 357                 cmu_hsi: clock-controller@13400000 {
 358                         compatible = "samsung,exynos850-cmu-hsi";
 359                         reg = <0x13400000 0x8000>;
 360                         #clock-cells = <1>;
 361
 362                         clocks = <&oscclk>,
 363                                  <&cmu_top CLK_DOUT_HSI_BUS>,
 364                                  <&cmu_top CLK_DOUT_HSI_MMC_CARD>,
 365                                  <&cmu_top CLK_DOUT_HSI_USB20DRD>;
 366                         clock-names = "oscclk", "dout_hsi_bus",
 367                                       "dout_hsi_mmc_card", "dout_hsi_usb20drd";
 368                 };
 369
 370                 cmu_is: clock-controller@14500000 {
 371                         compatible = "samsung,exynos850-cmu-is";
 372                         reg = <0x14500000 0x8000>;
 373                         #clock-cells = <1>;
 374
 375                         clocks = <&oscclk>,
 376                                  <&cmu_top CLK_DOUT_IS_BUS>,
 377                                  <&cmu_top CLK_DOUT_IS_ITP>,
 378                                  <&cmu_top CLK_DOUT_IS_VRA>,
 379                                  <&cmu_top CLK_DOUT_IS_GDC>;
 380                         clock-names = "oscclk", "dout_is_bus", "dout_is_itp",
 381                                       "dout_is_vra", "dout_is_gdc";
 382                 };
 383
 384                 cmu_aud: clock-controller@14a00000 {
 385                         compatible = "samsung,exynos850-cmu-aud";
 386                         reg = <0x14a00000 0x8000>;
 387                         #clock-cells = <1>;
 388
 389                         clocks = <&oscclk>, <&cmu_top CLK_DOUT_AUD>;
 390                         clock-names = "oscclk", "dout_aud";
 391                 };
 392
 393                 pinctrl_alive: pinctrl@11850000 {
 394                         compatible = "samsung,exynos850-pinctrl";
 395                         reg = <0x11850000 0x1000>;
 396
 397                         wakeup-interrupt-controller {
 398                                 compatible = "samsung,exynos850-wakeup-eint",
 399                                              "samsung,exynos7-wakeup-eint";
 400                         };
 401                 };
 402
 403                 pinctrl_cmgp: pinctrl@11c30000 {
 404                         compatible = "samsung,exynos850-pinctrl";
 405                         reg = <0x11c30000 0x1000>;
 406
 407                         wakeup-interrupt-controller {
 408                                 compatible = "samsung,exynos850-wakeup-eint",
 409                                              "samsung,exynos7-wakeup-eint";
 410                         };
 411                 };
 412
 413                 pinctrl_core: pinctrl@12070000 {
 414                         compatible = "samsung,exynos850-pinctrl";
 415                         reg = <0x12070000 0x1000>;
 416                         interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>;
 417                 };
 418
 419                 pinctrl_hsi: pinctrl@13430000 {
 420                         compatible = "samsung,exynos850-pinctrl";
 421                         reg = <0x13430000 0x1000>;
 422                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 423                 };
 424
 425                 pinctrl_peri: pinctrl@139b0000 {
 426                         compatible = "samsung,exynos850-pinctrl";
 427                         reg = <0x139b0000 0x1000>;
 428                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 429                 };
 430
 431                 pinctrl_aud: pinctrl@14a60000 {
 432                         compatible = "samsung,exynos850-pinctrl";
 433                         reg = <0x14a60000 0x1000>;
 434                 };
 435
 436                 rtc: rtc@11a30000 {
 437                         compatible = "samsung,exynos850-rtc", "samsung,s3c6410-rtc";
 438                         reg = <0x11a30000 0x100>;
 439                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 440                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 441                         clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>;
 442                         clock-names = "rtc";
 443                         status = "disabled";
 444                 };
 445
 446                 mmc_0: mmc@12100000 {
 447                         compatible = "samsung,exynos850-dw-mshc-smu",
 448                                      "samsung,exynos7-dw-mshc-smu";
 449                         reg = <0x12100000 0x2000>;
 450                         interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
 451                         #address-cells = <1>;
 452                         #size-cells = <0>;
 453                         clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>,
 454                                  <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>;
 455                         clock-names = "biu", "ciu";
 456                         fifo-depth = <0x40>;
 457                         status = "disabled";
 458                 };
 459
 460                 i2c_0: i2c@13830000 {
 461                         compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c";
 462                         reg = <0x13830000 0x100>;
 463                         interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 464                         #address-cells = <1>;
 465                         #size-cells = <0>;
 466                         pinctrl-names = "default";
 467                         pinctrl-0 = <&i2c0_pins>;
 468                         clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>;
 469                         clock-names = "i2c";
 470                         status = "disabled";
 471                 };
 472
 473                 i2c_1: i2c@13840000 {
 474                         compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c";
 475                         reg = <0x13840000 0x100>;
 476                         interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 477                         #address-cells = <1>;
 478                         #size-cells = <0>;
 479                         pinctrl-names = "default";
 480                         pinctrl-0 = <&i2c1_pins>;
 481                         clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>;
 482                         clock-names = "i2c";
 483                         status = "disabled";
 484                 };
 485
 486                 i2c_2: i2c@13850000 {
 487                         compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c";
 488                         reg = <0x13850000 0x100>;
 489                         interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
 490                         #address-cells = <1>;
 491                         #size-cells = <0>;
 492                         pinctrl-names = "default";
 493                         pinctrl-0 = <&i2c2_pins>;
 494                         clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>;
 495                         clock-names = "i2c";
 496                         status = "disabled";
 497                 };
 498
 499                 i2c_3: i2c@13860000 {
 500                         compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c";
 501                         reg = <0x13860000 0x100>;
 502                         interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 503                         #address-cells = <1>;
 504                         #size-cells = <0>;
 505                         pinctrl-names = "default";
 506                         pinctrl-0 = <&i2c3_pins>;
 507                         clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>;
 508                         clock-names = "i2c";
 509                         status = "disabled";
 510                 };
 511
 512                 i2c_4: i2c@13870000 {
 513                         compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c";
 514                         reg = <0x13870000 0x100>;
 515                         interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 516                         #address-cells = <1>;
 517                         #size-cells = <0>;
 518                         pinctrl-names = "default";
 519                         pinctrl-0 = <&i2c4_pins>;
 520                         clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>;
 521                         clock-names = "i2c";
 522                         status = "disabled";
 523                 };
 524
 525                 /* I2C_5 (also called CAM_PMIC_I2C in TRM) */
 526                 i2c_5: i2c@13880000 {
 527                         compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c";
 528                         reg = <0x13880000 0x100>;
 529                         interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 530                         #address-cells = <1>;
 531                         #size-cells = <0>;
 532                         pinctrl-names = "default";
 533                         pinctrl-0 = <&i2c5_pins>;
 534                         clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>;
 535                         clock-names = "i2c";
 536                         status = "disabled";
 537                 };
 538
 539                 /* I2C_6 (also called MOTOR_I2C in TRM) */
 540                 i2c_6: i2c@13890000 {
 541                         compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c";
 542                         reg = <0x13890000 0x100>;
 543                         interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 544                         #address-cells = <1>;
 545                         #size-cells = <0>;
 546                         pinctrl-names = "default";
 547                         pinctrl-0 = <&i2c6_pins>;
 548                         clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>;
 549                         clock-names = "i2c";
 550                         status = "disabled";
 551                 };
 552
 553                 sysmmu_mfcmscl: sysmmu@12c50000 {
 554                         compatible = "samsung,exynos-sysmmu";
 555                         reg = <0x12c50000 0x9000>;
 556                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 557                         clock-names = "sysmmu";
 558                         clocks = <&cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK>;
 559                         #iommu-cells = <0>;
 560                 };
 561
 562                 sysmmu_dpu: sysmmu@130c0000 {
 563                         compatible = "samsung,exynos-sysmmu";
 564                         reg = <0x130c0000 0x9000>;
 565                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 566                         clock-names = "sysmmu";
 567                         clocks = <&cmu_dpu CLK_GOUT_DPU_SMMU_CLK>;
 568                         #iommu-cells = <0>;
 569                 };
 570
 571                 sysmmu_is0: sysmmu@14550000 {
 572                         compatible = "samsung,exynos-sysmmu";
 573                         reg = <0x14550000 0x9000>;
 574                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 575                         clock-names = "sysmmu";
 576                         clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK>;
 577                         #iommu-cells = <0>;
 578                 };
 579
 580                 sysmmu_is1: sysmmu@14570000 {
 581                         compatible = "samsung,exynos-sysmmu";
 582                         reg = <0x14570000 0x9000>;
 583                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 584                         clock-names = "sysmmu";
 585                         clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK>;
 586                         #iommu-cells = <0>;
 587                 };
 588
 589                 sysmmu_aud: sysmmu@14850000 {
 590                         compatible = "samsung,exynos-sysmmu";
 591                         reg = <0x14850000 0x9000>;
 592                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 593                         clock-names = "sysmmu";
 594                         clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>;
 595                         #iommu-cells = <0>;
 596                 };
 597
 598                 sysreg_peri: syscon@10020000 {
 599                         compatible = "samsung,exynos850-peri-sysreg",
 600                                      "samsung,exynos850-sysreg", "syscon";
 601                         reg = <0x10020000 0x10000>;
 602                         clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>;
 603                 };
 604
 605                 sysreg_cmgp: syscon@11c20000 {
 606                         compatible = "samsung,exynos850-cmgp-sysreg",
 607                                      "samsung,exynos850-sysreg", "syscon";
 608                         reg = <0x11c20000 0x10000>;
 609                         clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>;
 610                 };
 611
 612                 usbdrd: usb@13600000 {
 613                         compatible = "samsung,exynos850-dwusb3";
 614                         ranges = <0x0 0x13600000 0x10000>;
 615                         clocks = <&cmu_hsi CLK_GOUT_USB_BUS_EARLY_CLK>,
 616                                  <&cmu_hsi CLK_GOUT_USB_REF_CLK>;
 617                         clock-names = "bus_early", "ref";
 618                         #address-cells = <1>;
 619                         #size-cells = <1>;
 620                         status = "disabled";
 621
 622                         usbdrd_dwc3: usb@0 {
 623                                 compatible = "snps,dwc3";
 624                                 reg = <0x0 0x10000>;
 625                                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 626                                 phys = <&usbdrd_phy 0>;
 627                                 phy-names = "usb2-phy";
 628                         };
 629                 };
 630
 631                 usbdrd_phy: phy@135d0000 {
 632                         compatible = "samsung,exynos850-usbdrd-phy";
 633                         reg = <0x135d0000 0x100>;
 634                         clocks = <&cmu_hsi CLK_GOUT_USB_PHY_ACLK>,
 635                                  <&cmu_hsi CLK_GOUT_USB_PHY_REF_CLK>;
 636                         clock-names = "phy", "ref";
 637                         samsung,pmu-syscon = <&pmu_system_controller>;
 638                         #phy-cells = <1>;
 639                         status = "disabled";
 640                 };
 641
 642                 usi_uart: usi@138200c0 {
 643                         compatible = "samsung,exynos850-usi";
 644                         reg = <0x138200c0 0x20>;
 645                         samsung,sysreg = <&sysreg_peri 0x1010>;
 646                         samsung,mode = <USI_V2_UART>;
 647                         #address-cells = <1>;
 648                         #size-cells = <1>;
 649                         ranges;
 650                         clocks = <&cmu_peri CLK_GOUT_UART_PCLK>,
 651                                  <&cmu_peri CLK_GOUT_UART_IPCLK>;
 652                         clock-names = "pclk", "ipclk";
 653                         status = "disabled";
 654
 655                         serial_0: serial@13820000 {
 656                                 compatible = "samsung,exynos850-uart";
 657                                 reg = <0x13820000 0xc0>;
 658                                 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
 659                                 pinctrl-names = "default";
 660                                 pinctrl-0 = <&uart0_pins>;
 661                                 clocks = <&cmu_peri CLK_GOUT_UART_PCLK>,
 662                                          <&cmu_peri CLK_GOUT_UART_IPCLK>;
 663                                 clock-names = "uart", "clk_uart_baud0";
 664                                 status = "disabled";
 665                         };
 666                 };
 667
 668                 usi_hsi2c_0: usi@138a00c0 {
 669                         compatible = "samsung,exynos850-usi";
 670                         reg = <0x138a00c0 0x20>;
 671                         samsung,sysreg = <&sysreg_peri 0x1020>;
 672                         samsung,mode = <USI_V2_I2C>;
 673                         #address-cells = <1>;
 674                         #size-cells = <1>;
 675                         ranges;
 676                         clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>,
 677                                  <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>;
 678                         clock-names = "pclk", "ipclk";
 679                         status = "disabled";
 680
 681                         hsi2c_0: i2c@138a0000 {
 682                                 compatible = "samsung,exynos850-hsi2c",
 683                                              "samsung,exynosautov9-hsi2c";
 684                                 reg = <0x138a0000 0xc0>;
 685                                 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 686                                 #address-cells = <1>;
 687                                 #size-cells = <0>;
 688                                 pinctrl-names = "default";
 689                                 pinctrl-0 = <&hsi2c0_pins>;
 690                                 clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>,
 691                                          <&cmu_peri CLK_GOUT_HSI2C0_PCLK>;
 692                                 clock-names = "hsi2c", "hsi2c_pclk";
 693                                 status = "disabled";
 694                         };
 695                 };
 696
 697                 usi_hsi2c_1: usi@138b00c0 {
 698                         compatible = "samsung,exynos850-usi";
 699                         reg = <0x138b00c0 0x20>;
 700                         samsung,sysreg = <&sysreg_peri 0x1030>;
 701                         samsung,mode = <USI_V2_I2C>;
 702                         #address-cells = <1>;
 703                         #size-cells = <1>;
 704                         ranges;
 705                         clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>,
 706                                  <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>;
 707                         clock-names = "pclk", "ipclk";
 708                         status = "disabled";
 709
 710                         hsi2c_1: i2c@138b0000 {
 711                                 compatible = "samsung,exynos850-hsi2c",
 712                                              "samsung,exynosautov9-hsi2c";
 713                                 reg = <0x138b0000 0xc0>;
 714                                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 715                                 #address-cells = <1>;
 716                                 #size-cells = <0>;
 717                                 pinctrl-names = "default";
 718                                 pinctrl-0 = <&hsi2c1_pins>;
 719                                 clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>,
 720                                          <&cmu_peri CLK_GOUT_HSI2C1_PCLK>;
 721                                 clock-names = "hsi2c", "hsi2c_pclk";
 722                                 status = "disabled";
 723                         };
 724                 };
 725
 726                 usi_hsi2c_2: usi@138c00c0 {
 727                         compatible = "samsung,exynos850-usi";
 728                         reg = <0x138c00c0 0x20>;
 729                         samsung,sysreg = <&sysreg_peri 0x1040>;
 730                         samsung,mode = <USI_V2_I2C>;
 731                         #address-cells = <1>;
 732                         #size-cells = <1>;
 733                         ranges;
 734                         clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>,
 735                                  <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>;
 736                         clock-names = "pclk", "ipclk";
 737                         status = "disabled";
 738
 739                         hsi2c_2: i2c@138c0000 {
 740                                 compatible = "samsung,exynos850-hsi2c",
 741                                              "samsung,exynosautov9-hsi2c";
 742                                 reg = <0x138c0000 0xc0>;
 743                                 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 744                                 #address-cells = <1>;
 745                                 #size-cells = <0>;
 746                                 pinctrl-names = "default";
 747                                 pinctrl-0 = <&hsi2c2_pins>;
 748                                 clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>,
 749                                          <&cmu_peri CLK_GOUT_HSI2C2_PCLK>;
 750                                 clock-names = "hsi2c", "hsi2c_pclk";
 751                                 status = "disabled";
 752                         };
 753                 };
 754
 755                 usi_spi_0: usi@139400c0 {
 756                         compatible = "samsung,exynos850-usi";
 757                         reg = <0x139400c0 0x20>;
 758                         samsung,sysreg = <&sysreg_peri 0x1050>;
 759                         samsung,mode = <USI_V2_SPI>;
 760                         #address-cells = <1>;
 761                         #size-cells = <1>;
 762                         ranges;
 763                         clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>,
 764                                  <&cmu_peri CLK_GOUT_SPI0_IPCLK>;
 765                         clock-names = "pclk", "ipclk";
 766                         status = "disabled";
 767
 768                         spi_0: spi@13940000 {
 769                                 compatible = "samsung,exynos850-spi";
 770                                 reg = <0x13940000 0x30>;
 771                                 clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>,
 772                                          <&cmu_peri CLK_GOUT_SPI0_IPCLK>;
 773                                 clock-names = "spi", "spi_busclk0";
 774                                 dmas = <&pdma0 5>, <&pdma0 4>;
 775                                 dma-names = "tx", "rx";
 776                                 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 777                                 pinctrl-0 = <&spi0_pins>;
 778                                 pinctrl-names = "default";
 779                                 num-cs = <1>;
 780                                 samsung,spi-src-clk = <0>;
 781                                 #address-cells = <1>;
 782                                 #size-cells = <0>;
 783                                 status = "disabled";
 784                         };
 785                 };
 786
 787                 usi_cmgp0: usi@11d000c0 {
 788                         compatible = "samsung,exynos850-usi";
 789                         reg = <0x11d000c0 0x20>;
 790                         samsung,sysreg = <&sysreg_cmgp 0x2000>;
 791                         samsung,mode = <USI_V2_I2C>;
 792                         #address-cells = <1>;
 793                         #size-cells = <1>;
 794                         ranges;
 795                         clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
 796                                  <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
 797                         clock-names = "pclk", "ipclk";
 798                         status = "disabled";
 799
 800                         hsi2c_3: i2c@11d00000 {
 801                                 compatible = "samsung,exynos850-hsi2c",
 802                                              "samsung,exynosautov9-hsi2c";
 803                                 reg = <0x11d00000 0xc0>;
 804                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 805                                 #address-cells = <1>;
 806                                 #size-cells = <0>;
 807                                 pinctrl-names = "default";
 808                                 pinctrl-0 = <&hsi2c3_pins>;
 809                                 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>,
 810                                          <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>;
 811                                 clock-names = "hsi2c", "hsi2c_pclk";
 812                                 status = "disabled";
 813                         };
 814
 815                         serial_1: serial@11d00000 {
 816                                 compatible = "samsung,exynos850-uart";
 817                                 reg = <0x11d00000 0xc0>;
 818                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 819                                 pinctrl-names = "default";
 820                                 pinctrl-0 = <&uart1_single_pins>;
 821                                 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
 822                                          <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
 823                                 clock-names = "uart", "clk_uart_baud0";
 824                                 status = "disabled";
 825                         };
 826
 827                         spi_1: spi@11d00000 {
 828                                 compatible = "samsung,exynos850-spi";
 829                                 reg = <0x11d00000 0x30>;
 830                                 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
 831                                          <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
 832                                 clock-names = "spi", "spi_busclk0";
 833                                 dmas = <&pdma0 12>, <&pdma0 13>;
 834                                 dma-names = "tx", "rx";
 835                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 836                                 pinctrl-0 = <&spi1_pins>;
 837                                 pinctrl-names = "default";
 838                                 num-cs = <1>;
 839                                 samsung,spi-src-clk = <0>;
 840                                 #address-cells = <1>;
 841                                 #size-cells = <0>;
 842                                 status = "disabled";
 843                         };
 844                 };
 845
 846                 usi_cmgp1: usi@11d200c0 {
 847                         compatible = "samsung,exynos850-usi";
 848                         reg = <0x11d200c0 0x20>;
 849                         samsung,sysreg = <&sysreg_cmgp 0x2010>;
 850                         samsung,mode = <USI_V2_I2C>;
 851                         #address-cells = <1>;
 852                         #size-cells = <1>;
 853                         ranges;
 854                         clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
 855                                  <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
 856                         clock-names = "pclk", "ipclk";
 857                         status = "disabled";
 858
 859                         hsi2c_4: i2c@11d20000 {
 860                                 compatible = "samsung,exynos850-hsi2c",
 861                                              "samsung,exynosautov9-hsi2c";
 862                                 reg = <0x11d20000 0xc0>;
 863                                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 864                                 #address-cells = <1>;
 865                                 #size-cells = <0>;
 866                                 pinctrl-names = "default";
 867                                 pinctrl-0 = <&hsi2c4_pins>;
 868                                 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>,
 869                                          <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>;
 870                                 clock-names = "hsi2c", "hsi2c_pclk";
 871                                 status = "disabled";
 872                         };
 873
 874                         serial_2: serial@11d20000 {
 875                                 compatible = "samsung,exynos850-uart";
 876                                 reg = <0x11d20000 0xc0>;
 877                                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 878                                 pinctrl-names = "default";
 879                                 pinctrl-0 = <&uart2_single_pins>;
 880                                 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
 881                                          <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
 882                                 clock-names = "uart", "clk_uart_baud0";
 883                                 status = "disabled";
 884                         };
 885
 886                         spi_2: spi@11d20000 {
 887                                 compatible = "samsung,exynos850-spi";
 888                                 reg = <0x11d20000 0x30>;
 889                                 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
 890                                          <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
 891                                 clock-names = "spi", "spi_busclk0";
 892                                 dmas = <&pdma0 14>, <&pdma0 15>;
 893                                 dma-names = "tx", "rx";
 894                                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 895                                 pinctrl-0 = <&spi2_pins>;
 896                                 pinctrl-names = "default";
 897                                 num-cs = <1>;
 898                                 samsung,spi-src-clk = <0>;
 899                                 #address-cells = <1>;
 900                                 #size-cells = <0>;
 901                                 status = "disabled";
 902                         };
 903                 };
 904         };
 905 };
 906
 907 #include "exynos850-pinctrl.dtsi"