arch/arm64/boot/dts/nvidia/tegra234.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 #include <dt-bindings/clock/tegra234-clock.h>
   4 #include <dt-bindings/gpio/tegra234-gpio.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/mailbox/tegra186-hsp.h>
   7 #include <dt-bindings/memory/tegra234-mc.h>
   8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
   9 #include <dt-bindings/power/tegra234-powergate.h>
  10 #include <dt-bindings/reset/tegra234-reset.h>
  11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
  12
  13 / {
  14         compatible = "nvidia,tegra234";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         bus@0 {
  20                 compatible = "simple-bus";
  21
  22                 #address-cells = <2>;
  23                 #size-cells = <2>;
  24                 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
  25
  26                 misc@100000 {
  27                         compatible = "nvidia,tegra234-misc";
  28                         reg = <0x0 0x00100000 0x0 0xf000>,
  29                               <0x0 0x0010f000 0x0 0x1000>;
  30                         status = "okay";
  31                 };
  32
  33                 timer@2080000 {
  34                         compatible = "nvidia,tegra234-timer";
  35                         reg = <0x0 0x02080000 0x0 0x00121000>;
  36                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  37                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  38                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  39                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
  40                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  41                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
  42                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  43                                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  44                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  45                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  46                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
  47                                      <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
  48                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
  49                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
  50                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
  51                                      <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
  52                         status = "okay";
  53                 };
  54
  55                 gpio: gpio@2200000 {
  56                         compatible = "nvidia,tegra234-gpio";
  57                         reg-names = "security", "gpio";
  58                         reg = <0x0 0x02200000 0x0 0x10000>,
  59                               <0x0 0x02210000 0x0 0x10000>;
  60                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
  61                                      <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
  62                                      <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
  63                                      <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
  64                                      <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
  65                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
  66                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
  67                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
  68                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
  69                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
  70                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
  71                                      <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
  72                                      <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
  73                                      <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
  74                                      <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
  75                                      <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
  76                                      <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
  77                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
  78                                      <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
  79                                      <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
  80                                      <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
  81                                      <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
  82                                      <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
  83                                      <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
  84                                      <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
  85                                      <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
  86                                      <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
  87                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
  88                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
  89                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
  90                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
  91                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
  92                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
  93                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
  94                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
  95                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
  96                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
  97                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
  98                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
  99                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
 100                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
 101                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
 102                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
 103                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
 104                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
 105                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
 106                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
 107                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
 108                         #interrupt-cells = <2>;
 109                         interrupt-controller;
 110                         #gpio-cells = <2>;
 111                         gpio-controller;
 112                         gpio-ranges = <&pinmux 0 0 164>;
 113                 };
 114
 115                 pinmux: pinmux@2430000 {
 116                         compatible = "nvidia,tegra234-pinmux";
 117                         reg = <0x0 0x2430000 0x0 0x19100>;
 118                 };
 119
 120                 gpcdma: dma-controller@2600000 {
 121                         compatible = "nvidia,tegra234-gpcdma",
 122                                      "nvidia,tegra186-gpcdma";
 123                         reg = <0x0 0x2600000 0x0 0x210000>;
 124                         resets = <&bpmp TEGRA234_RESET_GPCDMA>;
 125                         reset-names = "gpcdma";
 126                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
 127                                      <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 128                                      <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 129                                      <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 130                                      <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
 131                                      <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
 132                                      <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
 133                                      <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
 134                                      <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
 135                                      <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 136                                      <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 137                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
 138                                      <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 139                                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 140                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 141                                      <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 142                                      <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 143                                      <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 144                                      <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 145                                      <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
 146                                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 147                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 148                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 149                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 150                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 151                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 152                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 153                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 154                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 155                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 156                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 157                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 158                         #dma-cells = <1>;
 159                         iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
 160                         dma-channel-mask = <0xfffffffe>;
 161                         dma-coherent;
 162                 };
 163
 164                 aconnect@2900000 {
 165                         compatible = "nvidia,tegra234-aconnect",
 166                                      "nvidia,tegra210-aconnect";
 167                         clocks = <&bpmp TEGRA234_CLK_APE>,
 168                                  <&bpmp TEGRA234_CLK_APB2APE>;
 169                         clock-names = "ape", "apb2ape";
 170                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>;
 171                         status = "disabled";
 172
 173                         #address-cells = <2>;
 174                         #size-cells = <2>;
 175                         ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>;
 176
 177                         tegra_ahub: ahub@2900800 {
 178                                 compatible = "nvidia,tegra234-ahub";
 179                                 reg = <0x0 0x02900800 0x0 0x800>;
 180                                 clocks = <&bpmp TEGRA234_CLK_AHUB>;
 181                                 clock-names = "ahub";
 182                                 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
 183                                 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
 184                                 assigned-clock-rates = <81600000>;
 185                                 status = "disabled";
 186
 187                                 #address-cells = <2>;
 188                                 #size-cells = <2>;
 189                                 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>;
 190
 191                                 tegra_i2s1: i2s@2901000 {
 192                                         compatible = "nvidia,tegra234-i2s",
 193                                                      "nvidia,tegra210-i2s";
 194                                         reg = <0x0 0x2901000 0x0 0x100>;
 195                                         clocks = <&bpmp TEGRA234_CLK_I2S1>,
 196                                                  <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>;
 197                                         clock-names = "i2s", "sync_input";
 198                                         assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>;
 199                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
 200                                         assigned-clock-rates = <1536000>;
 201                                         sound-name-prefix = "I2S1";
 202                                         status = "disabled";
 203
 204                                         ports {
 205                                                 #address-cells = <1>;
 206                                                 #size-cells = <0>;
 207
 208                                                 port@0 {
 209                                                         reg = <0>;
 210
 211                                                         i2s1_cif: endpoint {
 212                                                                 remote-endpoint = <&xbar_i2s1>;
 213                                                         };
 214                                                 };
 215
 216                                                 i2s1_port: port@1 {
 217                                                         reg = <1>;
 218
 219                                                         i2s1_dap: endpoint {
 220                                                                 dai-format = "i2s";
 221                                                                 /* placeholder for external codec */
 222                                                         };
 223                                                 };
 224                                         };
 225                                 };
 226
 227                                 tegra_i2s2: i2s@2901100 {
 228                                         compatible = "nvidia,tegra234-i2s",
 229                                                      "nvidia,tegra210-i2s";
 230                                         reg = <0x0 0x2901100 0x0 0x100>;
 231                                         clocks = <&bpmp TEGRA234_CLK_I2S2>,
 232                                                  <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>;
 233                                         clock-names = "i2s", "sync_input";
 234                                         assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>;
 235                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
 236                                         assigned-clock-rates = <1536000>;
 237                                         sound-name-prefix = "I2S2";
 238                                         status = "disabled";
 239
 240                                         ports {
 241                                                 #address-cells = <1>;
 242                                                 #size-cells = <0>;
 243
 244                                                 port@0 {
 245                                                         reg = <0>;
 246
 247                                                         i2s2_cif: endpoint {
 248                                                                 remote-endpoint = <&xbar_i2s2>;
 249                                                         };
 250                                                 };
 251
 252                                                 i2s2_port: port@1 {
 253                                                         reg = <1>;
 254
 255                                                         i2s2_dap: endpoint {
 256                                                                 dai-format = "i2s";
 257                                                                 /* placeholder for external codec */
 258                                                         };
 259                                                 };
 260                                         };
 261                                 };
 262
 263                                 tegra_i2s3: i2s@2901200 {
 264                                         compatible = "nvidia,tegra234-i2s",
 265                                                      "nvidia,tegra210-i2s";
 266                                         reg = <0x0 0x2901200 0x0 0x100>;
 267                                         clocks = <&bpmp TEGRA234_CLK_I2S3>,
 268                                                  <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>;
 269                                         clock-names = "i2s", "sync_input";
 270                                         assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>;
 271                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
 272                                         assigned-clock-rates = <1536000>;
 273                                         sound-name-prefix = "I2S3";
 274                                         status = "disabled";
 275
 276                                         ports {
 277                                                 #address-cells = <1>;
 278                                                 #size-cells = <0>;
 279
 280                                                 port@0 {
 281                                                         reg = <0>;
 282
 283                                                         i2s3_cif: endpoint {
 284                                                                 remote-endpoint = <&xbar_i2s3>;
 285                                                         };
 286                                                 };
 287
 288                                                 i2s3_port: port@1 {
 289                                                         reg = <1>;
 290
 291                                                         i2s3_dap: endpoint {
 292                                                                 dai-format = "i2s";
 293                                                                 /* placeholder for external codec */
 294                                                         };
 295                                                 };
 296                                         };
 297                                 };
 298
 299                                 tegra_i2s4: i2s@2901300 {
 300                                         compatible = "nvidia,tegra234-i2s",
 301                                                      "nvidia,tegra210-i2s";
 302                                         reg = <0x0 0x2901300 0x0 0x100>;
 303                                         clocks = <&bpmp TEGRA234_CLK_I2S4>,
 304                                                  <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>;
 305                                         clock-names = "i2s", "sync_input";
 306                                         assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>;
 307                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
 308                                         assigned-clock-rates = <1536000>;
 309                                         sound-name-prefix = "I2S4";
 310                                         status = "disabled";
 311
 312                                         ports {
 313                                                 #address-cells = <1>;
 314                                                 #size-cells = <0>;
 315
 316                                                 port@0 {
 317                                                         reg = <0>;
 318
 319                                                         i2s4_cif: endpoint {
 320                                                                 remote-endpoint = <&xbar_i2s4>;
 321                                                         };
 322                                                 };
 323
 324                                                 i2s4_port: port@1 {
 325                                                         reg = <1>;
 326
 327                                                         i2s4_dap: endpoint {
 328                                                                 dai-format = "i2s";
 329                                                                 /* placeholder for external codec */
 330                                                         };
 331                                                 };
 332                                         };
 333                                 };
 334
 335                                 tegra_i2s5: i2s@2901400 {
 336                                         compatible = "nvidia,tegra234-i2s",
 337                                                      "nvidia,tegra210-i2s";
 338                                         reg = <0x0 0x2901400 0x0 0x100>;
 339                                         clocks = <&bpmp TEGRA234_CLK_I2S5>,
 340                                                  <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>;
 341                                         clock-names = "i2s", "sync_input";
 342                                         assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>;
 343                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
 344                                         assigned-clock-rates = <1536000>;
 345                                         sound-name-prefix = "I2S5";
 346                                         status = "disabled";
 347
 348                                         ports {
 349                                                 #address-cells = <1>;
 350                                                 #size-cells = <0>;
 351
 352                                                 port@0 {
 353                                                         reg = <0>;
 354
 355                                                         i2s5_cif: endpoint {
 356                                                                 remote-endpoint = <&xbar_i2s5>;
 357                                                         };
 358                                                 };
 359
 360                                                 i2s5_port: port@1 {
 361                                                         reg = <1>;
 362
 363                                                         i2s5_dap: endpoint {
 364                                                                 dai-format = "i2s";
 365                                                                 /* placeholder for external codec */
 366                                                         };
 367                                                 };
 368                                         };
 369                                 };
 370
 371                                 tegra_i2s6: i2s@2901500 {
 372                                         compatible = "nvidia,tegra234-i2s",
 373                                                      "nvidia,tegra210-i2s";
 374                                         reg = <0x0 0x2901500 0x0 0x100>;
 375                                         clocks = <&bpmp TEGRA234_CLK_I2S6>,
 376                                                  <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>;
 377                                         clock-names = "i2s", "sync_input";
 378                                         assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>;
 379                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
 380                                         assigned-clock-rates = <1536000>;
 381                                         sound-name-prefix = "I2S6";
 382                                         status = "disabled";
 383
 384                                         ports {
 385                                                 #address-cells = <1>;
 386                                                 #size-cells = <0>;
 387
 388                                                 port@0 {
 389                                                         reg = <0>;
 390
 391                                                         i2s6_cif: endpoint {
 392                                                                 remote-endpoint = <&xbar_i2s6>;
 393                                                         };
 394                                                 };
 395
 396                                                 i2s6_port: port@1 {
 397                                                         reg = <1>;
 398
 399                                                         i2s6_dap: endpoint {
 400                                                                 dai-format = "i2s";
 401                                                                 /* placeholder for external codec */
 402                                                         };
 403                                                 };
 404                                         };
 405                                 };
 406
 407                                 tegra_sfc1: sfc@2902000 {
 408                                         compatible = "nvidia,tegra234-sfc",
 409                                                      "nvidia,tegra210-sfc";
 410                                         reg = <0x0 0x2902000 0x0 0x200>;
 411                                         sound-name-prefix = "SFC1";
 412
 413                                         ports {
 414                                                 #address-cells = <1>;
 415                                                 #size-cells = <0>;
 416
 417                                                 port@0 {
 418                                                         reg = <0>;
 419
 420                                                         sfc1_cif_in: endpoint {
 421                                                                 remote-endpoint = <&xbar_sfc1_in>;
 422                                                         };
 423                                                 };
 424
 425                                                 sfc1_out_port: port@1 {
 426                                                         reg = <1>;
 427
 428                                                         sfc1_cif_out: endpoint {
 429                                                                 remote-endpoint = <&xbar_sfc1_out>;
 430                                                         };
 431                                                 };
 432                                         };
 433                                 };
 434
 435                                 tegra_sfc2: sfc@2902200 {
 436                                         compatible = "nvidia,tegra234-sfc",
 437                                                      "nvidia,tegra210-sfc";
 438                                         reg = <0x0 0x2902200 0x0 0x200>;
 439                                         sound-name-prefix = "SFC2";
 440
 441                                         ports {
 442                                                 #address-cells = <1>;
 443                                                 #size-cells = <0>;
 444
 445                                                 port@0 {
 446                                                         reg = <0>;
 447
 448                                                         sfc2_cif_in: endpoint {
 449                                                                 remote-endpoint = <&xbar_sfc2_in>;
 450                                                         };
 451                                                 };
 452
 453                                                 sfc2_out_port: port@1 {
 454                                                         reg = <1>;
 455
 456                                                         sfc2_cif_out: endpoint {
 457                                                                 remote-endpoint = <&xbar_sfc2_out>;
 458                                                         };
 459                                                 };
 460                                         };
 461                                 };
 462
 463                                 tegra_sfc3: sfc@2902400 {
 464                                         compatible = "nvidia,tegra234-sfc",
 465                                                      "nvidia,tegra210-sfc";
 466                                         reg = <0x0 0x2902400 0x0 0x200>;
 467                                         sound-name-prefix = "SFC3";
 468
 469                                         ports {
 470                                                 #address-cells = <1>;
 471                                                 #size-cells = <0>;
 472
 473                                                 port@0 {
 474                                                         reg = <0>;
 475
 476                                                         sfc3_cif_in: endpoint {
 477                                                                 remote-endpoint = <&xbar_sfc3_in>;
 478                                                         };
 479                                                 };
 480
 481                                                 sfc3_out_port: port@1 {
 482                                                         reg = <1>;
 483
 484                                                         sfc3_cif_out: endpoint {
 485                                                                 remote-endpoint = <&xbar_sfc3_out>;
 486                                                         };
 487                                                 };
 488                                         };
 489                                 };
 490
 491                                 tegra_sfc4: sfc@2902600 {
 492                                         compatible = "nvidia,tegra234-sfc",
 493                                                      "nvidia,tegra210-sfc";
 494                                         reg = <0x0 0x2902600 0x0 0x200>;
 495                                         sound-name-prefix = "SFC4";
 496
 497                                         ports {
 498                                                 #address-cells = <1>;
 499                                                 #size-cells = <0>;
 500
 501                                                 port@0 {
 502                                                         reg = <0>;
 503
 504                                                         sfc4_cif_in: endpoint {
 505                                                                 remote-endpoint = <&xbar_sfc4_in>;
 506                                                         };
 507                                                 };
 508
 509                                                 sfc4_out_port: port@1 {
 510                                                         reg = <1>;
 511
 512                                                         sfc4_cif_out: endpoint {
 513                                                                 remote-endpoint = <&xbar_sfc4_out>;
 514                                                         };
 515                                                 };
 516                                         };
 517                                 };
 518
 519                                 tegra_amx1: amx@2903000 {
 520                                         compatible = "nvidia,tegra234-amx",
 521                                                      "nvidia,tegra194-amx";
 522                                         reg = <0x0 0x2903000 0x0 0x100>;
 523                                         sound-name-prefix = "AMX1";
 524
 525                                         ports {
 526                                                 #address-cells = <1>;
 527                                                 #size-cells = <0>;
 528
 529                                                 port@0 {
 530                                                         reg = <0>;
 531
 532                                                         amx1_in1: endpoint {
 533                                                                 remote-endpoint = <&xbar_amx1_in1>;
 534                                                         };
 535                                                 };
 536
 537                                                 port@1 {
 538                                                         reg = <1>;
 539
 540                                                         amx1_in2: endpoint {
 541                                                                 remote-endpoint = <&xbar_amx1_in2>;
 542                                                         };
 543                                                 };
 544
 545                                                 port@2 {
 546                                                         reg = <2>;
 547
 548                                                         amx1_in3: endpoint {
 549                                                                 remote-endpoint = <&xbar_amx1_in3>;
 550                                                         };
 551                                                 };
 552
 553                                                 port@3 {
 554                                                         reg = <3>;
 555
 556                                                         amx1_in4: endpoint {
 557                                                                 remote-endpoint = <&xbar_amx1_in4>;
 558                                                         };
 559                                                 };
 560
 561                                                 amx1_out_port: port@4 {
 562                                                         reg = <4>;
 563
 564                                                         amx1_out: endpoint {
 565                                                                 remote-endpoint = <&xbar_amx1_out>;
 566                                                         };
 567                                                 };
 568                                         };
 569                                 };
 570
 571                                 tegra_amx2: amx@2903100 {
 572                                         compatible = "nvidia,tegra234-amx",
 573                                                      "nvidia,tegra194-amx";
 574                                         reg = <0x0 0x2903100 0x0 0x100>;
 575                                         sound-name-prefix = "AMX2";
 576
 577                                         ports {
 578                                                 #address-cells = <1>;
 579                                                 #size-cells = <0>;
 580
 581                                                 port@0 {
 582                                                         reg = <0>;
 583
 584                                                         amx2_in1: endpoint {
 585                                                                 remote-endpoint = <&xbar_amx2_in1>;
 586                                                         };
 587                                                 };
 588
 589                                                 port@1 {
 590                                                         reg = <1>;
 591
 592                                                         amx2_in2: endpoint {
 593                                                                 remote-endpoint = <&xbar_amx2_in2>;
 594                                                         };
 595                                                 };
 596
 597                                                 port@2 {
 598                                                         reg = <2>;
 599
 600                                                         amx2_in3: endpoint {
 601                                                                 remote-endpoint = <&xbar_amx2_in3>;
 602                                                         };
 603                                                 };
 604
 605                                                 port@3 {
 606                                                         reg = <3>;
 607
 608                                                         amx2_in4: endpoint {
 609                                                                 remote-endpoint = <&xbar_amx2_in4>;
 610                                                         };
 611                                                 };
 612
 613                                                 amx2_out_port: port@4 {
 614                                                         reg = <4>;
 615
 616                                                         amx2_out: endpoint {
 617                                                                 remote-endpoint = <&xbar_amx2_out>;
 618                                                         };
 619                                                 };
 620                                         };
 621                                 };
 622
 623                                 tegra_amx3: amx@2903200 {
 624                                         compatible = "nvidia,tegra234-amx",
 625                                                      "nvidia,tegra194-amx";
 626                                         reg = <0x0 0x2903200 0x0 0x100>;
 627                                         sound-name-prefix = "AMX3";
 628
 629                                         ports {
 630                                                 #address-cells = <1>;
 631                                                 #size-cells = <0>;
 632
 633                                                 port@0 {
 634                                                         reg = <0>;
 635
 636                                                         amx3_in1: endpoint {
 637                                                                 remote-endpoint = <&xbar_amx3_in1>;
 638                                                         };
 639                                                 };
 640
 641                                                 port@1 {
 642                                                         reg = <1>;
 643
 644                                                         amx3_in2: endpoint {
 645                                                                 remote-endpoint = <&xbar_amx3_in2>;
 646                                                         };
 647                                                 };
 648
 649                                                 port@2 {
 650                                                         reg = <2>;
 651
 652                                                         amx3_in3: endpoint {
 653                                                                 remote-endpoint = <&xbar_amx3_in3>;
 654                                                         };
 655                                                 };
 656
 657                                                 port@3 {
 658                                                         reg = <3>;
 659
 660                                                         amx3_in4: endpoint {
 661                                                                 remote-endpoint = <&xbar_amx3_in4>;
 662                                                         };
 663                                                 };
 664
 665                                                 amx3_out_port: port@4 {
 666                                                         reg = <4>;
 667
 668                                                         amx3_out: endpoint {
 669                                                                 remote-endpoint = <&xbar_amx3_out>;
 670                                                         };
 671                                                 };
 672                                         };
 673                                 };
 674
 675                                 tegra_amx4: amx@2903300 {
 676                                         compatible = "nvidia,tegra234-amx",
 677                                                      "nvidia,tegra194-amx";
 678                                         reg = <0x0 0x2903300 0x0 0x100>;
 679                                         sound-name-prefix = "AMX4";
 680
 681                                         ports {
 682                                                 #address-cells = <1>;
 683                                                 #size-cells = <0>;
 684
 685                                                 port@0 {
 686                                                         reg = <0>;
 687
 688                                                         amx4_in1: endpoint {
 689                                                                 remote-endpoint = <&xbar_amx4_in1>;
 690                                                         };
 691                                                 };
 692
 693                                                 port@1 {
 694                                                         reg = <1>;
 695
 696                                                         amx4_in2: endpoint {
 697                                                                 remote-endpoint = <&xbar_amx4_in2>;
 698                                                         };
 699                                                 };
 700
 701                                                 port@2 {
 702                                                         reg = <2>;
 703
 704                                                         amx4_in3: endpoint {
 705                                                                 remote-endpoint = <&xbar_amx4_in3>;
 706                                                         };
 707                                                 };
 708
 709                                                 port@3 {
 710                                                         reg = <3>;
 711
 712                                                         amx4_in4: endpoint {
 713                                                                 remote-endpoint = <&xbar_amx4_in4>;
 714                                                         };
 715                                                 };
 716
 717                                                 amx4_out_port: port@4 {
 718                                                         reg = <4>;
 719
 720                                                         amx4_out: endpoint {
 721                                                                 remote-endpoint = <&xbar_amx4_out>;
 722                                                         };
 723                                                 };
 724                                         };
 725                                 };
 726
 727                                 tegra_adx1: adx@2903800 {
 728                                         compatible = "nvidia,tegra234-adx",
 729                                                      "nvidia,tegra210-adx";
 730                                         reg = <0x0 0x2903800 0x0 0x100>;
 731                                         sound-name-prefix = "ADX1";
 732
 733                                         ports {
 734                                                 #address-cells = <1>;
 735                                                 #size-cells = <0>;
 736
 737                                                 port@0 {
 738                                                         reg = <0>;
 739
 740                                                         adx1_in: endpoint {
 741                                                                 remote-endpoint = <&xbar_adx1_in>;
 742                                                         };
 743                                                 };
 744
 745                                                 adx1_out1_port: port@1 {
 746                                                         reg = <1>;
 747
 748                                                         adx1_out1: endpoint {
 749                                                                 remote-endpoint = <&xbar_adx1_out1>;
 750                                                         };
 751                                                 };
 752
 753                                                 adx1_out2_port: port@2 {
 754                                                         reg = <2>;
 755
 756                                                         adx1_out2: endpoint {
 757                                                                 remote-endpoint = <&xbar_adx1_out2>;
 758                                                         };
 759                                                 };
 760
 761                                                 adx1_out3_port: port@3 {
 762                                                         reg = <3>;
 763
 764                                                         adx1_out3: endpoint {
 765                                                                 remote-endpoint = <&xbar_adx1_out3>;
 766                                                         };
 767                                                 };
 768
 769                                                 adx1_out4_port: port@4 {
 770                                                         reg = <4>;
 771
 772                                                         adx1_out4: endpoint {
 773                                                                 remote-endpoint = <&xbar_adx1_out4>;
 774                                                         };
 775                                                 };
 776                                         };
 777                                 };
 778
 779                                 tegra_adx2: adx@2903900 {
 780                                         compatible = "nvidia,tegra234-adx",
 781                                                      "nvidia,tegra210-adx";
 782                                         reg = <0x0 0x2903900 0x0 0x100>;
 783                                         sound-name-prefix = "ADX2";
 784
 785                                         ports {
 786                                                 #address-cells = <1>;
 787                                                 #size-cells = <0>;
 788
 789                                                 port@0 {
 790                                                         reg = <0>;
 791
 792                                                         adx2_in: endpoint {
 793                                                                 remote-endpoint = <&xbar_adx2_in>;
 794                                                         };
 795                                                 };
 796
 797                                                 adx2_out1_port: port@1 {
 798                                                         reg = <1>;
 799
 800                                                         adx2_out1: endpoint {
 801                                                                 remote-endpoint = <&xbar_adx2_out1>;
 802                                                         };
 803                                                 };
 804
 805                                                 adx2_out2_port: port@2 {
 806                                                         reg = <2>;
 807
 808                                                         adx2_out2: endpoint {
 809                                                                 remote-endpoint = <&xbar_adx2_out2>;
 810                                                         };
 811                                                 };
 812
 813                                                 adx2_out3_port: port@3 {
 814                                                         reg = <3>;
 815
 816                                                         adx2_out3: endpoint {
 817                                                                 remote-endpoint = <&xbar_adx2_out3>;
 818                                                         };
 819                                                 };
 820
 821                                                 adx2_out4_port: port@4 {
 822                                                         reg = <4>;
 823
 824                                                         adx2_out4: endpoint {
 825                                                                 remote-endpoint = <&xbar_adx2_out4>;
 826                                                         };
 827                                                 };
 828                                         };
 829                                 };
 830
 831                                 tegra_adx3: adx@2903a00 {
 832                                         compatible = "nvidia,tegra234-adx",
 833                                                      "nvidia,tegra210-adx";
 834                                         reg = <0x0 0x2903a00 0x0 0x100>;
 835                                         sound-name-prefix = "ADX3";
 836
 837                                         ports {
 838                                                 #address-cells = <1>;
 839                                                 #size-cells = <0>;
 840
 841                                                 port@0 {
 842                                                         reg = <0>;
 843
 844                                                         adx3_in: endpoint {
 845                                                                 remote-endpoint = <&xbar_adx3_in>;
 846                                                         };
 847                                                 };
 848
 849                                                 adx3_out1_port: port@1 {
 850                                                         reg = <1>;
 851
 852                                                         adx3_out1: endpoint {
 853                                                                 remote-endpoint = <&xbar_adx3_out1>;
 854                                                         };
 855                                                 };
 856
 857                                                 adx3_out2_port: port@2 {
 858                                                         reg = <2>;
 859
 860                                                         adx3_out2: endpoint {
 861                                                                 remote-endpoint = <&xbar_adx3_out2>;
 862                                                         };
 863                                                 };
 864
 865                                                 adx3_out3_port: port@3 {
 866                                                         reg = <3>;
 867
 868                                                         adx3_out3: endpoint {
 869                                                                 remote-endpoint = <&xbar_adx3_out3>;
 870                                                         };
 871                                                 };
 872
 873                                                 adx3_out4_port: port@4 {
 874                                                         reg = <4>;
 875
 876                                                         adx3_out4: endpoint {
 877                                                                 remote-endpoint = <&xbar_adx3_out4>;
 878                                                         };
 879                                                 };
 880                                         };
 881                                 };
 882
 883                                 tegra_adx4: adx@2903b00 {
 884                                         compatible = "nvidia,tegra234-adx",
 885                                                      "nvidia,tegra210-adx";
 886                                         reg = <0x0 0x2903b00 0x0 0x100>;
 887                                         sound-name-prefix = "ADX4";
 888
 889                                         ports {
 890                                                 #address-cells = <1>;
 891                                                 #size-cells = <0>;
 892
 893                                                 port@0 {
 894                                                         reg = <0>;
 895
 896                                                         adx4_in: endpoint {
 897                                                                 remote-endpoint = <&xbar_adx4_in>;
 898                                                         };
 899                                                 };
 900
 901                                                 adx4_out1_port: port@1 {
 902                                                         reg = <1>;
 903
 904                                                         adx4_out1: endpoint {
 905                                                                 remote-endpoint = <&xbar_adx4_out1>;
 906                                                         };
 907                                                 };
 908
 909                                                 adx4_out2_port: port@2 {
 910                                                         reg = <2>;
 911
 912                                                         adx4_out2: endpoint {
 913                                                                 remote-endpoint = <&xbar_adx4_out2>;
 914                                                         };
 915                                                 };
 916
 917                                                 adx4_out3_port: port@3 {
 918                                                         reg = <3>;
 919
 920                                                         adx4_out3: endpoint {
 921                                                                 remote-endpoint = <&xbar_adx4_out3>;
 922                                                         };
 923                                                 };
 924
 925                                                 adx4_out4_port: port@4 {
 926                                                         reg = <4>;
 927
 928                                                         adx4_out4: endpoint {
 929                                                                 remote-endpoint = <&xbar_adx4_out4>;
 930                                                         };
 931                                                 };
 932                                         };
 933                                 };
 934
 935
 936                                 tegra_dmic1: dmic@2904000 {
 937                                         compatible = "nvidia,tegra234-dmic",
 938                                                      "nvidia,tegra210-dmic";
 939                                         reg = <0x0 0x2904000 0x0 0x100>;
 940                                         clocks = <&bpmp TEGRA234_CLK_DMIC1>;
 941                                         clock-names = "dmic";
 942                                         assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>;
 943                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
 944                                         assigned-clock-rates = <3072000>;
 945                                         sound-name-prefix = "DMIC1";
 946                                         status = "disabled";
 947
 948                                         ports {
 949                                                 #address-cells = <1>;
 950                                                 #size-cells = <0>;
 951
 952                                                 port@0 {
 953                                                         reg = <0>;
 954
 955                                                         dmic1_cif: endpoint {
 956                                                                 remote-endpoint = <&xbar_dmic1>;
 957                                                         };
 958                                                 };
 959
 960                                                 dmic1_port: port@1 {
 961                                                         reg = <1>;
 962
 963                                                         dmic1_dap: endpoint {
 964                                                                 /* placeholder for external codec */
 965                                                         };
 966                                                 };
 967                                         };
 968                                 };
 969
 970                                 tegra_dmic2: dmic@2904100 {
 971                                         compatible = "nvidia,tegra234-dmic",
 972                                                      "nvidia,tegra210-dmic";
 973                                         reg = <0x0 0x2904100 0x0 0x100>;
 974                                         clocks = <&bpmp TEGRA234_CLK_DMIC2>;
 975                                         clock-names = "dmic";
 976                                         assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>;
 977                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
 978                                         assigned-clock-rates = <3072000>;
 979                                         sound-name-prefix = "DMIC2";
 980                                         status = "disabled";
 981
 982                                         ports {
 983                                                 #address-cells = <1>;
 984                                                 #size-cells = <0>;
 985
 986                                                 port@0 {
 987                                                         reg = <0>;
 988
 989                                                         dmic2_cif: endpoint {
 990                                                                 remote-endpoint = <&xbar_dmic2>;
 991                                                         };
 992                                                 };
 993
 994                                                 dmic2_port: port@1 {
 995                                                         reg = <1>;
 996
 997                                                         dmic2_dap: endpoint {
 998                                                                 /* placeholder for external codec */
 999                                                         };
1000                                                 };
1001                                         };
1002                                 };
1003
1004                                 tegra_dmic3: dmic@2904200 {
1005                                         compatible = "nvidia,tegra234-dmic",
1006                                                      "nvidia,tegra210-dmic";
1007                                         reg = <0x0 0x2904200 0x0 0x100>;
1008                                         clocks = <&bpmp TEGRA234_CLK_DMIC3>;
1009                                         clock-names = "dmic";
1010                                         assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>;
1011                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
1012                                         assigned-clock-rates = <3072000>;
1013                                         sound-name-prefix = "DMIC3";
1014                                         status = "disabled";
1015
1016                                         ports {
1017                                                 #address-cells = <1>;
1018                                                 #size-cells = <0>;
1019
1020                                                 port@0 {
1021                                                         reg = <0>;
1022
1023                                                         dmic3_cif: endpoint {
1024                                                                 remote-endpoint = <&xbar_dmic3>;
1025                                                         };
1026                                                 };
1027
1028                                                 dmic3_port: port@1 {
1029                                                         reg = <1>;
1030
1031                                                         dmic3_dap: endpoint {
1032                                                                 /* placeholder for external codec */
1033                                                         };
1034                                                 };
1035                                         };
1036                                 };
1037
1038                                 tegra_dmic4: dmic@2904300 {
1039                                         compatible = "nvidia,tegra234-dmic",
1040                                                      "nvidia,tegra210-dmic";
1041                                         reg = <0x0 0x2904300 0x0 0x100>;
1042                                         clocks = <&bpmp TEGRA234_CLK_DMIC4>;
1043                                         clock-names = "dmic";
1044                                         assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>;
1045                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
1046                                         assigned-clock-rates = <3072000>;
1047                                         sound-name-prefix = "DMIC4";
1048                                         status = "disabled";
1049
1050                                         ports {
1051                                                 #address-cells = <1>;
1052                                                 #size-cells = <0>;
1053
1054                                                 port@0 {
1055                                                         reg = <0>;
1056
1057                                                         dmic4_cif: endpoint {
1058                                                                 remote-endpoint = <&xbar_dmic4>;
1059                                                         };
1060                                                 };
1061
1062                                                 dmic4_port: port@1 {
1063                                                         reg = <1>;
1064
1065                                                         dmic4_dap: endpoint {
1066                                                                 /* placeholder for external codec */
1067                                                         };
1068                                                 };
1069                                         };
1070                                 };
1071
1072                                 tegra_dspk1: dspk@2905000 {
1073                                         compatible = "nvidia,tegra234-dspk",
1074                                                      "nvidia,tegra186-dspk";
1075                                         reg = <0x0 0x2905000 0x0 0x100>;
1076                                         clocks = <&bpmp TEGRA234_CLK_DSPK1>;
1077                                         clock-names = "dspk";
1078                                         assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>;
1079                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
1080                                         assigned-clock-rates = <12288000>;
1081                                         sound-name-prefix = "DSPK1";
1082                                         status = "disabled";
1083
1084                                         ports {
1085                                                 #address-cells = <1>;
1086                                                 #size-cells = <0>;
1087
1088                                                 port@0 {
1089                                                         reg = <0>;
1090
1091                                                         dspk1_cif: endpoint {
1092                                                                 remote-endpoint = <&xbar_dspk1>;
1093                                                         };
1094                                                 };
1095
1096                                                 dspk1_port: port@1 {
1097                                                         reg = <1>;
1098
1099                                                         dspk1_dap: endpoint {
1100                                                                 /* placeholder for external codec */
1101                                                         };
1102                                                 };
1103                                         };
1104                                 };
1105
1106                                 tegra_dspk2: dspk@2905100 {
1107                                         compatible = "nvidia,tegra234-dspk",
1108                                                      "nvidia,tegra186-dspk";
1109                                         reg = <0x0 0x2905100 0x0 0x100>;
1110                                         clocks = <&bpmp TEGRA234_CLK_DSPK2>;
1111                                         clock-names = "dspk";
1112                                         assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>;
1113                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
1114                                         assigned-clock-rates = <12288000>;
1115                                         sound-name-prefix = "DSPK2";
1116                                         status = "disabled";
1117
1118                                         ports {
1119                                                 #address-cells = <1>;
1120                                                 #size-cells = <0>;
1121
1122                                                 port@0 {
1123                                                         reg = <0>;
1124
1125                                                         dspk2_cif: endpoint {
1126                                                                 remote-endpoint = <&xbar_dspk2>;
1127                                                         };
1128                                                 };
1129
1130                                                 dspk2_port: port@1 {
1131                                                         reg = <1>;
1132
1133                                                         dspk2_dap: endpoint {
1134                                                                 /* placeholder for external codec */
1135                                                         };
1136                                                 };
1137                                         };
1138                                 };
1139
1140                                 tegra_ope1: processing-engine@2908000 {
1141                                         compatible = "nvidia,tegra234-ope",
1142                                                      "nvidia,tegra210-ope";
1143                                         reg = <0x0 0x2908000 0x0 0x100>;
1144                                         sound-name-prefix = "OPE1";
1145
1146                                         #address-cells = <2>;
1147                                         #size-cells = <2>;
1148                                         ranges;
1149
1150                                         equalizer@2908100 {
1151                                                 compatible = "nvidia,tegra234-peq",
1152                                                              "nvidia,tegra210-peq";
1153                                                 reg = <0x0 0x2908100 0x0 0x100>;
1154                                         };
1155
1156                                         dynamic-range-compressor@2908200 {
1157                                                 compatible = "nvidia,tegra234-mbdrc",
1158                                                              "nvidia,tegra210-mbdrc";
1159                                                 reg = <0x0 0x2908200 0x0 0x200>;
1160                                         };
1161
1162                                         ports {
1163                                                 #address-cells = <1>;
1164                                                 #size-cells = <0>;
1165
1166                                                 port@0 {
1167                                                         reg = <0x0>;
1168
1169                                                         ope1_cif_in_ep: endpoint {
1170                                                                 remote-endpoint =
1171                                                                         <&xbar_ope1_in_ep>;
1172                                                         };
1173                                                 };
1174
1175                                                 ope1_out_port: port@1 {
1176                                                         reg = <0x1>;
1177
1178                                                         ope1_cif_out_ep: endpoint {
1179                                                                 remote-endpoint =
1180                                                                         <&xbar_ope1_out_ep>;
1181                                                         };
1182                                                 };
1183                                         };
1184                                 };
1185
1186                                 tegra_mvc1: mvc@290a000 {
1187                                         compatible = "nvidia,tegra234-mvc",
1188                                                      "nvidia,tegra210-mvc";
1189                                         reg = <0x0 0x290a000 0x0 0x200>;
1190                                         sound-name-prefix = "MVC1";
1191
1192                                         ports {
1193                                                 #address-cells = <1>;
1194                                                 #size-cells = <0>;
1195
1196                                                 port@0 {
1197                                                         reg = <0>;
1198
1199                                                         mvc1_cif_in: endpoint {
1200                                                                 remote-endpoint = <&xbar_mvc1_in>;
1201                                                         };
1202                                                 };
1203
1204                                                 mvc1_out_port: port@1 {
1205                                                         reg = <1>;
1206
1207                                                         mvc1_cif_out: endpoint {
1208                                                                 remote-endpoint = <&xbar_mvc1_out>;
1209                                                         };
1210                                                 };
1211                                         };
1212                                 };
1213
1214                                 tegra_mvc2: mvc@290a200 {
1215                                         compatible = "nvidia,tegra234-mvc",
1216                                                      "nvidia,tegra210-mvc";
1217                                         reg = <0x0 0x290a200 0x0 0x200>;
1218                                         sound-name-prefix = "MVC2";
1219
1220                                         ports {
1221                                                 #address-cells = <1>;
1222                                                 #size-cells = <0>;
1223
1224                                                 port@0 {
1225                                                         reg = <0>;
1226
1227                                                         mvc2_cif_in: endpoint {
1228                                                                 remote-endpoint = <&xbar_mvc2_in>;
1229                                                         };
1230                                                 };
1231
1232                                                 mvc2_out_port: port@1 {
1233                                                         reg = <1>;
1234
1235                                                         mvc2_cif_out: endpoint {
1236                                                                 remote-endpoint = <&xbar_mvc2_out>;
1237                                                         };
1238                                                 };
1239                                         };
1240                                 };
1241
1242                                 tegra_amixer: amixer@290bb00 {
1243                                         compatible = "nvidia,tegra234-amixer",
1244                                                      "nvidia,tegra210-amixer";
1245                                         reg = <0x0 0x290bb00 0x0 0x800>;
1246                                         sound-name-prefix = "MIXER1";
1247
1248                                         ports {
1249                                                 #address-cells = <1>;
1250                                                 #size-cells = <0>;
1251
1252                                                 port@0 {
1253                                                         reg = <0x0>;
1254
1255                                                         mix_in1: endpoint {
1256                                                                 remote-endpoint = <&xbar_mix_in1>;
1257                                                         };
1258                                                 };
1259
1260                                                 port@1 {
1261                                                         reg = <0x1>;
1262
1263                                                         mix_in2: endpoint {
1264                                                                 remote-endpoint = <&xbar_mix_in2>;
1265                                                         };
1266                                                 };
1267
1268                                                 port@2 {
1269                                                         reg = <0x2>;
1270
1271                                                         mix_in3: endpoint {
1272                                                                 remote-endpoint = <&xbar_mix_in3>;
1273                                                         };
1274                                                 };
1275
1276                                                 port@3 {
1277                                                         reg = <0x3>;
1278
1279                                                         mix_in4: endpoint {
1280                                                                 remote-endpoint = <&xbar_mix_in4>;
1281                                                         };
1282                                                 };
1283
1284                                                 port@4 {
1285                                                         reg = <0x4>;
1286
1287                                                         mix_in5: endpoint {
1288                                                                 remote-endpoint = <&xbar_mix_in5>;
1289                                                         };
1290                                                 };
1291
1292                                                 port@5 {
1293                                                         reg = <0x5>;
1294
1295                                                         mix_in6: endpoint {
1296                                                                 remote-endpoint = <&xbar_mix_in6>;
1297                                                         };
1298                                                 };
1299
1300                                                 port@6 {
1301                                                         reg = <0x6>;
1302
1303                                                         mix_in7: endpoint {
1304                                                                 remote-endpoint = <&xbar_mix_in7>;
1305                                                         };
1306                                                 };
1307
1308                                                 port@7 {
1309                                                         reg = <0x7>;
1310
1311                                                         mix_in8: endpoint {
1312                                                                 remote-endpoint = <&xbar_mix_in8>;
1313                                                         };
1314                                                 };
1315
1316                                                 port@8 {
1317                                                         reg = <0x8>;
1318
1319                                                         mix_in9: endpoint {
1320                                                                 remote-endpoint = <&xbar_mix_in9>;
1321                                                         };
1322                                                 };
1323
1324                                                 port@9 {
1325                                                         reg = <0x9>;
1326
1327                                                         mix_in10: endpoint {
1328                                                                 remote-endpoint = <&xbar_mix_in10>;
1329                                                         };
1330                                                 };
1331
1332                                                 mix_out1_port: port@a {
1333                                                         reg = <0xa>;
1334
1335                                                         mix_out1: endpoint {
1336                                                                 remote-endpoint = <&xbar_mix_out1>;
1337                                                         };
1338                                                 };
1339
1340                                                 mix_out2_port: port@b {
1341                                                         reg = <0xb>;
1342
1343                                                         mix_out2: endpoint {
1344                                                                 remote-endpoint = <&xbar_mix_out2>;
1345                                                         };
1346                                                 };
1347
1348                                                 mix_out3_port: port@c {
1349                                                         reg = <0xc>;
1350
1351                                                         mix_out3: endpoint {
1352                                                                 remote-endpoint = <&xbar_mix_out3>;
1353                                                         };
1354                                                 };
1355
1356                                                 mix_out4_port: port@d {
1357                                                         reg = <0xd>;
1358
1359                                                         mix_out4: endpoint {
1360                                                                 remote-endpoint = <&xbar_mix_out4>;
1361                                                         };
1362                                                 };
1363
1364                                                 mix_out5_port: port@e {
1365                                                         reg = <0xe>;
1366
1367                                                         mix_out5: endpoint {
1368                                                                 remote-endpoint = <&xbar_mix_out5>;
1369                                                         };
1370                                                 };
1371                                         };
1372                                 };
1373
1374                                 tegra_admaif: admaif@290f000 {
1375                                         compatible = "nvidia,tegra234-admaif",
1376                                                      "nvidia,tegra186-admaif";
1377                                         reg = <0x0 0x0290f000 0x0 0x1000>;
1378                                         dmas = <&adma 1>, <&adma 1>,
1379                                                <&adma 2>, <&adma 2>,
1380                                                <&adma 3>, <&adma 3>,
1381                                                <&adma 4>, <&adma 4>,
1382                                                <&adma 5>, <&adma 5>,
1383                                                <&adma 6>, <&adma 6>,
1384                                                <&adma 7>, <&adma 7>,
1385                                                <&adma 8>, <&adma 8>,
1386                                                <&adma 9>, <&adma 9>,
1387                                                <&adma 10>, <&adma 10>,
1388                                                <&adma 11>, <&adma 11>,
1389                                                <&adma 12>, <&adma 12>,
1390                                                <&adma 13>, <&adma 13>,
1391                                                <&adma 14>, <&adma 14>,
1392                                                <&adma 15>, <&adma 15>,
1393                                                <&adma 16>, <&adma 16>,
1394                                                <&adma 17>, <&adma 17>,
1395                                                <&adma 18>, <&adma 18>,
1396                                                <&adma 19>, <&adma 19>,
1397                                                <&adma 20>, <&adma 20>;
1398                                         dma-names = "rx1", "tx1",
1399                                                     "rx2", "tx2",
1400                                                     "rx3", "tx3",
1401                                                     "rx4", "tx4",
1402                                                     "rx5", "tx5",
1403                                                     "rx6", "tx6",
1404                                                     "rx7", "tx7",
1405                                                     "rx8", "tx8",
1406                                                     "rx9", "tx9",
1407                                                     "rx10", "tx10",
1408                                                     "rx11", "tx11",
1409                                                     "rx12", "tx12",
1410                                                     "rx13", "tx13",
1411                                                     "rx14", "tx14",
1412                                                     "rx15", "tx15",
1413                                                     "rx16", "tx16",
1414                                                     "rx17", "tx17",
1415                                                     "rx18", "tx18",
1416                                                     "rx19", "tx19",
1417                                                     "rx20", "tx20";
1418                                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>,
1419                                                         <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>;
1420                                         interconnect-names = "dma-mem", "write";
1421                                         iommus = <&smmu_niso0 TEGRA234_SID_APE>;
1422
1423                                         ports {
1424                                                 #address-cells = <1>;
1425                                                 #size-cells = <0>;
1426
1427                                                 admaif0_port: port@0 {
1428                                                         reg = <0x0>;
1429
1430                                                         admaif0: endpoint {
1431                                                                 remote-endpoint = <&xbar_admaif0>;
1432                                                         };
1433                                                 };
1434
1435                                                 admaif1_port: port@1 {
1436                                                         reg = <0x1>;
1437
1438                                                         admaif1: endpoint {
1439                                                                 remote-endpoint = <&xbar_admaif1>;
1440                                                         };
1441                                                 };
1442
1443                                                 admaif2_port: port@2 {
1444                                                         reg = <0x2>;
1445
1446                                                         admaif2: endpoint {
1447                                                                 remote-endpoint = <&xbar_admaif2>;
1448                                                         };
1449                                                 };
1450
1451                                                 admaif3_port: port@3 {
1452                                                         reg = <0x3>;
1453
1454                                                         admaif3: endpoint {
1455                                                                 remote-endpoint = <&xbar_admaif3>;
1456                                                         };
1457                                                 };
1458
1459                                                 admaif4_port: port@4 {
1460                                                         reg = <0x4>;
1461
1462                                                         admaif4: endpoint {
1463                                                                 remote-endpoint = <&xbar_admaif4>;
1464                                                         };
1465                                                 };
1466
1467                                                 admaif5_port: port@5 {
1468                                                         reg = <0x5>;
1469
1470                                                         admaif5: endpoint {
1471                                                                 remote-endpoint = <&xbar_admaif5>;
1472                                                         };
1473                                                 };
1474
1475                                                 admaif6_port: port@6 {
1476                                                         reg = <0x6>;
1477
1478                                                         admaif6: endpoint {
1479                                                                 remote-endpoint = <&xbar_admaif6>;
1480                                                         };
1481                                                 };
1482
1483                                                 admaif7_port: port@7 {
1484                                                         reg = <0x7>;
1485
1486                                                         admaif7: endpoint {
1487                                                                 remote-endpoint = <&xbar_admaif7>;
1488                                                         };
1489                                                 };
1490
1491                                                 admaif8_port: port@8 {
1492                                                         reg = <0x8>;
1493
1494                                                         admaif8: endpoint {
1495                                                                 remote-endpoint = <&xbar_admaif8>;
1496                                                         };
1497                                                 };
1498
1499                                                 admaif9_port: port@9 {
1500                                                         reg = <0x9>;
1501
1502                                                         admaif9: endpoint {
1503                                                                 remote-endpoint = <&xbar_admaif9>;
1504                                                         };
1505                                                 };
1506
1507                                                 admaif10_port: port@a {
1508                                                         reg = <0xa>;
1509
1510                                                         admaif10: endpoint {
1511                                                                 remote-endpoint = <&xbar_admaif10>;
1512                                                         };
1513                                                 };
1514
1515                                                 admaif11_port: port@b {
1516                                                         reg = <0xb>;
1517
1518                                                         admaif11: endpoint {
1519                                                                 remote-endpoint = <&xbar_admaif11>;
1520                                                         };
1521                                                 };
1522
1523                                                 admaif12_port: port@c {
1524                                                         reg = <0xc>;
1525
1526                                                         admaif12: endpoint {
1527                                                                 remote-endpoint = <&xbar_admaif12>;
1528                                                         };
1529                                                 };
1530
1531                                                 admaif13_port: port@d {
1532                                                         reg = <0xd>;
1533
1534                                                         admaif13: endpoint {
1535                                                                 remote-endpoint = <&xbar_admaif13>;
1536                                                         };
1537                                                 };
1538
1539                                                 admaif14_port: port@e {
1540                                                         reg = <0xe>;
1541
1542                                                         admaif14: endpoint {
1543                                                                 remote-endpoint = <&xbar_admaif14>;
1544                                                         };
1545                                                 };
1546
1547                                                 admaif15_port: port@f {
1548                                                         reg = <0xf>;
1549
1550                                                         admaif15: endpoint {
1551                                                                 remote-endpoint = <&xbar_admaif15>;
1552                                                         };
1553                                                 };
1554
1555                                                 admaif16_port: port@10 {
1556                                                         reg = <0x10>;
1557
1558                                                         admaif16: endpoint {
1559                                                                 remote-endpoint = <&xbar_admaif16>;
1560                                                         };
1561                                                 };
1562
1563                                                 admaif17_port: port@11 {
1564                                                         reg = <0x11>;
1565
1566                                                         admaif17: endpoint {
1567                                                                 remote-endpoint = <&xbar_admaif17>;
1568                                                         };
1569                                                 };
1570
1571                                                 admaif18_port: port@12 {
1572                                                         reg = <0x12>;
1573
1574                                                         admaif18: endpoint {
1575                                                                 remote-endpoint = <&xbar_admaif18>;
1576                                                         };
1577                                                 };
1578
1579                                                 admaif19_port: port@13 {
1580                                                         reg = <0x13>;
1581
1582                                                         admaif19: endpoint {
1583                                                                 remote-endpoint = <&xbar_admaif19>;
1584                                                         };
1585                                                 };
1586                                         };
1587                                 };
1588
1589                                 tegra_asrc: asrc@2910000 {
1590                                         compatible = "nvidia,tegra234-asrc",
1591                                                      "nvidia,tegra186-asrc";
1592                                         reg = <0x0 0x2910000 0x0 0x2000>;
1593                                         sound-name-prefix = "ASRC1";
1594
1595                                         ports {
1596                                                 #address-cells = <1>;
1597                                                 #size-cells = <0>;
1598
1599                                                 port@0 {
1600                                                         reg = <0x0>;
1601
1602                                                         asrc_in1_ep: endpoint {
1603                                                                 remote-endpoint =
1604                                                                         <&xbar_asrc_in1_ep>;
1605                                                         };
1606                                                 };
1607
1608                                                 port@1 {
1609                                                         reg = <0x1>;
1610
1611                                                         asrc_in2_ep: endpoint {
1612                                                                 remote-endpoint =
1613                                                                         <&xbar_asrc_in2_ep>;
1614                                                         };
1615                                                 };
1616
1617                                                 port@2 {
1618                                                         reg = <0x2>;
1619
1620                                                         asrc_in3_ep: endpoint {
1621                                                                 remote-endpoint =
1622                                                                         <&xbar_asrc_in3_ep>;
1623                                                         };
1624                                                 };
1625
1626                                                 port@3 {
1627                                                         reg = <0x3>;
1628
1629                                                         asrc_in4_ep: endpoint {
1630                                                                 remote-endpoint =
1631                                                                         <&xbar_asrc_in4_ep>;
1632                                                         };
1633                                                 };
1634
1635                                                 port@4 {
1636                                                         reg = <0x4>;
1637
1638                                                         asrc_in5_ep: endpoint {
1639                                                                 remote-endpoint =
1640                                                                         <&xbar_asrc_in5_ep>;
1641                                                         };
1642                                                 };
1643
1644                                                 port@5 {
1645                                                         reg = <0x5>;
1646
1647                                                         asrc_in6_ep: endpoint {
1648                                                                 remote-endpoint =
1649                                                                         <&xbar_asrc_in6_ep>;
1650                                                         };
1651                                                 };
1652
1653                                                 port@6 {
1654                                                         reg = <0x6>;
1655
1656                                                         asrc_in7_ep: endpoint {
1657                                                                 remote-endpoint =
1658                                                                         <&xbar_asrc_in7_ep>;
1659                                                         };
1660                                                 };
1661
1662                                                 asrc_out1_port: port@7 {
1663                                                         reg = <0x7>;
1664
1665                                                         asrc_out1_ep: endpoint {
1666                                                                 remote-endpoint =
1667                                                                         <&xbar_asrc_out1_ep>;
1668                                                         };
1669                                                 };
1670
1671                                                 asrc_out2_port: port@8 {
1672                                                         reg = <0x8>;
1673
1674                                                         asrc_out2_ep: endpoint {
1675                                                                 remote-endpoint =
1676                                                                         <&xbar_asrc_out2_ep>;
1677                                                         };
1678                                                 };
1679
1680                                                 asrc_out3_port: port@9 {
1681                                                         reg = <0x9>;
1682
1683                                                         asrc_out3_ep: endpoint {
1684                                                                 remote-endpoint =
1685                                                                         <&xbar_asrc_out3_ep>;
1686                                                         };
1687                                                 };
1688
1689                                                 asrc_out4_port: port@a {
1690                                                         reg = <0xa>;
1691
1692                                                         asrc_out4_ep: endpoint {
1693                                                                 remote-endpoint =
1694                                                                         <&xbar_asrc_out4_ep>;
1695                                                         };
1696                                                 };
1697
1698                                                 asrc_out5_port: port@b {
1699                                                         reg = <0xb>;
1700
1701                                                         asrc_out5_ep: endpoint {
1702                                                                 remote-endpoint =
1703                                                                         <&xbar_asrc_out5_ep>;
1704                                                         };
1705                                                 };
1706
1707                                                 asrc_out6_port: port@c {
1708                                                         reg = <0xc>;
1709
1710                                                         asrc_out6_ep: endpoint {
1711                                                                 remote-endpoint =
1712                                                                         <&xbar_asrc_out6_ep>;
1713                                                         };
1714                                                 };
1715                                         };
1716                                 };
1717
1718                                 ports {
1719                                         #address-cells = <1>;
1720                                         #size-cells = <0>;
1721
1722                                         port@0 {
1723                                                 reg = <0x0>;
1724
1725                                                 xbar_admaif0: endpoint {
1726                                                         remote-endpoint = <&admaif0>;
1727                                                 };
1728                                         };
1729
1730                                         port@1 {
1731                                                 reg = <0x1>;
1732
1733                                                 xbar_admaif1: endpoint {
1734                                                         remote-endpoint = <&admaif1>;
1735                                                 };
1736                                         };
1737
1738                                         port@2 {
1739                                                 reg = <0x2>;
1740
1741                                                 xbar_admaif2: endpoint {
1742                                                         remote-endpoint = <&admaif2>;
1743                                                 };
1744                                         };
1745
1746                                         port@3 {
1747                                                 reg = <0x3>;
1748
1749                                                 xbar_admaif3: endpoint {
1750                                                         remote-endpoint = <&admaif3>;
1751                                                 };
1752                                         };
1753
1754                                         port@4 {
1755                                                 reg = <0x4>;
1756
1757                                                 xbar_admaif4: endpoint {
1758                                                         remote-endpoint = <&admaif4>;
1759                                                 };
1760                                         };
1761
1762                                         port@5 {
1763                                                 reg = <0x5>;
1764
1765                                                 xbar_admaif5: endpoint {
1766                                                         remote-endpoint = <&admaif5>;
1767                                                 };
1768                                         };
1769
1770                                         port@6 {
1771                                                 reg = <0x6>;
1772
1773                                                 xbar_admaif6: endpoint {
1774                                                         remote-endpoint = <&admaif6>;
1775                                                 };
1776                                         };
1777
1778                                         port@7 {
1779                                                 reg = <0x7>;
1780
1781                                                 xbar_admaif7: endpoint {
1782                                                         remote-endpoint = <&admaif7>;
1783                                                 };
1784                                         };
1785
1786                                         port@8 {
1787                                                 reg = <0x8>;
1788
1789                                                 xbar_admaif8: endpoint {
1790                                                         remote-endpoint = <&admaif8>;
1791                                                 };
1792                                         };
1793
1794                                         port@9 {
1795                                                 reg = <0x9>;
1796
1797                                                 xbar_admaif9: endpoint {
1798                                                         remote-endpoint = <&admaif9>;
1799                                                 };
1800                                         };
1801
1802                                         port@a {
1803                                                 reg = <0xa>;
1804
1805                                                 xbar_admaif10: endpoint {
1806                                                         remote-endpoint = <&admaif10>;
1807                                                 };
1808                                         };
1809
1810                                         port@b {
1811                                                 reg = <0xb>;
1812
1813                                                 xbar_admaif11: endpoint {
1814                                                         remote-endpoint = <&admaif11>;
1815                                                 };
1816                                         };
1817
1818                                         port@c {
1819                                                 reg = <0xc>;
1820
1821                                                 xbar_admaif12: endpoint {
1822                                                         remote-endpoint = <&admaif12>;
1823                                                 };
1824                                         };
1825
1826                                         port@d {
1827                                                 reg = <0xd>;
1828
1829                                                 xbar_admaif13: endpoint {
1830                                                         remote-endpoint = <&admaif13>;
1831                                                 };
1832                                         };
1833
1834                                         port@e {
1835                                                 reg = <0xe>;
1836
1837                                                 xbar_admaif14: endpoint {
1838                                                         remote-endpoint = <&admaif14>;
1839                                                 };
1840                                         };
1841
1842                                         port@f {
1843                                                 reg = <0xf>;
1844
1845                                                 xbar_admaif15: endpoint {
1846                                                         remote-endpoint = <&admaif15>;
1847                                                 };
1848                                         };
1849
1850                                         port@10 {
1851                                                 reg = <0x10>;
1852
1853                                                 xbar_admaif16: endpoint {
1854                                                         remote-endpoint = <&admaif16>;
1855                                                 };
1856                                         };
1857
1858                                         port@11 {
1859                                                 reg = <0x11>;
1860
1861                                                 xbar_admaif17: endpoint {
1862                                                         remote-endpoint = <&admaif17>;
1863                                                 };
1864                                         };
1865
1866                                         port@12 {
1867                                                 reg = <0x12>;
1868
1869                                                 xbar_admaif18: endpoint {
1870                                                         remote-endpoint = <&admaif18>;
1871                                                 };
1872                                         };
1873
1874                                         port@13 {
1875                                                 reg = <0x13>;
1876
1877                                                 xbar_admaif19: endpoint {
1878                                                         remote-endpoint = <&admaif19>;
1879                                                 };
1880                                         };
1881
1882                                         xbar_i2s1_port: port@14 {
1883                                                 reg = <0x14>;
1884
1885                                                 xbar_i2s1: endpoint {
1886                                                         remote-endpoint = <&i2s1_cif>;
1887                                                 };
1888                                         };
1889
1890                                         xbar_i2s2_port: port@15 {
1891                                                 reg = <0x15>;
1892
1893                                                 xbar_i2s2: endpoint {
1894                                                         remote-endpoint = <&i2s2_cif>;
1895                                                 };
1896                                         };
1897
1898                                         xbar_i2s3_port: port@16 {
1899                                                 reg = <0x16>;
1900
1901                                                 xbar_i2s3: endpoint {
1902                                                         remote-endpoint = <&i2s3_cif>;
1903                                                 };
1904                                         };
1905
1906                                         xbar_i2s4_port: port@17 {
1907                                                 reg = <0x17>;
1908
1909                                                 xbar_i2s4: endpoint {
1910                                                         remote-endpoint = <&i2s4_cif>;
1911                                                 };
1912                                         };
1913
1914                                         xbar_i2s5_port: port@18 {
1915                                                 reg = <0x18>;
1916
1917                                                 xbar_i2s5: endpoint {
1918                                                         remote-endpoint = <&i2s5_cif>;
1919                                                 };
1920                                         };
1921
1922                                         xbar_i2s6_port: port@19 {
1923                                                 reg = <0x19>;
1924
1925                                                 xbar_i2s6: endpoint {
1926                                                         remote-endpoint = <&i2s6_cif>;
1927                                                 };
1928                                         };
1929
1930                                         xbar_dmic1_port: port@1a {
1931                                                 reg = <0x1a>;
1932
1933                                                 xbar_dmic1: endpoint {
1934                                                         remote-endpoint = <&dmic1_cif>;
1935                                                 };
1936                                         };
1937
1938                                         xbar_dmic2_port: port@1b {
1939                                                 reg = <0x1b>;
1940
1941                                                 xbar_dmic2: endpoint {
1942                                                         remote-endpoint = <&dmic2_cif>;
1943                                                 };
1944                                         };
1945
1946                                         xbar_dmic3_port: port@1c {
1947                                                 reg = <0x1c>;
1948
1949                                                 xbar_dmic3: endpoint {
1950                                                         remote-endpoint = <&dmic3_cif>;
1951                                                 };
1952                                         };
1953
1954                                         xbar_dmic4_port: port@1d {
1955                                                 reg = <0x1d>;
1956
1957                                                 xbar_dmic4: endpoint {
1958                                                         remote-endpoint = <&dmic4_cif>;
1959                                                 };
1960                                         };
1961
1962                                         xbar_dspk1_port: port@1e {
1963                                                 reg = <0x1e>;
1964
1965                                                 xbar_dspk1: endpoint {
1966                                                         remote-endpoint = <&dspk1_cif>;
1967                                                 };
1968                                         };
1969
1970                                         xbar_dspk2_port: port@1f {
1971                                                 reg = <0x1f>;
1972
1973                                                 xbar_dspk2: endpoint {
1974                                                         remote-endpoint = <&dspk2_cif>;
1975                                                 };
1976                                         };
1977
1978                                         xbar_sfc1_in_port: port@20 {
1979                                                 reg = <0x20>;
1980
1981                                                 xbar_sfc1_in: endpoint {
1982                                                         remote-endpoint = <&sfc1_cif_in>;
1983                                                 };
1984                                         };
1985
1986                                         port@21 {
1987                                                 reg = <0x21>;
1988
1989                                                 xbar_sfc1_out: endpoint {
1990                                                         remote-endpoint = <&sfc1_cif_out>;
1991                                                 };
1992                                         };
1993
1994                                         xbar_sfc2_in_port: port@22 {
1995                                                 reg = <0x22>;
1996
1997                                                 xbar_sfc2_in: endpoint {
1998                                                         remote-endpoint = <&sfc2_cif_in>;
1999                                                 };
2000                                         };
2001
2002                                         port@23 {
2003                                                 reg = <0x23>;
2004
2005                                                 xbar_sfc2_out: endpoint {
2006                                                         remote-endpoint = <&sfc2_cif_out>;
2007                                                 };
2008                                         };
2009
2010                                         xbar_sfc3_in_port: port@24 {
2011                                                 reg = <0x24>;
2012
2013                                                 xbar_sfc3_in: endpoint {
2014                                                         remote-endpoint = <&sfc3_cif_in>;
2015                                                 };
2016                                         };
2017
2018                                         port@25 {
2019                                                 reg = <0x25>;
2020
2021                                                 xbar_sfc3_out: endpoint {
2022                                                         remote-endpoint = <&sfc3_cif_out>;
2023                                                 };
2024                                         };
2025
2026                                         xbar_sfc4_in_port: port@26 {
2027                                                 reg = <0x26>;
2028
2029                                                 xbar_sfc4_in: endpoint {
2030                                                         remote-endpoint = <&sfc4_cif_in>;
2031                                                 };
2032                                         };
2033
2034                                         port@27 {
2035                                                 reg = <0x27>;
2036
2037                                                 xbar_sfc4_out: endpoint {
2038                                                         remote-endpoint = <&sfc4_cif_out>;
2039                                                 };
2040                                         };
2041
2042                                         xbar_mvc1_in_port: port@28 {
2043                                                 reg = <0x28>;
2044
2045                                                 xbar_mvc1_in: endpoint {
2046                                                         remote-endpoint = <&mvc1_cif_in>;
2047                                                 };
2048                                         };
2049
2050                                         port@29 {
2051                                                 reg = <0x29>;
2052
2053                                                 xbar_mvc1_out: endpoint {
2054                                                         remote-endpoint = <&mvc1_cif_out>;
2055                                                 };
2056                                         };
2057
2058                                         xbar_mvc2_in_port: port@2a {
2059                                                 reg = <0x2a>;
2060
2061                                                 xbar_mvc2_in: endpoint {
2062                                                         remote-endpoint = <&mvc2_cif_in>;
2063                                                 };
2064                                         };
2065
2066                                         port@2b {
2067                                                 reg = <0x2b>;
2068
2069                                                 xbar_mvc2_out: endpoint {
2070                                                         remote-endpoint = <&mvc2_cif_out>;
2071                                                 };
2072                                         };
2073
2074                                         xbar_amx1_in1_port: port@2c {
2075                                                 reg = <0x2c>;
2076
2077                                                 xbar_amx1_in1: endpoint {
2078                                                         remote-endpoint = <&amx1_in1>;
2079                                                 };
2080                                         };
2081
2082                                         xbar_amx1_in2_port: port@2d {
2083                                                 reg = <0x2d>;
2084
2085                                                 xbar_amx1_in2: endpoint {
2086                                                         remote-endpoint = <&amx1_in2>;
2087                                                 };
2088                                         };
2089
2090                                         xbar_amx1_in3_port: port@2e {
2091                                                 reg = <0x2e>;
2092
2093                                                 xbar_amx1_in3: endpoint {
2094                                                         remote-endpoint = <&amx1_in3>;
2095                                                 };
2096                                         };
2097
2098                                         xbar_amx1_in4_port: port@2f {
2099                                                 reg = <0x2f>;
2100
2101                                                 xbar_amx1_in4: endpoint {
2102                                                         remote-endpoint = <&amx1_in4>;
2103                                                 };
2104                                         };
2105
2106                                         port@30 {
2107                                                 reg = <0x30>;
2108
2109                                                 xbar_amx1_out: endpoint {
2110                                                         remote-endpoint = <&amx1_out>;
2111                                                 };
2112                                         };
2113
2114                                         xbar_amx2_in1_port: port@31 {
2115                                                 reg = <0x31>;
2116
2117                                                 xbar_amx2_in1: endpoint {
2118                                                         remote-endpoint = <&amx2_in1>;
2119                                                 };
2120                                         };
2121
2122                                         xbar_amx2_in2_port: port@32 {
2123                                                 reg = <0x32>;
2124
2125                                                 xbar_amx2_in2: endpoint {
2126                                                         remote-endpoint = <&amx2_in2>;
2127                                                 };
2128                                         };
2129
2130                                         xbar_amx2_in3_port: port@33 {
2131                                                 reg = <0x33>;
2132
2133                                                 xbar_amx2_in3: endpoint {
2134                                                         remote-endpoint = <&amx2_in3>;
2135                                                 };
2136                                         };
2137
2138                                         xbar_amx2_in4_port: port@34 {
2139                                                 reg = <0x34>;
2140
2141                                                 xbar_amx2_in4: endpoint {
2142                                                         remote-endpoint = <&amx2_in4>;
2143                                                 };
2144                                         };
2145
2146                                         port@35 {
2147                                                 reg = <0x35>;
2148
2149                                                 xbar_amx2_out: endpoint {
2150                                                         remote-endpoint = <&amx2_out>;
2151                                                 };
2152                                         };
2153
2154                                         xbar_amx3_in1_port: port@36 {
2155                                                 reg = <0x36>;
2156
2157                                                 xbar_amx3_in1: endpoint {
2158                                                         remote-endpoint = <&amx3_in1>;
2159                                                 };
2160                                         };
2161
2162                                         xbar_amx3_in2_port: port@37 {
2163                                                 reg = <0x37>;
2164
2165                                                 xbar_amx3_in2: endpoint {
2166                                                         remote-endpoint = <&amx3_in2>;
2167                                                 };
2168                                         };
2169
2170                                         xbar_amx3_in3_port: port@38 {
2171                                                 reg = <0x38>;
2172
2173                                                 xbar_amx3_in3: endpoint {
2174                                                         remote-endpoint = <&amx3_in3>;
2175                                                 };
2176                                         };
2177
2178                                         xbar_amx3_in4_port: port@39 {
2179                                                 reg = <0x39>;
2180
2181                                                 xbar_amx3_in4: endpoint {
2182                                                         remote-endpoint = <&amx3_in4>;
2183                                                 };
2184                                         };
2185
2186                                         port@3a {
2187                                                 reg = <0x3a>;
2188
2189                                                 xbar_amx3_out: endpoint {
2190                                                         remote-endpoint = <&amx3_out>;
2191                                                 };
2192                                         };
2193
2194                                         xbar_amx4_in1_port: port@3b {
2195                                                 reg = <0x3b>;
2196
2197                                                 xbar_amx4_in1: endpoint {
2198                                                         remote-endpoint = <&amx4_in1>;
2199                                                 };
2200                                         };
2201
2202                                         xbar_amx4_in2_port: port@3c {
2203                                                 reg = <0x3c>;
2204
2205                                                 xbar_amx4_in2: endpoint {
2206                                                         remote-endpoint = <&amx4_in2>;
2207                                                 };
2208                                         };
2209
2210                                         xbar_amx4_in3_port: port@3d {
2211                                                 reg = <0x3d>;
2212
2213                                                 xbar_amx4_in3: endpoint {
2214                                                         remote-endpoint = <&amx4_in3>;
2215                                                 };
2216                                         };
2217
2218                                         xbar_amx4_in4_port: port@3e {
2219                                                 reg = <0x3e>;
2220
2221                                                 xbar_amx4_in4: endpoint {
2222                                                         remote-endpoint = <&amx4_in4>;
2223                                                 };
2224                                         };
2225
2226                                         port@3f {
2227                                                 reg = <0x3f>;
2228
2229                                                 xbar_amx4_out: endpoint {
2230                                                         remote-endpoint = <&amx4_out>;
2231                                                 };
2232                                         };
2233
2234                                         xbar_adx1_in_port: port@40 {
2235                                                 reg = <0x40>;
2236
2237                                                 xbar_adx1_in: endpoint {
2238                                                         remote-endpoint = <&adx1_in>;
2239                                                 };
2240                                         };
2241
2242                                         port@41 {
2243                                                 reg = <0x41>;
2244
2245                                                 xbar_adx1_out1: endpoint {
2246                                                         remote-endpoint = <&adx1_out1>;
2247                                                 };
2248                                         };
2249
2250                                         port@42 {
2251                                                 reg = <0x42>;
2252
2253                                                 xbar_adx1_out2: endpoint {
2254                                                         remote-endpoint = <&adx1_out2>;
2255                                                 };
2256                                         };
2257
2258                                         port@43 {
2259                                                 reg = <0x43>;
2260
2261                                                 xbar_adx1_out3: endpoint {
2262                                                         remote-endpoint = <&adx1_out3>;
2263                                                 };
2264                                         };
2265
2266                                         port@44 {
2267                                                 reg = <0x44>;
2268
2269                                                 xbar_adx1_out4: endpoint {
2270                                                         remote-endpoint = <&adx1_out4>;
2271                                                 };
2272                                         };
2273
2274                                         xbar_adx2_in_port: port@45 {
2275                                                 reg = <0x45>;
2276
2277                                                 xbar_adx2_in: endpoint {
2278                                                         remote-endpoint = <&adx2_in>;
2279                                                 };
2280                                         };
2281
2282                                         port@46 {
2283                                                 reg = <0x46>;
2284
2285                                                 xbar_adx2_out1: endpoint {
2286                                                         remote-endpoint = <&adx2_out1>;
2287                                                 };
2288                                         };
2289
2290                                         port@47 {
2291                                                 reg = <0x47>;
2292
2293                                                 xbar_adx2_out2: endpoint {
2294                                                         remote-endpoint = <&adx2_out2>;
2295                                                 };
2296                                         };
2297
2298                                         port@48 {
2299                                                 reg = <0x48>;
2300
2301                                                 xbar_adx2_out3: endpoint {
2302                                                         remote-endpoint = <&adx2_out3>;
2303                                                 };
2304                                         };
2305
2306                                         port@49 {
2307                                                 reg = <0x49>;
2308
2309                                                 xbar_adx2_out4: endpoint {
2310                                                         remote-endpoint = <&adx2_out4>;
2311                                                 };
2312                                         };
2313
2314                                         xbar_adx3_in_port: port@4a {
2315                                                 reg = <0x4a>;
2316
2317                                                 xbar_adx3_in: endpoint {
2318                                                         remote-endpoint = <&adx3_in>;
2319                                                 };
2320                                         };
2321
2322                                         port@4b {
2323                                                 reg = <0x4b>;
2324
2325                                                 xbar_adx3_out1: endpoint {
2326                                                         remote-endpoint = <&adx3_out1>;
2327                                                 };
2328                                         };
2329
2330                                         port@4c {
2331                                                 reg = <0x4c>;
2332
2333                                                 xbar_adx3_out2: endpoint {
2334                                                         remote-endpoint = <&adx3_out2>;
2335                                                 };
2336                                         };
2337
2338                                         port@4d {
2339                                                 reg = <0x4d>;
2340
2341                                                 xbar_adx3_out3: endpoint {
2342                                                         remote-endpoint = <&adx3_out3>;
2343                                                 };
2344                                         };
2345
2346                                         port@4e {
2347                                                 reg = <0x4e>;
2348
2349                                                 xbar_adx3_out4: endpoint {
2350                                                         remote-endpoint = <&adx3_out4>;
2351                                                 };
2352                                         };
2353
2354                                         xbar_adx4_in_port: port@4f {
2355                                                 reg = <0x4f>;
2356
2357                                                 xbar_adx4_in: endpoint {
2358                                                         remote-endpoint = <&adx4_in>;
2359                                                 };
2360                                         };
2361
2362                                         port@50 {
2363                                                 reg = <0x50>;
2364
2365                                                 xbar_adx4_out1: endpoint {
2366                                                         remote-endpoint = <&adx4_out1>;
2367                                                 };
2368                                         };
2369
2370                                         port@51 {
2371                                                 reg = <0x51>;
2372
2373                                                 xbar_adx4_out2: endpoint {
2374                                                         remote-endpoint = <&adx4_out2>;
2375                                                 };
2376                                         };
2377
2378                                         port@52 {
2379                                                 reg = <0x52>;
2380
2381                                                 xbar_adx4_out3: endpoint {
2382                                                         remote-endpoint = <&adx4_out3>;
2383                                                 };
2384                                         };
2385
2386                                         port@53 {
2387                                                 reg = <0x53>;
2388
2389                                                 xbar_adx4_out4: endpoint {
2390                                                         remote-endpoint = <&adx4_out4>;
2391                                                 };
2392                                         };
2393
2394                                         xbar_mix_in1_port: port@54 {
2395                                                 reg = <0x54>;
2396
2397                                                 xbar_mix_in1: endpoint {
2398                                                         remote-endpoint = <&mix_in1>;
2399                                                 };
2400                                         };
2401
2402                                         xbar_mix_in2_port: port@55 {
2403                                                 reg = <0x55>;
2404
2405                                                 xbar_mix_in2: endpoint {
2406                                                         remote-endpoint = <&mix_in2>;
2407                                                 };
2408                                         };
2409
2410                                         xbar_mix_in3_port: port@56 {
2411                                                 reg = <0x56>;
2412
2413                                                 xbar_mix_in3: endpoint {
2414                                                         remote-endpoint = <&mix_in3>;
2415                                                 };
2416                                         };
2417
2418                                         xbar_mix_in4_port: port@57 {
2419                                                 reg = <0x57>;
2420
2421                                                 xbar_mix_in4: endpoint {
2422                                                         remote-endpoint = <&mix_in4>;
2423                                                 };
2424                                         };
2425
2426                                         xbar_mix_in5_port: port@58 {
2427                                                 reg = <0x58>;
2428
2429                                                 xbar_mix_in5: endpoint {
2430                                                         remote-endpoint = <&mix_in5>;
2431                                                 };
2432                                         };
2433
2434                                         xbar_mix_in6_port: port@59 {
2435                                                 reg = <0x59>;
2436
2437                                                 xbar_mix_in6: endpoint {
2438                                                         remote-endpoint = <&mix_in6>;
2439                                                 };
2440                                         };
2441
2442                                         xbar_mix_in7_port: port@5a {
2443                                                 reg = <0x5a>;
2444
2445                                                 xbar_mix_in7: endpoint {
2446                                                         remote-endpoint = <&mix_in7>;
2447                                                 };
2448                                         };
2449
2450                                         xbar_mix_in8_port: port@5b {
2451                                                 reg = <0x5b>;
2452
2453                                                 xbar_mix_in8: endpoint {
2454                                                         remote-endpoint = <&mix_in8>;
2455                                                 };
2456                                         };
2457
2458                                         xbar_mix_in9_port: port@5c {
2459                                                 reg = <0x5c>;
2460
2461                                                 xbar_mix_in9: endpoint {
2462                                                         remote-endpoint = <&mix_in9>;
2463                                                 };
2464                                         };
2465
2466                                         xbar_mix_in10_port: port@5d {
2467                                                 reg = <0x5d>;
2468
2469                                                 xbar_mix_in10: endpoint {
2470                                                         remote-endpoint = <&mix_in10>;
2471                                                 };
2472                                         };
2473
2474                                         port@5e {
2475                                                 reg = <0x5e>;
2476
2477                                                 xbar_mix_out1: endpoint {
2478                                                         remote-endpoint = <&mix_out1>;
2479                                                 };
2480                                         };
2481
2482                                         port@5f {
2483                                                 reg = <0x5f>;
2484
2485                                                 xbar_mix_out2: endpoint {
2486                                                         remote-endpoint = <&mix_out2>;
2487                                                 };
2488                                         };
2489
2490                                         port@60 {
2491                                                 reg = <0x60>;
2492
2493                                                 xbar_mix_out3: endpoint {
2494                                                         remote-endpoint = <&mix_out3>;
2495                                                 };
2496                                         };
2497
2498                                         port@61 {
2499                                                 reg = <0x61>;
2500
2501                                                 xbar_mix_out4: endpoint {
2502                                                         remote-endpoint = <&mix_out4>;
2503                                                 };
2504                                         };
2505
2506                                         port@62 {
2507                                                 reg = <0x62>;
2508
2509                                                 xbar_mix_out5: endpoint {
2510                                                         remote-endpoint = <&mix_out5>;
2511                                                 };
2512                                         };
2513
2514                                         xbar_asrc_in1_port: port@63 {
2515                                                 reg = <0x63>;
2516
2517                                                 xbar_asrc_in1_ep: endpoint {
2518                                                         remote-endpoint = <&asrc_in1_ep>;
2519                                                 };
2520                                         };
2521
2522                                         port@64 {
2523                                                 reg = <0x64>;
2524
2525                                                 xbar_asrc_out1_ep: endpoint {
2526                                                         remote-endpoint = <&asrc_out1_ep>;
2527                                                 };
2528                                         };
2529
2530                                         xbar_asrc_in2_port: port@65 {
2531                                                 reg = <0x65>;
2532
2533                                                 xbar_asrc_in2_ep: endpoint {
2534                                                         remote-endpoint = <&asrc_in2_ep>;
2535                                                 };
2536                                         };
2537
2538                                         port@66 {
2539                                                 reg = <0x66>;
2540
2541                                                 xbar_asrc_out2_ep: endpoint {
2542                                                         remote-endpoint = <&asrc_out2_ep>;
2543                                                 };
2544                                         };
2545
2546                                         xbar_asrc_in3_port: port@67 {
2547                                                 reg = <0x67>;
2548
2549                                                 xbar_asrc_in3_ep: endpoint {
2550                                                         remote-endpoint = <&asrc_in3_ep>;
2551                                                 };
2552                                         };
2553
2554                                         port@68 {
2555                                                 reg = <0x68>;
2556
2557                                                 xbar_asrc_out3_ep: endpoint {
2558                                                         remote-endpoint = <&asrc_out3_ep>;
2559                                                 };
2560                                         };
2561
2562                                         xbar_asrc_in4_port: port@69 {
2563                                                 reg = <0x69>;
2564
2565                                                 xbar_asrc_in4_ep: endpoint {
2566                                                         remote-endpoint = <&asrc_in4_ep>;
2567                                                 };
2568                                         };
2569
2570                                         port@6a {
2571                                                 reg = <0x6a>;
2572
2573                                                 xbar_asrc_out4_ep: endpoint {
2574                                                         remote-endpoint = <&asrc_out4_ep>;
2575                                                 };
2576                                         };
2577
2578                                         xbar_asrc_in5_port: port@6b {
2579                                                 reg = <0x6b>;
2580
2581                                                 xbar_asrc_in5_ep: endpoint {
2582                                                         remote-endpoint = <&asrc_in5_ep>;
2583                                                 };
2584                                         };
2585
2586                                         port@6c {
2587                                                 reg = <0x6c>;
2588
2589                                                 xbar_asrc_out5_ep: endpoint {
2590                                                         remote-endpoint = <&asrc_out5_ep>;
2591                                                 };
2592                                         };
2593
2594                                         xbar_asrc_in6_port: port@6d {
2595                                                 reg = <0x6d>;
2596
2597                                                 xbar_asrc_in6_ep: endpoint {
2598                                                         remote-endpoint = <&asrc_in6_ep>;
2599                                                 };
2600                                         };
2601
2602                                         port@6e {
2603                                                 reg = <0x6e>;
2604
2605                                                 xbar_asrc_out6_ep: endpoint {
2606                                                         remote-endpoint = <&asrc_out6_ep>;
2607                                                 };
2608                                         };
2609
2610                                         xbar_asrc_in7_port: port@6f {
2611                                                 reg = <0x6f>;
2612
2613                                                 xbar_asrc_in7_ep: endpoint {
2614                                                         remote-endpoint = <&asrc_in7_ep>;
2615                                                 };
2616                                         };
2617
2618                                         xbar_ope1_in_port: port@70 {
2619                                                 reg = <0x70>;
2620
2621                                                 xbar_ope1_in_ep: endpoint {
2622                                                         remote-endpoint = <&ope1_cif_in_ep>;
2623                                                 };
2624                                         };
2625
2626                                         port@71 {
2627                                                 reg = <0x71>;
2628
2629                                                 xbar_ope1_out_ep: endpoint {
2630                                                         remote-endpoint = <&ope1_cif_out_ep>;
2631                                                 };
2632                                         };
2633                                 };
2634                         };
2635
2636                         adma: dma-controller@2930000 {
2637                                 compatible = "nvidia,tegra234-adma",
2638                                              "nvidia,tegra186-adma";
2639                                 reg = <0x0 0x02930000 0x0 0x20000>;
2640                                 interrupt-parent = <&agic>;
2641                                 interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
2642                                               <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
2643                                               <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
2644                                               <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2645                                               <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2646                                               <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
2647                                               <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
2648                                               <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
2649                                               <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2650                                               <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
2651                                               <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
2652                                               <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
2653                                               <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
2654                                               <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
2655                                               <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
2656                                               <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
2657                                               <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
2658                                               <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
2659                                               <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
2660                                               <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
2661                                               <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
2662                                               <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
2663                                               <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
2664                                               <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
2665                                               <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
2666                                               <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
2667                                               <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
2668                                               <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
2669                                               <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
2670                                               <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
2671                                               <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
2672                                               <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
2673                                 #dma-cells = <1>;
2674                                 clocks = <&bpmp TEGRA234_CLK_AHUB>;
2675                                 clock-names = "d_audio";
2676                                 status = "disabled";
2677                         };
2678
2679                         agic: interrupt-controller@2a40000 {
2680                                 compatible = "nvidia,tegra234-agic",
2681                                              "nvidia,tegra210-agic";
2682                                 #interrupt-cells = <3>;
2683                                 interrupt-controller;
2684                                 reg = <0x0 0x02a41000 0x0 0x1000>,
2685                                       <0x0 0x02a42000 0x0 0x2000>;
2686                                 interrupts = <GIC_SPI 145
2687                                               (GIC_CPU_MASK_SIMPLE(4) |
2688                                                IRQ_TYPE_LEVEL_HIGH)>;
2689                                 clocks = <&bpmp TEGRA234_CLK_APE>;
2690                                 clock-names = "clk";
2691                                 status = "disabled";
2692                         };
2693                 };
2694
2695                 mc: memory-controller@2c00000 {
2696                         compatible = "nvidia,tegra234-mc";
2697                         reg = <0x0 0x02c00000 0x0 0x10000>,   /* MC-SID */
2698                               <0x0 0x02c10000 0x0 0x10000>,   /* MC Broadcast*/
2699                               <0x0 0x02c20000 0x0 0x10000>,   /* MC0 */
2700                               <0x0 0x02c30000 0x0 0x10000>,   /* MC1 */
2701                               <0x0 0x02c40000 0x0 0x10000>,   /* MC2 */
2702                               <0x0 0x02c50000 0x0 0x10000>,   /* MC3 */
2703                               <0x0 0x02b80000 0x0 0x10000>,   /* MC4 */
2704                               <0x0 0x02b90000 0x0 0x10000>,   /* MC5 */
2705                               <0x0 0x02ba0000 0x0 0x10000>,   /* MC6 */
2706                               <0x0 0x02bb0000 0x0 0x10000>,   /* MC7 */
2707                               <0x0 0x01700000 0x0 0x10000>,   /* MC8 */
2708                               <0x0 0x01710000 0x0 0x10000>,   /* MC9 */
2709                               <0x0 0x01720000 0x0 0x10000>,   /* MC10 */
2710                               <0x0 0x01730000 0x0 0x10000>,   /* MC11 */
2711                               <0x0 0x01740000 0x0 0x10000>,   /* MC12 */
2712                               <0x0 0x01750000 0x0 0x10000>,   /* MC13 */
2713                               <0x0 0x01760000 0x0 0x10000>,   /* MC14 */
2714                               <0x0 0x01770000 0x0 0x10000>;   /* MC15 */
2715                         reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
2716                                     "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10",
2717                                     "ch11", "ch12", "ch13", "ch14", "ch15";
2718                         interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
2719                         #interconnect-cells = <1>;
2720                         status = "okay";
2721
2722                         #address-cells = <2>;
2723                         #size-cells = <2>;
2724                         ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>,
2725                                  <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>,
2726                                  <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>;
2727
2728                         /*
2729                          * Bit 39 of addresses passing through the memory
2730                          * controller selects the XBAR format used when memory
2731                          * is accessed. This is used to transparently access
2732                          * memory in the XBAR format used by the discrete GPU
2733                          * (bit 39 set) or Tegra (bit 39 clear).
2734                          *
2735                          * As a consequence, the operating system must ensure
2736                          * that bit 39 is never used implicitly, for example
2737                          * via an I/O virtual address mapping of an IOMMU. If
2738                          * devices require access to the XBAR switch, their
2739                          * drivers must set this bit explicitly.
2740                          *
2741                          * Limit the DMA range for memory clients to [38:0].
2742                          */
2743                         dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>;
2744
2745                         emc: external-memory-controller@2c60000 {
2746                                 compatible = "nvidia,tegra234-emc";
2747                                 reg = <0x0 0x02c60000 0x0 0x90000>,
2748                                       <0x0 0x01780000 0x0 0x80000>;
2749                                 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
2750                                 clocks = <&bpmp TEGRA234_CLK_EMC>;
2751                                 clock-names = "emc";
2752                                 status = "okay";
2753
2754                                 #interconnect-cells = <0>;
2755
2756                                 nvidia,bpmp = <&bpmp>;
2757                         };
2758                 };
2759
2760                 uarta: serial@3100000 {
2761                         compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
2762                         reg = <0x0 0x03100000 0x0 0x10000>;
2763                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2764                         clocks = <&bpmp TEGRA234_CLK_UARTA>;
2765                         resets = <&bpmp TEGRA234_RESET_UARTA>;
2766                         status = "disabled";
2767                 };
2768
2769                 uarte: serial@3140000 {
2770                         compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
2771                         reg = <0x0 0x03140000 0x0 0x10000>;
2772                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2773                         clocks = <&bpmp TEGRA234_CLK_UARTE>;
2774                         resets = <&bpmp TEGRA234_RESET_UARTE>;
2775                         dmas = <&gpcdma 20>, <&gpcdma 20>;
2776                         dma-names = "rx", "tx";
2777                         status = "disabled";
2778                 };
2779
2780                 gen1_i2c: i2c@3160000 {
2781                         compatible = "nvidia,tegra194-i2c";
2782                         reg = <0x0 0x3160000 0x0 0x100>;
2783                         status = "disabled";
2784                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
2785                         #address-cells = <1>;
2786                         #size-cells = <0>;
2787                         clock-frequency = <400000>;
2788                         clocks = <&bpmp TEGRA234_CLK_I2C1>,
2789                                  <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2790                         assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
2791                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2792                         clock-names = "div-clk", "parent";
2793                         resets = <&bpmp TEGRA234_RESET_I2C1>;
2794                         reset-names = "i2c";
2795                         dmas = <&gpcdma 21>, <&gpcdma 21>;
2796                         dma-names = "rx", "tx";
2797                 };
2798
2799                 cam_i2c: i2c@3180000 {
2800                         compatible = "nvidia,tegra194-i2c";
2801                         reg = <0x0 0x3180000 0x0 0x100>;
2802                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
2803                         #address-cells = <1>;
2804                         #size-cells = <0>;
2805                         status = "disabled";
2806                         clock-frequency = <400000>;
2807                         clocks = <&bpmp TEGRA234_CLK_I2C3>,
2808                                  <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2809                         assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
2810                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2811                         clock-names = "div-clk", "parent";
2812                         resets = <&bpmp TEGRA234_RESET_I2C3>;
2813                         reset-names = "i2c";
2814                         dmas = <&gpcdma 23>, <&gpcdma 23>;
2815                         dma-names = "rx", "tx";
2816                 };
2817
2818                 dp_aux_ch1_i2c: i2c@3190000 {
2819                         compatible = "nvidia,tegra194-i2c";
2820                         reg = <0x0 0x3190000 0x0 0x100>;
2821                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
2822                         #address-cells = <1>;
2823                         #size-cells = <0>;
2824                         status = "disabled";
2825                         clock-frequency = <100000>;
2826                         clocks = <&bpmp TEGRA234_CLK_I2C4>,
2827                                  <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2828                         assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
2829                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2830                         clock-names = "div-clk", "parent";
2831                         resets = <&bpmp TEGRA234_RESET_I2C4>;
2832                         reset-names = "i2c";
2833                         dmas = <&gpcdma 26>, <&gpcdma 26>;
2834                         dma-names = "rx", "tx";
2835                 };
2836
2837                 dp_aux_ch0_i2c: i2c@31b0000 {
2838                         compatible = "nvidia,tegra194-i2c";
2839                         reg = <0x0 0x31b0000 0x0 0x100>;
2840                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
2841                         #address-cells = <1>;
2842                         #size-cells = <0>;
2843                         status = "disabled";
2844                         clock-frequency = <100000>;
2845                         clocks = <&bpmp TEGRA234_CLK_I2C6>,
2846                                  <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2847                         assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
2848                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2849                         clock-names = "div-clk", "parent";
2850                         resets = <&bpmp TEGRA234_RESET_I2C6>;
2851                         reset-names = "i2c";
2852                         dmas = <&gpcdma 30>, <&gpcdma 30>;
2853                         dma-names = "rx", "tx";
2854                 };
2855
2856                 dp_aux_ch2_i2c: i2c@31c0000 {
2857                         compatible = "nvidia,tegra194-i2c";
2858                         reg = <0x0 0x31c0000 0x0 0x100>;
2859                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
2860                         #address-cells = <1>;
2861                         #size-cells = <0>;
2862                         status = "disabled";
2863                         clock-frequency = <100000>;
2864                         clocks = <&bpmp TEGRA234_CLK_I2C7>,
2865                                  <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2866                         assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
2867                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2868                         clock-names = "div-clk", "parent";
2869                         resets = <&bpmp TEGRA234_RESET_I2C7>;
2870                         reset-names = "i2c";
2871                         dmas = <&gpcdma 27>, <&gpcdma 27>;
2872                         dma-names = "rx", "tx";
2873                 };
2874
2875                 uarti: serial@31d0000 {
2876                         compatible = "arm,sbsa-uart";
2877                         reg = <0x0 0x31d0000 0x0 0x10000>;
2878                         interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
2879                         status = "disabled";
2880                 };
2881
2882                 dp_aux_ch3_i2c: i2c@31e0000 {
2883                         compatible = "nvidia,tegra194-i2c";
2884                         reg = <0x0 0x31e0000 0x0 0x100>;
2885                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
2886                         #address-cells = <1>;
2887                         #size-cells = <0>;
2888                         status = "disabled";
2889                         clock-frequency = <100000>;
2890                         clocks = <&bpmp TEGRA234_CLK_I2C9>,
2891                                  <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2892                         assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
2893                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2894                         clock-names = "div-clk", "parent";
2895                         resets = <&bpmp TEGRA234_RESET_I2C9>;
2896                         reset-names = "i2c";
2897                         dmas = <&gpcdma 31>, <&gpcdma 31>;
2898                         dma-names = "rx", "tx";
2899                 };
2900
2901                 spi@3210000 {
2902                         compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
2903                         reg = <0x0 0x03210000 0x0 0x1000>;
2904                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
2905                         #address-cells = <1>;
2906                         #size-cells = <0>;
2907                         clocks = <&bpmp TEGRA234_CLK_SPI1>;
2908                         assigned-clocks = <&bpmp TEGRA234_CLK_SPI1>;
2909                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2910                         clock-names = "spi";
2911                         iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
2912                         resets = <&bpmp TEGRA234_RESET_SPI1>;
2913                         reset-names = "spi";
2914                         dmas = <&gpcdma 15>, <&gpcdma 15>;
2915                         dma-names = "rx", "tx";
2916                         dma-coherent;
2917                         status = "disabled";
2918                 };
2919
2920                 spi@3230000 {
2921                         compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
2922                         reg = <0x0 0x03230000 0x0 0x1000>;
2923                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2924                         #address-cells = <1>;
2925                         #size-cells = <0>;
2926                         clocks = <&bpmp TEGRA234_CLK_SPI3>;
2927                         clock-names = "spi";
2928                         iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
2929                         assigned-clocks = <&bpmp TEGRA234_CLK_SPI3>;
2930                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2931                         resets = <&bpmp TEGRA234_RESET_SPI3>;
2932                         reset-names = "spi";
2933                         dmas = <&gpcdma 17>, <&gpcdma 17>;
2934                         dma-names = "rx", "tx";
2935                         dma-coherent;
2936                         status = "disabled";
2937                 };
2938
2939                 spi@3270000 {
2940                         compatible = "nvidia,tegra234-qspi";
2941                         reg = <0x0 0x3270000 0x0 0x1000>;
2942                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
2943                         #address-cells = <1>;
2944                         #size-cells = <0>;
2945                         clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
2946                                  <&bpmp TEGRA234_CLK_QSPI0_PM>;
2947                         clock-names = "qspi", "qspi_out";
2948                         resets = <&bpmp TEGRA234_RESET_QSPI0>;
2949                         status = "disabled";
2950                 };
2951
2952                 pwm1: pwm@3280000 {
2953                         compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2954                         reg = <0x0 0x3280000 0x0 0x10000>;
2955                         clocks = <&bpmp TEGRA234_CLK_PWM1>;
2956                         resets = <&bpmp TEGRA234_RESET_PWM1>;
2957                         reset-names = "pwm";
2958                         status = "disabled";
2959                         #pwm-cells = <2>;
2960                 };
2961
2962                 pwm2: pwm@3290000 {
2963                         compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2964                         reg = <0x0 0x3290000 0x0 0x10000>;
2965                         clocks = <&bpmp TEGRA234_CLK_PWM2>;
2966                         resets = <&bpmp TEGRA234_RESET_PWM2>;
2967                         reset-names = "pwm";
2968                         status = "disabled";
2969                         #pwm-cells = <2>;
2970                 };
2971
2972                 pwm3: pwm@32a0000 {
2973                         compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2974                         reg = <0x0 0x32a0000 0x0 0x10000>;
2975                         clocks = <&bpmp TEGRA234_CLK_PWM3>;
2976                         resets = <&bpmp TEGRA234_RESET_PWM3>;
2977                         reset-names = "pwm";
2978                         status = "disabled";
2979                         #pwm-cells = <2>;
2980                 };
2981
2982                 pwm5: pwm@32c0000 {
2983                         compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2984                         reg = <0x0 0x32c0000 0x0 0x10000>;
2985                         clocks = <&bpmp TEGRA234_CLK_PWM5>;
2986                         resets = <&bpmp TEGRA234_RESET_PWM5>;
2987                         reset-names = "pwm";
2988                         status = "disabled";
2989                         #pwm-cells = <2>;
2990                 };
2991
2992                 pwm6: pwm@32d0000 {
2993                         compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2994                         reg = <0x0 0x32d0000 0x0 0x10000>;
2995                         clocks = <&bpmp TEGRA234_CLK_PWM6>;
2996                         resets = <&bpmp TEGRA234_RESET_PWM6>;
2997                         reset-names = "pwm";
2998                         status = "disabled";
2999                         #pwm-cells = <2>;
3000                 };
3001
3002                 pwm7: pwm@32e0000 {
3003                         compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
3004                         reg = <0x0 0x32e0000 0x0 0x10000>;
3005                         clocks = <&bpmp TEGRA234_CLK_PWM7>;
3006                         resets = <&bpmp TEGRA234_RESET_PWM7>;
3007                         reset-names = "pwm";
3008                         status = "disabled";
3009                         #pwm-cells = <2>;
3010                 };
3011
3012                 pwm8: pwm@32f0000 {
3013                         compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
3014                         reg = <0x0 0x32f0000 0x0 0x10000>;
3015                         clocks = <&bpmp TEGRA234_CLK_PWM8>;
3016                         resets = <&bpmp TEGRA234_RESET_PWM8>;
3017                         reset-names = "pwm";
3018                         status = "disabled";
3019                         #pwm-cells = <2>;
3020                 };
3021
3022                 spi@3300000 {
3023                         compatible = "nvidia,tegra234-qspi";
3024                         reg = <0x0 0x3300000 0x0 0x1000>;
3025                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
3026                         #address-cells = <1>;
3027                         #size-cells = <0>;
3028                         clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>,
3029                                  <&bpmp TEGRA234_CLK_QSPI1_PM>;
3030                         clock-names = "qspi", "qspi_out";
3031                         resets = <&bpmp TEGRA234_RESET_QSPI1>;
3032                         status = "disabled";
3033                 };
3034
3035                 mmc@3400000 {
3036                         compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
3037                         reg = <0x0 0x03400000 0x0 0x20000>;
3038                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
3039                         clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
3040                                  <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
3041                         clock-names = "sdhci", "tmclk";
3042                         assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
3043                                           <&bpmp TEGRA234_CLK_PLLC4_MUXED>;
3044                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>,
3045                                                  <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>;
3046                         resets = <&bpmp TEGRA234_RESET_SDMMC1>;
3047                         reset-names = "sdhci";
3048                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>,
3049                                         <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>;
3050                         interconnect-names = "dma-mem", "write";
3051                         iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>;
3052                         pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
3053                         pinctrl-0 = <&sdmmc1_3v3>;
3054                         pinctrl-1 = <&sdmmc1_1v8>;
3055                         nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
3056                         nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>;
3057                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
3058                         nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
3059                         nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
3060                         nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
3061                         nvidia,default-tap = <14>;
3062                         nvidia,default-trim = <0x8>;
3063                         sd-uhs-sdr25;
3064                         sd-uhs-sdr50;
3065                         sd-uhs-ddr50;
3066                         sd-uhs-sdr104;
3067                         status = "disabled";
3068                 };
3069
3070                 mmc@3460000 {
3071                         compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
3072                         reg = <0x0 0x03460000 0x0 0x20000>;
3073                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
3074                         clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
3075                                  <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
3076                         clock-names = "sdhci", "tmclk";
3077                         assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
3078                                           <&bpmp TEGRA234_CLK_PLLC4>;
3079                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>;
3080                         resets = <&bpmp TEGRA234_RESET_SDMMC4>;
3081                         reset-names = "sdhci";
3082                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>,
3083                                         <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>;
3084                         interconnect-names = "dma-mem", "write";
3085                         iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>;
3086                         nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
3087                         nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
3088                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
3089                         nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
3090                         nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
3091                         nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
3092                         nvidia,default-tap = <0x8>;
3093                         nvidia,default-trim = <0x14>;
3094                         nvidia,dqs-trim = <40>;
3095                         supports-cqe;
3096                         status = "disabled";
3097                 };
3098
3099                 hda@3510000 {
3100                         compatible = "nvidia,tegra234-hda";
3101                         reg = <0x0 0x3510000 0x0 0x10000>;
3102                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
3103                         clocks = <&bpmp TEGRA234_CLK_AZA_BIT>,
3104                                  <&bpmp TEGRA234_CLK_AZA_2XBIT>;
3105                         clock-names = "hda", "hda2codec_2x";
3106                         resets = <&bpmp TEGRA234_RESET_HDA>,
3107                                  <&bpmp TEGRA234_RESET_HDACODEC>;
3108                         reset-names = "hda", "hda2codec_2x";
3109                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
3110                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>,
3111                                         <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>;
3112                         interconnect-names = "dma-mem", "write";
3113                         iommus = <&smmu_niso0 TEGRA234_SID_HDA>;
3114                         status = "disabled";
3115                 };
3116
3117                 xusb_padctl: padctl@3520000 {
3118                         compatible = "nvidia,tegra234-xusb-padctl";
3119                         reg = <0x0 0x03520000 0x0 0x20000>,
3120                               <0x0 0x03540000 0x0 0x10000>;
3121                         reg-names = "padctl", "ao";
3122                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
3123
3124                         resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>;
3125                         reset-names = "padctl";
3126
3127                         status = "disabled";
3128
3129                         pads {
3130                                 usb2 {
3131                                         clocks = <&bpmp TEGRA234_CLK_USB2_TRK>;
3132                                         clock-names = "trk";
3133
3134                                         lanes {
3135                                                 usb2-0 {
3136                                                         nvidia,function = "xusb";
3137                                                         status = "disabled";
3138                                                         #phy-cells = <0>;
3139                                                 };
3140
3141                                                 usb2-1 {
3142                                                         nvidia,function = "xusb";
3143                                                         status = "disabled";
3144                                                         #phy-cells = <0>;
3145                                                 };
3146
3147                                                 usb2-2 {
3148                                                         nvidia,function = "xusb";
3149                                                         status = "disabled";
3150                                                         #phy-cells = <0>;
3151                                                 };
3152
3153                                                 usb2-3 {
3154                                                         nvidia,function = "xusb";
3155                                                         status = "disabled";
3156                                                         #phy-cells = <0>;
3157                                                 };
3158                                         };
3159                                 };
3160
3161                                 usb3 {
3162                                         lanes {
3163                                                 usb3-0 {
3164                                                         nvidia,function = "xusb";
3165                                                         status = "disabled";
3166                                                         #phy-cells = <0>;
3167                                                 };
3168
3169                                                 usb3-1 {
3170                                                         nvidia,function = "xusb";
3171                                                         status = "disabled";
3172                                                         #phy-cells = <0>;
3173                                                 };
3174
3175                                                 usb3-2 {
3176                                                         nvidia,function = "xusb";
3177                                                         status = "disabled";
3178                                                         #phy-cells = <0>;
3179                                                 };
3180
3181                                                 usb3-3 {
3182                                                         nvidia,function = "xusb";
3183                                                         status = "disabled";
3184                                                         #phy-cells = <0>;
3185                                                 };
3186                                         };
3187                                 };
3188                         };
3189
3190                         ports {
3191                                 usb2-0 {
3192                                         status = "disabled";
3193                                 };
3194
3195                                 usb2-1 {
3196                                         status = "disabled";
3197                                 };
3198
3199                                 usb2-2 {
3200                                         status = "disabled";
3201                                 };
3202
3203                                 usb2-3 {
3204                                         status = "disabled";
3205                                 };
3206
3207                                 usb3-0 {
3208                                         status = "disabled";
3209                                 };
3210
3211                                 usb3-1 {
3212                                         status = "disabled";
3213                                 };
3214
3215                                 usb3-2 {
3216                                         status = "disabled";
3217                                 };
3218
3219                                 usb3-3 {
3220                                         status = "disabled";
3221                                 };
3222                         };
3223                 };
3224
3225                 usb@3550000 {
3226                         compatible = "nvidia,tegra234-xudc";
3227                         reg = <0x0 0x03550000 0x0 0x8000>,
3228                               <0x0 0x03558000 0x0 0x8000>;
3229                         reg-names = "base", "fpci";
3230                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
3231                         clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>,
3232                                  <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
3233                                  <&bpmp TEGRA234_CLK_XUSB_SS>,
3234                                  <&bpmp TEGRA234_CLK_XUSB_FS>;
3235                         clock-names = "dev", "ss", "ss_src", "fs_src";
3236                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>,
3237                                         <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>;
3238                         interconnect-names = "dma-mem", "write";
3239                         iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>;
3240                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>,
3241                                         <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>;
3242                         power-domain-names = "dev", "ss";
3243                         nvidia,xusb-padctl = <&xusb_padctl>;
3244                         dma-coherent;
3245                         status = "disabled";
3246                 };
3247
3248                 usb@3610000 {
3249                         compatible = "nvidia,tegra234-xusb";
3250                         reg = <0x0 0x03610000 0x0 0x40000>,
3251                               <0x0 0x03600000 0x0 0x10000>,
3252                               <0x0 0x03650000 0x0 0x10000>;
3253                         reg-names = "hcd", "fpci", "bar2";
3254
3255                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
3256                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
3257
3258                         clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>,
3259                                  <&bpmp TEGRA234_CLK_XUSB_FALCON>,
3260                                  <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
3261                                  <&bpmp TEGRA234_CLK_XUSB_SS>,
3262                                  <&bpmp TEGRA234_CLK_CLK_M>,
3263                                  <&bpmp TEGRA234_CLK_XUSB_FS>,
3264                                  <&bpmp TEGRA234_CLK_UTMIP_PLL>,
3265                                  <&bpmp TEGRA234_CLK_CLK_M>,
3266                                  <&bpmp TEGRA234_CLK_PLLE>;
3267                         clock-names = "xusb_host", "xusb_falcon_src",
3268                                       "xusb_ss", "xusb_ss_src", "xusb_hs_src",
3269                                       "xusb_fs_src", "pll_u_480m", "clk_m",
3270                                       "pll_e";
3271                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>,
3272                                         <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>;
3273                         interconnect-names = "dma-mem", "write";
3274                         iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>;
3275
3276                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>,
3277                                         <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>;
3278                         power-domain-names = "xusb_host", "xusb_ss";
3279
3280                         nvidia,xusb-padctl = <&xusb_padctl>;
3281                         dma-coherent;
3282                         status = "disabled";
3283                 };
3284
3285                 fuse@3810000 {
3286                         compatible = "nvidia,tegra234-efuse";
3287                         reg = <0x0 0x03810000 0x0 0x10000>;
3288                         clocks = <&bpmp TEGRA234_CLK_FUSE>;
3289                         clock-names = "fuse";
3290                 };
3291
3292                 hte_lic: hardware-timestamp@3aa0000 {
3293                         compatible = "nvidia,tegra234-gte-lic";
3294                         reg = <0x0 0x3aa0000 0x0 0x10000>;
3295                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3296                         nvidia,int-threshold = <1>;
3297                         #timestamp-cells = <1>;
3298                 };
3299
3300                 hsp_top0: hsp@3c00000 {
3301                         compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
3302                         reg = <0x0 0x03c00000 0x0 0xa0000>;
3303                         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
3304                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
3305                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
3306                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
3307                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
3308                                      <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
3309                                      <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
3310                                      <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
3311                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
3312                         interrupt-names = "doorbell", "shared0", "shared1", "shared2",
3313                                           "shared3", "shared4", "shared5", "shared6",
3314                                           "shared7";
3315                         #mbox-cells = <2>;
3316                 };
3317
3318                 p2u_hsio_0: phy@3e00000 {
3319                         compatible = "nvidia,tegra234-p2u";
3320                         reg = <0x0 0x03e00000 0x0 0x10000>;
3321                         reg-names = "ctl";
3322
3323                         #phy-cells = <0>;
3324                 };
3325
3326                 p2u_hsio_1: phy@3e10000 {
3327                         compatible = "nvidia,tegra234-p2u";
3328                         reg = <0x0 0x03e10000 0x0 0x10000>;
3329                         reg-names = "ctl";
3330
3331                         #phy-cells = <0>;
3332                 };
3333
3334                 p2u_hsio_2: phy@3e20000 {
3335                         compatible = "nvidia,tegra234-p2u";
3336                         reg = <0x0 0x03e20000 0x0 0x10000>;
3337                         reg-names = "ctl";
3338
3339                         #phy-cells = <0>;
3340                 };
3341
3342                 p2u_hsio_3: phy@3e30000 {
3343                         compatible = "nvidia,tegra234-p2u";
3344                         reg = <0x0 0x03e30000 0x0 0x10000>;
3345                         reg-names = "ctl";
3346
3347                         #phy-cells = <0>;
3348                 };
3349
3350                 p2u_hsio_4: phy@3e40000 {
3351                         compatible = "nvidia,tegra234-p2u";
3352                         reg = <0x0 0x03e40000 0x0 0x10000>;
3353                         reg-names = "ctl";
3354
3355                         #phy-cells = <0>;
3356                 };
3357
3358                 p2u_hsio_5: phy@3e50000 {
3359                         compatible = "nvidia,tegra234-p2u";
3360                         reg = <0x0 0x03e50000 0x0 0x10000>;
3361                         reg-names = "ctl";
3362
3363                         #phy-cells = <0>;
3364                 };
3365
3366                 p2u_hsio_6: phy@3e60000 {
3367                         compatible = "nvidia,tegra234-p2u";
3368                         reg = <0x0 0x03e60000 0x0 0x10000>;
3369                         reg-names = "ctl";
3370
3371                         #phy-cells = <0>;
3372                 };
3373
3374                 p2u_hsio_7: phy@3e70000 {
3375                         compatible = "nvidia,tegra234-p2u";
3376                         reg = <0x0 0x03e70000 0x0 0x10000>;
3377                         reg-names = "ctl";
3378
3379                         #phy-cells = <0>;
3380                 };
3381
3382                 p2u_nvhs_0: phy@3e90000 {
3383                         compatible = "nvidia,tegra234-p2u";
3384                         reg = <0x0 0x03e90000 0x0 0x10000>;
3385                         reg-names = "ctl";
3386
3387                         #phy-cells = <0>;
3388                 };
3389
3390                 p2u_nvhs_1: phy@3ea0000 {
3391                         compatible = "nvidia,tegra234-p2u";
3392                         reg = <0x0 0x03ea0000 0x0 0x10000>;
3393                         reg-names = "ctl";
3394
3395                         #phy-cells = <0>;
3396                 };
3397
3398                 p2u_nvhs_2: phy@3eb0000 {
3399                         compatible = "nvidia,tegra234-p2u";
3400                         reg = <0x0 0x03eb0000 0x0 0x10000>;
3401                         reg-names = "ctl";
3402
3403                         #phy-cells = <0>;
3404                 };
3405
3406                 p2u_nvhs_3: phy@3ec0000 {
3407                         compatible = "nvidia,tegra234-p2u";
3408                         reg = <0x0 0x03ec0000 0x0 0x10000>;
3409                         reg-names = "ctl";
3410
3411                         #phy-cells = <0>;
3412                 };
3413
3414                 p2u_nvhs_4: phy@3ed0000 {
3415                         compatible = "nvidia,tegra234-p2u";
3416                         reg = <0x0 0x03ed0000 0x0 0x10000>;
3417                         reg-names = "ctl";
3418
3419                         #phy-cells = <0>;
3420                 };
3421
3422                 p2u_nvhs_5: phy@3ee0000 {
3423                         compatible = "nvidia,tegra234-p2u";
3424                         reg = <0x0 0x03ee0000 0x0 0x10000>;
3425                         reg-names = "ctl";
3426
3427                         #phy-cells = <0>;
3428                 };
3429
3430                 p2u_nvhs_6: phy@3ef0000 {
3431                         compatible = "nvidia,tegra234-p2u";
3432                         reg = <0x0 0x03ef0000 0x0 0x10000>;
3433                         reg-names = "ctl";
3434
3435                         #phy-cells = <0>;
3436                 };
3437
3438                 p2u_nvhs_7: phy@3f00000 {
3439                         compatible = "nvidia,tegra234-p2u";
3440                         reg = <0x0 0x03f00000 0x0 0x10000>;
3441                         reg-names = "ctl";
3442
3443                         #phy-cells = <0>;
3444                 };
3445
3446                 p2u_gbe_0: phy@3f20000 {
3447                         compatible = "nvidia,tegra234-p2u";
3448                         reg = <0x0 0x03f20000 0x0 0x10000>;
3449                         reg-names = "ctl";
3450
3451                         #phy-cells = <0>;
3452                 };
3453
3454                 p2u_gbe_1: phy@3f30000 {
3455                         compatible = "nvidia,tegra234-p2u";
3456                         reg = <0x0 0x03f30000 0x0 0x10000>;
3457                         reg-names = "ctl";
3458
3459                         #phy-cells = <0>;
3460                 };
3461
3462                 p2u_gbe_2: phy@3f40000 {
3463                         compatible = "nvidia,tegra234-p2u";
3464                         reg = <0x0 0x03f40000 0x0 0x10000>;
3465                         reg-names = "ctl";
3466
3467                         #phy-cells = <0>;
3468                 };
3469
3470                 p2u_gbe_3: phy@3f50000 {
3471                         compatible = "nvidia,tegra234-p2u";
3472                         reg = <0x0 0x03f50000 0x0 0x10000>;
3473                         reg-names = "ctl";
3474
3475                         #phy-cells = <0>;
3476                 };
3477
3478                 p2u_gbe_4: phy@3f60000 {
3479                         compatible = "nvidia,tegra234-p2u";
3480                         reg = <0x0 0x03f60000 0x0 0x10000>;
3481                         reg-names = "ctl";
3482
3483                         #phy-cells = <0>;
3484                 };
3485
3486                 p2u_gbe_5: phy@3f70000 {
3487                         compatible = "nvidia,tegra234-p2u";
3488                         reg = <0x0 0x03f70000 0x0 0x10000>;
3489                         reg-names = "ctl";
3490
3491                         #phy-cells = <0>;
3492                 };
3493
3494                 p2u_gbe_6: phy@3f80000 {
3495                         compatible = "nvidia,tegra234-p2u";
3496                         reg = <0x0 0x03f80000 0x0 0x10000>;
3497                         reg-names = "ctl";
3498
3499                         #phy-cells = <0>;
3500                 };
3501
3502                 p2u_gbe_7: phy@3f90000 {
3503                         compatible = "nvidia,tegra234-p2u";
3504                         reg = <0x0 0x03f90000 0x0 0x10000>;
3505                         reg-names = "ctl";
3506
3507                         #phy-cells = <0>;
3508                 };
3509
3510                 ethernet@6800000 {
3511                         compatible = "nvidia,tegra234-mgbe";
3512                         reg = <0x0 0x06800000 0x0 0x10000>,
3513                               <0x0 0x06810000 0x0 0x10000>,
3514                               <0x0 0x068a0000 0x0 0x10000>;
3515                         reg-names = "hypervisor", "mac", "xpcs";
3516                         interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
3517                         interrupt-names = "common";
3518                         clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
3519                                  <&bpmp TEGRA234_CLK_MGBE0_MAC>,
3520                                  <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
3521                                  <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
3522                                  <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
3523                                  <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
3524                                  <&bpmp TEGRA234_CLK_MGBE0_TX>,
3525                                  <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
3526                                  <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
3527                                  <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
3528                                  <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
3529                                  <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
3530                         clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
3531                                       "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
3532                                       "rx-pcs", "tx-pcs";
3533                         resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
3534                                  <&bpmp TEGRA234_RESET_MGBE0_PCS>;
3535                         reset-names = "mac", "pcs";
3536                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
3537                                         <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
3538                         interconnect-names = "dma-mem", "write";
3539                         iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
3540                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
3541                         status = "disabled";
3542
3543                         snps,axi-config = <&mgbe0_axi_setup>;
3544
3545                         mgbe0_axi_setup: stmmac-axi-config {
3546                                 snps,blen = <256 128 64 32>;
3547                                 snps,rd_osr_lmt = <63>;
3548                                 snps,wr_osr_lmt = <63>;
3549                         };
3550                 };
3551
3552                 ethernet@6900000 {
3553                         compatible = "nvidia,tegra234-mgbe";
3554                         reg = <0x0 0x06900000 0x0 0x10000>,
3555                               <0x0 0x06910000 0x0 0x10000>,
3556                               <0x0 0x069a0000 0x0 0x10000>;
3557                         reg-names = "hypervisor", "mac", "xpcs";
3558                         interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
3559                         interrupt-names = "common";
3560                         clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>,
3561                                  <&bpmp TEGRA234_CLK_MGBE1_MAC>,
3562                                  <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>,
3563                                  <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>,
3564                                  <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>,
3565                                  <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>,
3566                                  <&bpmp TEGRA234_CLK_MGBE1_TX>,
3567                                  <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>,
3568                                  <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>,
3569                                  <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>,
3570                                  <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>,
3571                                  <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>;
3572                         clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
3573                                       "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
3574                                       "rx-pcs", "tx-pcs";
3575                         resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>,
3576                                  <&bpmp TEGRA234_RESET_MGBE1_PCS>;
3577                         reset-names = "mac", "pcs";
3578                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>,
3579                                         <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>;
3580                         interconnect-names = "dma-mem", "write";
3581                         iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>;
3582                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
3583                         status = "disabled";
3584
3585                         snps,axi-config = <&mgbe1_axi_setup>;
3586
3587                         mgbe1_axi_setup: stmmac-axi-config {
3588                                 snps,blen = <256 128 64 32>;
3589                                 snps,rd_osr_lmt = <63>;
3590                                 snps,wr_osr_lmt = <63>;
3591                         };
3592                 };
3593
3594                 ethernet@6a00000 {
3595                         compatible = "nvidia,tegra234-mgbe";
3596                         reg = <0x0 0x06a00000 0x0 0x10000>,
3597                               <0x0 0x06a10000 0x0 0x10000>,
3598                               <0x0 0x06aa0000 0x0 0x10000>;
3599                         reg-names = "hypervisor", "mac", "xpcs";
3600                         interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
3601                         interrupt-names = "common";
3602                         clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>,
3603                                  <&bpmp TEGRA234_CLK_MGBE2_MAC>,
3604                                  <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>,
3605                                  <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>,
3606                                  <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>,
3607                                  <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>,
3608                                  <&bpmp TEGRA234_CLK_MGBE2_TX>,
3609                                  <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>,
3610                                  <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>,
3611                                  <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>,
3612                                  <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>,
3613                                  <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>;
3614                         clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
3615                                       "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
3616                                       "rx-pcs", "tx-pcs";
3617                         resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>,
3618                                  <&bpmp TEGRA234_RESET_MGBE2_PCS>;
3619                         reset-names = "mac", "pcs";
3620                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>,
3621                                         <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>;
3622                         interconnect-names = "dma-mem", "write";
3623                         iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>;
3624                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
3625                         status = "disabled";
3626
3627                         snps,axi-config = <&mgbe2_axi_setup>;
3628
3629                         mgbe2_axi_setup: stmmac-axi-config {
3630                                 snps,blen = <256 128 64 32>;
3631                                 snps,rd_osr_lmt = <63>;
3632                                 snps,wr_osr_lmt = <63>;
3633                         };
3634                 };
3635
3636                 ethernet@6b00000 {
3637                         compatible = "nvidia,tegra234-mgbe";
3638                         reg = <0x0 0x06b00000 0x0 0x10000>,
3639                               <0x0 0x06b10000 0x0 0x10000>,
3640                               <0x0 0x06ba0000 0x0 0x10000>;
3641                         reg-names = "hypervisor", "mac", "xpcs";
3642                         interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
3643                         interrupt-names = "common";
3644                         clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>,
3645                                  <&bpmp TEGRA234_CLK_MGBE3_MAC>,
3646                                  <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>,
3647                                  <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>,
3648                                  <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>,
3649                                  <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>,
3650                                  <&bpmp TEGRA234_CLK_MGBE3_TX>,
3651                                  <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>,
3652                                  <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>,
3653                                  <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>,
3654                                  <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>,
3655                                  <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>;
3656                         clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
3657                                       "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
3658                                       "rx-pcs", "tx-pcs";
3659                         resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>,
3660                                  <&bpmp TEGRA234_RESET_MGBE3_PCS>;
3661                         reset-names = "mac", "pcs";
3662                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>,
3663                                         <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>;
3664                         interconnect-names = "dma-mem", "write";
3665                         iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>;
3666                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
3667                         status = "disabled";
3668                 };
3669
3670                 smmu_niso1: iommu@8000000 {
3671                         compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
3672                         reg = <0x0 0x8000000 0x0 0x1000000>,
3673                               <0x0 0x7000000 0x0 0x1000000>;
3674                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3675                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
3676                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3677                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
3678                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3679                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3680                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3681                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3682                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3683                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3684                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3685                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3686                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3687                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3688                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3689                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3690                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3691                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3692                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3693                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3694                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3695                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3696                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3697                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3698                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3699                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3700                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3701                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3702                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3703                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3704                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3705                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3706                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3707                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3708                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3709                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3710                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3711                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3712                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3713                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3714                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3715                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3716                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3717                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3718                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3719                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3720                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3721                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3722                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3723                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3724                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3725                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3726                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3727                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3728                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3729                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3730                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3731                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3732                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3733                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3734                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3735                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3736                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3737                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3738                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3739                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3740                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3741                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3742                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3743                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3744                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3745                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3746                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3747                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3748                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3749                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3750                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3751                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3752                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3753                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3754                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3755                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3756                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3757                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3758                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3759                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3760                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3761                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3762                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3763                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3764                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3765                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3766                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3767                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3768                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3769                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3770                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3771                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3772                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3773                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3774                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3775                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3776                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3777                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3778                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3779                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3780                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3781                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3782                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3783                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3784                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3785                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3786                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3787                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3788                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3789                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3790                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3791                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3792                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3793                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3794                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3795                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3796                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3797                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3798                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3799                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3800                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3801                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3802                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3803                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
3804                         stream-match-mask = <0x7f80>;
3805                         #global-interrupts = <2>;
3806                         #iommu-cells = <1>;
3807
3808                         nvidia,memory-controller = <&mc>;
3809                         status = "okay";
3810                 };
3811
3812                 sce-fabric@b600000 {
3813                         compatible = "nvidia,tegra234-sce-fabric";
3814                         reg = <0x0 0xb600000 0x0 0x40000>;
3815                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
3816                         status = "okay";
3817                 };
3818
3819                 rce-fabric@be00000 {
3820                         compatible = "nvidia,tegra234-rce-fabric";
3821                         reg = <0x0 0xbe00000 0x0 0x40000>;
3822                         interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
3823                         status = "okay";
3824                 };
3825
3826                 hsp_aon: hsp@c150000 {
3827                         compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
3828                         reg = <0x0 0x0c150000 0x0 0x90000>;
3829                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
3830                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
3831                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
3832                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
3833                         /*
3834                          * Shared interrupt 0 is routed only to AON/SPE, so
3835                          * we only have 4 shared interrupts for the CCPLEX.
3836                          */
3837                         interrupt-names = "shared1", "shared2", "shared3", "shared4";
3838                         #mbox-cells = <2>;
3839                 };
3840
3841                 hte_aon: hardware-timestamp@c1e0000 {
3842                         compatible = "nvidia,tegra234-gte-aon";
3843                         reg = <0x0 0xc1e0000 0x0 0x10000>;
3844                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3845                         nvidia,int-threshold = <1>;
3846                         nvidia,gpio-controller = <&gpio_aon>;
3847                         #timestamp-cells = <1>;
3848                 };
3849
3850                 gen2_i2c: i2c@c240000 {
3851                         compatible = "nvidia,tegra194-i2c";
3852                         reg = <0x0 0xc240000 0x0 0x100>;
3853                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
3854                         #address-cells = <1>;
3855                         #size-cells = <0>;
3856                         status = "disabled";
3857                         clock-frequency = <100000>;
3858                         clocks = <&bpmp TEGRA234_CLK_I2C2>,
3859                                  <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3860                         clock-names = "div-clk", "parent";
3861                         assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
3862                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3863                         resets = <&bpmp TEGRA234_RESET_I2C2>;
3864                         reset-names = "i2c";
3865                         dmas = <&gpcdma 22>, <&gpcdma 22>;
3866                         dma-names = "rx", "tx";
3867                 };
3868
3869                 gen8_i2c: i2c@c250000 {
3870                         compatible = "nvidia,tegra194-i2c";
3871                         reg = <0x0 0xc250000 0x0 0x100>;
3872                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3873                         #address-cells = <1>;
3874                         #size-cells = <0>;
3875                         status = "disabled";
3876                         clock-frequency = <400000>;
3877                         clocks = <&bpmp TEGRA234_CLK_I2C8>,
3878                                  <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3879                         clock-names = "div-clk", "parent";
3880                         assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
3881                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3882                         resets = <&bpmp TEGRA234_RESET_I2C8>;
3883                         reset-names = "i2c";
3884                         dmas = <&gpcdma 0>, <&gpcdma 0>;
3885                         dma-names = "rx", "tx";
3886                 };
3887
3888                 spi@c260000 {
3889                         compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
3890                         reg = <0x0 0x0c260000 0x0 0x1000>;
3891                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3892                         #address-cells = <1>;
3893                         #size-cells = <0>;
3894                         clocks = <&bpmp TEGRA234_CLK_SPI2>;
3895                         clock-names = "spi";
3896                         iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
3897                         assigned-clocks = <&bpmp TEGRA234_CLK_SPI2>;
3898                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3899                         resets = <&bpmp TEGRA234_RESET_SPI2>;
3900                         reset-names = "spi";
3901                         dmas = <&gpcdma 19>, <&gpcdma 19>;
3902                         dma-names = "rx", "tx";
3903                         dma-coherent;
3904                         status = "disabled";
3905                 };
3906
3907                 rtc@c2a0000 {
3908                         compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
3909                         reg = <0x0 0x0c2a0000 0x0 0x10000>;
3910                         interrupt-parent = <&pmc>;
3911                         interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
3912                         clocks = <&bpmp TEGRA234_CLK_CLK_32K>;
3913                         clock-names = "rtc";
3914                         status = "disabled";
3915                 };
3916
3917                 gpio_aon: gpio@c2f0000 {
3918                         compatible = "nvidia,tegra234-gpio-aon";
3919                         reg-names = "security", "gpio";
3920                         reg = <0x0 0x0c2f0000 0x0 0x1000>,
3921                               <0x0 0x0c2f1000 0x0 0x1000>;
3922                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
3923                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
3924                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
3925                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
3926                         #interrupt-cells = <2>;
3927                         interrupt-controller;
3928                         #gpio-cells = <2>;
3929                         gpio-controller;
3930                         gpio-ranges = <&pinmux_aon 0 0 32>;
3931                 };
3932
3933                 pinmux_aon: pinmux@c300000 {
3934                         compatible = "nvidia,tegra234-pinmux-aon";
3935                         reg = <0x0 0xc300000 0x0 0x4000>;
3936                 };
3937
3938                 pwm4: pwm@c340000 {
3939                         compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
3940                         reg = <0x0 0xc340000 0x0 0x10000>;
3941                         clocks = <&bpmp TEGRA234_CLK_PWM4>;
3942                         resets = <&bpmp TEGRA234_RESET_PWM4>;
3943                         reset-names = "pwm";
3944                         status = "disabled";
3945                         #pwm-cells = <2>;
3946                 };
3947
3948                 pmc: pmc@c360000 {
3949                         compatible = "nvidia,tegra234-pmc";
3950                         reg = <0x0 0x0c360000 0x0 0x10000>,
3951                               <0x0 0x0c370000 0x0 0x10000>,
3952                               <0x0 0x0c380000 0x0 0x10000>,
3953                               <0x0 0x0c390000 0x0 0x10000>,
3954                               <0x0 0x0c3a0000 0x0 0x10000>;
3955                         reg-names = "pmc", "wake", "aotag", "scratch", "misc";
3956
3957                         #interrupt-cells = <2>;
3958                         interrupt-controller;
3959
3960                         sdmmc1_1v8: sdmmc1-1v8 {
3961                                 pins = "sdmmc1-hv";
3962                                 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
3963                         };
3964
3965                         sdmmc1_3v3: sdmmc1-3v3 {
3966                                 pins = "sdmmc1-hv";
3967                                 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
3968                         };
3969
3970                         sdmmc3_1v8: sdmmc3-1v8 {
3971                                 pins = "sdmmc3-hv";
3972                                 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
3973                         };
3974
3975                         sdmmc3_3v3: sdmmc3-3v3 {
3976                                 pins = "sdmmc3-hv";
3977                                 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
3978                         };
3979                 };
3980
3981                 aon-fabric@c600000 {
3982                         compatible = "nvidia,tegra234-aon-fabric";
3983                         reg = <0x0 0xc600000 0x0 0x40000>;
3984                         interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
3985                         status = "okay";
3986                 };
3987
3988                 bpmp-fabric@d600000 {
3989                         compatible = "nvidia,tegra234-bpmp-fabric";
3990                         reg = <0x0 0xd600000 0x0 0x40000>;
3991                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3992                         status = "okay";
3993                 };
3994
3995                 dce-fabric@de00000 {
3996                         compatible = "nvidia,tegra234-sce-fabric";
3997                         reg = <0x0 0xde00000 0x0 0x40000>;
3998                         interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
3999                         status = "okay";
4000                 };
4001
4002                 ccplex@e000000 {
4003                         compatible = "nvidia,tegra234-ccplex-cluster";
4004                         reg = <0x0 0x0e000000 0x0 0x5ffff>;
4005                         nvidia,bpmp = <&bpmp>;
4006                         status = "okay";
4007                 };
4008
4009                 gic: interrupt-controller@f400000 {
4010                         compatible = "arm,gic-v3";
4011                         reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */
4012                               <0x0 0x0f440000 0x0 0x200000>; /* GICR */
4013                         interrupt-parent = <&gic>;
4014                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
4015
4016                         #redistributor-regions = <1>;
4017                         #interrupt-cells = <3>;
4018                         interrupt-controller;
4019                 };
4020
4021                 smmu_iso: iommu@10000000 {
4022                         compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
4023                         reg = <0x0 0x10000000 0x0 0x1000000>;
4024                         interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4025                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4026                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4027                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4028                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4029                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4030                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4031                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4032                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4033                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4034                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4035                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4036                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4037                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4038                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4039                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4040                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4041                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4042                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4043                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4044                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4045                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4046                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4047                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4048                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4049                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4050                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4051                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4052                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4053                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4054                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4055                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4056                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4057                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4058                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4059                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4060                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4061                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4062                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4063                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4064                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4065                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4066                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4067                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4068                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4069                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4070                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4071                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4072                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4073                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4074                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4075                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4076                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4077                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4078                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4079                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4080                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4081                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4082                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4083                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4084                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4085                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4086                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4087                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4088                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4089                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4090                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4091                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4092                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4093                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4094                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4095                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4096                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4097                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4098                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4099                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4100                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4101                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4102                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4103                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4104                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4105                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4106                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4107                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4108                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4109                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4110                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4111                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4112                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4113                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4114                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4115                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4116                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4117                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4118                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4119                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4120                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4121                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4122                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4123                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4124                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4125                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4126                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4127                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4128                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4129                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4130                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4131                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4132                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4133                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4134                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4135                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4136                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4137                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4138                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4139                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4140                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4141                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4142                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4143                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4144                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4145                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4146                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4147                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4148                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4149                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4150                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4151                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4152                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
4153                         stream-match-mask = <0x7f80>;
4154                         #global-interrupts = <1>;
4155                         #iommu-cells = <1>;
4156
4157                         nvidia,memory-controller = <&mc>;
4158                         status = "okay";
4159                 };
4160
4161                 smmu_niso0: iommu@12000000 {
4162                         compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
4163                         reg = <0x0 0x12000000 0x0 0x1000000>,
4164                               <0x0 0x11000000 0x0 0x1000000>;
4165                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4166                                      <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
4167                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4168                                      <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
4169                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4170                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4171                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4172                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4173                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4174                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4175                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4176                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4177                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4178                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4179                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4180                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4181                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4182                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4183                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4184                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4185                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4186                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4187                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4188                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4189                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4190                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4191                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4192                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4193                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4194                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4195                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4196                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4197                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4198                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4199                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4200                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4201                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4202                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4203                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4204                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4205                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4206                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4207                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4208                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4209                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4210                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4211                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4212                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4213                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4214                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4215                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4216                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4217                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4218                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4219                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4220                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4221                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4222                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4223                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4224                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4225                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4226                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4227                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4228                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4229                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4230                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4231                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4232                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4233                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4234                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4235                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4236                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4237                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4238                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4239                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4240                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4241                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4242                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4243                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4244                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4245                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4246                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4247                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4248                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4249                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4250                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4251                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4252                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4253                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4254                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4255                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4256                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4257                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4258                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4259                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4260                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4261                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4262                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4263                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4264                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4265                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4266                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4267                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4268                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4269                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4270                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4271                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4272                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4273                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4274                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4275                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4276                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4277                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4278                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4279                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4280                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4281                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4282                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4283                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4284                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4285                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4286                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4287                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4288                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4289                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4290                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4291                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4292                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4293                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
4294                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
4295                         stream-match-mask = <0x7f80>;
4296                         #global-interrupts = <2>;
4297                         #iommu-cells = <1>;
4298
4299                         nvidia,memory-controller = <&mc>;
4300                         status = "okay";
4301                 };
4302
4303                 cbb-fabric@13a00000 {
4304                         compatible = "nvidia,tegra234-cbb-fabric";
4305                         reg = <0x0 0x13a00000 0x0 0x400000>;
4306                         interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
4307                         status = "okay";
4308                 };
4309
4310                 host1x@13e00000 {
4311                         compatible = "nvidia,tegra234-host1x";
4312                         reg = <0x0 0x13e00000 0x0 0x10000>,
4313                               <0x0 0x13e10000 0x0 0x10000>,
4314                               <0x0 0x13e40000 0x0 0x10000>;
4315                         reg-names = "common", "hypervisor", "vm";
4316                         interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4317                                      <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
4318                                      <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
4319                                      <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
4320                                      <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
4321                                      <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
4322                                      <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
4323                                      <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
4324                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
4325                         interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4",
4326                                           "syncpt5", "syncpt6", "syncpt7", "host1x";
4327                         clocks = <&bpmp TEGRA234_CLK_HOST1X>;
4328                         clock-names = "host1x";
4329
4330                         #address-cells = <2>;
4331                         #size-cells = <2>;
4332                         ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>;
4333
4334                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>;
4335                         interconnect-names = "dma-mem";
4336                         iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>;
4337                         dma-coherent;
4338
4339                         /* Context isolation domains */
4340                         iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
4341                                     <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>,
4342                                     <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>,
4343                                     <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>,
4344                                     <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>,
4345                                     <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>,
4346                                     <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>,
4347                                     <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>,
4348                                     <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>,
4349                                     <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>,
4350                                     <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>,
4351                                     <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>,
4352                                     <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>,
4353                                     <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>,
4354                                     <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>,
4355                                     <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>;
4356
4357                         vic@15340000 {
4358                                 compatible = "nvidia,tegra234-vic";
4359                                 reg = <0x0 0x15340000 0x0 0x00040000>;
4360                                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
4361                                 clocks = <&bpmp TEGRA234_CLK_VIC>;
4362                                 clock-names = "vic";
4363                                 resets = <&bpmp TEGRA234_RESET_VIC>;
4364                                 reset-names = "vic";
4365
4366                                 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>;
4367                                 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>,
4368                                                 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>;
4369                                 interconnect-names = "dma-mem", "write";
4370                                 iommus = <&smmu_niso1 TEGRA234_SID_VIC>;
4371                                 dma-coherent;
4372                         };
4373
4374                         nvdec@15480000 {
4375                                 compatible = "nvidia,tegra234-nvdec";
4376                                 reg = <0x0 0x15480000 0x0 0x00040000>;
4377                                 clocks = <&bpmp TEGRA234_CLK_NVDEC>,
4378                                          <&bpmp TEGRA234_CLK_FUSE>,
4379                                          <&bpmp TEGRA234_CLK_TSEC_PKA>;
4380                                 clock-names = "nvdec", "fuse", "tsec_pka";
4381                                 resets = <&bpmp TEGRA234_RESET_NVDEC>;
4382                                 reset-names = "nvdec";
4383                                 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
4384                                 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
4385                                                 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
4386                                 interconnect-names = "dma-mem", "write";
4387                                 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
4388                                 dma-coherent;
4389
4390                                 nvidia,memory-controller = <&mc>;
4391
4392                                 /*
4393                                  * Placeholder values that firmware needs to update with the real
4394                                  * offsets parsed from the microcode headers.
4395                                  */
4396                                 nvidia,bl-manifest-offset = <0>;
4397                                 nvidia,bl-data-offset = <0>;
4398                                 nvidia,bl-code-offset = <0>;
4399                                 nvidia,os-manifest-offset = <0>;
4400                                 nvidia,os-data-offset = <0>;
4401                                 nvidia,os-code-offset = <0>;
4402
4403                                 /*
4404                                  * Firmware needs to set this to "okay" once the above values have
4405                                  * been updated.
4406                                  */
4407                                 status = "disabled";
4408                         };
4409                 };
4410
4411                 pcie@140a0000 {
4412                         compatible = "nvidia,tegra234-pcie";
4413                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>;
4414                         reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K)      */
4415                               <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */
4416                               <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
4417                               <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
4418                               <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
4419                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4420
4421                         #address-cells = <3>;
4422                         #size-cells = <2>;
4423                         device_type = "pci";
4424                         num-lanes = <4>;
4425                         num-viewport = <8>;
4426                         linux,pci-domain = <8>;
4427
4428                         clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>;
4429                         clock-names = "core";
4430
4431                         resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>,
4432                                  <&bpmp TEGRA234_RESET_PEX2_CORE_8>;
4433                         reset-names = "apb", "core";
4434
4435                         interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
4436                                      <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
4437                         interrupt-names = "intr", "msi";
4438
4439                         #interrupt-cells = <1>;
4440                         interrupt-map-mask = <0 0 0 0>;
4441                         interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
4442
4443                         nvidia,bpmp = <&bpmp 8>;
4444
4445                         nvidia,aspm-cmrt-us = <60>;
4446                         nvidia,aspm-pwr-on-t-us = <20>;
4447                         nvidia,aspm-l0s-entrance-latency-us = <3>;
4448
4449                         bus-range = <0x0 0xff>;
4450
4451                         ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
4452                                  <0x02000000 0x0  0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4453                                  <0x01000000 0x0  0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4454
4455                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>,
4456                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>;
4457                         interconnect-names = "dma-mem", "write";
4458                         iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>;
4459                         iommu-map-mask = <0x0>;
4460                         dma-coherent;
4461
4462                         status = "disabled";
4463                 };
4464
4465                 pcie@140c0000 {
4466                         compatible = "nvidia,tegra234-pcie";
4467                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>;
4468                         reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K)      */
4469                               <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */
4470                               <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
4471                               <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K)       */
4472                               <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
4473                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4474
4475                         #address-cells = <3>;
4476                         #size-cells = <2>;
4477                         device_type = "pci";
4478                         num-lanes = <4>;
4479                         num-viewport = <8>;
4480                         linux,pci-domain = <9>;
4481
4482                         clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>;
4483                         clock-names = "core";
4484
4485                         resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>,
4486                                  <&bpmp TEGRA234_RESET_PEX2_CORE_9>;
4487                         reset-names = "apb", "core";
4488
4489                         interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
4490                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
4491                         interrupt-names = "intr", "msi";
4492
4493                         #interrupt-cells = <1>;
4494                         interrupt-map-mask = <0 0 0 0>;
4495                         interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
4496
4497                         nvidia,bpmp = <&bpmp 9>;
4498
4499                         nvidia,aspm-cmrt-us = <60>;
4500                         nvidia,aspm-pwr-on-t-us = <20>;
4501                         nvidia,aspm-l0s-entrance-latency-us = <3>;
4502
4503                         bus-range = <0x0 0xff>;
4504
4505                         ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */
4506                                  <0x02000000 0x0  0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4507                                  <0x01000000 0x0  0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4508
4509                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>,
4510                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>;
4511                         interconnect-names = "dma-mem", "write";
4512                         iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>;
4513                         iommu-map-mask = <0x0>;
4514                         dma-coherent;
4515
4516                         status = "disabled";
4517                 };
4518
4519                 pcie@140e0000 {
4520                         compatible = "nvidia,tegra234-pcie";
4521                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
4522                         reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K)      */
4523                               <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */
4524                               <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
4525                               <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K)       */
4526                               <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
4527                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4528
4529                         #address-cells = <3>;
4530                         #size-cells = <2>;
4531                         device_type = "pci";
4532                         num-lanes = <4>;
4533                         num-viewport = <8>;
4534                         linux,pci-domain = <10>;
4535
4536                         clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
4537                         clock-names = "core";
4538
4539                         resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
4540                                  <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
4541                         reset-names = "apb", "core";
4542
4543                         interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
4544                                      <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
4545                         interrupt-names = "intr", "msi";
4546
4547                         #interrupt-cells = <1>;
4548                         interrupt-map-mask = <0 0 0 0>;
4549                         interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
4550
4551                         nvidia,bpmp = <&bpmp 10>;
4552
4553                         nvidia,aspm-cmrt-us = <60>;
4554                         nvidia,aspm-pwr-on-t-us = <20>;
4555                         nvidia,aspm-l0s-entrance-latency-us = <3>;
4556
4557                         bus-range = <0x0 0xff>;
4558
4559                         ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
4560                                  <0x02000000 0x0  0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4561                                  <0x01000000 0x0  0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4562
4563                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
4564                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
4565                         interconnect-names = "dma-mem", "write";
4566                         iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
4567                         iommu-map-mask = <0x0>;
4568                         dma-coherent;
4569
4570                         status = "disabled";
4571                 };
4572
4573                 pcie-ep@140e0000 {
4574                         compatible = "nvidia,tegra234-pcie-ep";
4575                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
4576                         reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K)      */
4577                               <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
4578                               <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K)           */
4579                               <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G)        */
4580                         reg-names = "appl", "atu_dma", "dbi", "addr_space";
4581
4582                         num-lanes = <4>;
4583
4584                         clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
4585                         clock-names = "core";
4586
4587                         resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
4588                                  <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
4589                         reset-names = "apb", "core";
4590
4591                         interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
4592                         interrupt-names = "intr";
4593
4594                         nvidia,bpmp = <&bpmp 10>;
4595
4596                         nvidia,enable-ext-refclk;
4597                         nvidia,aspm-cmrt-us = <60>;
4598                         nvidia,aspm-pwr-on-t-us = <20>;
4599                         nvidia,aspm-l0s-entrance-latency-us = <3>;
4600
4601                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
4602                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
4603                         interconnect-names = "dma-mem", "write";
4604                         iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
4605                         iommu-map-mask = <0x0>;
4606                         dma-coherent;
4607
4608                         status = "disabled";
4609                 };
4610
4611                 pcie@14100000 {
4612                         compatible = "nvidia,tegra234-pcie";
4613                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
4614                         reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K)      */
4615                               <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
4616                               <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
4617                               <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K)       */
4618                               <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB)               */
4619                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4620
4621                         #address-cells = <3>;
4622                         #size-cells = <2>;
4623                         device_type = "pci";
4624                         num-lanes = <1>;
4625                         num-viewport = <8>;
4626                         linux,pci-domain = <1>;
4627
4628                         clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>;
4629                         clock-names = "core";
4630
4631                         resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>,
4632                                  <&bpmp TEGRA234_RESET_PEX0_CORE_1>;
4633                         reset-names = "apb", "core";
4634
4635                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
4636                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
4637                         interrupt-names = "intr", "msi";
4638
4639                         #interrupt-cells = <1>;
4640                         interrupt-map-mask = <0 0 0 0>;
4641                         interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
4642
4643                         nvidia,bpmp = <&bpmp 1>;
4644
4645                         nvidia,aspm-cmrt-us = <60>;
4646                         nvidia,aspm-pwr-on-t-us = <20>;
4647                         nvidia,aspm-l0s-entrance-latency-us = <3>;
4648
4649                         bus-range = <0x0 0xff>;
4650
4651                         ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
4652                                  <0x02000000 0x0  0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4653                                  <0x01000000 0x0  0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4654
4655                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>,
4656                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>;
4657                         interconnect-names = "dma-mem", "write";
4658                         iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>;
4659                         iommu-map-mask = <0x0>;
4660                         dma-coherent;
4661
4662                         status = "disabled";
4663                 };
4664
4665                 pcie@14120000 {
4666                         compatible = "nvidia,tegra234-pcie";
4667                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
4668                         reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K)      */
4669                               <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
4670                               <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
4671                               <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K)       */
4672                               <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB)               */
4673                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4674
4675                         #address-cells = <3>;
4676                         #size-cells = <2>;
4677                         device_type = "pci";
4678                         num-lanes = <1>;
4679                         num-viewport = <8>;
4680                         linux,pci-domain = <2>;
4681
4682                         clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>;
4683                         clock-names = "core";
4684
4685                         resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>,
4686                                  <&bpmp TEGRA234_RESET_PEX0_CORE_2>;
4687                         reset-names = "apb", "core";
4688
4689                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
4690                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
4691                         interrupt-names = "intr", "msi";
4692
4693                         #interrupt-cells = <1>;
4694                         interrupt-map-mask = <0 0 0 0>;
4695                         interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
4696
4697                         nvidia,bpmp = <&bpmp 2>;
4698
4699                         nvidia,aspm-cmrt-us = <60>;
4700                         nvidia,aspm-pwr-on-t-us = <20>;
4701                         nvidia,aspm-l0s-entrance-latency-us = <3>;
4702
4703                         bus-range = <0x0 0xff>;
4704
4705                         ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
4706                                  <0x02000000 0x0  0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4707                                  <0x01000000 0x0  0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4708
4709                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>,
4710                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>;
4711                         interconnect-names = "dma-mem", "write";
4712                         iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>;
4713                         iommu-map-mask = <0x0>;
4714                         dma-coherent;
4715
4716                         status = "disabled";
4717                 };
4718
4719                 pcie@14140000 {
4720                         compatible = "nvidia,tegra234-pcie";
4721                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
4722                         reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K)      */
4723                               <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
4724                               <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
4725                               <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K)       */
4726                               <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
4727                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4728
4729                         #address-cells = <3>;
4730                         #size-cells = <2>;
4731                         device_type = "pci";
4732                         num-lanes = <1>;
4733                         num-viewport = <8>;
4734                         linux,pci-domain = <3>;
4735
4736                         clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>;
4737                         clock-names = "core";
4738
4739                         resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>,
4740                                  <&bpmp TEGRA234_RESET_PEX0_CORE_3>;
4741                         reset-names = "apb", "core";
4742
4743                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
4744                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
4745                         interrupt-names = "intr", "msi";
4746
4747                         #interrupt-cells = <1>;
4748                         interrupt-map-mask = <0 0 0 0>;
4749                         interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
4750
4751                         nvidia,bpmp = <&bpmp 3>;
4752
4753                         nvidia,aspm-cmrt-us = <60>;
4754                         nvidia,aspm-pwr-on-t-us = <20>;
4755                         nvidia,aspm-l0s-entrance-latency-us = <3>;
4756
4757                         bus-range = <0x0 0xff>;
4758
4759                         ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
4760                                  <0x02000000 0x0  0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4761                                  <0x01000000 0x0  0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4762
4763                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>,
4764                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>;
4765                         interconnect-names = "dma-mem", "write";
4766                         iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>;
4767                         iommu-map-mask = <0x0>;
4768                         dma-coherent;
4769
4770                         status = "disabled";
4771                 };
4772
4773                 pcie@14160000 {
4774                         compatible = "nvidia,tegra234-pcie";
4775                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
4776                         reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
4777                               <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
4778                               <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
4779                               <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K)       */
4780                               <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
4781                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4782
4783                         #address-cells = <3>;
4784                         #size-cells = <2>;
4785                         device_type = "pci";
4786                         num-lanes = <4>;
4787                         num-viewport = <8>;
4788                         linux,pci-domain = <4>;
4789
4790                         clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
4791                         clock-names = "core";
4792
4793                         resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
4794                                  <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
4795                         reset-names = "apb", "core";
4796
4797                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
4798                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
4799                         interrupt-names = "intr", "msi";
4800
4801                         #interrupt-cells = <1>;
4802                         interrupt-map-mask = <0 0 0 0>;
4803                         interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
4804
4805                         nvidia,bpmp = <&bpmp 4>;
4806
4807                         nvidia,aspm-cmrt-us = <60>;
4808                         nvidia,aspm-pwr-on-t-us = <20>;
4809                         nvidia,aspm-l0s-entrance-latency-us = <3>;
4810
4811                         bus-range = <0x0 0xff>;
4812
4813                         ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
4814                                  <0x02000000 0x0  0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4815                                  <0x01000000 0x0  0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4816
4817                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>,
4818                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>;
4819                         interconnect-names = "dma-mem", "write";
4820                         iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>;
4821                         iommu-map-mask = <0x0>;
4822                         dma-coherent;
4823
4824                         status = "disabled";
4825                 };
4826
4827                 pcie@14180000 {
4828                         compatible = "nvidia,tegra234-pcie";
4829                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>;
4830                         reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K)      */
4831                               <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
4832                               <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
4833                               <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K)       */
4834                               <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
4835                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4836
4837                         #address-cells = <3>;
4838                         #size-cells = <2>;
4839                         device_type = "pci";
4840                         num-lanes = <4>;
4841                         num-viewport = <8>;
4842                         linux,pci-domain = <0>;
4843
4844                         clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>;
4845                         clock-names = "core";
4846
4847                         resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>,
4848                                  <&bpmp TEGRA234_RESET_PEX0_CORE_0>;
4849                         reset-names = "apb", "core";
4850
4851                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
4852                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
4853                         interrupt-names = "intr", "msi";
4854
4855                         #interrupt-cells = <1>;
4856                         interrupt-map-mask = <0 0 0 0>;
4857                         interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4858
4859                         nvidia,bpmp = <&bpmp 0>;
4860
4861                         nvidia,aspm-cmrt-us = <60>;
4862                         nvidia,aspm-pwr-on-t-us = <20>;
4863                         nvidia,aspm-l0s-entrance-latency-us = <3>;
4864
4865                         bus-range = <0x0 0xff>;
4866
4867                         ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
4868                                  <0x02000000 0x0  0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4869                                  <0x01000000 0x0  0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4870
4871                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>,
4872                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>;
4873                         interconnect-names = "dma-mem", "write";
4874                         iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>;
4875                         iommu-map-mask = <0x0>;
4876                         dma-coherent;
4877
4878                         status = "disabled";
4879                 };
4880
4881                 pcie@141a0000 {
4882                         compatible = "nvidia,tegra234-pcie";
4883                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
4884                         reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
4885                               <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
4886                               <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
4887                               <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
4888                               <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
4889                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4890
4891                         #address-cells = <3>;
4892                         #size-cells = <2>;
4893                         device_type = "pci";
4894                         num-lanes = <8>;
4895                         num-viewport = <8>;
4896                         linux,pci-domain = <5>;
4897
4898                         clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
4899                         clock-names = "core";
4900
4901                         resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
4902                                  <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
4903                         reset-names = "apb", "core";
4904
4905                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
4906                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
4907                         interrupt-names = "intr", "msi";
4908
4909                         #interrupt-cells = <1>;
4910                         interrupt-map-mask = <0 0 0 0>;
4911                         interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
4912
4913                         nvidia,bpmp = <&bpmp 5>;
4914
4915                         nvidia,aspm-cmrt-us = <60>;
4916                         nvidia,aspm-pwr-on-t-us = <20>;
4917                         nvidia,aspm-l0s-entrance-latency-us = <3>;
4918
4919                         bus-range = <0x0 0xff>;
4920
4921                         ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */
4922                                  <0x02000000 0x0  0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4923                                  <0x01000000 0x0  0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4924
4925                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
4926                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
4927                         interconnect-names = "dma-mem", "write";
4928                         iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
4929                         iommu-map-mask = <0x0>;
4930                         dma-coherent;
4931
4932                         status = "disabled";
4933                 };
4934
4935                 pcie-ep@141a0000 {
4936                         compatible = "nvidia,tegra234-pcie-ep";
4937                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
4938                         reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
4939                               <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
4940                               <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
4941                               <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G)        */
4942                         reg-names = "appl", "atu_dma", "dbi", "addr_space";
4943
4944                         num-lanes = <8>;
4945
4946                         clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
4947                         clock-names = "core";
4948
4949                         resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
4950                                  <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
4951                         reset-names = "apb", "core";
4952
4953                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
4954                         interrupt-names = "intr";
4955
4956                         nvidia,bpmp = <&bpmp 5>;
4957
4958                         nvidia,enable-ext-refclk;
4959                         nvidia,aspm-cmrt-us = <60>;
4960                         nvidia,aspm-pwr-on-t-us = <20>;
4961                         nvidia,aspm-l0s-entrance-latency-us = <3>;
4962
4963                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
4964                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
4965                         interconnect-names = "dma-mem", "write";
4966                         iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
4967                         iommu-map-mask = <0x0>;
4968                         dma-coherent;
4969
4970                         status = "disabled";
4971                 };
4972
4973                 pcie@141c0000 {
4974                         compatible = "nvidia,tegra234-pcie";
4975                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
4976                         reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K)      */
4977                               <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */
4978                               <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
4979                               <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K)       */
4980                               <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
4981                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4982
4983                         #address-cells = <3>;
4984                         #size-cells = <2>;
4985                         device_type = "pci";
4986                         num-lanes = <4>;
4987                         num-viewport = <8>;
4988                         linux,pci-domain = <6>;
4989
4990                         clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
4991                         clock-names = "core";
4992
4993                         resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
4994                                  <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
4995                         reset-names = "apb", "core";
4996
4997                         interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
4998                                      <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
4999                         interrupt-names = "intr", "msi";
5000
5001                         #interrupt-cells = <1>;
5002                         interrupt-map-mask = <0 0 0 0>;
5003                         interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
5004
5005                         nvidia,bpmp = <&bpmp 6>;
5006
5007                         nvidia,aspm-cmrt-us = <60>;
5008                         nvidia,aspm-pwr-on-t-us = <20>;
5009                         nvidia,aspm-l0s-entrance-latency-us = <3>;
5010
5011                         bus-range = <0x0 0xff>;
5012
5013                         ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
5014                                  <0x02000000 0x0  0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
5015                                  <0x01000000 0x0  0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
5016
5017                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
5018                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
5019                         interconnect-names = "dma-mem", "write";
5020                         iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
5021                         iommu-map-mask = <0x0>;
5022                         dma-coherent;
5023
5024                         status = "disabled";
5025                 };
5026
5027                 pcie-ep@141c0000 {
5028                         compatible = "nvidia,tegra234-pcie-ep";
5029                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
5030                         reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K)      */
5031                               <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
5032                               <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K)           */
5033                               <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G)        */
5034                         reg-names = "appl", "atu_dma", "dbi", "addr_space";
5035
5036                         num-lanes = <4>;
5037
5038                         clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
5039                         clock-names = "core";
5040
5041                         resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
5042                                  <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
5043                         reset-names = "apb", "core";
5044
5045                         interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
5046                         interrupt-names = "intr";
5047
5048                         nvidia,bpmp = <&bpmp 6>;
5049
5050                         nvidia,enable-ext-refclk;
5051                         nvidia,aspm-cmrt-us = <60>;
5052                         nvidia,aspm-pwr-on-t-us = <20>;
5053                         nvidia,aspm-l0s-entrance-latency-us = <3>;
5054
5055                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
5056                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
5057                         interconnect-names = "dma-mem", "write";
5058                         iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
5059                         iommu-map-mask = <0x0>;
5060                         dma-coherent;
5061
5062                         status = "disabled";
5063                 };
5064
5065                 pcie@141e0000 {
5066                         compatible = "nvidia,tegra234-pcie";
5067                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
5068                         reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K)      */
5069                               <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */
5070                               <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
5071                               <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K)       */
5072                               <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
5073                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
5074
5075                         #address-cells = <3>;
5076                         #size-cells = <2>;
5077                         device_type = "pci";
5078                         num-lanes = <8>;
5079                         num-viewport = <8>;
5080                         linux,pci-domain = <7>;
5081
5082                         clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
5083                         clock-names = "core";
5084
5085                         resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
5086                                  <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
5087                         reset-names = "apb", "core";
5088
5089                         interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
5090                                      <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
5091                         interrupt-names = "intr", "msi";
5092
5093                         #interrupt-cells = <1>;
5094                         interrupt-map-mask = <0 0 0 0>;
5095                         interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
5096
5097                         nvidia,bpmp = <&bpmp 7>;
5098
5099                         nvidia,aspm-cmrt-us = <60>;
5100                         nvidia,aspm-pwr-on-t-us = <20>;
5101                         nvidia,aspm-l0s-entrance-latency-us = <3>;
5102
5103                         bus-range = <0x0 0xff>;
5104
5105                         ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */
5106                                  <0x02000000 0x0  0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
5107                                  <0x01000000 0x0  0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
5108
5109                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
5110                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
5111                         interconnect-names = "dma-mem", "write";
5112                         iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
5113                         iommu-map-mask = <0x0>;
5114                         dma-coherent;
5115
5116                         status = "disabled";
5117                 };
5118
5119                 pcie-ep@141e0000 {
5120                         compatible = "nvidia,tegra234-pcie-ep";
5121                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
5122                         reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K)      */
5123                               <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
5124                               <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K)           */
5125                               <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G)        */
5126                         reg-names = "appl", "atu_dma", "dbi", "addr_space";
5127
5128                         num-lanes = <8>;
5129
5130                         clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
5131                         clock-names = "core";
5132
5133                         resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
5134                                  <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
5135                         reset-names = "apb", "core";
5136
5137                         interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
5138                         interrupt-names = "intr";
5139
5140                         nvidia,bpmp = <&bpmp 7>;
5141
5142                         nvidia,enable-ext-refclk;
5143                         nvidia,aspm-cmrt-us = <60>;
5144                         nvidia,aspm-pwr-on-t-us = <20>;
5145                         nvidia,aspm-l0s-entrance-latency-us = <3>;
5146
5147                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
5148                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
5149                         interconnect-names = "dma-mem", "write";
5150                         iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
5151                         iommu-map-mask = <0x0>;
5152                         dma-coherent;
5153
5154                         status = "disabled";
5155                 };
5156         };
5157
5158         sram@40000000 {
5159                 compatible = "nvidia,tegra234-sysram", "mmio-sram";
5160                 reg = <0x0 0x40000000 0x0 0x80000>;
5161
5162                 #address-cells = <1>;
5163                 #size-cells = <1>;
5164                 ranges = <0x0 0x0 0x40000000 0x80000>;
5165
5166                 no-memory-wc;
5167
5168                 cpu_bpmp_tx: sram@70000 {
5169                         reg = <0x70000 0x1000>;
5170                         label = "cpu-bpmp-tx";
5171                         pool;
5172                 };
5173
5174                 cpu_bpmp_rx: sram@71000 {
5175                         reg = <0x71000 0x1000>;
5176                         label = "cpu-bpmp-rx";
5177                         pool;
5178                 };
5179         };
5180
5181         bpmp: bpmp {
5182                 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
5183                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
5184                                     TEGRA_HSP_DB_MASTER_BPMP>;
5185                 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
5186                 #clock-cells = <1>;
5187                 #reset-cells = <1>;
5188                 #power-domain-cells = <1>;
5189                 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>,
5190                                 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>,
5191                                 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>,
5192                                 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>;
5193                 interconnect-names = "read", "write", "dma-mem", "dma-write";
5194                 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>;
5195
5196                 bpmp_i2c: i2c {
5197                         compatible = "nvidia,tegra186-bpmp-i2c";
5198                         nvidia,bpmp-bus-id = <5>;
5199                         #address-cells = <1>;
5200                         #size-cells = <0>;
5201                 };
5202
5203                 bpmp_thermal: thermal {
5204                         compatible = "nvidia,tegra186-bpmp-thermal";
5205                         #thermal-sensor-cells = <1>;
5206                 };
5207         };
5208
5209         cpus {
5210                 #address-cells = <1>;
5211                 #size-cells = <0>;
5212
5213                 cpu0_0: cpu@0 {
5214                         compatible = "arm,cortex-a78";
5215                         device_type = "cpu";
5216                         reg = <0x00000>;
5217
5218                         enable-method = "psci";
5219
5220                         operating-points-v2 = <&cl0_opp_tbl>;
5221                         interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
5222
5223                         i-cache-size = <65536>;
5224                         i-cache-line-size = <64>;
5225                         i-cache-sets = <256>;
5226                         d-cache-size = <65536>;
5227                         d-cache-line-size = <64>;
5228                         d-cache-sets = <256>;
5229                         next-level-cache = <&l2c0_0>;
5230                 };
5231
5232                 cpu0_1: cpu@100 {
5233                         compatible = "arm,cortex-a78";
5234                         device_type = "cpu";
5235                         reg = <0x00100>;
5236
5237                         enable-method = "psci";
5238
5239                         operating-points-v2 = <&cl0_opp_tbl>;
5240                         interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
5241
5242                         i-cache-size = <65536>;
5243                         i-cache-line-size = <64>;
5244                         i-cache-sets = <256>;
5245                         d-cache-size = <65536>;
5246                         d-cache-line-size = <64>;
5247                         d-cache-sets = <256>;
5248                         next-level-cache = <&l2c0_1>;
5249                 };
5250
5251                 cpu0_2: cpu@200 {
5252                         compatible = "arm,cortex-a78";
5253                         device_type = "cpu";
5254                         reg = <0x00200>;
5255
5256                         enable-method = "psci";
5257
5258                         operating-points-v2 = <&cl0_opp_tbl>;
5259                         interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
5260
5261                         i-cache-size = <65536>;
5262                         i-cache-line-size = <64>;
5263                         i-cache-sets = <256>;
5264                         d-cache-size = <65536>;
5265                         d-cache-line-size = <64>;
5266                         d-cache-sets = <256>;
5267                         next-level-cache = <&l2c0_2>;
5268                 };
5269
5270                 cpu0_3: cpu@300 {
5271                         compatible = "arm,cortex-a78";
5272                         device_type = "cpu";
5273                         reg = <0x00300>;
5274
5275                         enable-method = "psci";
5276
5277                         operating-points-v2 = <&cl0_opp_tbl>;
5278                         interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
5279
5280                         i-cache-size = <65536>;
5281                         i-cache-line-size = <64>;
5282                         i-cache-sets = <256>;
5283                         d-cache-size = <65536>;
5284                         d-cache-line-size = <64>;
5285                         d-cache-sets = <256>;
5286                         next-level-cache = <&l2c0_3>;
5287                 };
5288
5289                 cpu1_0: cpu@10000 {
5290                         compatible = "arm,cortex-a78";
5291                         device_type = "cpu";
5292                         reg = <0x10000>;
5293
5294                         enable-method = "psci";
5295
5296                         operating-points-v2 = <&cl1_opp_tbl>;
5297                         interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
5298
5299                         i-cache-size = <65536>;
5300                         i-cache-line-size = <64>;
5301                         i-cache-sets = <256>;
5302                         d-cache-size = <65536>;
5303                         d-cache-line-size = <64>;
5304                         d-cache-sets = <256>;
5305                         next-level-cache = <&l2c1_0>;
5306                 };
5307
5308                 cpu1_1: cpu@10100 {
5309                         compatible = "arm,cortex-a78";
5310                         device_type = "cpu";
5311                         reg = <0x10100>;
5312
5313                         enable-method = "psci";
5314
5315                         operating-points-v2 = <&cl1_opp_tbl>;
5316                         interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
5317
5318                         i-cache-size = <65536>;
5319                         i-cache-line-size = <64>;
5320                         i-cache-sets = <256>;
5321                         d-cache-size = <65536>;
5322                         d-cache-line-size = <64>;
5323                         d-cache-sets = <256>;
5324                         next-level-cache = <&l2c1_1>;
5325                 };
5326
5327                 cpu1_2: cpu@10200 {
5328                         compatible = "arm,cortex-a78";
5329                         device_type = "cpu";
5330                         reg = <0x10200>;
5331
5332                         enable-method = "psci";
5333
5334                         operating-points-v2 = <&cl1_opp_tbl>;
5335                         interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
5336
5337                         i-cache-size = <65536>;
5338                         i-cache-line-size = <64>;
5339                         i-cache-sets = <256>;
5340                         d-cache-size = <65536>;
5341                         d-cache-line-size = <64>;
5342                         d-cache-sets = <256>;
5343                         next-level-cache = <&l2c1_2>;
5344                 };
5345
5346                 cpu1_3: cpu@10300 {
5347                         compatible = "arm,cortex-a78";
5348                         device_type = "cpu";
5349                         reg = <0x10300>;
5350
5351                         enable-method = "psci";
5352
5353                         operating-points-v2 = <&cl1_opp_tbl>;
5354                         interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
5355
5356                         i-cache-size = <65536>;
5357                         i-cache-line-size = <64>;
5358                         i-cache-sets = <256>;
5359                         d-cache-size = <65536>;
5360                         d-cache-line-size = <64>;
5361                         d-cache-sets = <256>;
5362                         next-level-cache = <&l2c1_3>;
5363                 };
5364
5365                 cpu2_0: cpu@20000 {
5366                         compatible = "arm,cortex-a78";
5367                         device_type = "cpu";
5368                         reg = <0x20000>;
5369
5370                         enable-method = "psci";
5371
5372                         operating-points-v2 = <&cl2_opp_tbl>;
5373                         interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
5374
5375                         i-cache-size = <65536>;
5376                         i-cache-line-size = <64>;
5377                         i-cache-sets = <256>;
5378                         d-cache-size = <65536>;
5379                         d-cache-line-size = <64>;
5380                         d-cache-sets = <256>;
5381                         next-level-cache = <&l2c2_0>;
5382                 };
5383
5384                 cpu2_1: cpu@20100 {
5385                         compatible = "arm,cortex-a78";
5386                         device_type = "cpu";
5387                         reg = <0x20100>;
5388
5389                         enable-method = "psci";
5390
5391                         operating-points-v2 = <&cl2_opp_tbl>;
5392                         interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
5393
5394                         i-cache-size = <65536>;
5395                         i-cache-line-size = <64>;
5396                         i-cache-sets = <256>;
5397                         d-cache-size = <65536>;
5398                         d-cache-line-size = <64>;
5399                         d-cache-sets = <256>;
5400                         next-level-cache = <&l2c2_1>;
5401                 };
5402
5403                 cpu2_2: cpu@20200 {
5404                         compatible = "arm,cortex-a78";
5405                         device_type = "cpu";
5406                         reg = <0x20200>;
5407
5408                         enable-method = "psci";
5409
5410                         operating-points-v2 = <&cl2_opp_tbl>;
5411                         interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
5412
5413                         i-cache-size = <65536>;
5414                         i-cache-line-size = <64>;
5415                         i-cache-sets = <256>;
5416                         d-cache-size = <65536>;
5417                         d-cache-line-size = <64>;
5418                         d-cache-sets = <256>;
5419                         next-level-cache = <&l2c2_2>;
5420                 };
5421
5422                 cpu2_3: cpu@20300 {
5423                         compatible = "arm,cortex-a78";
5424                         device_type = "cpu";
5425                         reg = <0x20300>;
5426
5427                         enable-method = "psci";
5428
5429                         operating-points-v2 = <&cl2_opp_tbl>;
5430                         interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
5431
5432                         i-cache-size = <65536>;
5433                         i-cache-line-size = <64>;
5434                         i-cache-sets = <256>;
5435                         d-cache-size = <65536>;
5436                         d-cache-line-size = <64>;
5437                         d-cache-sets = <256>;
5438                         next-level-cache = <&l2c2_3>;
5439                 };
5440
5441                 cpu-map {
5442                         cluster0 {
5443                                 core0 {
5444                                         cpu = <&cpu0_0>;
5445                                 };
5446
5447                                 core1 {
5448                                         cpu = <&cpu0_1>;
5449                                 };
5450
5451                                 core2 {
5452                                         cpu = <&cpu0_2>;
5453                                 };
5454
5455                                 core3 {
5456                                         cpu = <&cpu0_3>;
5457                                 };
5458                         };
5459
5460                         cluster1 {
5461                                 core0 {
5462                                         cpu = <&cpu1_0>;
5463                                 };
5464
5465                                 core1 {
5466                                         cpu = <&cpu1_1>;
5467                                 };
5468
5469                                 core2 {
5470                                         cpu = <&cpu1_2>;
5471                                 };
5472
5473                                 core3 {
5474                                         cpu = <&cpu1_3>;
5475                                 };
5476                         };
5477
5478                         cluster2 {
5479                                 core0 {
5480                                         cpu = <&cpu2_0>;
5481                                 };
5482
5483                                 core1 {
5484                                         cpu = <&cpu2_1>;
5485                                 };
5486
5487                                 core2 {
5488                                         cpu = <&cpu2_2>;
5489                                 };
5490
5491                                 core3 {
5492                                         cpu = <&cpu2_3>;
5493                                 };
5494                         };
5495                 };
5496
5497                 l2c0_0: l2-cache00 {
5498                         compatible = "cache";
5499                         cache-size = <262144>;
5500                         cache-line-size = <64>;
5501                         cache-sets = <512>;
5502                         cache-unified;
5503                         cache-level = <2>;
5504                         next-level-cache = <&l3c0>;
5505                 };
5506
5507                 l2c0_1: l2-cache01 {
5508                         compatible = "cache";
5509                         cache-size = <262144>;
5510                         cache-line-size = <64>;
5511                         cache-sets = <512>;
5512                         cache-unified;
5513                         cache-level = <2>;
5514                         next-level-cache = <&l3c0>;
5515                 };
5516
5517                 l2c0_2: l2-cache02 {
5518                         compatible = "cache";
5519                         cache-size = <262144>;
5520                         cache-line-size = <64>;
5521                         cache-sets = <512>;
5522                         cache-unified;
5523                         cache-level = <2>;
5524                         next-level-cache = <&l3c0>;
5525                 };
5526
5527                 l2c0_3: l2-cache03 {
5528                         compatible = "cache";
5529                         cache-size = <262144>;
5530                         cache-line-size = <64>;
5531                         cache-sets = <512>;
5532                         cache-unified;
5533                         cache-level = <2>;
5534                         next-level-cache = <&l3c0>;
5535                 };
5536
5537                 l2c1_0: l2-cache10 {
5538                         compatible = "cache";
5539                         cache-size = <262144>;
5540                         cache-line-size = <64>;
5541                         cache-sets = <512>;
5542                         cache-unified;
5543                         cache-level = <2>;
5544                         next-level-cache = <&l3c1>;
5545                 };
5546
5547                 l2c1_1: l2-cache11 {
5548                         compatible = "cache";
5549                         cache-size = <262144>;
5550                         cache-line-size = <64>;
5551                         cache-sets = <512>;
5552                         cache-unified;
5553                         cache-level = <2>;
5554                         next-level-cache = <&l3c1>;
5555                 };
5556
5557                 l2c1_2: l2-cache12 {
5558                         compatible = "cache";
5559                         cache-size = <262144>;
5560                         cache-line-size = <64>;
5561                         cache-sets = <512>;
5562                         cache-unified;
5563                         cache-level = <2>;
5564                         next-level-cache = <&l3c1>;
5565                 };
5566
5567                 l2c1_3: l2-cache13 {
5568                         compatible = "cache";
5569                         cache-size = <262144>;
5570                         cache-line-size = <64>;
5571                         cache-sets = <512>;
5572                         cache-unified;
5573                         cache-level = <2>;
5574                         next-level-cache = <&l3c1>;
5575                 };
5576
5577                 l2c2_0: l2-cache20 {
5578                         compatible = "cache";
5579                         cache-size = <262144>;
5580                         cache-line-size = <64>;
5581                         cache-sets = <512>;
5582                         cache-unified;
5583                         cache-level = <2>;
5584                         next-level-cache = <&l3c2>;
5585                 };
5586
5587                 l2c2_1: l2-cache21 {
5588                         compatible = "cache";
5589                         cache-size = <262144>;
5590                         cache-line-size = <64>;
5591                         cache-sets = <512>;
5592                         cache-unified;
5593                         cache-level = <2>;
5594                         next-level-cache = <&l3c2>;
5595                 };
5596
5597                 l2c2_2: l2-cache22 {
5598                         compatible = "cache";
5599                         cache-size = <262144>;
5600                         cache-line-size = <64>;
5601                         cache-sets = <512>;
5602                         cache-unified;
5603                         cache-level = <2>;
5604                         next-level-cache = <&l3c2>;
5605                 };
5606
5607                 l2c2_3: l2-cache23 {
5608                         compatible = "cache";
5609                         cache-size = <262144>;
5610                         cache-line-size = <64>;
5611                         cache-sets = <512>;
5612                         cache-unified;
5613                         cache-level = <2>;
5614                         next-level-cache = <&l3c2>;
5615                 };
5616
5617                 l3c0: l3-cache0 {
5618                         compatible = "cache";
5619                         cache-unified;
5620                         cache-size = <2097152>;
5621                         cache-line-size = <64>;
5622                         cache-sets = <2048>;
5623                         cache-level = <3>;
5624                 };
5625
5626                 l3c1: l3-cache1 {
5627                         compatible = "cache";
5628                         cache-unified;
5629                         cache-size = <2097152>;
5630                         cache-line-size = <64>;
5631                         cache-sets = <2048>;
5632                         cache-level = <3>;
5633                 };
5634
5635                 l3c2: l3-cache2 {
5636                         compatible = "cache";
5637                         cache-unified;
5638                         cache-size = <2097152>;
5639                         cache-line-size = <64>;
5640                         cache-sets = <2048>;
5641                         cache-level = <3>;
5642                 };
5643         };
5644
5645         dsu-pmu0 {
5646                 compatible = "arm,dsu-pmu";
5647                 interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
5648                 cpus = <&cpu0_0>, <&cpu0_1>, <&cpu0_2>, <&cpu0_3>;
5649         };
5650
5651         dsu-pmu1 {
5652                 compatible = "arm,dsu-pmu";
5653                 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
5654                 cpus = <&cpu1_0>, <&cpu1_1>, <&cpu1_2>, <&cpu1_3>;
5655         };
5656
5657         dsu-pmu2 {
5658                 compatible = "arm,dsu-pmu";
5659                 interrupts = <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
5660                 cpus = <&cpu2_0>, <&cpu2_1>, <&cpu2_2>, <&cpu2_3>;
5661         };
5662
5663         pmu {
5664                 compatible = "arm,cortex-a78-pmu";
5665                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
5666                 status = "okay";
5667         };
5668
5669         psci {
5670                 compatible = "arm,psci-1.0";
5671                 status = "okay";
5672                 method = "smc";
5673         };
5674
5675         tcu: serial {
5676                 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu";
5677                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
5678                          <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
5679                 mbox-names = "rx", "tx";
5680                 status = "disabled";
5681         };
5682
5683         sound {
5684                 status = "disabled";
5685
5686                 clocks = <&bpmp TEGRA234_CLK_PLLA>,
5687                          <&bpmp TEGRA234_CLK_PLLA_OUT0>;
5688                 clock-names = "pll_a", "plla_out0";
5689                 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>,
5690                                   <&bpmp TEGRA234_CLK_PLLA_OUT0>,
5691                                   <&bpmp TEGRA234_CLK_AUD_MCLK>;
5692                 assigned-clock-parents = <0>,
5693                                          <&bpmp TEGRA234_CLK_PLLA>,
5694                                          <&bpmp TEGRA234_CLK_PLLA_OUT0>;
5695         };
5696
5697         thermal-zones {
5698                 cpu-thermal {
5699                         thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CPU>;
5700                         status = "disabled";
5701                 };
5702
5703                 gpu-thermal {
5704                         thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_GPU>;
5705                         status = "disabled";
5706                 };
5707
5708                 cv0-thermal {
5709                         thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV0>;
5710                         status = "disabled";
5711                 };
5712
5713                 cv1-thermal {
5714                         thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV1>;
5715                         status = "disabled";
5716                 };
5717
5718                 cv2-thermal {
5719                         thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV2>;
5720                         status = "disabled";
5721                 };
5722
5723                 soc0-thermal {
5724                         thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC0>;
5725                         status = "disabled";
5726                 };
5727
5728                 soc1-thermal {
5729                         thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC1>;
5730                         status = "disabled";
5731                 };
5732
5733                 soc2-thermal {
5734                         thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC2>;
5735                         status = "disabled";
5736                 };
5737
5738                 tj-thermal {
5739                         thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX>;
5740                         status = "disabled";
5741                 };
5742         };
5743
5744         timer {
5745                 compatible = "arm,armv8-timer";
5746                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
5747                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
5748                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
5749                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
5750                 interrupt-parent = <&gic>;
5751                 always-on;
5752         };
5753
5754         cl0_opp_tbl: opp-table-cluster0 {
5755                 compatible = "operating-points-v2";
5756                 opp-shared;
5757
5758                 cl0_ch1_opp1: opp-115200000 {
5759                           opp-hz = /bits/ 64 <115200000>;
5760                           opp-peak-kBps = <816000>;
5761                 };
5762
5763                 cl0_ch1_opp2: opp-192000000 {
5764                         opp-hz = /bits/ 64 <192000000>;
5765                         opp-peak-kBps = <816000>;
5766                 };
5767
5768                 cl0_ch1_opp3: opp-268800000 {
5769                         opp-hz = /bits/ 64 <268800000>;
5770                         opp-peak-kBps = <816000>;
5771                 };
5772
5773                 cl0_ch1_opp4: opp-345600000 {
5774                         opp-hz = /bits/ 64 <345600000>;
5775                         opp-peak-kBps = <816000>;
5776                 };
5777
5778                 cl0_ch1_opp5: opp-422400000 {
5779                         opp-hz = /bits/ 64 <422400000>;
5780                         opp-peak-kBps = <816000>;
5781                 };
5782
5783                 cl0_ch1_opp6: opp-499200000 {
5784                         opp-hz = /bits/ 64 <499200000>;
5785                         opp-peak-kBps = <816000>;
5786                 };
5787
5788                 cl0_ch1_opp7: opp-576000000 {
5789                         opp-hz = /bits/ 64 <576000000>;
5790                         opp-peak-kBps = <816000>;
5791                 };
5792
5793                 cl0_ch1_opp8: opp-652800000 {
5794                         opp-hz = /bits/ 64 <652800000>;
5795                         opp-peak-kBps = <816000>;
5796                 };
5797
5798                 cl0_ch1_opp9: opp-729600000 {
5799                         opp-hz = /bits/ 64 <729600000>;
5800                         opp-peak-kBps = <816000>;
5801                 };
5802
5803                 cl0_ch1_opp10: opp-806400000 {
5804                         opp-hz = /bits/ 64 <806400000>;
5805                         opp-peak-kBps = <816000>;
5806                 };
5807
5808                 cl0_ch1_opp11: opp-883200000 {
5809                         opp-hz = /bits/ 64 <883200000>;
5810                         opp-peak-kBps = <816000>;
5811                 };
5812
5813                 cl0_ch1_opp12: opp-960000000 {
5814                         opp-hz = /bits/ 64 <960000000>;
5815                         opp-peak-kBps = <816000>;
5816                 };
5817
5818                 cl0_ch1_opp13: opp-1036800000 {
5819                         opp-hz = /bits/ 64 <1036800000>;
5820                         opp-peak-kBps = <816000>;
5821                 };
5822
5823                 cl0_ch1_opp14: opp-1113600000 {
5824                         opp-hz = /bits/ 64 <1113600000>;
5825                         opp-peak-kBps = <1632000>;
5826                 };
5827
5828                 cl0_ch1_opp15: opp-1190400000 {
5829                         opp-hz = /bits/ 64 <1190400000>;
5830                         opp-peak-kBps = <1632000>;
5831                 };
5832
5833                 cl0_ch1_opp16: opp-1267200000 {
5834                         opp-hz = /bits/ 64 <1267200000>;
5835                         opp-peak-kBps = <1632000>;
5836                 };
5837
5838                 cl0_ch1_opp17: opp-1344000000 {
5839                         opp-hz = /bits/ 64 <1344000000>;
5840                         opp-peak-kBps = <1632000>;
5841                 };
5842
5843                 cl0_ch1_opp18: opp-1420800000 {
5844                         opp-hz = /bits/ 64 <1420800000>;
5845                         opp-peak-kBps = <1632000>;
5846                 };
5847
5848                 cl0_ch1_opp19: opp-1497600000 {
5849                         opp-hz = /bits/ 64 <1497600000>;
5850                         opp-peak-kBps = <3200000>;
5851                 };
5852
5853                 cl0_ch1_opp20: opp-1574400000 {
5854                         opp-hz = /bits/ 64 <1574400000>;
5855                         opp-peak-kBps = <3200000>;
5856                 };
5857
5858                 cl0_ch1_opp21: opp-1651200000 {
5859                         opp-hz = /bits/ 64 <1651200000>;
5860                         opp-peak-kBps = <3200000>;
5861                 };
5862
5863                 cl0_ch1_opp22: opp-1728000000 {
5864                         opp-hz = /bits/ 64 <1728000000>;
5865                         opp-peak-kBps = <3200000>;
5866                 };
5867
5868                 cl0_ch1_opp23: opp-1804800000 {
5869                         opp-hz = /bits/ 64 <1804800000>;
5870                         opp-peak-kBps = <3200000>;
5871                 };
5872
5873                 cl0_ch1_opp24: opp-1881600000 {
5874                         opp-hz = /bits/ 64 <1881600000>;
5875                         opp-peak-kBps = <3200000>;
5876                 };
5877
5878                 cl0_ch1_opp25: opp-1958400000 {
5879                         opp-hz = /bits/ 64 <1958400000>;
5880                         opp-peak-kBps = <3200000>;
5881                 };
5882
5883                 cl0_ch1_opp26: opp-2035200000 {
5884                         opp-hz = /bits/ 64 <2035200000>;
5885                         opp-peak-kBps = <3200000>;
5886                 };
5887
5888                 cl0_ch1_opp27: opp-2112000000 {
5889                         opp-hz = /bits/ 64 <2112000000>;
5890                         opp-peak-kBps = <6400000>;
5891                 };
5892
5893                 cl0_ch1_opp28: opp-2188800000 {
5894                         opp-hz = /bits/ 64 <2188800000>;
5895                         opp-peak-kBps = <6400000>;
5896                 };
5897
5898                 cl0_ch1_opp29: opp-2201600000 {
5899                         opp-hz = /bits/ 64 <2201600000>;
5900                         opp-peak-kBps = <6400000>;
5901                 };
5902         };
5903
5904         cl1_opp_tbl: opp-table-cluster1 {
5905                 compatible = "operating-points-v2";
5906                 opp-shared;
5907
5908                 cl1_ch1_opp1: opp-115200000 {
5909                           opp-hz = /bits/ 64 <115200000>;
5910                           opp-peak-kBps = <816000>;
5911                 };
5912
5913                 cl1_ch1_opp2: opp-192000000 {
5914                         opp-hz = /bits/ 64 <192000000>;
5915                         opp-peak-kBps = <816000>;
5916                 };
5917
5918                 cl1_ch1_opp3: opp-268800000 {
5919                         opp-hz = /bits/ 64 <268800000>;
5920                         opp-peak-kBps = <816000>;
5921                 };
5922
5923                 cl1_ch1_opp4: opp-345600000 {
5924                         opp-hz = /bits/ 64 <345600000>;
5925                         opp-peak-kBps = <816000>;
5926                 };
5927
5928                 cl1_ch1_opp5: opp-422400000 {
5929                         opp-hz = /bits/ 64 <422400000>;
5930                         opp-peak-kBps = <816000>;
5931                 };
5932
5933                 cl1_ch1_opp6: opp-499200000 {
5934                         opp-hz = /bits/ 64 <499200000>;
5935                         opp-peak-kBps = <816000>;
5936                 };
5937
5938                 cl1_ch1_opp7: opp-576000000 {
5939                         opp-hz = /bits/ 64 <576000000>;
5940                         opp-peak-kBps = <816000>;
5941                 };
5942
5943                 cl1_ch1_opp8: opp-652800000 {
5944                         opp-hz = /bits/ 64 <652800000>;
5945                         opp-peak-kBps = <816000>;
5946                 };
5947
5948                 cl1_ch1_opp9: opp-729600000 {
5949                         opp-hz = /bits/ 64 <729600000>;
5950                         opp-peak-kBps = <816000>;
5951                 };
5952
5953                 cl1_ch1_opp10: opp-806400000 {
5954                         opp-hz = /bits/ 64 <806400000>;
5955                         opp-peak-kBps = <816000>;
5956                 };
5957
5958                 cl1_ch1_opp11: opp-883200000 {
5959                         opp-hz = /bits/ 64 <883200000>;
5960                         opp-peak-kBps = <816000>;
5961                 };
5962
5963                 cl1_ch1_opp12: opp-960000000 {
5964                         opp-hz = /bits/ 64 <960000000>;
5965                         opp-peak-kBps = <816000>;
5966                 };
5967
5968                 cl1_ch1_opp13: opp-1036800000 {
5969                         opp-hz = /bits/ 64 <1036800000>;
5970                         opp-peak-kBps = <816000>;
5971                 };
5972
5973                 cl1_ch1_opp14: opp-1113600000 {
5974                         opp-hz = /bits/ 64 <1113600000>;
5975                         opp-peak-kBps = <1632000>;
5976                 };
5977
5978                 cl1_ch1_opp15: opp-1190400000 {
5979                         opp-hz = /bits/ 64 <1190400000>;
5980                         opp-peak-kBps = <1632000>;
5981                 };
5982
5983                 cl1_ch1_opp16: opp-1267200000 {
5984                         opp-hz = /bits/ 64 <1267200000>;
5985                         opp-peak-kBps = <1632000>;
5986                 };
5987
5988                 cl1_ch1_opp17: opp-1344000000 {
5989                         opp-hz = /bits/ 64 <1344000000>;
5990                         opp-peak-kBps = <1632000>;
5991                 };
5992
5993                 cl1_ch1_opp18: opp-1420800000 {
5994                         opp-hz = /bits/ 64 <1420800000>;
5995                         opp-peak-kBps = <1632000>;
5996                 };
5997
5998                 cl1_ch1_opp19: opp-1497600000 {
5999                         opp-hz = /bits/ 64 <1497600000>;
6000                         opp-peak-kBps = <3200000>;
6001                 };
6002
6003                 cl1_ch1_opp20: opp-1574400000 {
6004                         opp-hz = /bits/ 64 <1574400000>;
6005                         opp-peak-kBps = <3200000>;
6006                 };
6007
6008                 cl1_ch1_opp21: opp-1651200000 {
6009                         opp-hz = /bits/ 64 <1651200000>;
6010                         opp-peak-kBps = <3200000>;
6011                 };
6012
6013                 cl1_ch1_opp22: opp-1728000000 {
6014                         opp-hz = /bits/ 64 <1728000000>;
6015                         opp-peak-kBps = <3200000>;
6016                 };
6017
6018                 cl1_ch1_opp23: opp-1804800000 {
6019                         opp-hz = /bits/ 64 <1804800000>;
6020                         opp-peak-kBps = <3200000>;
6021                 };
6022
6023                 cl1_ch1_opp24: opp-1881600000 {
6024                         opp-hz = /bits/ 64 <1881600000>;
6025                         opp-peak-kBps = <3200000>;
6026                 };
6027
6028                 cl1_ch1_opp25: opp-1958400000 {
6029                         opp-hz = /bits/ 64 <1958400000>;
6030                         opp-peak-kBps = <3200000>;
6031                 };
6032
6033                 cl1_ch1_opp26: opp-2035200000 {
6034                         opp-hz = /bits/ 64 <2035200000>;
6035                         opp-peak-kBps = <3200000>;
6036                 };
6037
6038                 cl1_ch1_opp27: opp-2112000000 {
6039                         opp-hz = /bits/ 64 <2112000000>;
6040                         opp-peak-kBps = <6400000>;
6041                 };
6042
6043                 cl1_ch1_opp28: opp-2188800000 {
6044                         opp-hz = /bits/ 64 <2188800000>;
6045                         opp-peak-kBps = <6400000>;
6046                 };
6047
6048                 cl1_ch1_opp29: opp-2201600000 {
6049                         opp-hz = /bits/ 64 <2201600000>;
6050                         opp-peak-kBps = <6400000>;
6051                 };
6052         };
6053
6054         cl2_opp_tbl: opp-table-cluster2 {
6055                 compatible = "operating-points-v2";
6056                 opp-shared;
6057
6058                 cl2_ch1_opp1: opp-115200000 {
6059                           opp-hz = /bits/ 64 <115200000>;
6060                           opp-peak-kBps = <816000>;
6061                 };
6062
6063                 cl2_ch1_opp2: opp-192000000 {
6064                         opp-hz = /bits/ 64 <192000000>;
6065                         opp-peak-kBps = <816000>;
6066                 };
6067
6068                 cl2_ch1_opp3: opp-268800000 {
6069                         opp-hz = /bits/ 64 <268800000>;
6070                         opp-peak-kBps = <816000>;
6071                 };
6072
6073                 cl2_ch1_opp4: opp-345600000 {
6074                         opp-hz = /bits/ 64 <345600000>;
6075                         opp-peak-kBps = <816000>;
6076                 };
6077
6078                 cl2_ch1_opp5: opp-422400000 {
6079                         opp-hz = /bits/ 64 <422400000>;
6080                         opp-peak-kBps = <816000>;
6081                 };
6082
6083                 cl2_ch1_opp6: opp-499200000 {
6084                         opp-hz = /bits/ 64 <499200000>;
6085                         opp-peak-kBps = <816000>;
6086                 };
6087
6088                 cl2_ch1_opp7: opp-576000000 {
6089                         opp-hz = /bits/ 64 <576000000>;
6090                         opp-peak-kBps = <816000>;
6091                 };
6092
6093                 cl2_ch1_opp8: opp-652800000 {
6094                         opp-hz = /bits/ 64 <652800000>;
6095                         opp-peak-kBps = <816000>;
6096                 };
6097
6098                 cl2_ch1_opp9: opp-729600000 {
6099                         opp-hz = /bits/ 64 <729600000>;
6100                         opp-peak-kBps = <816000>;
6101                 };
6102
6103                 cl2_ch1_opp10: opp-806400000 {
6104                         opp-hz = /bits/ 64 <806400000>;
6105                         opp-peak-kBps = <816000>;
6106                 };
6107
6108                 cl2_ch1_opp11: opp-883200000 {
6109                         opp-hz = /bits/ 64 <883200000>;
6110                         opp-peak-kBps = <816000>;
6111                 };
6112
6113                 cl2_ch1_opp12: opp-960000000 {
6114                         opp-hz = /bits/ 64 <960000000>;
6115                         opp-peak-kBps = <816000>;
6116                 };
6117
6118                 cl2_ch1_opp13: opp-1036800000 {
6119                         opp-hz = /bits/ 64 <1036800000>;
6120                         opp-peak-kBps = <816000>;
6121                 };
6122
6123                 cl2_ch1_opp14: opp-1113600000 {
6124                         opp-hz = /bits/ 64 <1113600000>;
6125                         opp-peak-kBps = <1632000>;
6126                 };
6127
6128                 cl2_ch1_opp15: opp-1190400000 {
6129                         opp-hz = /bits/ 64 <1190400000>;
6130                         opp-peak-kBps = <1632000>;
6131                 };
6132
6133                 cl2_ch1_opp16: opp-1267200000 {
6134                         opp-hz = /bits/ 64 <1267200000>;
6135                         opp-peak-kBps = <1632000>;
6136                 };
6137
6138                 cl2_ch1_opp17: opp-1344000000 {
6139                         opp-hz = /bits/ 64 <1344000000>;
6140                         opp-peak-kBps = <1632000>;
6141                 };
6142
6143                 cl2_ch1_opp18: opp-1420800000 {
6144                         opp-hz = /bits/ 64 <1420800000>;
6145                         opp-peak-kBps = <1632000>;
6146                 };
6147
6148                 cl2_ch1_opp19: opp-1497600000 {
6149                         opp-hz = /bits/ 64 <1497600000>;
6150                         opp-peak-kBps = <3200000>;
6151                 };
6152
6153                 cl2_ch1_opp20: opp-1574400000 {
6154                         opp-hz = /bits/ 64 <1574400000>;
6155                         opp-peak-kBps = <3200000>;
6156                 };
6157
6158                 cl2_ch1_opp21: opp-1651200000 {
6159                         opp-hz = /bits/ 64 <1651200000>;
6160                         opp-peak-kBps = <3200000>;
6161                 };
6162
6163                 cl2_ch1_opp22: opp-1728000000 {
6164                         opp-hz = /bits/ 64 <1728000000>;
6165                         opp-peak-kBps = <3200000>;
6166                 };
6167
6168                 cl2_ch1_opp23: opp-1804800000 {
6169                         opp-hz = /bits/ 64 <1804800000>;
6170                         opp-peak-kBps = <3200000>;
6171                 };
6172
6173                 cl2_ch1_opp24: opp-1881600000 {
6174                         opp-hz = /bits/ 64 <1881600000>;
6175                         opp-peak-kBps = <3200000>;
6176                 };
6177
6178                 cl2_ch1_opp25: opp-1958400000 {
6179                         opp-hz = /bits/ 64 <1958400000>;
6180                         opp-peak-kBps = <3200000>;
6181                 };
6182
6183                 cl2_ch1_opp26: opp-2035200000 {
6184                         opp-hz = /bits/ 64 <2035200000>;
6185                         opp-peak-kBps = <3200000>;
6186                 };
6187
6188                 cl2_ch1_opp27: opp-2112000000 {
6189                         opp-hz = /bits/ 64 <2112000000>;
6190                         opp-peak-kBps = <6400000>;
6191                 };
6192
6193                 cl2_ch1_opp28: opp-2188800000 {
6194                         opp-hz = /bits/ 64 <2188800000>;
6195                         opp-peak-kBps = <6400000>;
6196                 };
6197
6198                 cl2_ch1_opp29: opp-2201600000 {
6199                         opp-hz = /bits/ 64 <2201600000>;
6200                         opp-peak-kBps = <6400000>;
6201                 };
6202         };
6203 };