arch/arm64/boot/dts/qcom/ipq8074.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
   8
   9 / {
  10         #address-cells = <2>;
  11         #size-cells = <2>;
  12
  13         model = "Qualcomm Technologies, Inc. IPQ8074";
  14         compatible = "qcom,ipq8074";
  15         interrupt-parent = <&intc>;
  16
  17         clocks {
  18                 sleep_clk: sleep_clk {
  19                         compatible = "fixed-clock";
  20                         clock-frequency = <32768>;
  21                         #clock-cells = <0>;
  22                 };
  23
  24                 xo: xo {
  25                         compatible = "fixed-clock";
  26                         clock-frequency = <19200000>;
  27                         #clock-cells = <0>;
  28                 };
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 CPU0: cpu@0 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a53";
  38                         reg = <0x0>;
  39                         next-level-cache = <&L2_0>;
  40                         enable-method = "psci";
  41                 };
  42
  43                 CPU1: cpu@1 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a53";
  46                         enable-method = "psci";
  47                         reg = <0x1>;
  48                         next-level-cache = <&L2_0>;
  49                 };
  50
  51                 CPU2: cpu@2 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53";
  54                         enable-method = "psci";
  55                         reg = <0x2>;
  56                         next-level-cache = <&L2_0>;
  57                 };
  58
  59                 CPU3: cpu@3 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a53";
  62                         enable-method = "psci";
  63                         reg = <0x3>;
  64                         next-level-cache = <&L2_0>;
  65                 };
  66
  67                 L2_0: l2-cache {
  68                         compatible = "cache";
  69                         cache-level = <2>;
  70                         cache-unified;
  71                 };
  72         };
  73
  74         pmu {
  75                 compatible = "arm,cortex-a53-pmu";
  76                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  77         };
  78
  79         psci {
  80                 compatible = "arm,psci-1.0";
  81                 method = "smc";
  82         };
  83
  84         reserved-memory {
  85                 #address-cells = <2>;
  86                 #size-cells = <2>;
  87                 ranges;
  88
  89                 bootloader@4a600000 {
  90                         reg = <0x0 0x4a600000 0x0 0x400000>;
  91                         no-map;
  92                 };
  93
  94                 sbl@4aa00000 {
  95                         reg = <0x0 0x4aa00000 0x0 0x100000>;
  96                         no-map;
  97                 };
  98
  99                 smem@4ab00000 {
 100                         compatible = "qcom,smem";
 101                         reg = <0x0 0x4ab00000 0x0 0x100000>;
 102                         no-map;
 103
 104                         hwlocks = <&tcsr_mutex 3>;
 105                 };
 106
 107                 memory@4ac00000 {
 108                         reg = <0x0 0x4ac00000 0x0 0x400000>;
 109                         no-map;
 110                 };
 111         };
 112
 113         firmware {
 114                 scm {
 115                         compatible = "qcom,scm-ipq8074", "qcom,scm";
 116                         qcom,dload-mode = <&tcsr 0x6100>;
 117                 };
 118         };
 119
 120         soc: soc@0 {
 121                 #address-cells = <1>;
 122                 #size-cells = <1>;
 123                 ranges = <0 0 0 0xffffffff>;
 124                 compatible = "simple-bus";
 125
 126                 ssphy_1: phy@58000 {
 127                         compatible = "qcom,ipq8074-qmp-usb3-phy";
 128                         reg = <0x00058000 0x1000>;
 129
 130                         clocks = <&gcc GCC_USB1_AUX_CLK>,
 131                                  <&xo>,
 132                                  <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
 133                                  <&gcc GCC_USB1_PIPE_CLK>;
 134                         clock-names = "aux",
 135                                       "ref",
 136                                       "cfg_ahb",
 137                                       "pipe";
 138                         clock-output-names = "usb3phy_1_cc_pipe_clk";
 139                         #clock-cells = <0>;
 140                         #phy-cells = <0>;
 141
 142                         resets = <&gcc GCC_USB1_PHY_BCR>,
 143                                  <&gcc GCC_USB3PHY_1_PHY_BCR>;
 144                         reset-names = "phy",
 145                                       "phy_phy";
 146
 147                         status = "disabled";
 148                 };
 149
 150                 qusb_phy_1: phy@59000 {
 151                         compatible = "qcom,ipq8074-qusb2-phy";
 152                         reg = <0x00059000 0x180>;
 153                         #phy-cells = <0>;
 154
 155                         clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
 156                                  <&xo>;
 157                         clock-names = "cfg_ahb", "ref";
 158
 159                         resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
 160                         status = "disabled";
 161                 };
 162
 163                 ssphy_0: phy@78000 {
 164                         compatible = "qcom,ipq8074-qmp-usb3-phy";
 165                         reg = <0x00078000 0x1000>;
 166
 167                         clocks = <&gcc GCC_USB0_AUX_CLK>,
 168                                  <&xo>,
 169                                  <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
 170                                  <&gcc GCC_USB0_PIPE_CLK>;
 171                         clock-names = "aux",
 172                                       "ref",
 173                                       "cfg_ahb",
 174                                       "pipe";
 175                         clock-output-names = "usb3phy_0_cc_pipe_clk";
 176                         #clock-cells = <0>;
 177                         #phy-cells = <0>;
 178
 179                         resets = <&gcc GCC_USB0_PHY_BCR>,
 180                                  <&gcc GCC_USB3PHY_0_PHY_BCR>;
 181                         reset-names = "phy",
 182                                       "phy_phy";
 183
 184                         status = "disabled";
 185                 };
 186
 187                 qusb_phy_0: phy@79000 {
 188                         compatible = "qcom,ipq8074-qusb2-phy";
 189                         reg = <0x00079000 0x180>;
 190                         #phy-cells = <0>;
 191
 192                         clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
 193                                  <&xo>;
 194                         clock-names = "cfg_ahb", "ref";
 195
 196                         resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
 197                         status = "disabled";
 198                 };
 199
 200                 pcie_qmp0: phy@84000 {
 201                         compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
 202                         reg = <0x00084000 0x1000>;
 203
 204                         clocks = <&gcc GCC_PCIE0_AUX_CLK>,
 205                                  <&gcc GCC_PCIE0_AHB_CLK>,
 206                                  <&gcc GCC_PCIE0_PIPE_CLK>;
 207                         clock-names = "aux",
 208                                       "cfg_ahb",
 209                                       "pipe";
 210
 211                         clock-output-names = "pcie20_phy0_pipe_clk";
 212                         #clock-cells = <0>;
 213
 214                         #phy-cells = <0>;
 215
 216                         resets = <&gcc GCC_PCIE0_PHY_BCR>,
 217                                  <&gcc GCC_PCIE0PHY_PHY_BCR>;
 218                         reset-names = "phy",
 219                                       "common";
 220                         status = "disabled";
 221                 };
 222
 223                 pcie_qmp1: phy@8e000 {
 224                         compatible = "qcom,ipq8074-qmp-pcie-phy";
 225                         reg = <0x0008e000 0x1000>;
 226
 227                         clocks = <&gcc GCC_PCIE1_AUX_CLK>,
 228                                  <&gcc GCC_PCIE1_AHB_CLK>,
 229                                  <&gcc GCC_PCIE1_PIPE_CLK>;
 230                         clock-names = "aux",
 231                                       "cfg_ahb",
 232                                       "pipe";
 233
 234                         clock-output-names = "pcie20_phy1_pipe_clk";
 235                         #clock-cells = <0>;
 236
 237                         #phy-cells = <0>;
 238
 239                         resets = <&gcc GCC_PCIE1_PHY_BCR>,
 240                                  <&gcc GCC_PCIE1PHY_PHY_BCR>;
 241                         reset-names = "phy",
 242                                       "common";
 243                         status = "disabled";
 244                 };
 245
 246                 mdio: mdio@90000 {
 247                         compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio";
 248                         reg = <0x00090000 0x64>;
 249                         #address-cells = <1>;
 250                         #size-cells = <0>;
 251
 252                         clocks = <&gcc GCC_MDIO_AHB_CLK>;
 253                         clock-names = "gcc_mdio_ahb_clk";
 254
 255                         clock-frequency = <6250000>;
 256
 257                         status = "disabled";
 258                 };
 259
 260                 qfprom: efuse@a4000 {
 261                         compatible = "qcom,ipq8074-qfprom", "qcom,qfprom";
 262                         reg = <0x000a4000 0x2000>;
 263                         #address-cells = <1>;
 264                         #size-cells = <1>;
 265                 };
 266
 267                 prng: rng@e3000 {
 268                         compatible = "qcom,prng-ee";
 269                         reg = <0x000e3000 0x1000>;
 270                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 271                         clock-names = "core";
 272                         status = "disabled";
 273                 };
 274
 275                 tsens: thermal-sensor@4a9000 {
 276                         compatible = "qcom,ipq8074-tsens";
 277                         reg = <0x4a9000 0x1000>, /* TM */
 278                               <0x4a8000 0x1000>; /* SROT */
 279                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 280                         interrupt-names = "combined";
 281                         #qcom,sensors = <16>;
 282                         #thermal-sensor-cells = <1>;
 283                 };
 284
 285                 cryptobam: dma-controller@704000 {
 286                         compatible = "qcom,bam-v1.7.0";
 287                         reg = <0x00704000 0x20000>;
 288                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 289                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
 290                         clock-names = "bam_clk";
 291                         #dma-cells = <1>;
 292                         qcom,ee = <1>;
 293                         qcom,controlled-remotely;
 294                         status = "disabled";
 295                 };
 296
 297                 crypto: crypto@73a000 {
 298                         compatible = "qcom,crypto-v5.1";
 299                         reg = <0x0073a000 0x6000>;
 300                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
 301                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 302                                  <&gcc GCC_CRYPTO_CLK>;
 303                         clock-names = "iface", "bus", "core";
 304                         dmas = <&cryptobam 2>, <&cryptobam 3>;
 305                         dma-names = "rx", "tx";
 306                         status = "disabled";
 307                 };
 308
 309                 tlmm: pinctrl@1000000 {
 310                         compatible = "qcom,ipq8074-pinctrl";
 311                         reg = <0x01000000 0x300000>;
 312                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 313                         gpio-controller;
 314                         gpio-ranges = <&tlmm 0 0 70>;
 315                         #gpio-cells = <2>;
 316                         interrupt-controller;
 317                         #interrupt-cells = <2>;
 318
 319                         serial_4_pins: serial4-state {
 320                                 pins = "gpio23", "gpio24";
 321                                 function = "blsp4_uart1";
 322                                 drive-strength = <8>;
 323                                 bias-disable;
 324                         };
 325
 326                         i2c_0_pins: i2c-0-state {
 327                                 pins = "gpio42", "gpio43";
 328                                 function = "blsp1_i2c";
 329                                 drive-strength = <8>;
 330                                 bias-disable;
 331                         };
 332
 333                         spi_0_pins: spi-0-state {
 334                                 pins = "gpio38", "gpio39", "gpio40", "gpio41";
 335                                 function = "blsp0_spi";
 336                                 drive-strength = <8>;
 337                                 bias-disable;
 338                         };
 339
 340                         hsuart_pins: hsuart-state {
 341                                 pins = "gpio46", "gpio47", "gpio48", "gpio49";
 342                                 function = "blsp2_uart";
 343                                 drive-strength = <8>;
 344                                 bias-disable;
 345                         };
 346
 347                         qpic_pins: qpic-state {
 348                                 pins = "gpio1", "gpio3", "gpio4",
 349                                        "gpio5", "gpio6", "gpio7",
 350                                        "gpio8", "gpio10", "gpio11",
 351                                        "gpio12", "gpio13", "gpio14",
 352                                        "gpio15", "gpio16", "gpio17";
 353                                 function = "qpic";
 354                                 drive-strength = <8>;
 355                                 bias-disable;
 356                         };
 357                 };
 358
 359                 gcc: gcc@1800000 {
 360                         compatible = "qcom,gcc-ipq8074";
 361                         reg = <0x01800000 0x80000>;
 362                         clocks = <&xo>,
 363                                  <&sleep_clk>,
 364                                  <&pcie_qmp0>,
 365                                  <&pcie_qmp1>;
 366                         clock-names = "xo",
 367                                       "sleep_clk",
 368                                       "pcie0_pipe",
 369                                       "pcie1_pipe";
 370                         #clock-cells = <1>;
 371                         #power-domain-cells = <1>;
 372                         #reset-cells = <1>;
 373                 };
 374
 375                 tcsr_mutex: hwlock@1905000 {
 376                         compatible = "qcom,tcsr-mutex";
 377                         reg = <0x01905000 0x20000>;
 378                         #hwlock-cells = <1>;
 379                 };
 380
 381                 tcsr: syscon@1937000 {
 382                         compatible = "qcom,tcsr-ipq8074", "syscon";
 383                         reg = <0x01937000 0x21000>;
 384                 };
 385
 386                 spmi_bus: spmi@200f000 {
 387                         compatible = "qcom,spmi-pmic-arb";
 388                         reg = <0x0200f000 0x001000>,
 389                               <0x02400000 0x800000>,
 390                               <0x02c00000 0x800000>,
 391                               <0x03800000 0x200000>,
 392                               <0x0200a000 0x000700>;
 393                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 394                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 395                         interrupt-names = "periph_irq";
 396                         qcom,ee = <0>;
 397                         qcom,channel = <0>;
 398                         #address-cells = <2>;
 399                         #size-cells = <0>;
 400                         interrupt-controller;
 401                         #interrupt-cells = <4>;
 402                 };
 403
 404                 sdhc_1: mmc@7824900 {
 405                         compatible = "qcom,ipq8074-sdhci", "qcom,sdhci-msm-v4";
 406                         reg = <0x7824900 0x500>, <0x7824000 0x800>;
 407                         reg-names = "hc", "core";
 408
 409                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 410                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 411                         interrupt-names = "hc_irq", "pwr_irq";
 412
 413                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 414                                  <&gcc GCC_SDCC1_APPS_CLK>,
 415                                  <&xo>;
 416                         clock-names = "iface", "core", "xo";
 417                         resets = <&gcc GCC_SDCC1_BCR>;
 418                         max-frequency = <384000000>;
 419                         mmc-ddr-1_8v;
 420                         mmc-hs200-1_8v;
 421                         mmc-hs400-1_8v;
 422                         bus-width = <8>;
 423
 424                         status = "disabled";
 425                 };
 426
 427                 blsp_dma: dma-controller@7884000 {
 428                         compatible = "qcom,bam-v1.7.0";
 429                         reg = <0x07884000 0x2b000>;
 430                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 431                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 432                         clock-names = "bam_clk";
 433                         #dma-cells = <1>;
 434                         qcom,ee = <0>;
 435                 };
 436
 437                 blsp1_uart1: serial@78af000 {
 438                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 439                         reg = <0x078af000 0x200>;
 440                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 441                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 442                                  <&gcc GCC_BLSP1_AHB_CLK>;
 443                         clock-names = "core", "iface";
 444                         status = "disabled";
 445                 };
 446
 447                 blsp1_uart3: serial@78b1000 {
 448                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 449                         reg = <0x078b1000 0x200>;
 450                         interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
 451                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
 452                                 <&gcc GCC_BLSP1_AHB_CLK>;
 453                         clock-names = "core", "iface";
 454                         dmas = <&blsp_dma 4>,
 455                                 <&blsp_dma 5>;
 456                         dma-names = "tx", "rx";
 457                         pinctrl-0 = <&hsuart_pins>;
 458                         pinctrl-names = "default";
 459                         status = "disabled";
 460                 };
 461
 462                 blsp1_uart5: serial@78b3000 {
 463                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 464                         reg = <0x078b3000 0x200>;
 465                         interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
 466                         clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
 467                                  <&gcc GCC_BLSP1_AHB_CLK>;
 468                         clock-names = "core", "iface";
 469                         pinctrl-0 = <&serial_4_pins>;
 470                         pinctrl-names = "default";
 471                         status = "disabled";
 472                 };
 473
 474                 blsp1_spi1: spi@78b5000 {
 475                         compatible = "qcom,spi-qup-v2.2.1";
 476                         #address-cells = <1>;
 477                         #size-cells = <0>;
 478                         reg = <0x078b5000 0x600>;
 479                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 480                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 481                                 <&gcc GCC_BLSP1_AHB_CLK>;
 482                         clock-names = "core", "iface";
 483                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
 484                         dma-names = "tx", "rx";
 485                         pinctrl-0 = <&spi_0_pins>;
 486                         pinctrl-names = "default";
 487                         status = "disabled";
 488                 };
 489
 490                 blsp1_i2c2: i2c@78b6000 {
 491                         compatible = "qcom,i2c-qup-v2.2.1";
 492                         #address-cells = <1>;
 493                         #size-cells = <0>;
 494                         reg = <0x078b6000 0x600>;
 495                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 496                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
 497                                  <&gcc GCC_BLSP1_AHB_CLK>;
 498                         clock-names = "core", "iface";
 499                         clock-frequency = <400000>;
 500                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
 501                         dma-names = "tx", "rx";
 502                         pinctrl-0 = <&i2c_0_pins>;
 503                         pinctrl-names = "default";
 504                         status = "disabled";
 505                 };
 506
 507                 blsp1_i2c3: i2c@78b7000 {
 508                         compatible = "qcom,i2c-qup-v2.2.1";
 509                         #address-cells = <1>;
 510                         #size-cells = <0>;
 511                         reg = <0x078b7000 0x600>;
 512                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 513                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
 514                                  <&gcc GCC_BLSP1_AHB_CLK>;
 515                         clock-names = "core", "iface";
 516                         clock-frequency = <100000>;
 517                         dmas = <&blsp_dma 16>, <&blsp_dma 17>;
 518                         dma-names = "tx", "rx";
 519                         status = "disabled";
 520                 };
 521
 522                 blsp1_spi4: spi@78b8000 {
 523                         compatible = "qcom,spi-qup-v2.2.1";
 524                         #address-cells = <1>;
 525                         #size-cells = <0>;
 526                         reg = <0x78b8000 0x600>;
 527                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 528                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
 529                                  <&gcc GCC_BLSP1_AHB_CLK>;
 530                         clock-names = "core", "iface";
 531                         dmas = <&blsp_dma 18>, <&blsp_dma 19>;
 532                         dma-names = "tx", "rx";
 533                         status = "disabled";
 534                 };
 535
 536                 blsp1_i2c5: i2c@78b9000 {
 537                         compatible = "qcom,i2c-qup-v2.2.1";
 538                         #address-cells = <1>;
 539                         #size-cells = <0>;
 540                         reg = <0x78b9000 0x600>;
 541                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 542                         clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
 543                                  <&gcc GCC_BLSP1_AHB_CLK>;
 544                         clock-names = "core", "iface";
 545                         clock-frequency = <400000>;
 546                         dmas = <&blsp_dma 20>, <&blsp_dma 21>;
 547                         dma-names = "tx", "rx";
 548                         status = "disabled";
 549                 };
 550
 551                 blsp1_spi5: spi@78b9000 {
 552                         compatible = "qcom,spi-qup-v2.2.1";
 553                         #address-cells = <1>;
 554                         #size-cells = <0>;
 555                         reg = <0x78b9000 0x600>;
 556                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 557                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 558                                  <&gcc GCC_BLSP1_AHB_CLK>;
 559                         clock-names = "core", "iface";
 560                         dmas = <&blsp_dma 20>, <&blsp_dma 21>;
 561                         dma-names = "tx", "rx";
 562                         status = "disabled";
 563                 };
 564
 565                 blsp1_i2c6: i2c@78ba000 {
 566                         compatible = "qcom,i2c-qup-v2.2.1";
 567                         #address-cells = <1>;
 568                         #size-cells = <0>;
 569                         reg = <0x078ba000 0x600>;
 570                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
 571                         clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
 572                                  <&gcc GCC_BLSP1_AHB_CLK>;
 573                         clock-names = "core", "iface";
 574                         clock-frequency = <100000>;
 575                         dmas = <&blsp_dma 22>, <&blsp_dma 23>;
 576                         dma-names = "tx", "rx";
 577                         status = "disabled";
 578                 };
 579
 580                 qpic_bam: dma-controller@7984000 {
 581                         compatible = "qcom,bam-v1.7.0";
 582                         reg = <0x07984000 0x1a000>;
 583                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 584                         clocks = <&gcc GCC_QPIC_AHB_CLK>;
 585                         clock-names = "bam_clk";
 586                         #dma-cells = <1>;
 587                         qcom,ee = <0>;
 588                         status = "disabled";
 589                 };
 590
 591                 qpic_nand: nand-controller@79b0000 {
 592                         compatible = "qcom,ipq8074-nand";
 593                         reg = <0x079b0000 0x10000>;
 594                         #address-cells = <1>;
 595                         #size-cells = <0>;
 596                         clocks = <&gcc GCC_QPIC_CLK>,
 597                                  <&gcc GCC_QPIC_AHB_CLK>;
 598                         clock-names = "core", "aon";
 599
 600                         dmas = <&qpic_bam 0>,
 601                                <&qpic_bam 1>,
 602                                <&qpic_bam 2>;
 603                         dma-names = "tx", "rx", "cmd";
 604                         pinctrl-0 = <&qpic_pins>;
 605                         pinctrl-names = "default";
 606                         status = "disabled";
 607                 };
 608
 609                 usb_0: usb@8af8800 {
 610                         compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
 611                         reg = <0x08af8800 0x400>;
 612                         #address-cells = <1>;
 613                         #size-cells = <1>;
 614                         ranges;
 615
 616                         clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 617                                 <&gcc GCC_USB0_MASTER_CLK>,
 618                                 <&gcc GCC_USB0_SLEEP_CLK>,
 619                                 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 620                         clock-names = "cfg_noc",
 621                                 "core",
 622                                 "sleep",
 623                                 "mock_utmi";
 624
 625                         assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 626                                           <&gcc GCC_USB0_MASTER_CLK>,
 627                                           <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 628                         assigned-clock-rates = <133330000>,
 629                                                 <133330000>,
 630                                                 <19200000>;
 631
 632                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 633                                      <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 634                                      <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 635                         interrupt-names = "pwr_event",
 636                                           "qusb2_phy",
 637                                           "ss_phy_irq";
 638
 639                         power-domains = <&gcc USB0_GDSC>;
 640
 641                         resets = <&gcc GCC_USB0_BCR>;
 642                         status = "disabled";
 643
 644                         dwc_0: usb@8a00000 {
 645                                 compatible = "snps,dwc3";
 646                                 reg = <0x8a00000 0xcd00>;
 647                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 648                                 phys = <&qusb_phy_0>, <&ssphy_0>;
 649                                 phy-names = "usb2-phy", "usb3-phy";
 650                                 snps,is-utmi-l1-suspend;
 651                                 snps,hird-threshold = /bits/ 8 <0x0>;
 652                                 snps,dis_u2_susphy_quirk;
 653                                 snps,dis_u3_susphy_quirk;
 654                                 dr_mode = "host";
 655                         };
 656                 };
 657
 658                 usb_1: usb@8cf8800 {
 659                         compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
 660                         reg = <0x08cf8800 0x400>;
 661                         #address-cells = <1>;
 662                         #size-cells = <1>;
 663                         ranges;
 664
 665                         clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
 666                                 <&gcc GCC_USB1_MASTER_CLK>,
 667                                 <&gcc GCC_USB1_SLEEP_CLK>,
 668                                 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 669                         clock-names = "cfg_noc",
 670                                 "core",
 671                                 "sleep",
 672                                 "mock_utmi";
 673
 674                         assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
 675                                           <&gcc GCC_USB1_MASTER_CLK>,
 676                                           <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 677                         assigned-clock-rates = <133330000>,
 678                                                 <133330000>,
 679                                                 <19200000>;
 680
 681                         interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 682                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 683                                      <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 684                         interrupt-names = "pwr_event",
 685                                           "qusb2_phy",
 686                                           "ss_phy_irq";
 687
 688                         power-domains = <&gcc USB1_GDSC>;
 689
 690                         resets = <&gcc GCC_USB1_BCR>;
 691                         status = "disabled";
 692
 693                         dwc_1: usb@8c00000 {
 694                                 compatible = "snps,dwc3";
 695                                 reg = <0x8c00000 0xcd00>;
 696                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 697                                 phys = <&qusb_phy_1>, <&ssphy_1>;
 698                                 phy-names = "usb2-phy", "usb3-phy";
 699                                 snps,is-utmi-l1-suspend;
 700                                 snps,hird-threshold = /bits/ 8 <0x0>;
 701                                 snps,dis_u2_susphy_quirk;
 702                                 snps,dis_u3_susphy_quirk;
 703                                 dr_mode = "host";
 704                         };
 705                 };
 706
 707                 intc: interrupt-controller@b000000 {
 708                         compatible = "qcom,msm-qgic2";
 709                         #address-cells = <1>;
 710                         #size-cells = <1>;
 711                         interrupt-controller;
 712                         #interrupt-cells = <3>;
 713                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 714                         ranges = <0 0xb00a000 0xffd>;
 715
 716                         v2m@0 {
 717                                 compatible = "arm,gic-v2m-frame";
 718                                 msi-controller;
 719                                 reg = <0x0 0xffd>;
 720                         };
 721                 };
 722
 723                 watchdog: watchdog@b017000 {
 724                         compatible = "qcom,kpss-wdt";
 725                         reg = <0xb017000 0x1000>;
 726                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
 727                         clocks = <&sleep_clk>;
 728                         timeout-sec = <30>;
 729                 };
 730
 731                 apcs_glb: mailbox@b111000 {
 732                         compatible = "qcom,ipq8074-apcs-apps-global",
 733                                      "qcom,ipq6018-apcs-apps-global";
 734                         reg = <0x0b111000 0x1000>;
 735                         clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
 736                         clock-names = "pll", "xo", "gpll0";
 737
 738                         #clock-cells = <1>;
 739                         #mbox-cells = <1>;
 740                 };
 741
 742                 a53pll: clock@b116000 {
 743                         compatible = "qcom,ipq8074-a53pll";
 744                         reg = <0x0b116000 0x40>;
 745                         #clock-cells = <0>;
 746                         clocks = <&xo>;
 747                         clock-names = "xo";
 748                 };
 749
 750                 timer@b120000 {
 751                         #address-cells = <1>;
 752                         #size-cells = <1>;
 753                         ranges;
 754                         compatible = "arm,armv7-timer-mem";
 755                         reg = <0x0b120000 0x1000>;
 756
 757                         frame@b120000 {
 758                                 frame-number = <0>;
 759                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 760                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 761                                 reg = <0x0b121000 0x1000>,
 762                                       <0x0b122000 0x1000>;
 763                         };
 764
 765                         frame@b123000 {
 766                                 frame-number = <1>;
 767                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 768                                 reg = <0x0b123000 0x1000>;
 769                                 status = "disabled";
 770                         };
 771
 772                         frame@b124000 {
 773                                 frame-number = <2>;
 774                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 775                                 reg = <0x0b124000 0x1000>;
 776                                 status = "disabled";
 777                         };
 778
 779                         frame@b125000 {
 780                                 frame-number = <3>;
 781                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 782                                 reg = <0x0b125000 0x1000>;
 783                                 status = "disabled";
 784                         };
 785
 786                         frame@b126000 {
 787                                 frame-number = <4>;
 788                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 789                                 reg = <0x0b126000 0x1000>;
 790                                 status = "disabled";
 791                         };
 792
 793                         frame@b127000 {
 794                                 frame-number = <5>;
 795                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 796                                 reg = <0x0b127000 0x1000>;
 797                                 status = "disabled";
 798                         };
 799
 800                         frame@b128000 {
 801                                 frame-number = <6>;
 802                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 803                                 reg = <0x0b128000 0x1000>;
 804                                 status = "disabled";
 805                         };
 806                 };
 807
 808                 pcie1: pcie@10000000 {
 809                         compatible = "qcom,pcie-ipq8074";
 810                         reg = <0x10000000 0xf1d>,
 811                               <0x10000f20 0xa8>,
 812                               <0x00088000 0x2000>,
 813                               <0x10100000 0x1000>;
 814                         reg-names = "dbi", "elbi", "parf", "config";
 815                         device_type = "pci";
 816                         linux,pci-domain = <1>;
 817                         bus-range = <0x00 0xff>;
 818                         num-lanes = <1>;
 819                         max-link-speed = <2>;
 820                         #address-cells = <3>;
 821                         #size-cells = <2>;
 822
 823                         phys = <&pcie_qmp1>;
 824                         phy-names = "pciephy";
 825
 826                         ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>,   /* I/O */
 827                                  <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
 828
 829                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 830                         interrupt-names = "msi";
 831                         #interrupt-cells = <1>;
 832                         interrupt-map-mask = <0 0 0 0x7>;
 833                         interrupt-map = <0 0 0 1 &intc 0 0 142
 834                                          IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 835                                         <0 0 0 2 &intc 0 0 143
 836                                          IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 837                                         <0 0 0 3 &intc 0 0 144
 838                                          IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 839                                         <0 0 0 4 &intc 0 0 145
 840                                          IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 841
 842                         clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
 843                                  <&gcc GCC_PCIE1_AXI_M_CLK>,
 844                                  <&gcc GCC_PCIE1_AXI_S_CLK>,
 845                                  <&gcc GCC_PCIE1_AHB_CLK>,
 846                                  <&gcc GCC_PCIE1_AUX_CLK>;
 847                         clock-names = "iface",
 848                                       "axi_m",
 849                                       "axi_s",
 850                                       "ahb",
 851                                       "aux";
 852                         resets = <&gcc GCC_PCIE1_PIPE_ARES>,
 853                                  <&gcc GCC_PCIE1_SLEEP_ARES>,
 854                                  <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
 855                                  <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
 856                                  <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
 857                                  <&gcc GCC_PCIE1_AHB_ARES>,
 858                                  <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
 859                         reset-names = "pipe",
 860                                       "sleep",
 861                                       "sticky",
 862                                       "axi_m",
 863                                       "axi_s",
 864                                       "ahb",
 865                                       "axi_m_sticky";
 866                         status = "disabled";
 867                 };
 868
 869                 pcie0: pcie@20000000 {
 870                         compatible = "qcom,pcie-ipq8074-gen3";
 871                         reg = <0x20000000 0xf1d>,
 872                               <0x20000f20 0xa8>,
 873                               <0x20001000 0x1000>,
 874                               <0x00080000 0x4000>,
 875                               <0x20100000 0x1000>;
 876                         reg-names = "dbi", "elbi", "atu", "parf", "config";
 877                         device_type = "pci";
 878                         linux,pci-domain = <0>;
 879                         bus-range = <0x00 0xff>;
 880                         num-lanes = <1>;
 881                         max-link-speed = <3>;
 882                         #address-cells = <3>;
 883                         #size-cells = <2>;
 884
 885                         phys = <&pcie_qmp0>;
 886                         phy-names = "pciephy";
 887
 888                         ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>,   /* I/O */
 889                                  <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
 890
 891                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 892                         interrupt-names = "msi";
 893                         #interrupt-cells = <1>;
 894                         interrupt-map-mask = <0 0 0 0x7>;
 895                         interrupt-map = <0 0 0 1 &intc 0 0 75
 896                                          IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 897                                         <0 0 0 2 &intc 0 0 78
 898                                          IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 899                                         <0 0 0 3 &intc 0 0 79
 900                                          IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 901                                         <0 0 0 4 &intc 0 0 83
 902                                          IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 903
 904                         clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
 905                                  <&gcc GCC_PCIE0_AXI_M_CLK>,
 906                                  <&gcc GCC_PCIE0_AXI_S_CLK>,
 907                                  <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
 908                                  <&gcc GCC_PCIE0_RCHNG_CLK>;
 909                         clock-names = "iface",
 910                                       "axi_m",
 911                                       "axi_s",
 912                                       "axi_bridge",
 913                                       "rchng";
 914
 915                         resets = <&gcc GCC_PCIE0_PIPE_ARES>,
 916                                  <&gcc GCC_PCIE0_SLEEP_ARES>,
 917                                  <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
 918                                  <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
 919                                  <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
 920                                  <&gcc GCC_PCIE0_AHB_ARES>,
 921                                  <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
 922                                  <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
 923                         reset-names = "pipe",
 924                                       "sleep",
 925                                       "sticky",
 926                                       "axi_m",
 927                                       "axi_s",
 928                                       "ahb",
 929                                       "axi_m_sticky",
 930                                       "axi_s_sticky";
 931                         status = "disabled";
 932                 };
 933         };
 934
 935         timer {
 936                 compatible = "arm,armv8-timer";
 937                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 938                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 939                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 940                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 941         };
 942
 943         thermal-zones {
 944                 nss-top-thermal {
 945                         polling-delay-passive = <250>;
 946                         polling-delay = <1000>;
 947
 948                         thermal-sensors = <&tsens 4>;
 949
 950                         trips {
 951                                 nss-top-crit {
 952                                         temperature = <110000>;
 953                                         hysteresis = <1000>;
 954                                         type = "critical";
 955                                 };
 956                         };
 957                 };
 958
 959                 nss0-thermal {
 960                         polling-delay-passive = <250>;
 961                         polling-delay = <1000>;
 962
 963                         thermal-sensors = <&tsens 5>;
 964
 965                         trips {
 966                                 nss-0-crit {
 967                                         temperature = <110000>;
 968                                         hysteresis = <1000>;
 969                                         type = "critical";
 970                                 };
 971                         };
 972                 };
 973
 974                 nss1-thermal {
 975                         polling-delay-passive = <250>;
 976                         polling-delay = <1000>;
 977
 978                         thermal-sensors = <&tsens 6>;
 979
 980                         trips {
 981                                 nss-1-crit {
 982                                         temperature = <110000>;
 983                                         hysteresis = <1000>;
 984                                         type = "critical";
 985                                 };
 986                         };
 987                 };
 988
 989                 wcss-phya0-thermal {
 990                         polling-delay-passive = <250>;
 991                         polling-delay = <1000>;
 992
 993                         thermal-sensors = <&tsens 7>;
 994
 995                         trips {
 996                                 wcss-phya0-crit {
 997                                         temperature = <110000>;
 998                                         hysteresis = <1000>;
 999                                         type = "critical";
1000                                 };
1001                         };
1002                 };
1003
1004                 wcss-phya1-thermal {
1005                         polling-delay-passive = <250>;
1006                         polling-delay = <1000>;
1007
1008                         thermal-sensors = <&tsens 8>;
1009
1010                         trips {
1011                                 wcss-phya1-crit {
1012                                         temperature = <110000>;
1013                                         hysteresis = <1000>;
1014                                         type = "critical";
1015                                 };
1016                         };
1017                 };
1018
1019                 cpu0_thermal: cpu0-thermal {
1020                         polling-delay-passive = <250>;
1021                         polling-delay = <1000>;
1022
1023                         thermal-sensors = <&tsens 9>;
1024
1025                         trips {
1026                                 cpu0-crit {
1027                                         temperature = <110000>;
1028                                         hysteresis = <1000>;
1029                                         type = "critical";
1030                                 };
1031                         };
1032                 };
1033
1034                 cpu1_thermal: cpu1-thermal {
1035                         polling-delay-passive = <250>;
1036                         polling-delay = <1000>;
1037
1038                         thermal-sensors = <&tsens 10>;
1039
1040                         trips {
1041                                 cpu1-crit {
1042                                         temperature = <110000>;
1043                                         hysteresis = <1000>;
1044                                         type = "critical";
1045                                 };
1046                         };
1047                 };
1048
1049                 cpu2_thermal: cpu2-thermal {
1050                         polling-delay-passive = <250>;
1051                         polling-delay = <1000>;
1052
1053                         thermal-sensors = <&tsens 11>;
1054
1055                         trips {
1056                                 cpu2-crit {
1057                                         temperature = <110000>;
1058                                         hysteresis = <1000>;
1059                                         type = "critical";
1060                                 };
1061                         };
1062                 };
1063
1064                 cpu3_thermal: cpu3-thermal {
1065                         polling-delay-passive = <250>;
1066                         polling-delay = <1000>;
1067
1068                         thermal-sensors = <&tsens 12>;
1069
1070                         trips {
1071                                 cpu3-crit {
1072                                         temperature = <110000>;
1073                                         hysteresis = <1000>;
1074                                         type = "critical";
1075                                 };
1076                         };
1077                 };
1078
1079                 cluster_thermal: cluster-thermal {
1080                         polling-delay-passive = <250>;
1081                         polling-delay = <1000>;
1082
1083                         thermal-sensors = <&tsens 13>;
1084
1085                         trips {
1086                                 cluster-crit {
1087                                         temperature = <110000>;
1088                                         hysteresis = <1000>;
1089                                         type = "critical";
1090                                 };
1091                         };
1092                 };
1093
1094                 wcss-phyb0-thermal {
1095                         polling-delay-passive = <250>;
1096                         polling-delay = <1000>;
1097
1098                         thermal-sensors = <&tsens 14>;
1099
1100                         trips {
1101                                 wcss-phyb0-crit {
1102                                         temperature = <110000>;
1103                                         hysteresis = <1000>;
1104                                         type = "critical";
1105                                 };
1106                         };
1107                 };
1108
1109                 wcss-phyb1-thermal {
1110                         polling-delay-passive = <250>;
1111                         polling-delay = <1000>;
1112
1113                         thermal-sensors = <&tsens 15>;
1114
1115                         trips {
1116                                 wcss-phyb1-crit {
1117                                         temperature = <110000>;
1118                                         hysteresis = <1000>;
1119                                         type = "critical";
1120                                 };
1121                         };
1122                 };
1123         };
1124 };