1 // SPDX-License-Identifier: BSD-3-Clause
3 * SDX75 SoC device tree source
5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/interconnect/qcom,icc.h>
12 #include <dt-bindings/interconnect/qcom,sdx75.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/qcom,rpmhpd.h>
15 #include <dt-bindings/power/qcom-rpmpd.h>
16 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 interrupt-parent = <&intc>;
27 compatible = "fixed-clock";
28 clock-frequency = <76800000>;
32 sleep_clk: sleep-clk {
33 compatible = "fixed-clock";
34 clock-frequency = <32000>;
45 compatible = "arm,cortex-a55";
47 clocks = <&cpufreq_hw 0>;
48 enable-method = "psci";
49 power-domains = <&CPU_PD0>;
50 power-domain-names = "psci";
51 qcom,freq-domain = <&cpufreq_hw 0>;
52 capacity-dmips-mhz = <1024>;
53 dynamic-power-coefficient = <100>;
54 next-level-cache = <&L2_0>;
60 next-level-cache = <&L3_0>;
71 compatible = "arm,cortex-a55";
73 clocks = <&cpufreq_hw 0>;
74 enable-method = "psci";
75 power-domains = <&CPU_PD1>;
76 power-domain-names = "psci";
77 qcom,freq-domain = <&cpufreq_hw 0>;
78 capacity-dmips-mhz = <1024>;
79 dynamic-power-coefficient = <100>;
80 next-level-cache = <&L2_100>;
86 next-level-cache = <&L3_0>;
92 compatible = "arm,cortex-a55";
94 clocks = <&cpufreq_hw 0>;
95 enable-method = "psci";
96 power-domains = <&CPU_PD2>;
97 power-domain-names = "psci";
98 qcom,freq-domain = <&cpufreq_hw 0>;
99 capacity-dmips-mhz = <1024>;
100 dynamic-power-coefficient = <100>;
101 next-level-cache = <&L2_200>;
104 compatible = "cache";
107 next-level-cache = <&L3_0>;
113 compatible = "arm,cortex-a55";
115 clocks = <&cpufreq_hw 0>;
116 enable-method = "psci";
117 power-domains = <&CPU_PD3>;
118 power-domain-names = "psci";
119 qcom,freq-domain = <&cpufreq_hw 0>;
120 capacity-dmips-mhz = <1024>;
121 dynamic-power-coefficient = <100>;
122 next-level-cache = <&L2_300>;
125 compatible = "cache";
128 next-level-cache = <&L3_0>;
153 entry-method = "psci";
155 CPU_OFF: cpu-sleep-0 {
156 compatible = "arm,idle-state";
157 entry-latency-us = <235>;
158 exit-latency-us = <428>;
159 min-residency-us = <1774>;
160 arm,psci-suspend-param = <0x40000003>;
164 CPU_RAIL_OFF: cpu-rail-sleep-1 {
165 compatible = "arm,idle-state";
166 entry-latency-us = <800>;
167 exit-latency-us = <750>;
168 min-residency-us = <4090>;
169 arm,psci-suspend-param = <0x40000004>;
176 CLUSTER_SLEEP_0: cluster-sleep-0 {
177 compatible = "domain-idle-state";
178 arm,psci-suspend-param = <0x41000044>;
179 entry-latency-us = <1050>;
180 exit-latency-us = <2500>;
181 min-residency-us = <5309>;
184 CLUSTER_SLEEP_1: cluster-sleep-1 {
185 compatible = "domain-idle-state";
186 arm,psci-suspend-param = <0x41001344>;
187 entry-latency-us = <2761>;
188 exit-latency-us = <3964>;
189 min-residency-us = <8467>;
192 CLUSTER_SLEEP_2: cluster-sleep-2 {
193 compatible = "domain-idle-state";
194 arm,psci-suspend-param = <0x4100b344>;
195 entry-latency-us = <2793>;
196 exit-latency-us = <4023>;
197 min-residency-us = <9826>;
204 compatible = "qcom,scm-sdx75", "qcom,scm";
208 clk_virt: interconnect-0 {
209 compatible = "qcom,sdx75-clk-virt";
210 #interconnect-cells = <2>;
211 qcom,bcm-voters = <&apps_bcm_voter>;
212 clocks = <&rpmhcc RPMH_QPIC_CLK>;
215 mc_virt: interconnect-1 {
216 compatible = "qcom,sdx75-mc-virt";
217 #interconnect-cells = <2>;
218 qcom,bcm-voters = <&apps_bcm_voter>;
222 device_type = "memory";
223 reg = <0x0 0x80000000 0x0 0x0>;
227 compatible = "arm,armv8-pmuv3";
228 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
232 compatible = "arm,psci-1.0";
235 CPU_PD0: power-domain-cpu0 {
236 #power-domain-cells = <0>;
237 power-domains = <&CLUSTER_PD>;
238 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
241 CPU_PD1: power-domain-cpu1 {
242 #power-domain-cells = <0>;
243 power-domains = <&CLUSTER_PD>;
244 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
247 CPU_PD2: power-domain-cpu2 {
248 #power-domain-cells = <0>;
249 power-domains = <&CLUSTER_PD>;
250 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
253 CPU_PD3: power-domain-cpu3 {
254 #power-domain-cells = <0>;
255 power-domains = <&CLUSTER_PD>;
256 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
259 CLUSTER_PD: power-domain-cpu-cluster0 {
260 #power-domain-cells = <0>;
261 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>;
266 #address-cells = <2>;
270 gunyah_hyp_mem: gunyah-hyp@80000000 {
271 reg = <0x0 0x80000000 0x0 0x800000>;
275 hyp_elf_package_mem: hyp-elf-package@80800000 {
276 reg = <0x0 0x80800000 0x0 0x200000>;
280 access_control_db_mem: access-control-db@81380000 {
281 reg = <0x0 0x81380000 0x0 0x80000>;
285 qteetz_mem: qteetz@814e0000 {
286 reg = <0x0 0x814e0000 0x0 0x2a0000>;
290 trusted_apps_mem: trusted-apps@81780000 {
291 reg = <0x0 0x81780000 0x0 0xa00000>;
295 xbl_ramdump_mem: xbl-ramdump@87a00000 {
296 reg = <0x0 0x87a00000 0x0 0x1c0000>;
300 cpucp_fw_mem: cpucp-fw@87c00000 {
301 reg = <0x0 0x87c00000 0x0 0x100000>;
305 xbl_dtlog_mem: xbl-dtlog@87d00000 {
306 reg = <0x0 0x87d00000 0x0 0x40000>;
310 xbl_sc_mem: xbl-sc@87d40000 {
311 reg = <0x0 0x87d40000 0x0 0x40000>;
315 modem_efs_shared_mem: modem-efs-shared@87d80000 {
316 reg = <0x0 0x87d80000 0x0 0x10000>;
320 aop_image_mem: aop-image@87e00000 {
321 reg = <0x0 0x87e00000 0x0 0x20000>;
325 smem_mem: smem@87e20000 {
326 reg = <0x0 0x87e20000 0x0 0xc0000>;
330 aop_cmd_db_mem: aop-cmd-db@87ee0000 {
331 compatible = "qcom,cmd-db";
332 reg = <0x0 0x87ee0000 0x0 0x20000>;
336 aop_config_mem: aop-config@87f00000 {
337 reg = <0x0 0x87f00000 0x0 0x20000>;
341 ipa_fw_mem: ipa-fw@87f20000 {
342 reg = <0x0 0x87f20000 0x0 0x10000>;
346 secdata_mem: secdata@87f30000 {
347 reg = <0x0 0x87f30000 0x0 0x1000>;
351 tme_crashdump_mem: tme-crashdump@87f31000 {
352 reg = <0x0 0x87f31000 0x0 0x40000>;
356 tme_log_mem: tme-log@87f71000 {
357 reg = <0x0 0x87f71000 0x0 0x4000>;
361 uefi_log_mem: uefi-log@87f75000 {
362 reg = <0x0 0x87f75000 0x0 0x10000>;
366 qdss_mem: qdss@88800000 {
367 reg = <0x0 0x88800000 0x0 0x300000>;
371 audio_heap_mem: audio-heap@88b00000 {
372 compatible = "shared-dma-pool";
373 reg = <0x0 0x88b00000 0x0 0x400000>;
377 mpss_dsmharq_mem: mpss-dsmharq@88f00000 {
378 reg = <0x0 0x88f00000 0x0 0x5080000>;
382 q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 {
383 reg = <0x0 0x8df80000 0x0 0x80000>;
387 mpssadsp_mem: mpssadsp@8e000000 {
388 reg = <0x0 0x8e000000 0x0 0xf400000>;
392 gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 {
393 reg = <0x0 0xbdb00000 0x0 0x2000000>;
397 smmu_debug_buf_mem: smmu-debug-buf@bfb00000 {
398 reg = <0x0 0xbfb00000 0x0 0x100000>;
402 hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 {
403 reg = <0x0 0xbfc00000 0x0 0x400000>;
409 compatible = "qcom,smem";
410 memory-region = <&smem_mem>;
411 hwlocks = <&tcsr_mutex 3>;
415 compatible = "simple-bus";
416 #address-cells = <2>;
418 ranges = <0 0 0 0 0x10 0>;
419 dma-ranges = <0 0 0 0 0x10 0>;
421 gcc: clock-controller@80000 {
422 compatible = "qcom,sdx75-gcc";
423 reg = <0x0 0x0080000 0x0 0x1f7400>;
424 clocks = <&rpmhcc RPMH_CXO_CLK>,
441 #power-domain-cells = <1>;
444 qupv3_id_0: geniqup@9c0000 {
445 compatible = "qcom,geni-se-qup";
446 reg = <0x0 0x009c0000 0x0 0x2000>;
447 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
448 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
449 clock-names = "m-ahb",
451 iommus = <&apps_smmu 0xe3 0x0>;
452 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
453 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>;
454 interconnect-names = "qup-core";
455 #address-cells = <2>;
460 uart1: serial@984000 {
461 compatible = "qcom,geni-debug-uart";
462 reg = <0x0 0x00984000 0x0 0x4000>;
463 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
465 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
466 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
467 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
468 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
469 interconnect-names = "qup-core",
471 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
472 pinctrl-0 = <&qupv3_se1_2uart_active>;
473 pinctrl-1 = <&qupv3_se1_2uart_sleep>;
474 pinctrl-names = "default",
480 usb_hsphy: phy@ff4000 {
481 compatible = "qcom,sdx75-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy";
482 reg = <0x0 0x00ff4000 0x0 0x154>;
485 clocks = <&rpmhcc RPMH_CXO_CLK>;
488 resets = <&gcc GCC_QUSB2PHY_BCR>;
493 usb_qmpphy: phy@ff6000 {
494 compatible = "qcom,sdx75-qmp-usb3-uni-phy";
495 reg = <0x0 0x00ff6000 0x0 0x2000>;
497 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
498 <&gcc GCC_USB2_CLKREF_EN>,
499 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
500 <&gcc GCC_USB3_PHY_PIPE_CLK>;
506 power-domains = <&gcc GCC_USB3_PHY_GDSC>;
508 resets = <&gcc GCC_USB3_PHY_BCR>,
509 <&gcc GCC_USB3PHY_PHY_BCR>;
514 clock-output-names = "usb3_uni_phy_pipe_clk_src";
521 system_noc: interconnect@1640000 {
522 compatible = "qcom,sdx75-system-noc";
523 reg = <0x0 0x01640000 0x0 0x4b400>;
524 #interconnect-cells = <2>;
525 qcom,bcm-voters = <&apps_bcm_voter>;
528 pcie_anoc: interconnect@16c0000 {
529 compatible = "qcom,sdx75-pcie-anoc";
530 reg = <0x0 0x016c0000 0x0 0x14200>;
531 #interconnect-cells = <2>;
532 qcom,bcm-voters = <&apps_bcm_voter>;
535 tcsr_mutex: hwlock@1f40000 {
536 compatible = "qcom,tcsr-mutex";
537 reg = <0x0 0x01f40000 0x0 0x40000>;
542 compatible = "qcom,sdx75-dwc3", "qcom,dwc3";
543 reg = <0x0 0x0a6f8800 0x0 0x400>;
544 #address-cells = <2>;
548 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
549 <&gcc GCC_USB30_MASTER_CLK>,
550 <&gcc GCC_USB30_MSTR_AXI_CLK>,
551 <&gcc GCC_USB30_SLEEP_CLK>,
552 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
553 clock-names = "cfg_noc",
559 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
560 <&gcc GCC_USB30_MASTER_CLK>;
561 assigned-clock-rates = <19200000>, <200000000>;
563 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
564 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
565 <&pdc 9 IRQ_TYPE_EDGE_RISING>,
566 <&pdc 10 IRQ_TYPE_EDGE_RISING>;
567 interrupt-names = "hs_phy_irq",
572 power-domains = <&gcc GCC_USB30_GDSC>;
574 resets = <&gcc GCC_USB30_BCR>;
576 interconnects = <&system_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
577 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
578 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
579 &system_noc SLAVE_USB3 QCOM_ICC_TAG_ALWAYS>;
580 interconnect-names = "usb-ddr",
585 usb_dwc3: usb@a600000 {
586 compatible = "snps,dwc3";
587 reg = <0x0 0x0a600000 0x0 0xcd00>;
588 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
589 iommus = <&apps_smmu 0x80 0x0>;
590 snps,dis_u2_susphy_quirk;
591 snps,dis_enblslpm_quirk;
594 phy-names = "usb2-phy",
598 #address-cells = <1>;
604 usb_1_dwc3_hs: endpoint {
611 usb_1_dwc3_ss: endpoint {
618 pdc: interrupt-controller@b220000 {
619 compatible = "qcom,sdx75-pdc", "qcom,pdc";
620 reg = <0x0 0xb220000 0x0 0x30000>,
621 <0x0 0x174000f0 0x0 0x64>;
622 qcom,pdc-ranges = <0 147 52>,
625 #interrupt-cells = <2>;
626 interrupt-parent = <&intc>;
627 interrupt-controller;
630 spmi_bus: spmi@c400000 {
631 compatible = "qcom,spmi-pmic-arb";
632 reg = <0x0 0x0c400000 0x0 0x3000>,
633 <0x0 0x0c500000 0x0 0x400000>,
634 <0x0 0x0c440000 0x0 0x80000>,
635 <0x0 0x0c4c0000 0x0 0x10000>,
636 <0x0 0x0c42d000 0x0 0x4000>;
642 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
643 interrupt-names = "periph_irq";
647 #address-cells = <2>;
649 interrupt-controller;
650 #interrupt-cells = <4>;
653 tlmm: pinctrl@f000000 {
654 compatible = "qcom,sdx75-tlmm";
655 reg = <0x0 0x0f000000 0x0 0x400000>;
656 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
659 gpio-ranges = <&tlmm 0 0 133>;
660 interrupt-controller;
661 #interrupt-cells = <2>;
662 wakeup-parent = <&pdc>;
664 qupv3_se1_2uart_active: qupv3-se1-2uart-active-state {
667 function = "qup_se1_l2_mira";
668 drive-strength = <2>;
674 function = "qup_se1_l3_mira";
675 drive-strength = <2>;
680 qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state {
681 pins = "gpio12", "gpio13";
683 drive-strength = <2>;
688 apps_smmu: iommu@15000000 {
689 compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500";
690 reg = <0x0 0x15000000 0x0 0x40000>;
692 #global-interrupts = <2>;
694 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
701 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
703 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
704 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
706 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
707 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
710 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
713 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
714 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
715 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
716 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
720 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
721 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
724 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
725 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
726 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
729 intc: interrupt-controller@17200000 {
730 compatible = "arm,gic-v3";
731 #interrupt-cells = <3>;
732 interrupt-controller;
733 #redistributor-regions = <1>;
734 redistributor-stride = <0x0 0x20000>;
735 reg = <0x0 0x17200000 0x0 0x10000>,
736 <0x0 0x17260000 0x0 0x80000>;
737 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
741 compatible = "arm,armv7-timer-mem";
742 reg = <0x0 0x17420000 0x0 0x1000>;
743 #address-cells = <1>;
745 ranges = <0 0 0 0x20000000>;
748 reg = <0x17421000 0x1000>,
751 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
756 reg = <0x17423000 0x1000>;
758 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
763 reg = <0x17425000 0x1000>;
765 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
770 reg = <0x17427000 0x1000>;
772 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
777 reg = <0x17429000 0x1000>;
779 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
784 reg = <0x1742b000 0x1000>;
786 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
791 reg = <0x1742d000 0x1000>;
793 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
798 apps_rsc: rsc@17a00000 {
800 compatible = "qcom,rpmh-rsc";
801 reg = <0x0 0x17a00000 0x0 0x10000>,
802 <0x0 0x17a10000 0x0 0x10000>,
803 <0x0 0x17a20000 0x0 0x10000>;
804 reg-names = "drv-0", "drv-1", "drv-2";
805 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
806 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
807 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
809 power-domains = <&CLUSTER_PD>;
810 qcom,tcs-offset = <0xd00>;
812 qcom,tcs-config = <ACTIVE_TCS 3>,
817 apps_bcm_voter: bcm-voter {
818 compatible = "qcom,bcm-voter";
821 rpmhcc: clock-controller {
822 compatible = "qcom,sdx75-rpmh-clk";
823 clocks = <&xo_board>;
828 rpmhpd: power-controller {
829 compatible = "qcom,sdx75-rpmhpd";
830 #power-domain-cells = <1>;
831 operating-points-v2 = <&rpmhpd_opp_table>;
833 rpmhpd_opp_table: opp-table {
834 compatible = "operating-points-v2";
836 rpmhpd_opp_ret: opp-16 {
837 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
840 rpmhpd_opp_min_svs: opp-48 {
841 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
844 rpmhpd_opp_low_svs: opp-64 {
845 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
848 rpmhpd_opp_svs: opp-128 {
849 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
852 rpmhpd_opp_svs_l1: opp-192 {
853 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
856 rpmhpd_opp_nom: opp-256 {
857 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
860 rpmhpd_opp_nom_l1: opp-320 {
861 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
864 rpmhpd_opp_nom_l2: opp-336 {
865 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
868 rpmhpd_opp_turbo: opp-384 {
869 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
872 rpmhpd_opp_turbo_l1: opp-416 {
873 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
879 cpufreq_hw: cpufreq@17d91000 {
880 compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss";
881 reg = <0x0 0x17d91000 0x0 0x1000>;
882 reg-names = "freq-domain0";
883 clocks = <&rpmhcc RPMH_CXO_CLK>,
887 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
888 interrupt-names = "dcvsh-irq-0";
889 #freq-domain-cells = <1>;
893 dc_noc: interconnect@190e0000 {
894 compatible = "qcom,sdx75-dc-noc";
895 reg = <0x0 0x190e0000 0x0 0x8200>;
896 #interconnect-cells = <2>;
897 qcom,bcm-voters = <&apps_bcm_voter>;
900 gem_noc: interconnect@19100000 {
901 compatible = "qcom,sdx75-gem-noc";
902 reg = <0x0 0x19100000 0x0 0x34080>;
903 #interconnect-cells = <2>;
904 qcom,bcm-voters = <&apps_bcm_voter>;
909 compatible = "arm,armv8-timer";
910 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
911 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
912 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
913 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;