arch/arm64/boot/dts/ti/k3-am62-main.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
   2 /*
   3  * Device Tree Source for AM625 SoC Family Main Domain peripherals
   4  *
   5  * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 &cbass_main {
   9         oc_sram: sram@70000000 {
  10                 compatible = "mmio-sram";
  11                 reg = <0x00 0x70000000 0x00 0x10000>;
  12                 #address-cells = <1>;
  13                 #size-cells = <1>;
  14                 ranges = <0x0 0x00 0x70000000 0x10000>;
  15         };
  16
  17         gic500: interrupt-controller@1800000 {
  18                 compatible = "arm,gic-v3";
  19                 #address-cells = <2>;
  20                 #size-cells = <2>;
  21                 ranges;
  22                 #interrupt-cells = <3>;
  23                 interrupt-controller;
  24                 reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
  25                       <0x00 0x01880000 0x00 0xc0000>,   /* GICR */
  26                       <0x00 0x01880000 0x00 0xc0000>,   /* GICR */
  27                       <0x01 0x00000000 0x00 0x2000>,    /* GICC */
  28                       <0x01 0x00010000 0x00 0x1000>,    /* GICH */
  29                       <0x01 0x00020000 0x00 0x2000>;    /* GICV */
  30                 /*
  31                  * vcpumntirq:
  32                  * virtual CPU interface maintenance interrupt
  33                  */
  34                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  35
  36                 gic_its: msi-controller@1820000 {
  37                         compatible = "arm,gic-v3-its";
  38                         reg = <0x00 0x01820000 0x00 0x10000>;
  39                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
  40                         msi-controller;
  41                         #msi-cells = <1>;
  42                 };
  43         };
  44
  45         main_conf: bus@100000 {
  46                 compatible = "simple-bus";
  47                 #address-cells = <1>;
  48                 #size-cells = <1>;
  49                 ranges = <0x0 0x00 0x00100000 0x20000>;
  50
  51                 phy_gmii_sel: phy@4044 {
  52                         compatible = "ti,am654-phy-gmii-sel";
  53                         reg = <0x4044 0x8>;
  54                         #phy-cells = <1>;
  55                 };
  56
  57                 epwm_tbclk: clock-controller@4130 {
  58                         compatible = "ti,am62-epwm-tbclk";
  59                         reg = <0x4130 0x4>;
  60                         #clock-cells = <1>;
  61                 };
  62
  63                 audio_refclk0: clock-controller@82e0 {
  64                         compatible = "ti,am62-audio-refclk";
  65                         reg = <0x82e0 0x4>;
  66                         clocks = <&k3_clks 157 0>;
  67                         assigned-clocks = <&k3_clks 157 0>;
  68                         assigned-clock-parents = <&k3_clks 157 8>;
  69                         #clock-cells = <0>;
  70                 };
  71
  72                 audio_refclk1: clock-controller@82e4 {
  73                         compatible = "ti,am62-audio-refclk";
  74                         reg = <0x82e4 0x4>;
  75                         clocks = <&k3_clks 157 10>;
  76                         assigned-clocks = <&k3_clks 157 10>;
  77                         assigned-clock-parents = <&k3_clks 157 18>;
  78                         #clock-cells = <0>;
  79                 };
  80         };
  81
  82         dmss: bus@48000000 {
  83                 bootph-all;
  84                 compatible = "simple-bus";
  85                 #address-cells = <2>;
  86                 #size-cells = <2>;
  87                 dma-ranges;
  88                 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
  89
  90                 ti,sci-dev-id = <25>;
  91
  92                 secure_proxy_main: mailbox@4d000000 {
  93                         bootph-all;
  94                         compatible = "ti,am654-secure-proxy";
  95                         #mbox-cells = <1>;
  96                         reg-names = "target_data", "rt", "scfg";
  97                         reg = <0x00 0x4d000000 0x00 0x80000>,
  98                               <0x00 0x4a600000 0x00 0x80000>,
  99                               <0x00 0x4a400000 0x00 0x80000>;
 100                         interrupt-names = "rx_012";
 101                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 102                 };
 103
 104                 inta_main_dmss: interrupt-controller@48000000 {
 105                         compatible = "ti,sci-inta";
 106                         reg = <0x00 0x48000000 0x00 0x100000>;
 107                         #interrupt-cells = <0>;
 108                         interrupt-controller;
 109                         interrupt-parent = <&gic500>;
 110                         msi-controller;
 111                         ti,sci = <&dmsc>;
 112                         ti,sci-dev-id = <28>;
 113                         ti,interrupt-ranges = <4 68 36>;
 114                         ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
 115                 };
 116
 117                 main_bcdma: dma-controller@485c0100 {
 118                         compatible = "ti,am64-dmss-bcdma";
 119                         reg = <0x00 0x485c0100 0x00 0x100>,
 120                               <0x00 0x4c000000 0x00 0x20000>,
 121                               <0x00 0x4a820000 0x00 0x20000>,
 122                               <0x00 0x4aa40000 0x00 0x20000>,
 123                               <0x00 0x4bc00000 0x00 0x100000>,
 124                               <0x00 0x48600000 0x00 0x8000>,
 125                               <0x00 0x484a4000 0x00 0x2000>,
 126                               <0x00 0x484c2000 0x00 0x2000>,
 127                               <0x00 0x48420000 0x00 0x2000>;
 128                         reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
 129                                     "ring", "tchan", "rchan", "bchan";
 130                         msi-parent = <&inta_main_dmss>;
 131                         #dma-cells = <3>;
 132
 133                         ti,sci = <&dmsc>;
 134                         ti,sci-dev-id = <26>;
 135                         ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
 136                         ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
 137                         ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
 138                 };
 139
 140                 main_pktdma: dma-controller@485c0000 {
 141                         compatible = "ti,am64-dmss-pktdma";
 142                         reg = <0x00 0x485c0000 0x00 0x100>,
 143                               <0x00 0x4a800000 0x00 0x20000>,
 144                               <0x00 0x4aa00000 0x00 0x40000>,
 145                               <0x00 0x4b800000 0x00 0x400000>,
 146                               <0x00 0x485e0000 0x00 0x10000>,
 147                               <0x00 0x484a0000 0x00 0x2000>,
 148                               <0x00 0x484c0000 0x00 0x2000>,
 149                               <0x00 0x48430000 0x00 0x1000>;
 150                         reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
 151                                     "ring", "tchan", "rchan", "rflow";
 152                         msi-parent = <&inta_main_dmss>;
 153                         #dma-cells = <2>;
 154
 155                         ti,sci = <&dmsc>;
 156                         ti,sci-dev-id = <30>;
 157                         ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
 158                                                 <0x24>, /* CPSW_TX_CHAN */
 159                                                 <0x25>, /* SAUL_TX_0_CHAN */
 160                                                 <0x26>; /* SAUL_TX_1_CHAN */
 161                         ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
 162                                                 <0x11>, /* RING_CPSW_TX_CHAN */
 163                                                 <0x12>, /* RING_SAUL_TX_0_CHAN */
 164                                                 <0x13>; /* RING_SAUL_TX_1_CHAN */
 165                         ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
 166                                                 <0x2b>, /* CPSW_RX_CHAN */
 167                                                 <0x2d>, /* SAUL_RX_0_CHAN */
 168                                                 <0x2f>, /* SAUL_RX_1_CHAN */
 169                                                 <0x31>, /* SAUL_RX_2_CHAN */
 170                                                 <0x33>; /* SAUL_RX_3_CHAN */
 171                         ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
 172                                                 <0x2c>, /* FLOW_CPSW_RX_CHAN */
 173                                                 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
 174                                                 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
 175                 };
 176         };
 177
 178         dmsc: system-controller@44043000 {
 179                 bootph-all;
 180                 compatible = "ti,k2g-sci";
 181                 ti,host-id = <12>;
 182                 mbox-names = "rx", "tx";
 183                 mboxes = <&secure_proxy_main 12>,
 184                          <&secure_proxy_main 13>;
 185                 reg-names = "debug_messages";
 186                 reg = <0x00 0x44043000 0x00 0xfe0>;
 187
 188                 k3_pds: power-controller {
 189                         bootph-all;
 190                         compatible = "ti,sci-pm-domain";
 191                         #power-domain-cells = <2>;
 192                 };
 193
 194                 k3_clks: clock-controller {
 195                         bootph-all;
 196                         compatible = "ti,k2g-sci-clk";
 197                         #clock-cells = <2>;
 198                 };
 199
 200                 k3_reset: reset-controller {
 201                         bootph-all;
 202                         compatible = "ti,sci-reset";
 203                         #reset-cells = <2>;
 204                 };
 205         };
 206
 207         crypto: crypto@40900000 {
 208                 compatible = "ti,am62-sa3ul";
 209                 reg = <0x00 0x40900000 0x00 0x1200>;
 210                 #address-cells = <2>;
 211                 #size-cells = <2>;
 212                 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
 213
 214                 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
 215                        <&main_pktdma 0x7507 0>;
 216                 dma-names = "tx", "rx1", "rx2";
 217         };
 218
 219         secure_proxy_sa3: mailbox@43600000 {
 220                 bootph-pre-ram;
 221                 compatible = "ti,am654-secure-proxy";
 222                 #mbox-cells = <1>;
 223                 reg-names = "target_data", "rt", "scfg";
 224                 reg = <0x00 0x43600000 0x00 0x10000>,
 225                       <0x00 0x44880000 0x00 0x20000>,
 226                       <0x00 0x44860000 0x00 0x20000>;
 227                 /*
 228                  * Marked Disabled:
 229                  * Node is incomplete as it is meant for bootloaders and
 230                  * firmware on non-MPU processors
 231                  */
 232                 status = "disabled";
 233         };
 234
 235         main_pmx0: pinctrl@f4000 {
 236                 bootph-all;
 237                 compatible = "pinctrl-single";
 238                 reg = <0x00 0xf4000 0x00 0x2ac>;
 239                 #pinctrl-cells = <1>;
 240                 pinctrl-single,register-width = <32>;
 241                 pinctrl-single,function-mask = <0xffffffff>;
 242         };
 243
 244         main_esm: esm@420000 {
 245                 bootph-pre-ram;
 246                 compatible = "ti,j721e-esm";
 247                 reg = <0x00 0x420000 0x00 0x1000>;
 248                 ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
 249         };
 250
 251         main_timer0: timer@2400000 {
 252                 bootph-all;
 253                 compatible = "ti,am654-timer";
 254                 reg = <0x00 0x2400000 0x00 0x400>;
 255                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 256                 clocks = <&k3_clks 36 2>;
 257                 clock-names = "fck";
 258                 assigned-clocks = <&k3_clks 36 2>;
 259                 assigned-clock-parents = <&k3_clks 36 3>;
 260                 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
 261                 ti,timer-pwm;
 262         };
 263
 264         main_timer1: timer@2410000 {
 265                 compatible = "ti,am654-timer";
 266                 reg = <0x00 0x2410000 0x00 0x400>;
 267                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 268                 clocks = <&k3_clks 37 2>;
 269                 clock-names = "fck";
 270                 assigned-clocks = <&k3_clks 37 2>;
 271                 assigned-clock-parents = <&k3_clks 37 3>;
 272                 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
 273                 ti,timer-pwm;
 274         };
 275
 276         main_timer2: timer@2420000 {
 277                 compatible = "ti,am654-timer";
 278                 reg = <0x00 0x2420000 0x00 0x400>;
 279                 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 280                 clocks = <&k3_clks 38 2>;
 281                 clock-names = "fck";
 282                 assigned-clocks = <&k3_clks 38 2>;
 283                 assigned-clock-parents = <&k3_clks 38 3>;
 284                 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
 285                 ti,timer-pwm;
 286         };
 287
 288         main_timer3: timer@2430000 {
 289                 compatible = "ti,am654-timer";
 290                 reg = <0x00 0x2430000 0x00 0x400>;
 291                 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 292                 clocks = <&k3_clks 39 2>;
 293                 clock-names = "fck";
 294                 assigned-clocks = <&k3_clks 39 2>;
 295                 assigned-clock-parents = <&k3_clks 39 3>;
 296                 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
 297                 ti,timer-pwm;
 298         };
 299
 300         main_timer4: timer@2440000 {
 301                 compatible = "ti,am654-timer";
 302                 reg = <0x00 0x2440000 0x00 0x400>;
 303                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 304                 clocks = <&k3_clks 40 2>;
 305                 clock-names = "fck";
 306                 assigned-clocks = <&k3_clks 40 2>;
 307                 assigned-clock-parents = <&k3_clks 40 3>;
 308                 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
 309                 ti,timer-pwm;
 310         };
 311
 312         main_timer5: timer@2450000 {
 313                 compatible = "ti,am654-timer";
 314                 reg = <0x00 0x2450000 0x00 0x400>;
 315                 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 316                 clocks = <&k3_clks 41 2>;
 317                 clock-names = "fck";
 318                 assigned-clocks = <&k3_clks 41 2>;
 319                 assigned-clock-parents = <&k3_clks 41 3>;
 320                 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
 321                 ti,timer-pwm;
 322         };
 323
 324         main_timer6: timer@2460000 {
 325                 compatible = "ti,am654-timer";
 326                 reg = <0x00 0x2460000 0x00 0x400>;
 327                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 328                 clocks = <&k3_clks 42 2>;
 329                 clock-names = "fck";
 330                 assigned-clocks = <&k3_clks 42 2>;
 331                 assigned-clock-parents = <&k3_clks 42 3>;
 332                 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
 333                 ti,timer-pwm;
 334         };
 335
 336         main_timer7: timer@2470000 {
 337                 compatible = "ti,am654-timer";
 338                 reg = <0x00 0x2470000 0x00 0x400>;
 339                 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 340                 clocks = <&k3_clks 43 2>;
 341                 clock-names = "fck";
 342                 assigned-clocks = <&k3_clks 43 2>;
 343                 assigned-clock-parents = <&k3_clks 43 3>;
 344                 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
 345                 ti,timer-pwm;
 346         };
 347
 348         main_uart0: serial@2800000 {
 349                 compatible = "ti,am64-uart", "ti,am654-uart";
 350                 reg = <0x00 0x02800000 0x00 0x100>;
 351                 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 352                 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
 353                 clocks = <&k3_clks 146 0>;
 354                 clock-names = "fclk";
 355                 status = "disabled";
 356         };
 357
 358         main_uart1: serial@2810000 {
 359                 compatible = "ti,am64-uart", "ti,am654-uart";
 360                 reg = <0x00 0x02810000 0x00 0x100>;
 361                 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 362                 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
 363                 clocks = <&k3_clks 152 0>;
 364                 clock-names = "fclk";
 365                 status = "disabled";
 366         };
 367
 368         main_uart2: serial@2820000 {
 369                 compatible = "ti,am64-uart", "ti,am654-uart";
 370                 reg = <0x00 0x02820000 0x00 0x100>;
 371                 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 372                 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
 373                 clocks = <&k3_clks 153 0>;
 374                 clock-names = "fclk";
 375                 status = "disabled";
 376         };
 377
 378         main_uart3: serial@2830000 {
 379                 compatible = "ti,am64-uart", "ti,am654-uart";
 380                 reg = <0x00 0x02830000 0x00 0x100>;
 381                 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
 382                 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
 383                 clocks = <&k3_clks 154 0>;
 384                 clock-names = "fclk";
 385                 status = "disabled";
 386         };
 387
 388         main_uart4: serial@2840000 {
 389                 compatible = "ti,am64-uart", "ti,am654-uart";
 390                 reg = <0x00 0x02840000 0x00 0x100>;
 391                 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
 392                 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
 393                 clocks = <&k3_clks 155 0>;
 394                 clock-names = "fclk";
 395                 status = "disabled";
 396         };
 397
 398         main_uart5: serial@2850000 {
 399                 compatible = "ti,am64-uart", "ti,am654-uart";
 400                 reg = <0x00 0x02850000 0x00 0x100>;
 401                 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
 402                 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
 403                 clocks = <&k3_clks 156 0>;
 404                 clock-names = "fclk";
 405                 status = "disabled";
 406         };
 407
 408         main_uart6: serial@2860000 {
 409                 compatible = "ti,am64-uart", "ti,am654-uart";
 410                 reg = <0x00 0x02860000 0x00 0x100>;
 411                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 412                 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
 413                 clocks = <&k3_clks 158 0>;
 414                 clock-names = "fclk";
 415                 status = "disabled";
 416         };
 417
 418         main_i2c0: i2c@20000000 {
 419                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
 420                 reg = <0x00 0x20000000 0x00 0x100>;
 421                 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 422                 #address-cells = <1>;
 423                 #size-cells = <0>;
 424                 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
 425                 clocks = <&k3_clks 102 2>;
 426                 clock-names = "fck";
 427                 status = "disabled";
 428         };
 429
 430         main_i2c1: i2c@20010000 {
 431                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
 432                 reg = <0x00 0x20010000 0x00 0x100>;
 433                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 434                 #address-cells = <1>;
 435                 #size-cells = <0>;
 436                 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
 437                 clocks = <&k3_clks 103 2>;
 438                 clock-names = "fck";
 439                 status = "disabled";
 440         };
 441
 442         main_i2c2: i2c@20020000 {
 443                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
 444                 reg = <0x00 0x20020000 0x00 0x100>;
 445                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 446                 #address-cells = <1>;
 447                 #size-cells = <0>;
 448                 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
 449                 clocks = <&k3_clks 104 2>;
 450                 clock-names = "fck";
 451                 status = "disabled";
 452         };
 453
 454         main_i2c3: i2c@20030000 {
 455                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
 456                 reg = <0x00 0x20030000 0x00 0x100>;
 457                 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 458                 #address-cells = <1>;
 459                 #size-cells = <0>;
 460                 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
 461                 clocks = <&k3_clks 105 2>;
 462                 clock-names = "fck";
 463                 status = "disabled";
 464         };
 465
 466         main_spi0: spi@20100000 {
 467                 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
 468                 reg = <0x00 0x20100000 0x00 0x400>;
 469                 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 470                 #address-cells = <1>;
 471                 #size-cells = <0>;
 472                 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
 473                 clocks = <&k3_clks 141 0>;
 474                 status = "disabled";
 475         };
 476
 477         main_spi1: spi@20110000 {
 478                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 479                 reg = <0x00 0x20110000 0x00 0x400>;
 480                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 481                 #address-cells = <1>;
 482                 #size-cells = <0>;
 483                 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
 484                 clocks = <&k3_clks 142 0>;
 485                 status = "disabled";
 486         };
 487
 488         main_spi2: spi@20120000 {
 489                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 490                 reg = <0x00 0x20120000 0x00 0x400>;
 491                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 492                 #address-cells = <1>;
 493                 #size-cells = <0>;
 494                 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
 495                 clocks = <&k3_clks 143 0>;
 496                 status = "disabled";
 497         };
 498
 499         main_gpio_intr: interrupt-controller@a00000 {
 500                 compatible = "ti,sci-intr";
 501                 reg = <0x00 0x00a00000 0x00 0x800>;
 502                 ti,intr-trigger-type = <1>;
 503                 interrupt-controller;
 504                 interrupt-parent = <&gic500>;
 505                 #interrupt-cells = <1>;
 506                 ti,sci = <&dmsc>;
 507                 ti,sci-dev-id = <3>;
 508                 ti,interrupt-ranges = <0 32 16>;
 509         };
 510
 511         main_gpio0: gpio@600000 {
 512                 compatible = "ti,am64-gpio", "ti,keystone-gpio";
 513                 reg = <0x0 0x00600000 0x0 0x100>;
 514                 gpio-ranges = <&main_pmx0  0  0 32>,
 515                               <&main_pmx0 32 33 38>,
 516                               <&main_pmx0 70 72 22>;
 517                 gpio-controller;
 518                 #gpio-cells = <2>;
 519                 interrupt-parent = <&main_gpio_intr>;
 520                 interrupts = <190>, <191>, <192>,
 521                              <193>, <194>, <195>;
 522                 interrupt-controller;
 523                 #interrupt-cells = <2>;
 524                 ti,ngpio = <92>;
 525                 ti,davinci-gpio-unbanked = <0>;
 526                 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
 527                 clocks = <&k3_clks 77 0>;
 528                 clock-names = "gpio";
 529         };
 530
 531         main_gpio1: gpio@601000 {
 532                 compatible = "ti,am64-gpio", "ti,keystone-gpio";
 533                 reg = <0x0 0x00601000 0x0 0x100>;
 534                 gpio-controller;
 535                 gpio-ranges = <&main_pmx0  0  94 41>,
 536                               <&main_pmx0 41 136  6>,
 537                               <&main_pmx0 47 143  3>,
 538                               <&main_pmx0 50 149  2>;
 539                 #gpio-cells = <2>;
 540                 interrupt-parent = <&main_gpio_intr>;
 541                 interrupts = <180>, <181>, <182>,
 542                              <183>, <184>, <185>;
 543                 interrupt-controller;
 544                 #interrupt-cells = <2>;
 545                 ti,ngpio = <52>;
 546                 ti,davinci-gpio-unbanked = <0>;
 547                 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
 548                 clocks = <&k3_clks 78 0>;
 549                 clock-names = "gpio";
 550         };
 551
 552         sdhci0: mmc@fa10000 {
 553                 compatible = "ti,am62-sdhci";
 554                 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
 555                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 556                 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
 557                 clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
 558                 clock-names = "clk_ahb", "clk_xin";
 559                 assigned-clocks = <&k3_clks 57 6>;
 560                 assigned-clock-parents = <&k3_clks 57 8>;
 561                 bus-width = <8>;
 562                 mmc-ddr-1_8v;
 563                 mmc-hs200-1_8v;
 564                 ti,clkbuf-sel = <0x7>;
 565                 ti,otap-del-sel-legacy = <0x0>;
 566                 ti,otap-del-sel-mmc-hs = <0x0>;
 567                 ti,otap-del-sel-ddr52 = <0x5>;
 568                 ti,otap-del-sel-hs200 = <0x5>;
 569                 ti,itap-del-sel-legacy = <0xa>;
 570                 ti,itap-del-sel-mmc-hs = <0x1>;
 571                 status = "disabled";
 572         };
 573
 574         sdhci1: mmc@fa00000 {
 575                 compatible = "ti,am62-sdhci";
 576                 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
 577                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 578                 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
 579                 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
 580                 clock-names = "clk_ahb", "clk_xin";
 581                 bus-width = <4>;
 582                 ti,clkbuf-sel = <0x7>;
 583                 ti,otap-del-sel-legacy = <0x8>;
 584                 ti,otap-del-sel-sd-hs = <0x0>;
 585                 ti,otap-del-sel-sdr12 = <0x0>;
 586                 ti,otap-del-sel-sdr25 = <0x0>;
 587                 ti,otap-del-sel-sdr50 = <0x8>;
 588                 ti,otap-del-sel-sdr104 = <0x7>;
 589                 ti,otap-del-sel-ddr50 = <0x4>;
 590                 ti,itap-del-sel-legacy = <0xa>;
 591                 ti,itap-del-sel-sd-hs = <0x1>;
 592                 ti,itap-del-sel-sdr12 = <0xa>;
 593                 ti,itap-del-sel-sdr25 = <0x1>;
 594                 status = "disabled";
 595         };
 596
 597         sdhci2: mmc@fa20000 {
 598                 compatible = "ti,am62-sdhci";
 599                 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
 600                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 601                 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
 602                 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
 603                 clock-names = "clk_ahb", "clk_xin";
 604                 bus-width = <4>;
 605                 ti,clkbuf-sel = <0x7>;
 606                 ti,otap-del-sel-legacy = <0x8>;
 607                 ti,otap-del-sel-sd-hs = <0x0>;
 608                 ti,otap-del-sel-sdr12 = <0x0>;
 609                 ti,otap-del-sel-sdr25 = <0x0>;
 610                 ti,otap-del-sel-sdr50 = <0x8>;
 611                 ti,otap-del-sel-sdr104 = <0x7>;
 612                 ti,otap-del-sel-ddr50 = <0x8>;
 613                 ti,itap-del-sel-legacy = <0xa>;
 614                 ti,itap-del-sel-sd-hs = <0xa>;
 615                 ti,itap-del-sel-sdr12 = <0xa>;
 616                 ti,itap-del-sel-sdr25 = <0x1>;
 617                 status = "disabled";
 618         };
 619
 620         usbss0: dwc3-usb@f900000 {
 621                 compatible = "ti,am62-usb";
 622                 reg = <0x00 0x0f900000 0x00 0x800>;
 623                 clocks = <&k3_clks 161 3>;
 624                 clock-names = "ref";
 625                 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
 626                 #address-cells = <2>;
 627                 #size-cells = <2>;
 628                 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
 629                 ranges;
 630                 status = "disabled";
 631
 632                 usb0: usb@31000000 {
 633                         compatible = "snps,dwc3";
 634                         reg = <0x00 0x31000000 0x00 0x50000>;
 635                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
 636                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
 637                         interrupt-names = "host", "peripheral";
 638                         maximum-speed = "high-speed";
 639                         dr_mode = "otg";
 640                         snps,usb2-gadget-lpm-disable;
 641                         snps,usb2-lpm-disable;
 642                 };
 643         };
 644
 645         usbss1: dwc3-usb@f910000 {
 646                 compatible = "ti,am62-usb";
 647                 reg = <0x00 0x0f910000 0x00 0x800>;
 648                 clocks = <&k3_clks 162 3>;
 649                 clock-names = "ref";
 650                 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
 651                 #address-cells = <2>;
 652                 #size-cells = <2>;
 653                 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
 654                 ranges;
 655                 status = "disabled";
 656
 657                 usb1: usb@31100000 {
 658                         compatible = "snps,dwc3";
 659                         reg = <0x00 0x31100000 0x00 0x50000>;
 660                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
 661                                      <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
 662                         interrupt-names = "host", "peripheral";
 663                         maximum-speed = "high-speed";
 664                         dr_mode = "otg";
 665                         snps,usb2-gadget-lpm-disable;
 666                         snps,usb2-lpm-disable;
 667                 };
 668         };
 669
 670         fss: bus@fc00000 {
 671                 compatible = "simple-bus";
 672                 reg = <0x00 0x0fc00000 0x00 0x70000>;
 673                 #address-cells = <2>;
 674                 #size-cells = <2>;
 675                 ranges;
 676
 677                 ospi0: spi@fc40000 {
 678                         compatible = "ti,am654-ospi", "cdns,qspi-nor";
 679                         reg = <0x00 0x0fc40000 0x00 0x100>,
 680                               <0x05 0x00000000 0x01 0x00000000>;
 681                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 682                         cdns,fifo-depth = <256>;
 683                         cdns,fifo-width = <4>;
 684                         cdns,trigger-address = <0x0>;
 685                         clocks = <&k3_clks 75 7>;
 686                         assigned-clocks = <&k3_clks 75 7>;
 687                         assigned-clock-parents = <&k3_clks 75 8>;
 688                         assigned-clock-rates = <166666666>;
 689                         power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
 690                         #address-cells = <1>;
 691                         #size-cells = <0>;
 692                         status = "disabled";
 693                 };
 694         };
 695
 696         gpu: gpu@fd00000 {
 697                 compatible = "ti,am62-gpu", "img,img-axe";
 698                 reg = <0x00 0x0fd00000 0x00 0x20000>;
 699                 clocks = <&k3_clks 187 0>;
 700                 clock-names = "core";
 701                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 702                 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
 703         };
 704
 705         cpsw3g: ethernet@8000000 {
 706                 compatible = "ti,am642-cpsw-nuss";
 707                 #address-cells = <2>;
 708                 #size-cells = <2>;
 709                 reg = <0x00 0x08000000 0x00 0x200000>;
 710                 reg-names = "cpsw_nuss";
 711                 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
 712                 clocks = <&k3_clks 13 0>;
 713                 assigned-clocks = <&k3_clks 13 3>;
 714                 assigned-clock-parents = <&k3_clks 13 11>;
 715                 clock-names = "fck";
 716                 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
 717
 718                 dmas = <&main_pktdma 0xc600 15>,
 719                        <&main_pktdma 0xc601 15>,
 720                        <&main_pktdma 0xc602 15>,
 721                        <&main_pktdma 0xc603 15>,
 722                        <&main_pktdma 0xc604 15>,
 723                        <&main_pktdma 0xc605 15>,
 724                        <&main_pktdma 0xc606 15>,
 725                        <&main_pktdma 0xc607 15>,
 726                        <&main_pktdma 0x4600 15>;
 727                 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
 728                             "tx7", "rx";
 729
 730                 ethernet-ports {
 731                         #address-cells = <1>;
 732                         #size-cells = <0>;
 733
 734                         cpsw_port1: port@1 {
 735                                 reg = <1>;
 736                                 ti,mac-only;
 737                                 label = "port1";
 738                                 phys = <&phy_gmii_sel 1>;
 739                                 mac-address = [00 00 00 00 00 00];
 740                                 ti,syscon-efuse = <&wkup_conf 0x200>;
 741                         };
 742
 743                         cpsw_port2: port@2 {
 744                                 reg = <2>;
 745                                 ti,mac-only;
 746                                 label = "port2";
 747                                 phys = <&phy_gmii_sel 2>;
 748                                 mac-address = [00 00 00 00 00 00];
 749                         };
 750                 };
 751
 752                 cpsw3g_mdio: mdio@f00 {
 753                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 754                         reg = <0x00 0xf00 0x00 0x100>;
 755                         #address-cells = <1>;
 756                         #size-cells = <0>;
 757                         clocks = <&k3_clks 13 0>;
 758                         clock-names = "fck";
 759                         bus_freq = <1000000>;
 760                         status = "disabled";
 761                 };
 762
 763                 cpts@3d000 {
 764                         compatible = "ti,j721e-cpts";
 765                         reg = <0x00 0x3d000 0x00 0x400>;
 766                         clocks = <&k3_clks 13 3>;
 767                         clock-names = "cpts";
 768                         interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 769                         interrupt-names = "cpts";
 770                         ti,cpts-ext-ts-inputs = <4>;
 771                         ti,cpts-periodic-outputs = <2>;
 772                 };
 773         };
 774
 775         dss: dss@30200000 {
 776                 compatible = "ti,am625-dss";
 777                 reg = <0x00 0x30200000 0x00 0x1000>, /* common */
 778                       <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
 779                       <0x00 0x30206000 0x00 0x1000>, /* vid */
 780                       <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
 781                       <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
 782                       <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */
 783                       <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */
 784                       <0x00 0x30201000 0x00 0x1000>; /* common1 */
 785                 reg-names = "common", "vidl1", "vid",
 786                             "ovr1", "ovr2", "vp1", "vp2", "common1";
 787                 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
 788                 clocks = <&k3_clks 186 6>,
 789                          <&dss_vp1_clk>,
 790                          <&k3_clks 186 2>;
 791                 clock-names = "fck", "vp1", "vp2";
 792                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 793                 status = "disabled";
 794
 795                 dss_ports: ports {
 796                         #address-cells = <1>;
 797                         #size-cells = <0>;
 798                 };
 799         };
 800
 801         hwspinlock: spinlock@2a000000 {
 802                 compatible = "ti,am64-hwspinlock";
 803                 reg = <0x00 0x2a000000 0x00 0x1000>;
 804                 #hwlock-cells = <1>;
 805         };
 806
 807         mailbox0_cluster0: mailbox@29000000 {
 808                 compatible = "ti,am64-mailbox";
 809                 reg = <0x00 0x29000000 0x00 0x200>;
 810                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 811                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 812                 #mbox-cells = <1>;
 813                 ti,mbox-num-users = <4>;
 814                 ti,mbox-num-fifos = <16>;
 815         };
 816
 817         ecap0: pwm@23100000 {
 818                 compatible = "ti,am3352-ecap";
 819                 #pwm-cells = <3>;
 820                 reg = <0x00 0x23100000 0x00 0x100>;
 821                 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
 822                 clocks = <&k3_clks 51 0>;
 823                 clock-names = "fck";
 824                 status = "disabled";
 825         };
 826
 827         ecap1: pwm@23110000 {
 828                 compatible = "ti,am3352-ecap";
 829                 #pwm-cells = <3>;
 830                 reg = <0x00 0x23110000 0x00 0x100>;
 831                 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
 832                 clocks = <&k3_clks 52 0>;
 833                 clock-names = "fck";
 834                 status = "disabled";
 835         };
 836
 837         ecap2: pwm@23120000 {
 838                 compatible = "ti,am3352-ecap";
 839                 #pwm-cells = <3>;
 840                 reg = <0x00 0x23120000 0x00 0x100>;
 841                 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
 842                 clocks = <&k3_clks 53 0>;
 843                 clock-names = "fck";
 844                 status = "disabled";
 845         };
 846
 847         main_mcan0: can@20701000 {
 848                 compatible = "bosch,m_can";
 849                 reg = <0x00 0x20701000 0x00 0x200>,
 850                       <0x00 0x20708000 0x00 0x8000>;
 851                 reg-names = "m_can", "message_ram";
 852                 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
 853                 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
 854                 clock-names = "hclk", "cclk";
 855                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 856                              <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 857                 interrupt-names = "int0", "int1";
 858                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 859                 status = "disabled";
 860         };
 861
 862         main_rti0: watchdog@e000000 {
 863                 compatible = "ti,j7-rti-wdt";
 864                 reg = <0x00 0x0e000000 0x00 0x100>;
 865                 clocks = <&k3_clks 125 0>;
 866                 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
 867                 assigned-clocks = <&k3_clks 125 0>;
 868                 assigned-clock-parents = <&k3_clks 125 2>;
 869         };
 870
 871         main_rti1: watchdog@e010000 {
 872                 compatible = "ti,j7-rti-wdt";
 873                 reg = <0x00 0x0e010000 0x00 0x100>;
 874                 clocks = <&k3_clks 126 0>;
 875                 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
 876                 assigned-clocks = <&k3_clks 126 0>;
 877                 assigned-clock-parents = <&k3_clks 126 2>;
 878         };
 879
 880         main_rti2: watchdog@e020000 {
 881                 compatible = "ti,j7-rti-wdt";
 882                 reg = <0x00 0x0e020000 0x00 0x100>;
 883                 clocks = <&k3_clks 127 0>;
 884                 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
 885                 assigned-clocks = <&k3_clks 127 0>;
 886                 assigned-clock-parents = <&k3_clks 127 2>;
 887         };
 888
 889         main_rti3: watchdog@e030000 {
 890                 compatible = "ti,j7-rti-wdt";
 891                 reg = <0x00 0x0e030000 0x00 0x100>;
 892                 clocks = <&k3_clks 128 0>;
 893                 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
 894                 assigned-clocks = <&k3_clks 128 0>;
 895                 assigned-clock-parents = <&k3_clks 128 2>;
 896         };
 897
 898         main_rti15: watchdog@e0f0000 {
 899                 compatible = "ti,j7-rti-wdt";
 900                 reg = <0x00 0x0e0f0000 0x00 0x100>;
 901                 clocks = <&k3_clks 130 0>;
 902                 power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>;
 903                 assigned-clocks = <&k3_clks 130 0>;
 904                 assigned-clock-parents = <&k3_clks 130 2>;
 905         };
 906
 907         epwm0: pwm@23000000 {
 908                 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
 909                 #pwm-cells = <3>;
 910                 reg = <0x00 0x23000000 0x00 0x100>;
 911                 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
 912                 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
 913                 clock-names = "tbclk", "fck";
 914                 status = "disabled";
 915         };
 916
 917         epwm1: pwm@23010000 {
 918                 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
 919                 #pwm-cells = <3>;
 920                 reg = <0x00 0x23010000 0x00 0x100>;
 921                 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
 922                 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
 923                 clock-names = "tbclk", "fck";
 924                 status = "disabled";
 925         };
 926
 927         epwm2: pwm@23020000 {
 928                 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
 929                 #pwm-cells = <3>;
 930                 reg = <0x00 0x23020000 0x00 0x100>;
 931                 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
 932                 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
 933                 clock-names = "tbclk", "fck";
 934                 status = "disabled";
 935         };
 936
 937         mcasp0: audio-controller@2b00000 {
 938                 compatible = "ti,am33xx-mcasp-audio";
 939                 reg = <0x00 0x02b00000 0x00 0x2000>,
 940                       <0x00 0x02b08000 0x00 0x400>;
 941                 reg-names = "mpu", "dat";
 942                 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
 943                              <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
 944                 interrupt-names = "tx", "rx";
 945
 946                 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
 947                 dma-names = "tx", "rx";
 948
 949                 clocks = <&k3_clks 190 0>;
 950                 clock-names = "fck";
 951                 assigned-clocks = <&k3_clks 190 0>;
 952                 assigned-clock-parents = <&k3_clks 190 2>;
 953                 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
 954                 status = "disabled";
 955         };
 956
 957         mcasp1: audio-controller@2b10000 {
 958                 compatible = "ti,am33xx-mcasp-audio";
 959                 reg = <0x00 0x02b10000 0x00 0x2000>,
 960                       <0x00 0x02b18000 0x00 0x400>;
 961                 reg-names = "mpu", "dat";
 962                 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 963                              <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
 964                 interrupt-names = "tx", "rx";
 965
 966                 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
 967                 dma-names = "tx", "rx";
 968
 969                 clocks = <&k3_clks 191 0>;
 970                 clock-names = "fck";
 971                 assigned-clocks = <&k3_clks 191 0>;
 972                 assigned-clock-parents = <&k3_clks 191 2>;
 973                 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
 974                 status = "disabled";
 975         };
 976
 977         mcasp2: audio-controller@2b20000 {
 978                 compatible = "ti,am33xx-mcasp-audio";
 979                 reg = <0x00 0x02b20000 0x00 0x2000>,
 980                       <0x00 0x02b28000 0x00 0x400>;
 981                 reg-names = "mpu", "dat";
 982                 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
 983                              <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 984                 interrupt-names = "tx", "rx";
 985
 986                 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
 987                 dma-names = "tx", "rx";
 988
 989                 clocks = <&k3_clks 192 0>;
 990                 clock-names = "fck";
 991                 assigned-clocks = <&k3_clks 192 0>;
 992                 assigned-clock-parents = <&k3_clks 192 2>;
 993                 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
 994                 status = "disabled";
 995         };
 996
 997         ti_csi2rx0: ticsi2rx@30102000 {
 998                 compatible = "ti,j721e-csi2rx-shim";
 999                 dmas = <&main_bcdma 0 0x4700 0>;
1000                 dma-names = "rx0";
1001                 reg = <0x00 0x30102000 0x00 0x1000>;
1002                 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1003                 #address-cells = <2>;
1004                 #size-cells = <2>;
1005                 ranges;
1006                 status = "disabled";
1007
1008                 cdns_csi2rx0: csi-bridge@30101000 {
1009                         compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
1010                         reg = <0x00 0x30101000 0x00 0x1000>;
1011                         clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
1012                                 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
1013                         clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
1014                                 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
1015                         phys = <&dphy0>;
1016                         phy-names = "dphy";
1017
1018                         ports {
1019                                 #address-cells = <1>;
1020                                 #size-cells = <0>;
1021
1022                                 csi0_port0: port@0 {
1023                                         reg = <0>;
1024                                         status = "disabled";
1025                                 };
1026
1027                                 csi0_port1: port@1 {
1028                                         reg = <1>;
1029                                         status = "disabled";
1030                                 };
1031
1032                                 csi0_port2: port@2 {
1033                                         reg = <2>;
1034                                         status = "disabled";
1035                                 };
1036
1037                                 csi0_port3: port@3 {
1038                                         reg = <3>;
1039                                         status = "disabled";
1040                                 };
1041
1042                                 csi0_port4: port@4 {
1043                                         reg = <4>;
1044                                         status = "disabled";
1045                                 };
1046                         };
1047                 };
1048         };
1049
1050         dphy0: phy@30110000 {
1051                 compatible = "cdns,dphy-rx";
1052                 reg = <0x00 0x30110000 0x00 0x1100>;
1053                 #phy-cells = <0>;
1054                 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1055                 status = "disabled";
1056         };
1057
1058 };