arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
   2 /*
   3  * Device Tree Source for J721S2 SoC Family Main Domain peripherals
   4  *
   5  * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 #include <dt-bindings/phy/phy-cadence.h>
   9 #include <dt-bindings/phy/phy-ti.h>
  10
  11 / {
  12         serdes_refclk: clock-cmnrefclk {
  13                 #clock-cells = <0>;
  14                 compatible = "fixed-clock";
  15                 clock-frequency = <0>;
  16         };
  17 };
  18
  19 &cbass_main {
  20         msmc_ram: sram@70000000 {
  21                 compatible = "mmio-sram";
  22                 reg = <0x0 0x70000000 0x0 0x400000>;
  23                 #address-cells = <1>;
  24                 #size-cells = <1>;
  25                 ranges = <0x0 0x0 0x70000000 0x400000>;
  26
  27                 atf-sram@0 {
  28                         reg = <0x0 0x20000>;
  29                 };
  30
  31                 tifs-sram@1f0000 {
  32                         reg = <0x1f0000 0x10000>;
  33                 };
  34
  35                 l3cache-sram@200000 {
  36                         reg = <0x200000 0x200000>;
  37                 };
  38         };
  39
  40         scm_conf: syscon@104000 {
  41                 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
  42                 reg = <0x00 0x00104000 0x00 0x18000>;
  43                 #address-cells = <1>;
  44                 #size-cells = <1>;
  45                 ranges = <0x00 0x00 0x00104000 0x18000>;
  46
  47                 usb_serdes_mux: mux-controller@0 {
  48                         compatible = "reg-mux";
  49                         reg = <0x0 0x4>;
  50                         #mux-control-cells = <1>;
  51                         mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
  52                 };
  53
  54                 phy_gmii_sel_cpsw: phy@34 {
  55                         compatible = "ti,am654-phy-gmii-sel";
  56                         reg = <0x34 0x4>;
  57                         #phy-cells = <1>;
  58                 };
  59
  60                 serdes_ln_ctrl: mux-controller@80 {
  61                         compatible = "reg-mux";
  62                         reg = <0x80 0x10>;
  63                         #mux-control-cells = <1>;
  64                         mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
  65                                         <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */
  66                 };
  67
  68                 ehrpwm_tbclk: clock-controller@140 {
  69                         compatible = "ti,am654-ehrpwm-tbclk";
  70                         reg = <0x140 0x18>;
  71                         #clock-cells = <1>;
  72                 };
  73         };
  74
  75         main_ehrpwm0: pwm@3000000 {
  76                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
  77                 #pwm-cells = <3>;
  78                 reg = <0x00 0x3000000 0x00 0x100>;
  79                 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
  80                 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>;
  81                 clock-names = "tbclk", "fck";
  82                 status = "disabled";
  83         };
  84
  85         main_ehrpwm1: pwm@3010000 {
  86                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
  87                 #pwm-cells = <3>;
  88                 reg = <0x00 0x3010000 0x00 0x100>;
  89                 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
  90                 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>;
  91                 clock-names = "tbclk", "fck";
  92                 status = "disabled";
  93         };
  94
  95         main_ehrpwm2: pwm@3020000 {
  96                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
  97                 #pwm-cells = <3>;
  98                 reg = <0x00 0x3020000 0x00 0x100>;
  99                 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
 100                 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>;
 101                 clock-names = "tbclk", "fck";
 102                 status = "disabled";
 103         };
 104
 105         main_ehrpwm3: pwm@3030000 {
 106                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 107                 #pwm-cells = <3>;
 108                 reg = <0x00 0x3030000 0x00 0x100>;
 109                 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
 110                 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>;
 111                 clock-names = "tbclk", "fck";
 112                 status = "disabled";
 113         };
 114
 115         main_ehrpwm4: pwm@3040000 {
 116                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 117                 #pwm-cells = <3>;
 118                 reg = <0x00 0x3040000 0x00 0x100>;
 119                 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
 120                 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>;
 121                 clock-names = "tbclk", "fck";
 122                 status = "disabled";
 123         };
 124
 125         main_ehrpwm5: pwm@3050000 {
 126                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 127                 #pwm-cells = <3>;
 128                 reg = <0x00 0x3050000 0x00 0x100>;
 129                 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
 130                 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>;
 131                 clock-names = "tbclk", "fck";
 132                 status = "disabled";
 133         };
 134
 135         gic500: interrupt-controller@1800000 {
 136                 compatible = "arm,gic-v3";
 137                 #address-cells = <2>;
 138                 #size-cells = <2>;
 139                 ranges;
 140                 #interrupt-cells = <3>;
 141                 interrupt-controller;
 142                 reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */
 143                       <0x00 0x01900000 0x00 0x100000>, /* GICR */
 144                       <0x00 0x6f000000 0x00 0x2000>,   /* GICC */
 145                       <0x00 0x6f010000 0x00 0x1000>,   /* GICH */
 146                       <0x00 0x6f020000 0x00 0x2000>;   /* GICV */
 147
 148                 /* vcpumntirq: virtual CPU interface maintenance interrupt */
 149                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 150
 151                 gic_its: msi-controller@1820000 {
 152                         compatible = "arm,gic-v3-its";
 153                         reg = <0x00 0x01820000 0x00 0x10000>;
 154                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
 155                         msi-controller;
 156                         #msi-cells = <1>;
 157                 };
 158         };
 159
 160         main_gpio_intr: interrupt-controller@a00000 {
 161                 compatible = "ti,sci-intr";
 162                 reg = <0x00 0x00a00000 0x00 0x800>;
 163                 ti,intr-trigger-type = <1>;
 164                 interrupt-controller;
 165                 interrupt-parent = <&gic500>;
 166                 #interrupt-cells = <1>;
 167                 ti,sci = <&sms>;
 168                 ti,sci-dev-id = <148>;
 169                 ti,interrupt-ranges = <8 392 56>;
 170         };
 171
 172         main_pmx0: pinctrl@11c000 {
 173                 compatible = "pinctrl-single";
 174                 /* Proxy 0 addressing */
 175                 reg = <0x0 0x11c000 0x0 0x120>;
 176                 #pinctrl-cells = <1>;
 177                 pinctrl-single,register-width = <32>;
 178                 pinctrl-single,function-mask = <0xffffffff>;
 179         };
 180
 181         /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
 182         main_timerio_input: pinctrl@104200 {
 183                 compatible = "pinctrl-single";
 184                 reg = <0x00 0x104200 0x00 0x50>;
 185                 #pinctrl-cells = <1>;
 186                 pinctrl-single,register-width = <32>;
 187                 pinctrl-single,function-mask = <0x00000007>;
 188         };
 189
 190         /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
 191         main_timerio_output: pinctrl@104280 {
 192                 compatible = "pinctrl-single";
 193                 reg = <0x00 0x104280 0x00 0x20>;
 194                 #pinctrl-cells = <1>;
 195                 pinctrl-single,register-width = <32>;
 196                 pinctrl-single,function-mask = <0x0000001f>;
 197         };
 198
 199         main_crypto: crypto@4e00000 {
 200                 compatible = "ti,j721e-sa2ul";
 201                 reg = <0x00 0x04e00000 0x00 0x1200>;
 202                 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
 203                 #address-cells = <2>;
 204                 #size-cells = <2>;
 205                 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
 206
 207                 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
 208                        <&main_udmap 0x4a41>;
 209                 dma-names = "tx", "rx1", "rx2";
 210
 211                 rng: rng@4e10000 {
 212                         compatible = "inside-secure,safexcel-eip76";
 213                         reg = <0x00 0x04e10000 0x00 0x7d>;
 214                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 215                 };
 216         };
 217
 218         main_timer0: timer@2400000 {
 219                 compatible = "ti,am654-timer";
 220                 reg = <0x00 0x2400000 0x00 0x400>;
 221                 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
 222                 clocks = <&k3_clks 63 1>;
 223                 clock-names = "fck";
 224                 assigned-clocks = <&k3_clks 63 1>;
 225                 assigned-clock-parents = <&k3_clks 63 2>;
 226                 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
 227                 ti,timer-pwm;
 228         };
 229
 230         main_timer1: timer@2410000 {
 231                 compatible = "ti,am654-timer";
 232                 reg = <0x00 0x2410000 0x00 0x400>;
 233                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 234                 clocks = <&k3_clks 64 1>;
 235                 clock-names = "fck";
 236                 assigned-clocks = <&k3_clks 64 1>;
 237                 assigned-clock-parents = <&k3_clks 64 2>;
 238                 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
 239                 ti,timer-pwm;
 240         };
 241
 242         main_timer2: timer@2420000 {
 243                 compatible = "ti,am654-timer";
 244                 reg = <0x00 0x2420000 0x00 0x400>;
 245                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 246                 clocks = <&k3_clks 65 1>;
 247                 clock-names = "fck";
 248                 assigned-clocks = <&k3_clks 65 1>;
 249                 assigned-clock-parents = <&k3_clks 65 2>;
 250                 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
 251                 ti,timer-pwm;
 252         };
 253
 254         main_timer3: timer@2430000 {
 255                 compatible = "ti,am654-timer";
 256                 reg = <0x00 0x2430000 0x00 0x400>;
 257                 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
 258                 clocks = <&k3_clks 66 1>;
 259                 clock-names = "fck";
 260                 assigned-clocks = <&k3_clks 66 1>;
 261                 assigned-clock-parents = <&k3_clks 66 2>;
 262                 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
 263                 ti,timer-pwm;
 264         };
 265
 266         main_timer4: timer@2440000 {
 267                 compatible = "ti,am654-timer";
 268                 reg = <0x00 0x2440000 0x00 0x400>;
 269                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
 270                 clocks = <&k3_clks 67 1>;
 271                 clock-names = "fck";
 272                 assigned-clocks = <&k3_clks 67 1>;
 273                 assigned-clock-parents = <&k3_clks 67 2>;
 274                 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
 275                 ti,timer-pwm;
 276         };
 277
 278         main_timer5: timer@2450000 {
 279                 compatible = "ti,am654-timer";
 280                 reg = <0x00 0x2450000 0x00 0x400>;
 281                 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 282                 clocks = <&k3_clks 68 1>;
 283                 clock-names = "fck";
 284                 assigned-clocks = <&k3_clks 68 1>;
 285                 assigned-clock-parents = <&k3_clks 68 2>;
 286                 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
 287                 ti,timer-pwm;
 288         };
 289
 290         main_timer6: timer@2460000 {
 291                 compatible = "ti,am654-timer";
 292                 reg = <0x00 0x2460000 0x00 0x400>;
 293                 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
 294                 clocks = <&k3_clks 69 1>;
 295                 clock-names = "fck";
 296                 assigned-clocks = <&k3_clks 69 1>;
 297                 assigned-clock-parents = <&k3_clks 69 2>;
 298                 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
 299                 ti,timer-pwm;
 300         };
 301
 302         main_timer7: timer@2470000 {
 303                 compatible = "ti,am654-timer";
 304                 reg = <0x00 0x2470000 0x00 0x400>;
 305                 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
 306                 clocks = <&k3_clks 70 1>;
 307                 clock-names = "fck";
 308                 assigned-clocks = <&k3_clks 70 1>;
 309                 assigned-clock-parents = <&k3_clks 70 2>;
 310                 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
 311                 ti,timer-pwm;
 312         };
 313
 314         main_timer8: timer@2480000 {
 315                 compatible = "ti,am654-timer";
 316                 reg = <0x00 0x2480000 0x00 0x400>;
 317                 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
 318                 clocks = <&k3_clks 71 1>;
 319                 clock-names = "fck";
 320                 assigned-clocks = <&k3_clks 71 1>;
 321                 assigned-clock-parents = <&k3_clks 71 2>;
 322                 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
 323                 ti,timer-pwm;
 324         };
 325
 326         main_timer9: timer@2490000 {
 327                 compatible = "ti,am654-timer";
 328                 reg = <0x00 0x2490000 0x00 0x400>;
 329                 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
 330                 clocks = <&k3_clks 72 1>;
 331                 clock-names = "fck";
 332                 assigned-clocks = <&k3_clks 72 1>;
 333                 assigned-clock-parents = <&k3_clks 72 2>;
 334                 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
 335                 ti,timer-pwm;
 336         };
 337
 338         main_timer10: timer@24a0000 {
 339                 compatible = "ti,am654-timer";
 340                 reg = <0x00 0x24a0000 0x00 0x400>;
 341                 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
 342                 clocks = <&k3_clks 73 1>;
 343                 clock-names = "fck";
 344                 assigned-clocks = <&k3_clks 73 1>;
 345                 assigned-clock-parents = <&k3_clks 73 2>;
 346                 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
 347                 ti,timer-pwm;
 348         };
 349
 350         main_timer11: timer@24b0000 {
 351                 compatible = "ti,am654-timer";
 352                 reg = <0x00 0x24b0000 0x00 0x400>;
 353                 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
 354                 clocks = <&k3_clks 74 1>;
 355                 clock-names = "fck";
 356                 assigned-clocks = <&k3_clks 74 1>;
 357                 assigned-clock-parents = <&k3_clks 74 2>;
 358                 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
 359                 ti,timer-pwm;
 360         };
 361
 362         main_timer12: timer@24c0000 {
 363                 compatible = "ti,am654-timer";
 364                 reg = <0x00 0x24c0000 0x00 0x400>;
 365                 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
 366                 clocks = <&k3_clks 75 1>;
 367                 clock-names = "fck";
 368                 assigned-clocks = <&k3_clks 75 1>;
 369                 assigned-clock-parents = <&k3_clks 75 2>;
 370                 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
 371                 ti,timer-pwm;
 372         };
 373
 374         main_timer13: timer@24d0000 {
 375                 compatible = "ti,am654-timer";
 376                 reg = <0x00 0x24d0000 0x00 0x400>;
 377                 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
 378                 clocks = <&k3_clks 76 1>;
 379                 clock-names = "fck";
 380                 assigned-clocks = <&k3_clks 76 1>;
 381                 assigned-clock-parents = <&k3_clks 76 2>;
 382                 power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
 383                 ti,timer-pwm;
 384         };
 385
 386         main_timer14: timer@24e0000 {
 387                 compatible = "ti,am654-timer";
 388                 reg = <0x00 0x24e0000 0x00 0x400>;
 389                 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 390                 clocks = <&k3_clks 77 1>;
 391                 clock-names = "fck";
 392                 assigned-clocks = <&k3_clks 77 1>;
 393                 assigned-clock-parents = <&k3_clks 77 2>;
 394                 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
 395                 ti,timer-pwm;
 396         };
 397
 398         main_timer15: timer@24f0000 {
 399                 compatible = "ti,am654-timer";
 400                 reg = <0x00 0x24f0000 0x00 0x400>;
 401                 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 402                 clocks = <&k3_clks 78 1>;
 403                 clock-names = "fck";
 404                 assigned-clocks = <&k3_clks 78 1>;
 405                 assigned-clock-parents = <&k3_clks 78 2>;
 406                 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
 407                 ti,timer-pwm;
 408         };
 409
 410         main_timer16: timer@2500000 {
 411                 compatible = "ti,am654-timer";
 412                 reg = <0x00 0x2500000 0x00 0x400>;
 413                 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 414                 clocks = <&k3_clks 79 1>;
 415                 clock-names = "fck";
 416                 assigned-clocks = <&k3_clks 79 1>;
 417                 assigned-clock-parents = <&k3_clks 79 2>;
 418                 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
 419                 ti,timer-pwm;
 420         };
 421
 422         main_timer17: timer@2510000 {
 423                 compatible = "ti,am654-timer";
 424                 reg = <0x00 0x2510000 0x00 0x400>;
 425                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
 426                 clocks = <&k3_clks 80 1>;
 427                 clock-names = "fck";
 428                 assigned-clocks = <&k3_clks 80 1>;
 429                 assigned-clock-parents = <&k3_clks 80 2>;
 430                 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
 431                 ti,timer-pwm;
 432         };
 433
 434         main_timer18: timer@2520000 {
 435                 compatible = "ti,am654-timer";
 436                 reg = <0x00 0x2520000 0x00 0x400>;
 437                 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
 438                 clocks = <&k3_clks 81 1>;
 439                 clock-names = "fck";
 440                 assigned-clocks = <&k3_clks 81 1>;
 441                 assigned-clock-parents = <&k3_clks 81 2>;
 442                 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
 443                 ti,timer-pwm;
 444         };
 445
 446         main_timer19: timer@2530000 {
 447                 compatible = "ti,am654-timer";
 448                 reg = <0x00 0x2530000 0x00 0x400>;
 449                 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
 450                 clocks = <&k3_clks 82 1>;
 451                 clock-names = "fck";
 452                 assigned-clocks = <&k3_clks 82 1>;
 453                 assigned-clock-parents = <&k3_clks 82 2>;
 454                 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
 455                 ti,timer-pwm;
 456         };
 457
 458         main_uart0: serial@2800000 {
 459                 compatible = "ti,j721e-uart", "ti,am654-uart";
 460                 reg = <0x00 0x02800000 0x00 0x200>;
 461                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 462                 current-speed = <115200>;
 463                 clocks = <&k3_clks 146 3>;
 464                 clock-names = "fclk";
 465                 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
 466                 status = "disabled";
 467         };
 468
 469         main_uart1: serial@2810000 {
 470                 compatible = "ti,j721e-uart", "ti,am654-uart";
 471                 reg = <0x00 0x02810000 0x00 0x200>;
 472                 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 473                 current-speed = <115200>;
 474                 clocks = <&k3_clks 350 3>;
 475                 clock-names = "fclk";
 476                 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
 477                 status = "disabled";
 478         };
 479
 480         main_uart2: serial@2820000 {
 481                 compatible = "ti,j721e-uart", "ti,am654-uart";
 482                 reg = <0x00 0x02820000 0x00 0x200>;
 483                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 484                 current-speed = <115200>;
 485                 clocks = <&k3_clks 351 3>;
 486                 clock-names = "fclk";
 487                 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
 488                 status = "disabled";
 489         };
 490
 491         main_uart3: serial@2830000 {
 492                 compatible = "ti,j721e-uart", "ti,am654-uart";
 493                 reg = <0x00 0x02830000 0x00 0x200>;
 494                 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 495                 current-speed = <115200>;
 496                 clocks = <&k3_clks 352 3>;
 497                 clock-names = "fclk";
 498                 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
 499                 status = "disabled";
 500         };
 501
 502         main_uart4: serial@2840000 {
 503                 compatible = "ti,j721e-uart", "ti,am654-uart";
 504                 reg = <0x00 0x02840000 0x00 0x200>;
 505                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 506                 current-speed = <115200>;
 507                 clocks = <&k3_clks 353 3>;
 508                 clock-names = "fclk";
 509                 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
 510                 status = "disabled";
 511         };
 512
 513         main_uart5: serial@2850000 {
 514                 compatible = "ti,j721e-uart", "ti,am654-uart";
 515                 reg = <0x00 0x02850000 0x00 0x200>;
 516                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 517                 current-speed = <115200>;
 518                 clocks = <&k3_clks 354 3>;
 519                 clock-names = "fclk";
 520                 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
 521                 status = "disabled";
 522         };
 523
 524         main_uart6: serial@2860000 {
 525                 compatible = "ti,j721e-uart", "ti,am654-uart";
 526                 reg = <0x00 0x02860000 0x00 0x200>;
 527                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
 528                 current-speed = <115200>;
 529                 clocks = <&k3_clks 355 3>;
 530                 clock-names = "fclk";
 531                 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
 532                 status = "disabled";
 533         };
 534
 535         main_uart7: serial@2870000 {
 536                 compatible = "ti,j721e-uart", "ti,am654-uart";
 537                 reg = <0x00 0x02870000 0x00 0x200>;
 538                 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 539                 current-speed = <115200>;
 540                 clocks = <&k3_clks 356 3>;
 541                 clock-names = "fclk";
 542                 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
 543                 status = "disabled";
 544         };
 545
 546         main_uart8: serial@2880000 {
 547                 compatible = "ti,j721e-uart", "ti,am654-uart";
 548                 reg = <0x00 0x02880000 0x00 0x200>;
 549                 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 550                 current-speed = <115200>;
 551                 clocks = <&k3_clks 357 3>;
 552                 clock-names = "fclk";
 553                 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
 554                 status = "disabled";
 555         };
 556
 557         main_uart9: serial@2890000 {
 558                 compatible = "ti,j721e-uart", "ti,am654-uart";
 559                 reg = <0x00 0x02890000 0x00 0x200>;
 560                 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 561                 current-speed = <115200>;
 562                 clocks = <&k3_clks 358 3>;
 563                 clock-names = "fclk";
 564                 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
 565                 status = "disabled";
 566         };
 567
 568         main_gpio0: gpio@600000 {
 569                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 570                 reg = <0x00 0x00600000 0x00 0x100>;
 571                 gpio-controller;
 572                 #gpio-cells = <2>;
 573                 interrupt-parent = <&main_gpio_intr>;
 574                 interrupts = <145>, <146>, <147>, <148>, <149>;
 575                 interrupt-controller;
 576                 #interrupt-cells = <2>;
 577                 ti,ngpio = <66>;
 578                 ti,davinci-gpio-unbanked = <0>;
 579                 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
 580                 clocks = <&k3_clks 111 0>;
 581                 clock-names = "gpio";
 582                 status = "disabled";
 583         };
 584
 585         main_gpio2: gpio@610000 {
 586                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 587                 reg = <0x00 0x00610000 0x00 0x100>;
 588                 gpio-controller;
 589                 #gpio-cells = <2>;
 590                 interrupt-parent = <&main_gpio_intr>;
 591                 interrupts = <154>, <155>, <156>, <157>, <158>;
 592                 interrupt-controller;
 593                 #interrupt-cells = <2>;
 594                 ti,ngpio = <66>;
 595                 ti,davinci-gpio-unbanked = <0>;
 596                 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
 597                 clocks = <&k3_clks 112 0>;
 598                 clock-names = "gpio";
 599                 status = "disabled";
 600         };
 601
 602         main_gpio4: gpio@620000 {
 603                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 604                 reg = <0x00 0x00620000 0x00 0x100>;
 605                 gpio-controller;
 606                 #gpio-cells = <2>;
 607                 interrupt-parent = <&main_gpio_intr>;
 608                 interrupts = <163>, <164>, <165>, <166>, <167>;
 609                 interrupt-controller;
 610                 #interrupt-cells = <2>;
 611                 ti,ngpio = <66>;
 612                 ti,davinci-gpio-unbanked = <0>;
 613                 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
 614                 clocks = <&k3_clks 113 0>;
 615                 clock-names = "gpio";
 616                 status = "disabled";
 617         };
 618
 619         main_gpio6: gpio@630000 {
 620                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 621                 reg = <0x00 0x00630000 0x00 0x100>;
 622                 gpio-controller;
 623                 #gpio-cells = <2>;
 624                 interrupt-parent = <&main_gpio_intr>;
 625                 interrupts = <172>, <173>, <174>, <175>, <176>;
 626                 interrupt-controller;
 627                 #interrupt-cells = <2>;
 628                 ti,ngpio = <66>;
 629                 ti,davinci-gpio-unbanked = <0>;
 630                 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
 631                 clocks = <&k3_clks 114 0>;
 632                 clock-names = "gpio";
 633                 status = "disabled";
 634         };
 635
 636         main_i2c0: i2c@2000000 {
 637                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 638                 reg = <0x00 0x02000000 0x00 0x100>;
 639                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 640                 #address-cells = <1>;
 641                 #size-cells = <0>;
 642                 clocks = <&k3_clks 214 1>;
 643                 clock-names = "fck";
 644                 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
 645         };
 646
 647         main_i2c1: i2c@2010000 {
 648                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 649                 reg = <0x00 0x02010000 0x00 0x100>;
 650                 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 651                 #address-cells = <1>;
 652                 #size-cells = <0>;
 653                 clocks = <&k3_clks 215 1>;
 654                 clock-names = "fck";
 655                 power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
 656                 status = "disabled";
 657         };
 658
 659         main_i2c2: i2c@2020000 {
 660                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 661                 reg = <0x00 0x02020000 0x00 0x100>;
 662                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 663                 #address-cells = <1>;
 664                 #size-cells = <0>;
 665                 clocks = <&k3_clks 216 1>;
 666                 clock-names = "fck";
 667                 power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
 668                 status = "disabled";
 669         };
 670
 671         main_i2c3: i2c@2030000 {
 672                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 673                 reg = <0x00 0x02030000 0x00 0x100>;
 674                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 675                 #address-cells = <1>;
 676                 #size-cells = <0>;
 677                 clocks = <&k3_clks 217 1>;
 678                 clock-names = "fck";
 679                 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
 680                 status = "disabled";
 681         };
 682
 683         main_i2c4: i2c@2040000 {
 684                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 685                 reg = <0x00 0x02040000 0x00 0x100>;
 686                 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
 687                 #address-cells = <1>;
 688                 #size-cells = <0>;
 689                 clocks = <&k3_clks 218 1>;
 690                 clock-names = "fck";
 691                 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
 692                 status = "disabled";
 693         };
 694
 695         main_i2c5: i2c@2050000 {
 696                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 697                 reg = <0x00 0x02050000 0x00 0x100>;
 698                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 699                 #address-cells = <1>;
 700                 #size-cells = <0>;
 701                 clocks = <&k3_clks 219 1>;
 702                 clock-names = "fck";
 703                 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
 704                 status = "disabled";
 705         };
 706
 707         main_i2c6: i2c@2060000 {
 708                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 709                 reg = <0x00 0x02060000 0x00 0x100>;
 710                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 711                 #address-cells = <1>;
 712                 #size-cells = <0>;
 713                 clocks = <&k3_clks 220 1>;
 714                 clock-names = "fck";
 715                 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
 716                 status = "disabled";
 717         };
 718
 719         vpu: video-codec@4210000 {
 720                 compatible = "ti,j721s2-wave521c", "cnm,wave521c";
 721                 reg = <0x00 0x4210000 0x00 0x10000>;
 722                 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
 723                 clocks = <&k3_clks 179 2>;
 724                 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
 725         };
 726
 727         main_sdhci0: mmc@4f80000 {
 728                 compatible = "ti,j721e-sdhci-8bit";
 729                 reg = <0x00 0x04f80000 0x00 0x1000>,
 730                       <0x00 0x04f88000 0x00 0x400>;
 731                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 732                 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
 733                 clocks = <&k3_clks 98 7>, <&k3_clks 98 1>;
 734                 clock-names = "clk_ahb", "clk_xin";
 735                 assigned-clocks = <&k3_clks 98 1>;
 736                 assigned-clock-parents = <&k3_clks 98 2>;
 737                 bus-width = <8>;
 738                 ti,otap-del-sel-legacy = <0x0>;
 739                 ti,otap-del-sel-mmc-hs = <0x0>;
 740                 ti,otap-del-sel-ddr52 = <0x6>;
 741                 ti,otap-del-sel-hs200 = <0x8>;
 742                 ti,otap-del-sel-hs400 = <0x5>;
 743                 ti,itap-del-sel-legacy = <0x10>;
 744                 ti,itap-del-sel-mmc-hs = <0xa>;
 745                 ti,strobe-sel = <0x77>;
 746                 ti,clkbuf-sel = <0x7>;
 747                 ti,trm-icp = <0x8>;
 748                 mmc-ddr-1_8v;
 749                 mmc-hs200-1_8v;
 750                 mmc-hs400-1_8v;
 751                 dma-coherent;
 752                 status = "disabled";
 753         };
 754
 755         main_sdhci1: mmc@4fb0000 {
 756                 compatible = "ti,j721e-sdhci-4bit";
 757                 reg = <0x00 0x04fb0000 0x00 0x1000>,
 758                       <0x00 0x04fb8000 0x00 0x400>;
 759                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 760                 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
 761                 clocks = <&k3_clks 99 8>, <&k3_clks 99 1>;
 762                 clock-names = "clk_ahb", "clk_xin";
 763                 assigned-clocks = <&k3_clks 99 1>;
 764                 assigned-clock-parents = <&k3_clks 99 2>;
 765                 bus-width = <4>;
 766                 ti,otap-del-sel-legacy = <0x0>;
 767                 ti,otap-del-sel-sd-hs = <0x0>;
 768                 ti,otap-del-sel-sdr12 = <0xf>;
 769                 ti,otap-del-sel-sdr25 = <0xf>;
 770                 ti,otap-del-sel-sdr50 = <0xc>;
 771                 ti,otap-del-sel-sdr104 = <0x5>;
 772                 ti,otap-del-sel-ddr50 = <0xc>;
 773                 ti,itap-del-sel-legacy = <0x0>;
 774                 ti,itap-del-sel-sd-hs = <0x0>;
 775                 ti,itap-del-sel-sdr12 = <0x0>;
 776                 ti,itap-del-sel-sdr25 = <0x0>;
 777                 ti,itap-del-sel-ddr50 = <0x2>;
 778                 ti,clkbuf-sel = <0x7>;
 779                 ti,trm-icp = <0x8>;
 780                 dma-coherent;
 781                 /* Masking support for SDR104 capability */
 782                 sdhci-caps-mask = <0x00000003 0x00000000>;
 783                 status = "disabled";
 784         };
 785
 786         main_navss: bus@30000000 {
 787                 compatible = "simple-bus";
 788                 #address-cells = <2>;
 789                 #size-cells = <2>;
 790                 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
 791                 ti,sci-dev-id = <224>;
 792                 dma-coherent;
 793                 dma-ranges;
 794
 795                 main_navss_intr: interrupt-controller@310e0000 {
 796                         compatible = "ti,sci-intr";
 797                         reg = <0x00 0x310e0000 0x00 0x4000>;
 798                         ti,intr-trigger-type = <4>;
 799                         interrupt-controller;
 800                         interrupt-parent = <&gic500>;
 801                         #interrupt-cells = <1>;
 802                         ti,sci = <&sms>;
 803                         ti,sci-dev-id = <227>;
 804                         ti,interrupt-ranges = <0 64 64>,
 805                                               <64 448 64>,
 806                                               <128 672 64>;
 807                 };
 808
 809                 main_udmass_inta: msi-controller@33d00000 {
 810                         compatible = "ti,sci-inta";
 811                         reg = <0x00 0x33d00000 0x00 0x100000>;
 812                         interrupt-controller;
 813                         #interrupt-cells = <0>;
 814                         interrupt-parent = <&main_navss_intr>;
 815                         msi-controller;
 816                         ti,sci = <&sms>;
 817                         ti,sci-dev-id = <265>;
 818                         ti,interrupt-ranges = <0 0 256>;
 819                         ti,unmapped-event-sources = <&main_bcdma_csi>;
 820                 };
 821
 822                 secure_proxy_main: mailbox@32c00000 {
 823                         compatible = "ti,am654-secure-proxy";
 824                         #mbox-cells = <1>;
 825                         reg-names = "target_data", "rt", "scfg";
 826                         reg = <0x00 0x32c00000 0x00 0x100000>,
 827                               <0x00 0x32400000 0x00 0x100000>,
 828                               <0x00 0x32800000 0x00 0x100000>;
 829                         interrupt-names = "rx_011";
 830                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 831                 };
 832
 833                 hwspinlock: spinlock@30e00000 {
 834                         compatible = "ti,am654-hwspinlock";
 835                         reg = <0x00 0x30e00000 0x00 0x1000>;
 836                         #hwlock-cells = <1>;
 837                 };
 838
 839                 mailbox0_cluster0: mailbox@31f80000 {
 840                         compatible = "ti,am654-mailbox";
 841                         reg = <0x00 0x31f80000 0x00 0x200>;
 842                         #mbox-cells = <1>;
 843                         ti,mbox-num-users = <4>;
 844                         ti,mbox-num-fifos = <16>;
 845                         interrupt-parent = <&main_navss_intr>;
 846                         status = "disabled";
 847                 };
 848
 849                 mailbox0_cluster1: mailbox@31f81000 {
 850                         compatible = "ti,am654-mailbox";
 851                         reg = <0x00 0x31f81000 0x00 0x200>;
 852                         #mbox-cells = <1>;
 853                         ti,mbox-num-users = <4>;
 854                         ti,mbox-num-fifos = <16>;
 855                         interrupt-parent = <&main_navss_intr>;
 856                         status = "disabled";
 857                 };
 858
 859                 mailbox0_cluster2: mailbox@31f82000 {
 860                         compatible = "ti,am654-mailbox";
 861                         reg = <0x00 0x31f82000 0x00 0x200>;
 862                         #mbox-cells = <1>;
 863                         ti,mbox-num-users = <4>;
 864                         ti,mbox-num-fifos = <16>;
 865                         interrupt-parent = <&main_navss_intr>;
 866                         status = "disabled";
 867                 };
 868
 869                 mailbox0_cluster3: mailbox@31f83000 {
 870                         compatible = "ti,am654-mailbox";
 871                         reg = <0x00 0x31f83000 0x00 0x200>;
 872                         #mbox-cells = <1>;
 873                         ti,mbox-num-users = <4>;
 874                         ti,mbox-num-fifos = <16>;
 875                         interrupt-parent = <&main_navss_intr>;
 876                         status = "disabled";
 877                 };
 878
 879                 mailbox0_cluster4: mailbox@31f84000 {
 880                         compatible = "ti,am654-mailbox";
 881                         reg = <0x00 0x31f84000 0x00 0x200>;
 882                         #mbox-cells = <1>;
 883                         ti,mbox-num-users = <4>;
 884                         ti,mbox-num-fifos = <16>;
 885                         interrupt-parent = <&main_navss_intr>;
 886                         status = "disabled";
 887                 };
 888
 889                 mailbox0_cluster5: mailbox@31f85000 {
 890                         compatible = "ti,am654-mailbox";
 891                         reg = <0x00 0x31f85000 0x00 0x200>;
 892                         #mbox-cells = <1>;
 893                         ti,mbox-num-users = <4>;
 894                         ti,mbox-num-fifos = <16>;
 895                         interrupt-parent = <&main_navss_intr>;
 896                         status = "disabled";
 897                 };
 898
 899                 mailbox0_cluster6: mailbox@31f86000 {
 900                         compatible = "ti,am654-mailbox";
 901                         reg = <0x00 0x31f86000 0x00 0x200>;
 902                         #mbox-cells = <1>;
 903                         ti,mbox-num-users = <4>;
 904                         ti,mbox-num-fifos = <16>;
 905                         interrupt-parent = <&main_navss_intr>;
 906                         status = "disabled";
 907                 };
 908
 909                 mailbox0_cluster7: mailbox@31f87000 {
 910                         compatible = "ti,am654-mailbox";
 911                         reg = <0x00 0x31f87000 0x00 0x200>;
 912                         #mbox-cells = <1>;
 913                         ti,mbox-num-users = <4>;
 914                         ti,mbox-num-fifos = <16>;
 915                         interrupt-parent = <&main_navss_intr>;
 916                         status = "disabled";
 917                 };
 918
 919                 mailbox0_cluster8: mailbox@31f88000 {
 920                         compatible = "ti,am654-mailbox";
 921                         reg = <0x00 0x31f88000 0x00 0x200>;
 922                         #mbox-cells = <1>;
 923                         ti,mbox-num-users = <4>;
 924                         ti,mbox-num-fifos = <16>;
 925                         interrupt-parent = <&main_navss_intr>;
 926                         status = "disabled";
 927                 };
 928
 929                 mailbox0_cluster9: mailbox@31f89000 {
 930                         compatible = "ti,am654-mailbox";
 931                         reg = <0x00 0x31f89000 0x00 0x200>;
 932                         #mbox-cells = <1>;
 933                         ti,mbox-num-users = <4>;
 934                         ti,mbox-num-fifos = <16>;
 935                         interrupt-parent = <&main_navss_intr>;
 936                         status = "disabled";
 937                 };
 938
 939                 mailbox0_cluster10: mailbox@31f8a000 {
 940                         compatible = "ti,am654-mailbox";
 941                         reg = <0x00 0x31f8a000 0x00 0x200>;
 942                         #mbox-cells = <1>;
 943                         ti,mbox-num-users = <4>;
 944                         ti,mbox-num-fifos = <16>;
 945                         interrupt-parent = <&main_navss_intr>;
 946                         status = "disabled";
 947                 };
 948
 949                 mailbox0_cluster11: mailbox@31f8b000 {
 950                         compatible = "ti,am654-mailbox";
 951                         reg = <0x00 0x31f8b000 0x00 0x200>;
 952                         #mbox-cells = <1>;
 953                         ti,mbox-num-users = <4>;
 954                         ti,mbox-num-fifos = <16>;
 955                         interrupt-parent = <&main_navss_intr>;
 956                         status = "disabled";
 957                 };
 958
 959                 mailbox1_cluster0: mailbox@31f90000 {
 960                         compatible = "ti,am654-mailbox";
 961                         reg = <0x00 0x31f90000 0x00 0x200>;
 962                         #mbox-cells = <1>;
 963                         ti,mbox-num-users = <4>;
 964                         ti,mbox-num-fifos = <16>;
 965                         interrupt-parent = <&main_navss_intr>;
 966                         status = "disabled";
 967                 };
 968
 969                 mailbox1_cluster1: mailbox@31f91000 {
 970                         compatible = "ti,am654-mailbox";
 971                         reg = <0x00 0x31f91000 0x00 0x200>;
 972                         #mbox-cells = <1>;
 973                         ti,mbox-num-users = <4>;
 974                         ti,mbox-num-fifos = <16>;
 975                         interrupt-parent = <&main_navss_intr>;
 976                         status = "disabled";
 977                 };
 978
 979                 mailbox1_cluster2: mailbox@31f92000 {
 980                         compatible = "ti,am654-mailbox";
 981                         reg = <0x00 0x31f92000 0x00 0x200>;
 982                         #mbox-cells = <1>;
 983                         ti,mbox-num-users = <4>;
 984                         ti,mbox-num-fifos = <16>;
 985                         interrupt-parent = <&main_navss_intr>;
 986                         status = "disabled";
 987                 };
 988
 989                 mailbox1_cluster3: mailbox@31f93000 {
 990                         compatible = "ti,am654-mailbox";
 991                         reg = <0x00 0x31f93000 0x00 0x200>;
 992                         #mbox-cells = <1>;
 993                         ti,mbox-num-users = <4>;
 994                         ti,mbox-num-fifos = <16>;
 995                         interrupt-parent = <&main_navss_intr>;
 996                         status = "disabled";
 997                 };
 998
 999                 mailbox1_cluster4: mailbox@31f94000 {
1000                         compatible = "ti,am654-mailbox";
1001                         reg = <0x00 0x31f94000 0x00 0x200>;
1002                         #mbox-cells = <1>;
1003                         ti,mbox-num-users = <4>;
1004                         ti,mbox-num-fifos = <16>;
1005                         interrupt-parent = <&main_navss_intr>;
1006                         status = "disabled";
1007                 };
1008
1009                 mailbox1_cluster5: mailbox@31f95000 {
1010                         compatible = "ti,am654-mailbox";
1011                         reg = <0x00 0x31f95000 0x00 0x200>;
1012                         #mbox-cells = <1>;
1013                         ti,mbox-num-users = <4>;
1014                         ti,mbox-num-fifos = <16>;
1015                         interrupt-parent = <&main_navss_intr>;
1016                         status = "disabled";
1017                 };
1018
1019                 mailbox1_cluster6: mailbox@31f96000 {
1020                         compatible = "ti,am654-mailbox";
1021                         reg = <0x00 0x31f96000 0x00 0x200>;
1022                         #mbox-cells = <1>;
1023                         ti,mbox-num-users = <4>;
1024                         ti,mbox-num-fifos = <16>;
1025                         interrupt-parent = <&main_navss_intr>;
1026                         status = "disabled";
1027                 };
1028
1029                 mailbox1_cluster7: mailbox@31f97000 {
1030                         compatible = "ti,am654-mailbox";
1031                         reg = <0x00 0x31f97000 0x00 0x200>;
1032                         #mbox-cells = <1>;
1033                         ti,mbox-num-users = <4>;
1034                         ti,mbox-num-fifos = <16>;
1035                         interrupt-parent = <&main_navss_intr>;
1036                         status = "disabled";
1037                 };
1038
1039                 mailbox1_cluster8: mailbox@31f98000 {
1040                         compatible = "ti,am654-mailbox";
1041                         reg = <0x00 0x31f98000 0x00 0x200>;
1042                         #mbox-cells = <1>;
1043                         ti,mbox-num-users = <4>;
1044                         ti,mbox-num-fifos = <16>;
1045                         interrupt-parent = <&main_navss_intr>;
1046                         status = "disabled";
1047                 };
1048
1049                 mailbox1_cluster9: mailbox@31f99000 {
1050                         compatible = "ti,am654-mailbox";
1051                         reg = <0x00 0x31f99000 0x00 0x200>;
1052                         #mbox-cells = <1>;
1053                         ti,mbox-num-users = <4>;
1054                         ti,mbox-num-fifos = <16>;
1055                         interrupt-parent = <&main_navss_intr>;
1056                         status = "disabled";
1057                 };
1058
1059                 mailbox1_cluster10: mailbox@31f9a000 {
1060                         compatible = "ti,am654-mailbox";
1061                         reg = <0x00 0x31f9a000 0x00 0x200>;
1062                         #mbox-cells = <1>;
1063                         ti,mbox-num-users = <4>;
1064                         ti,mbox-num-fifos = <16>;
1065                         interrupt-parent = <&main_navss_intr>;
1066                         status = "disabled";
1067                 };
1068
1069                 mailbox1_cluster11: mailbox@31f9b000 {
1070                         compatible = "ti,am654-mailbox";
1071                         reg = <0x00 0x31f9b000 0x00 0x200>;
1072                         #mbox-cells = <1>;
1073                         ti,mbox-num-users = <4>;
1074                         ti,mbox-num-fifos = <16>;
1075                         interrupt-parent = <&main_navss_intr>;
1076                         status = "disabled";
1077                 };
1078
1079                 main_ringacc: ringacc@3c000000 {
1080                         compatible = "ti,am654-navss-ringacc";
1081                         reg = <0x0 0x3c000000 0x0 0x400000>,
1082                               <0x0 0x38000000 0x0 0x400000>,
1083                               <0x0 0x31120000 0x0 0x100>,
1084                               <0x0 0x33000000 0x0 0x40000>,
1085                               <0x0 0x31080000 0x0 0x40000>;
1086                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
1087                         ti,num-rings = <1024>;
1088                         ti,sci-rm-range-gp-rings = <0x1>;
1089                         ti,sci = <&sms>;
1090                         ti,sci-dev-id = <259>;
1091                         msi-parent = <&main_udmass_inta>;
1092                 };
1093
1094                 main_udmap: dma-controller@31150000 {
1095                         compatible = "ti,j721e-navss-main-udmap";
1096                         reg = <0x0 0x31150000 0x0 0x100>,
1097                               <0x0 0x34000000 0x0 0x80000>,
1098                               <0x0 0x35000000 0x0 0x200000>,
1099                               <0x0 0x30b00000 0x0 0x20000>,
1100                               <0x0 0x30c00000 0x0 0x8000>,
1101                               <0x0 0x30d00000 0x0 0x4000>;
1102                         reg-names = "gcfg", "rchanrt", "tchanrt",
1103                                     "tchan", "rchan", "rflow";
1104                         msi-parent = <&main_udmass_inta>;
1105                         #dma-cells = <1>;
1106
1107                         ti,sci = <&sms>;
1108                         ti,sci-dev-id = <263>;
1109                         ti,ringacc = <&main_ringacc>;
1110
1111                         ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
1112                                                 <0x0f>, /* TX_HCHAN */
1113                                                 <0x10>; /* TX_UHCHAN */
1114                         ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
1115                                                 <0x0b>, /* RX_HCHAN */
1116                                                 <0x0c>; /* RX_UHCHAN */
1117                         ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
1118                 };
1119
1120                 main_bcdma_csi: dma-controller@311a0000 {
1121                         compatible = "ti,j721s2-dmss-bcdma-csi";
1122                         reg = <0x00 0x311a0000 0x00 0x100>,
1123                               <0x00 0x35d00000 0x00 0x20000>,
1124                               <0x00 0x35c00000 0x00 0x10000>,
1125                               <0x00 0x35e00000 0x00 0x80000>;
1126                         reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
1127                         msi-parent = <&main_udmass_inta>;
1128                         #dma-cells = <3>;
1129                         ti,sci = <&sms>;
1130                         ti,sci-dev-id = <225>;
1131                         ti,sci-rm-range-rchan = <0x21>;
1132                         ti,sci-rm-range-tchan = <0x22>;
1133                 };
1134
1135                 cpts@310d0000 {
1136                         compatible = "ti,j721e-cpts";
1137                         reg = <0x0 0x310d0000 0x0 0x400>;
1138                         reg-names = "cpts";
1139                         clocks = <&k3_clks 226 5>;
1140                         clock-names = "cpts";
1141                         assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */
1142                         assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */
1143                         interrupts-extended = <&main_navss_intr 391>;
1144                         interrupt-names = "cpts";
1145                         ti,cpts-periodic-outputs = <6>;
1146                         ti,cpts-ext-ts-inputs = <8>;
1147                 };
1148         };
1149
1150         main_cpsw: ethernet@c200000 {
1151                 compatible = "ti,j721e-cpsw-nuss";
1152                 reg = <0x00 0xc200000 0x00 0x200000>;
1153                 reg-names = "cpsw_nuss";
1154                 ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>;
1155                 #address-cells = <2>;
1156                 #size-cells = <2>;
1157                 dma-coherent;
1158                 clocks = <&k3_clks 28 28>;
1159                 clock-names = "fck";
1160                 power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
1161
1162                 dmas = <&main_udmap 0xc640>,
1163                        <&main_udmap 0xc641>,
1164                        <&main_udmap 0xc642>,
1165                        <&main_udmap 0xc643>,
1166                        <&main_udmap 0xc644>,
1167                        <&main_udmap 0xc645>,
1168                        <&main_udmap 0xc646>,
1169                        <&main_udmap 0xc647>,
1170                        <&main_udmap 0x4640>;
1171                 dma-names = "tx0", "tx1", "tx2", "tx3",
1172                             "tx4", "tx5", "tx6", "tx7",
1173                             "rx";
1174
1175                 status = "disabled";
1176
1177                 ethernet-ports {
1178                         #address-cells = <1>;
1179                         #size-cells = <0>;
1180
1181                         main_cpsw_port1: port@1 {
1182                                 reg = <1>;
1183                                 ti,mac-only;
1184                                 label = "port1";
1185                                 phys = <&phy_gmii_sel_cpsw 1>;
1186                                 status = "disabled";
1187                         };
1188                 };
1189
1190                 main_cpsw_mdio: mdio@f00 {
1191                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1192                         reg = <0x00 0xf00 0x00 0x100>;
1193                         #address-cells = <1>;
1194                         #size-cells = <0>;
1195                         clocks = <&k3_clks 28 28>;
1196                         clock-names = "fck";
1197                         bus_freq = <1000000>;
1198                         status = "disabled";
1199                 };
1200
1201                 cpts@3d000 {
1202                         compatible = "ti,am65-cpts";
1203                         reg = <0x00 0x3d000 0x00 0x400>;
1204                         clocks = <&k3_clks 28 3>;
1205                         clock-names = "cpts";
1206                         interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1207                         interrupt-names = "cpts";
1208                         ti,cpts-ext-ts-inputs = <4>;
1209                         ti,cpts-periodic-outputs = <2>;
1210                 };
1211         };
1212
1213         usbss0: cdns-usb@4104000 {
1214                 compatible = "ti,j721e-usb";
1215                 reg = <0x00 0x04104000 0x00 0x100>;
1216                 clocks = <&k3_clks 360 16>, <&k3_clks 360 15>;
1217                 clock-names = "ref", "lpm";
1218                 assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
1219                 assigned-clock-parents = <&k3_clks 360 17>;
1220                 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
1221                 #address-cells = <2>;
1222                 #size-cells = <2>;
1223                 ranges;
1224                 dma-coherent;
1225
1226                 status = "disabled"; /* Needs pinmux */
1227
1228                 usb0: usb@6000000 {
1229                         compatible = "cdns,usb3";
1230                         reg = <0x00 0x06000000 0x00 0x10000>,
1231                               <0x00 0x06010000 0x00 0x10000>,
1232                               <0x00 0x06020000 0x00 0x10000>;
1233                         reg-names = "otg", "xhci", "dev";
1234                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1235                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1236                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1237                         interrupt-names = "host", "peripheral", "otg";
1238                         maximum-speed = "super-speed";
1239                         dr_mode = "otg";
1240                 };
1241         };
1242
1243         ti_csi2rx0: ticsi2rx@4500000 {
1244                 compatible = "ti,j721e-csi2rx-shim";
1245                 reg = <0x00 0x04500000 0x00 0x1000>;
1246                 ranges;
1247                 #address-cells = <2>;
1248                 #size-cells = <2>;
1249                 dmas = <&main_bcdma_csi 0 0x4940 0>;
1250                 dma-names = "rx0";
1251                 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
1252                 status = "disabled";
1253
1254                 cdns_csi2rx0: csi-bridge@4504000 {
1255                         compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
1256                         reg = <0x00 0x04504000 0x00 0x1000>;
1257                         clocks = <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>,
1258                                 <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>;
1259                         clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
1260                                 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
1261                         phys = <&dphy0>;
1262                         phy-names = "dphy";
1263
1264                         ports {
1265                                 #address-cells = <1>;
1266                                 #size-cells = <0>;
1267
1268                                 csi0_port0: port@0 {
1269                                         reg = <0>;
1270                                         status = "disabled";
1271                                 };
1272
1273                                 csi0_port1: port@1 {
1274                                         reg = <1>;
1275                                         status = "disabled";
1276                                 };
1277
1278                                 csi0_port2: port@2 {
1279                                         reg = <2>;
1280                                         status = "disabled";
1281                                 };
1282
1283                                 csi0_port3: port@3 {
1284                                         reg = <3>;
1285                                         status = "disabled";
1286                                 };
1287
1288                                 csi0_port4: port@4 {
1289                                         reg = <4>;
1290                                         status = "disabled";
1291                                 };
1292                         };
1293                 };
1294         };
1295
1296         ti_csi2rx1: ticsi2rx@4510000 {
1297                 compatible = "ti,j721e-csi2rx-shim";
1298                 reg = <0x00 0x04510000 0x00 0x1000>;
1299                 ranges;
1300                 #address-cells = <2>;
1301                 #size-cells = <2>;
1302                 dmas = <&main_bcdma_csi 0 0x4960 0>;
1303                 dma-names = "rx0";
1304                 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
1305                 status = "disabled";
1306
1307                 cdns_csi2rx1: csi-bridge@4514000 {
1308                         compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
1309                         reg = <0x00 0x04514000 0x00 0x1000>;
1310                         clocks = <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>,
1311                                 <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>;
1312                         clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
1313                                 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
1314                         phys = <&dphy1>;
1315                         phy-names = "dphy";
1316
1317                         ports {
1318                                 #address-cells = <1>;
1319                                 #size-cells = <0>;
1320
1321                                 csi1_port0: port@0 {
1322                                         reg = <0>;
1323                                         status = "disabled";
1324                                 };
1325
1326                                 csi1_port1: port@1 {
1327                                         reg = <1>;
1328                                         status = "disabled";
1329                                 };
1330
1331                                 csi1_port2: port@2 {
1332                                         reg = <2>;
1333                                         status = "disabled";
1334                                 };
1335
1336                                 csi1_port3: port@3 {
1337                                         reg = <3>;
1338                                         status = "disabled";
1339                                 };
1340
1341                                 csi1_port4: port@4 {
1342                                         reg = <4>;
1343                                         status = "disabled";
1344                                 };
1345                         };
1346                 };
1347         };
1348
1349         dphy0: phy@4580000 {
1350                 compatible = "cdns,dphy-rx";
1351                 reg = <0x00 0x04580000 0x00 0x1100>;
1352                 #phy-cells = <0>;
1353                 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1354                 status = "disabled";
1355         };
1356
1357         dphy1: phy@4590000 {
1358                 compatible = "cdns,dphy-rx";
1359                 reg = <0x00 0x04590000 0x00 0x1100>;
1360                 #phy-cells = <0>;
1361                 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
1362                 status = "disabled";
1363         };
1364
1365         serdes_wiz0: wiz@5060000 {
1366                 compatible = "ti,j721s2-wiz-10g";
1367                 #address-cells = <1>;
1368                 #size-cells = <1>;
1369                 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
1370                 clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
1371                 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
1372                 num-lanes = <4>;
1373                 #reset-cells = <1>;
1374                 #clock-cells = <1>;
1375                 ranges = <0x5060000 0x0 0x5060000 0x10000>;
1376
1377                 assigned-clocks = <&k3_clks 365 3>;
1378                 assigned-clock-parents = <&k3_clks 365 7>;
1379
1380                 serdes0: serdes@5060000 {
1381                         compatible = "ti,j721e-serdes-10g";
1382                         reg = <0x05060000 0x00010000>;
1383                         reg-names = "torrent_phy";
1384                         resets = <&serdes_wiz0 0>;
1385                         reset-names = "torrent_reset";
1386                         clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
1387                                  <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
1388                         clock-names = "refclk", "phy_en_refclk";
1389                         assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
1390                                           <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
1391                                           <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
1392                         assigned-clock-parents = <&k3_clks 365 3>,
1393                                                  <&k3_clks 365 3>,
1394                                                  <&k3_clks 365 3>;
1395                         #address-cells = <1>;
1396                         #size-cells = <0>;
1397                         #clock-cells = <1>;
1398
1399                         status = "disabled"; /* Needs lane config */
1400                 };
1401         };
1402
1403         pcie1_rc: pcie@2910000 {
1404                 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
1405                 reg = <0x00 0x02910000 0x00 0x1000>,
1406                       <0x00 0x02917000 0x00 0x400>,
1407                       <0x00 0x0d800000 0x00 0x800000>,
1408                       <0x00 0x18000000 0x00 0x1000>;
1409                 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
1410                 interrupt-names = "link_state";
1411                 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
1412                 device_type = "pci";
1413                 ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
1414                 max-link-speed = <3>;
1415                 num-lanes = <4>;
1416                 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
1417                 clocks = <&k3_clks 276 41>;
1418                 clock-names = "fck";
1419                 #address-cells = <3>;
1420                 #size-cells = <2>;
1421                 bus-range = <0x0 0xff>;
1422                 vendor-id = <0x104c>;
1423                 device-id = <0xb013>;
1424                 msi-map = <0x0 &gic_its 0x0 0x10000>;
1425                 dma-coherent;
1426                 ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
1427                          <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
1428                 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1429                 #interrupt-cells = <1>;
1430                 interrupt-map-mask = <0 0 0 7>;
1431                 interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
1432                                 <0 0 0 2 &pcie1_intc 0>, /* INT B */
1433                                 <0 0 0 3 &pcie1_intc 0>, /* INT C */
1434                                 <0 0 0 4 &pcie1_intc 0>; /* INT D */
1435
1436                 status = "disabled"; /* Needs gpio and serdes info */
1437
1438                 pcie1_intc: interrupt-controller {
1439                         interrupt-controller;
1440                         #interrupt-cells = <1>;
1441                         interrupt-parent = <&gic500>;
1442                         interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
1443                 };
1444         };
1445
1446         main_mcan0: can@2701000 {
1447                 compatible = "bosch,m_can";
1448                 reg = <0x00 0x02701000 0x00 0x200>,
1449                       <0x00 0x02708000 0x00 0x8000>;
1450                 reg-names = "m_can", "message_ram";
1451                 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1452                 clocks = <&k3_clks 182 0>, <&k3_clks 182 1>;
1453                 clock-names = "hclk", "cclk";
1454                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1455                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1456                 interrupt-names = "int0", "int1";
1457                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1458                 status = "disabled";
1459         };
1460
1461         main_mcan1: can@2711000 {
1462                 compatible = "bosch,m_can";
1463                 reg = <0x00 0x02711000 0x00 0x200>,
1464                       <0x00 0x02718000 0x00 0x8000>;
1465                 reg-names = "m_can", "message_ram";
1466                 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1467                 clocks = <&k3_clks 183 0>, <&k3_clks 183 1>;
1468                 clock-names = "hclk", "cclk";
1469                 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
1470                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
1471                 interrupt-names = "int0", "int1";
1472                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1473                 status = "disabled";
1474         };
1475
1476         main_mcan2: can@2721000 {
1477                 compatible = "bosch,m_can";
1478                 reg = <0x00 0x02721000 0x00 0x200>,
1479                       <0x00 0x02728000 0x00 0x8000>;
1480                 reg-names = "m_can", "message_ram";
1481                 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1482                 clocks = <&k3_clks 184 0>, <&k3_clks 184 1>;
1483                 clock-names = "hclk", "cclk";
1484                 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1485                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1486                 interrupt-names = "int0", "int1";
1487                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1488                 status = "disabled";
1489         };
1490
1491         main_mcan3: can@2731000 {
1492                 compatible = "bosch,m_can";
1493                 reg = <0x00 0x02731000 0x00 0x200>,
1494                       <0x00 0x02738000 0x00 0x8000>;
1495                 reg-names = "m_can", "message_ram";
1496                 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1497                 clocks = <&k3_clks 185 0>, <&k3_clks 185 1>;
1498                 clock-names = "hclk", "cclk";
1499                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1500                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
1501                 interrupt-names = "int0", "int1";
1502                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1503                 status = "disabled";
1504         };
1505
1506         main_mcan4: can@2741000 {
1507                 compatible = "bosch,m_can";
1508                 reg = <0x00 0x02741000 0x00 0x200>,
1509                       <0x00 0x02748000 0x00 0x8000>;
1510                 reg-names = "m_can", "message_ram";
1511                 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
1512                 clocks = <&k3_clks 186 0>, <&k3_clks 186 1>;
1513                 clock-names = "hclk", "cclk";
1514                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1515                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1516                 interrupt-names = "int0", "int1";
1517                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1518                 status = "disabled";
1519         };
1520
1521         main_mcan5: can@2751000 {
1522                 compatible = "bosch,m_can";
1523                 reg = <0x00 0x02751000 0x00 0x200>,
1524                       <0x00 0x02758000 0x00 0x8000>;
1525                 reg-names = "m_can", "message_ram";
1526                 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
1527                 clocks = <&k3_clks 187 0>, <&k3_clks 187 1>;
1528                 clock-names = "hclk", "cclk";
1529                 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
1530                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1531                 interrupt-names = "int0", "int1";
1532                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1533                 status = "disabled";
1534         };
1535
1536         main_mcan6: can@2761000 {
1537                 compatible = "bosch,m_can";
1538                 reg = <0x00 0x02761000 0x00 0x200>,
1539                       <0x00 0x02768000 0x00 0x8000>;
1540                 reg-names = "m_can", "message_ram";
1541                 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1542                 clocks = <&k3_clks 188 0>, <&k3_clks 188 1>;
1543                 clock-names = "hclk", "cclk";
1544                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1545                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1546                 interrupt-names = "int0", "int1";
1547                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1548                 status = "disabled";
1549         };
1550
1551         main_mcan7: can@2771000 {
1552                 compatible = "bosch,m_can";
1553                 reg = <0x00 0x02771000 0x00 0x200>,
1554                       <0x00 0x02778000 0x00 0x8000>;
1555                 reg-names = "m_can", "message_ram";
1556                 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1557                 clocks = <&k3_clks 189 0>, <&k3_clks 189 1>;
1558                 clock-names = "hclk", "cclk";
1559                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1560                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1561                 interrupt-names = "int0", "int1";
1562                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1563                 status = "disabled";
1564         };
1565
1566         main_mcan8: can@2781000 {
1567                 compatible = "bosch,m_can";
1568                 reg = <0x00 0x02781000 0x00 0x200>,
1569                       <0x00 0x02788000 0x00 0x8000>;
1570                 reg-names = "m_can", "message_ram";
1571                 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1572                 clocks = <&k3_clks 190 0>, <&k3_clks 190 1>;
1573                 clock-names = "hclk", "cclk";
1574                 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
1575                              <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
1576                 interrupt-names = "int0", "int1";
1577                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1578                 status = "disabled";
1579         };
1580
1581         main_mcan9: can@2791000 {
1582                 compatible = "bosch,m_can";
1583                 reg = <0x00 0x02791000 0x00 0x200>,
1584                       <0x00 0x02798000 0x00 0x8000>;
1585                 reg-names = "m_can", "message_ram";
1586                 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1587                 clocks = <&k3_clks 191 0>, <&k3_clks 191 1>;
1588                 clock-names = "hclk", "cclk";
1589                 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
1590                              <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
1591                 interrupt-names = "int0", "int1";
1592                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1593                 status = "disabled";
1594         };
1595
1596         main_mcan10: can@27a1000 {
1597                 compatible = "bosch,m_can";
1598                 reg = <0x00 0x027a1000 0x00 0x200>,
1599                       <0x00 0x027a8000 0x00 0x8000>;
1600                 reg-names = "m_can", "message_ram";
1601                 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1602                 clocks = <&k3_clks 192 0>, <&k3_clks 192 1>;
1603                 clock-names = "hclk", "cclk";
1604                 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
1605                              <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1606                 interrupt-names = "int0", "int1";
1607                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1608                 status = "disabled";
1609         };
1610
1611         main_mcan11: can@27b1000 {
1612                 compatible = "bosch,m_can";
1613                 reg = <0x00 0x027b1000 0x00 0x200>,
1614                       <0x00 0x027b8000 0x00 0x8000>;
1615                 reg-names = "m_can", "message_ram";
1616                 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1617                 clocks = <&k3_clks 193 0>, <&k3_clks 193 1>;
1618                 clock-names = "hclk", "cclk";
1619                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
1620                              <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1621                 interrupt-names = "int0", "int1";
1622                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1623                 status = "disabled";
1624         };
1625
1626         main_mcan12: can@27c1000 {
1627                 compatible = "bosch,m_can";
1628                 reg = <0x00 0x027c1000 0x00 0x200>,
1629                       <0x00 0x027c8000 0x00 0x8000>;
1630                 reg-names = "m_can", "message_ram";
1631                 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
1632                 clocks = <&k3_clks 194 0>, <&k3_clks 194 1>;
1633                 clock-names = "hclk", "cclk";
1634                 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1635                              <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
1636                 interrupt-names = "int0", "int1";
1637                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1638                 status = "disabled";
1639         };
1640
1641         main_mcan13: can@27d1000 {
1642                 compatible = "bosch,m_can";
1643                 reg = <0x00 0x027d1000 0x00 0x200>,
1644                       <0x00 0x027d8000 0x00 0x8000>;
1645                 reg-names = "m_can", "message_ram";
1646                 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
1647                 clocks = <&k3_clks 195 0>, <&k3_clks 195 1>;
1648                 clock-names = "hclk", "cclk";
1649                 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1650                              <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
1651                 interrupt-names = "int0", "int1";
1652                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1653                 status = "disabled";
1654         };
1655
1656         main_mcan14: can@2681000 {
1657                 compatible = "bosch,m_can";
1658                 reg = <0x00 0x02681000 0x00 0x200>,
1659                       <0x00 0x02688000 0x00 0x8000>;
1660                 reg-names = "m_can", "message_ram";
1661                 power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
1662                 clocks = <&k3_clks 197 0>, <&k3_clks 197 1>;
1663                 clock-names = "hclk", "cclk";
1664                 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1665                              <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
1666                 interrupt-names = "int0", "int1";
1667                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1668                 status = "disabled";
1669         };
1670
1671         main_mcan15: can@2691000 {
1672                 compatible = "bosch,m_can";
1673                 reg = <0x00 0x02691000 0x00 0x200>,
1674                       <0x00 0x02698000 0x00 0x8000>;
1675                 reg-names = "m_can", "message_ram";
1676                 power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>;
1677                 clocks = <&k3_clks 199 0>, <&k3_clks 199 1>;
1678                 clock-names = "hclk", "cclk";
1679                 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1680                              <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
1681                 interrupt-names = "int0", "int1";
1682                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1683                 status = "disabled";
1684         };
1685
1686         main_mcan16: can@26a1000 {
1687                 compatible = "bosch,m_can";
1688                 reg = <0x00 0x026a1000 0x00 0x200>,
1689                       <0x00 0x026a8000 0x00 0x8000>;
1690                 reg-names = "m_can", "message_ram";
1691                 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
1692                 clocks = <&k3_clks 201 0>, <&k3_clks 201 1>;
1693                 clock-names = "hclk", "cclk";
1694                 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
1695                              <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
1696                 interrupt-names = "int0", "int1";
1697                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1698                 status = "disabled";
1699         };
1700
1701         main_mcan17: can@26b1000 {
1702                 compatible = "bosch,m_can";
1703                 reg = <0x00 0x026b1000 0x00 0x200>,
1704                       <0x00 0x026b8000 0x00 0x8000>;
1705                 reg-names = "m_can", "message_ram";
1706                 power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>;
1707                 clocks = <&k3_clks 206 0>, <&k3_clks 206 1>;
1708                 clock-names = "hclk", "cclk";
1709                 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
1710                              <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
1711                 interrupt-names = "int0", "int1";
1712                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1713                 status = "disabled";
1714         };
1715
1716         main_spi0: spi@2100000 {
1717                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1718                 reg = <0x00 0x02100000 0x00 0x400>;
1719                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1720                 #address-cells = <1>;
1721                 #size-cells = <0>;
1722                 power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>;
1723                 clocks = <&k3_clks 339 1>;
1724                 status = "disabled";
1725         };
1726
1727         main_spi1: spi@2110000 {
1728                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1729                 reg = <0x00 0x02110000 0x00 0x400>;
1730                 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
1731                 #address-cells = <1>;
1732                 #size-cells = <0>;
1733                 power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>;
1734                 clocks = <&k3_clks 340 1>;
1735                 status = "disabled";
1736         };
1737
1738         main_spi2: spi@2120000 {
1739                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1740                 reg = <0x00 0x02120000 0x00 0x400>;
1741                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1742                 #address-cells = <1>;
1743                 #size-cells = <0>;
1744                 power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>;
1745                 clocks = <&k3_clks 341 1>;
1746                 status = "disabled";
1747         };
1748
1749         main_spi3: spi@2130000 {
1750                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1751                 reg = <0x00 0x02130000 0x00 0x400>;
1752                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1753                 #address-cells = <1>;
1754                 #size-cells = <0>;
1755                 power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>;
1756                 clocks = <&k3_clks 342 1>;
1757                 status = "disabled";
1758         };
1759
1760         main_spi4: spi@2140000 {
1761                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1762                 reg = <0x00 0x02140000 0x00 0x400>;
1763                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1764                 #address-cells = <1>;
1765                 #size-cells = <0>;
1766                 power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>;
1767                 clocks = <&k3_clks 343 1>;
1768                 status = "disabled";
1769         };
1770
1771         main_spi5: spi@2150000 {
1772                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1773                 reg = <0x00 0x02150000 0x00 0x400>;
1774                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1775                 #address-cells = <1>;
1776                 #size-cells = <0>;
1777                 power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>;
1778                 clocks = <&k3_clks 344 1>;
1779                 status = "disabled";
1780         };
1781
1782         main_spi6: spi@2160000 {
1783                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1784                 reg = <0x00 0x02160000 0x00 0x400>;
1785                 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1786                 #address-cells = <1>;
1787                 #size-cells = <0>;
1788                 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
1789                 clocks = <&k3_clks 345 1>;
1790                 status = "disabled";
1791         };
1792
1793         main_spi7: spi@2170000 {
1794                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1795                 reg = <0x00 0x02170000 0x00 0x400>;
1796                 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1797                 #address-cells = <1>;
1798                 #size-cells = <0>;
1799                 power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>;
1800                 clocks = <&k3_clks 346 1>;
1801                 status = "disabled";
1802         };
1803
1804         dss: dss@4a00000 {
1805                 compatible = "ti,j721e-dss";
1806                 reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1807                       <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1808                       <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1809                       <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1810                       <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1811                       <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1812                       <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1813                       <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1814                       <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1815                       <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1816                       <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1817                       <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1818                       <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1819                       <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1820                       <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1821                       <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1822                       <0x00 0x04af0000 0x00 0x10000>; /* wb */
1823                 reg-names = "common_m", "common_s0",
1824                             "common_s1", "common_s2",
1825                             "vidl1", "vidl2","vid1","vid2",
1826                             "ovr1", "ovr2", "ovr3", "ovr4",
1827                             "vp1", "vp2", "vp3", "vp4",
1828                             "wb";
1829                 clocks = <&k3_clks 158 0>,
1830                          <&k3_clks 158 2>,
1831                          <&k3_clks 158 5>,
1832                          <&k3_clks 158 14>,
1833                          <&k3_clks 158 18>;
1834                 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1835                 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
1836                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
1837                              <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
1838                              <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
1839                              <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1840                 interrupt-names = "common_m",
1841                                   "common_s0",
1842                                   "common_s1",
1843                                   "common_s2";
1844                 status = "disabled";
1845
1846                 dss_ports: ports {
1847                 };
1848         };
1849
1850         main_r5fss0: r5fss@5c00000 {
1851                 compatible = "ti,j721s2-r5fss";
1852                 ti,cluster-mode = <1>;
1853                 #address-cells = <1>;
1854                 #size-cells = <1>;
1855                 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1856                          <0x5d00000 0x00 0x5d00000 0x20000>;
1857                 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1858
1859                 main_r5fss0_core0: r5f@5c00000 {
1860                         compatible = "ti,j721s2-r5f";
1861                         reg = <0x5c00000 0x00010000>,
1862                               <0x5c10000 0x00010000>;
1863                         reg-names = "atcm", "btcm";
1864                         ti,sci = <&sms>;
1865                         ti,sci-dev-id = <279>;
1866                         ti,sci-proc-ids = <0x06 0xff>;
1867                         resets = <&k3_reset 279 1>;
1868                         firmware-name = "j721s2-main-r5f0_0-fw";
1869                         ti,atcm-enable = <1>;
1870                         ti,btcm-enable = <1>;
1871                         ti,loczrama = <1>;
1872                 };
1873
1874                 main_r5fss0_core1: r5f@5d00000 {
1875                         compatible = "ti,j721s2-r5f";
1876                         reg = <0x5d00000 0x00010000>,
1877                               <0x5d10000 0x00010000>;
1878                         reg-names = "atcm", "btcm";
1879                         ti,sci = <&sms>;
1880                         ti,sci-dev-id = <280>;
1881                         ti,sci-proc-ids = <0x07 0xff>;
1882                         resets = <&k3_reset 280 1>;
1883                         firmware-name = "j721s2-main-r5f0_1-fw";
1884                         ti,atcm-enable = <1>;
1885                         ti,btcm-enable = <1>;
1886                         ti,loczrama = <1>;
1887                 };
1888         };
1889
1890         main_r5fss1: r5fss@5e00000 {
1891                 compatible = "ti,j721s2-r5fss";
1892                 ti,cluster-mode = <1>;
1893                 #address-cells = <1>;
1894                 #size-cells = <1>;
1895                 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
1896                          <0x5f00000 0x00 0x5f00000 0x20000>;
1897                 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
1898
1899                 main_r5fss1_core0: r5f@5e00000 {
1900                         compatible = "ti,j721s2-r5f";
1901                         reg = <0x5e00000 0x00010000>,
1902                               <0x5e10000 0x00010000>;
1903                         reg-names = "atcm", "btcm";
1904                         ti,sci = <&sms>;
1905                         ti,sci-dev-id = <281>;
1906                         ti,sci-proc-ids = <0x08 0xff>;
1907                         resets = <&k3_reset 281 1>;
1908                         firmware-name = "j721s2-main-r5f1_0-fw";
1909                         ti,atcm-enable = <1>;
1910                         ti,btcm-enable = <1>;
1911                         ti,loczrama = <1>;
1912                 };
1913
1914                 main_r5fss1_core1: r5f@5f00000 {
1915                         compatible = "ti,j721s2-r5f";
1916                         reg = <0x5f00000 0x00010000>,
1917                               <0x5f10000 0x00010000>;
1918                         reg-names = "atcm", "btcm";
1919                         ti,sci = <&sms>;
1920                         ti,sci-dev-id = <282>;
1921                         ti,sci-proc-ids = <0x09 0xff>;
1922                         resets = <&k3_reset 282 1>;
1923                         firmware-name = "j721s2-main-r5f1_1-fw";
1924                         ti,atcm-enable = <1>;
1925                         ti,btcm-enable = <1>;
1926                         ti,loczrama = <1>;
1927                 };
1928         };
1929
1930         c71_0: dsp@64800000 {
1931                 compatible = "ti,j721s2-c71-dsp";
1932                 reg = <0x00 0x64800000 0x00 0x00080000>,
1933                       <0x00 0x64e00000 0x00 0x0000c000>;
1934                 reg-names = "l2sram", "l1dram";
1935                 ti,sci = <&sms>;
1936                 ti,sci-dev-id = <8>;
1937                 ti,sci-proc-ids = <0x30 0xff>;
1938                 resets = <&k3_reset 8 1>;
1939                 firmware-name = "j721s2-c71_0-fw";
1940                 status = "disabled";
1941         };
1942
1943         c71_1: dsp@65800000 {
1944                 compatible = "ti,j721s2-c71-dsp";
1945                 reg = <0x00 0x65800000 0x00 0x00080000>,
1946                       <0x00 0x65e00000 0x00 0x0000c000>;
1947                 reg-names = "l2sram", "l1dram";
1948                 ti,sci = <&sms>;
1949                 ti,sci-dev-id = <11>;
1950                 ti,sci-proc-ids = <0x31 0xff>;
1951                 resets = <&k3_reset 11 1>;
1952                 firmware-name = "j721s2-c71_1-fw";
1953                 status = "disabled";
1954         };
1955
1956         main_esm: esm@700000 {
1957                 compatible = "ti,j721e-esm";
1958                 reg = <0x00 0x700000 0x00 0x1000>;
1959                 ti,esm-pins = <688>, <689>;
1960                 bootph-pre-ram;
1961         };
1962
1963         watchdog0: watchdog@2200000 {
1964                 compatible = "ti,j7-rti-wdt";
1965                 reg = <0x00 0x2200000 0x00 0x100>;
1966                 clocks = <&k3_clks 286 1>;
1967                 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
1968                 assigned-clocks = <&k3_clks 286 1>;
1969                 assigned-clock-parents = <&k3_clks 286 5>;
1970         };
1971
1972         watchdog1: watchdog@2210000 {
1973                 compatible = "ti,j7-rti-wdt";
1974                 reg = <0x00 0x2210000 0x00 0x100>;
1975                 clocks = <&k3_clks 287 1>;
1976                 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
1977                 assigned-clocks = <&k3_clks 287 1>;
1978                 assigned-clock-parents = <&k3_clks 287 5>;
1979         };
1980
1981         /*
1982          * The following RTI instances are coupled with MCU R5Fs, c7x and
1983          * GPU so keeping them reserved as these will be used by their
1984          * respective firmware
1985          */
1986         watchdog2: watchdog@22f0000 {
1987                 compatible = "ti,j7-rti-wdt";
1988                 reg = <0x00 0x22f0000 0x00 0x100>;
1989                 clocks = <&k3_clks 290 1>;
1990                 power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>;
1991                 assigned-clocks = <&k3_clks 290 1>;
1992                 assigned-clock-parents = <&k3_clks 290 5>;
1993                 /* reserved for GPU */
1994                 status = "reserved";
1995         };
1996
1997         watchdog3: watchdog@2300000 {
1998                 compatible = "ti,j7-rti-wdt";
1999                 reg = <0x00 0x2300000 0x00 0x100>;
2000                 clocks = <&k3_clks 288 1>;
2001                 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
2002                 assigned-clocks = <&k3_clks 288 1>;
2003                 assigned-clock-parents = <&k3_clks 288 5>;
2004                 /* reserved for C7X_0 */
2005                 status = "reserved";
2006         };
2007
2008         watchdog4: watchdog@2310000 {
2009                 compatible = "ti,j7-rti-wdt";
2010                 reg = <0x00 0x2310000 0x00 0x100>;
2011                 clocks = <&k3_clks 289 1>;
2012                 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
2013                 assigned-clocks = <&k3_clks 289 1>;
2014                 assigned-clock-parents = <&k3_clks 289 5>;
2015                 /* reserved for C7X_1 */
2016                 status = "reserved";
2017         };
2018
2019         watchdog5: watchdog@23c0000 {
2020                 compatible = "ti,j7-rti-wdt";
2021                 reg = <0x00 0x23c0000 0x00 0x100>;
2022                 clocks = <&k3_clks 291 1>;
2023                 power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>;
2024                 assigned-clocks = <&k3_clks 291 1>;
2025                 assigned-clock-parents = <&k3_clks 291 5>;
2026                 /* reserved for MAIN_R5F0_0 */
2027                 status = "reserved";
2028         };
2029
2030         watchdog6: watchdog@23d0000 {
2031                 compatible = "ti,j7-rti-wdt";
2032                 reg = <0x00 0x23d0000 0x00 0x100>;
2033                 clocks = <&k3_clks 292 1>;
2034                 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
2035                 assigned-clocks = <&k3_clks 292 1>;
2036                 assigned-clock-parents = <&k3_clks 292 5>;
2037                 /* reserved for MAIN_R5F0_1 */
2038                 status = "reserved";
2039         };
2040
2041         watchdog7: watchdog@23e0000 {
2042                 compatible = "ti,j7-rti-wdt";
2043                 reg = <0x00 0x23e0000 0x00 0x100>;
2044                 clocks = <&k3_clks 293 1>;
2045                 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
2046                 assigned-clocks = <&k3_clks 293 1>;
2047                 assigned-clock-parents = <&k3_clks 293 5>;
2048                 /* reserved for MAIN_R5F1_0 */
2049                 status = "reserved";
2050         };
2051
2052         watchdog8: watchdog@23f0000 {
2053                 compatible = "ti,j7-rti-wdt";
2054                 reg = <0x00 0x23f0000 0x00 0x100>;
2055                 clocks = <&k3_clks 294 1>;
2056                 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
2057                 assigned-clocks = <&k3_clks 294 1>;
2058                 assigned-clock-parents = <&k3_clks 294 5>;
2059                 /* reserved for MAIN_R5F1_1 */
2060                 status = "reserved";
2061         };
2062 };