1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <uapi/asm/svm.h>
6 #include <uapi/asm/kvm.h>
9 * 32-bit intercept words in the VMCB Control Area, starting
10 * at Byte offset 000h.
13 enum intercept_words {
24 /* Byte offset 000h (word 0) */
25 INTERCEPT_CR0_READ = 0,
26 INTERCEPT_CR3_READ = 3,
27 INTERCEPT_CR4_READ = 4,
28 INTERCEPT_CR8_READ = 8,
29 INTERCEPT_CR0_WRITE = 16,
30 INTERCEPT_CR3_WRITE = 16 + 3,
31 INTERCEPT_CR4_WRITE = 16 + 4,
32 INTERCEPT_CR8_WRITE = 16 + 8,
33 /* Byte offset 004h (word 1) */
34 INTERCEPT_DR0_READ = 32,
42 INTERCEPT_DR0_WRITE = 48,
50 /* Byte offset 008h (word 2) */
51 INTERCEPT_EXCEPTION_OFFSET = 64,
52 /* Byte offset 00Ch (word 3) */
58 INTERCEPT_SELECTIVE_CR0,
82 INTERCEPT_TASK_SWITCH,
83 INTERCEPT_FERR_FREEZE,
85 /* Byte offset 010h (word 4) */
86 INTERCEPT_VMRUN = 128,
111 /* Byte offset 014h (word 5) */
112 INTERCEPT_INVLPGB = 160,
113 INTERCEPT_INVLPGB_ILLEGAL,
120 struct __attribute__ ((__packed__)) vmcb_control_area {
121 u32 intercepts[MAX_INTERCEPT];
122 u32 reserved_1[15 - MAX_INTERCEPT];
123 u16 pause_filter_thresh;
124 u16 pause_filter_count;
140 u32 exit_int_info_err;
153 u64 avic_backing_page; /* Offset 0xe0 */
154 u8 reserved_6[8]; /* Offset 0xe8 */
155 u64 avic_logical_id; /* Offset 0xf0 */
156 u64 avic_physical_id; /* Offset 0xf8 */
158 u64 vmsa_pa; /* Used for an SEV-ES guest */
161 * Offset 0x3e0, 32 bytes reserved
162 * for use by hypervisor/software.
168 #define TLB_CONTROL_DO_NOTHING 0
169 #define TLB_CONTROL_FLUSH_ALL_ASID 1
170 #define TLB_CONTROL_FLUSH_ASID 3
171 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
173 #define V_TPR_MASK 0x0f
175 #define V_IRQ_SHIFT 8
176 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
178 #define V_GIF_SHIFT 9
179 #define V_GIF_MASK (1 << V_GIF_SHIFT)
181 #define V_INTR_PRIO_SHIFT 16
182 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
184 #define V_IGN_TPR_SHIFT 20
185 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
187 #define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK | V_INTR_PRIO_MASK | V_IGN_TPR_MASK)
189 #define V_INTR_MASKING_SHIFT 24
190 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
192 #define V_GIF_ENABLE_SHIFT 25
193 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
195 #define AVIC_ENABLE_SHIFT 31
196 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
198 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
199 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
201 #define SVM_INTERRUPT_SHADOW_MASK BIT_ULL(0)
202 #define SVM_GUEST_INTERRUPT_MASK BIT_ULL(1)
204 #define SVM_IOIO_STR_SHIFT 2
205 #define SVM_IOIO_REP_SHIFT 3
206 #define SVM_IOIO_SIZE_SHIFT 4
207 #define SVM_IOIO_ASIZE_SHIFT 7
209 #define SVM_IOIO_TYPE_MASK 1
210 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
211 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
212 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
213 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
215 #define SVM_VM_CR_VALID_MASK 0x001fULL
216 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
217 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
219 #define SVM_NESTED_CTL_NP_ENABLE BIT(0)
220 #define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
221 #define SVM_NESTED_CTL_SEV_ES_ENABLE BIT(2)
224 #define SVM_TSC_RATIO_RSVD 0xffffff0000000000ULL
225 #define SVM_TSC_RATIO_MIN 0x0000000000000001ULL
226 #define SVM_TSC_RATIO_MAX 0x000000ffffffffffULL
227 #define SVM_TSC_RATIO_DEFAULT 0x0100000000ULL
231 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFFULL)
232 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31
233 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
235 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK GENMASK_ULL(11, 0)
236 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
237 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
238 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
239 #define AVIC_PHYSICAL_ID_TABLE_SIZE_MASK (0xFFULL)
241 #define AVIC_DOORBELL_PHYSICAL_ID_MASK GENMASK_ULL(11, 0)
243 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
245 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
246 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
247 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
249 enum avic_ipi_failure_cause {
250 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
251 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
252 AVIC_IPI_FAILURE_INVALID_TARGET,
253 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
258 * 0xff is broadcast, so the max index allowed for physical APIC ID
259 * table is 0xfe. APIC IDs above 0xff are reserved.
261 #define AVIC_MAX_PHYSICAL_ID_COUNT 0xff
263 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
264 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
274 /* Save area definition for legacy and SEV-MEM guests */
275 struct vmcb_save_area {
282 struct vmcb_seg gdtr;
283 struct vmcb_seg ldtr;
284 struct vmcb_seg idtr;
322 u32 spec_ctrl; /* Guest version of SPEC_CTRL at 0x2E0 */
325 /* Save area definition for SEV-ES and SEV-SNP guests */
326 struct sev_es_save_area {
333 struct vmcb_seg gdtr;
334 struct vmcb_seg ldtr;
335 struct vmcb_seg idtr;
373 u64 reserved_10; /* rax already available at 0x01f8 */
377 u64 reserved_11; /* rsp already available at 0x01d8 */
401 #define GHCB_SHARED_BUF_SIZE 2032
404 struct sev_es_save_area save;
405 u8 reserved_save[2048 - sizeof(struct sev_es_save_area)];
407 u8 shared_buffer[GHCB_SHARED_BUF_SIZE];
410 u16 protocol_version; /* negotiated SEV-ES/GHCB protocol version */
415 #define EXPECTED_VMCB_SAVE_AREA_SIZE 740
416 #define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1032
417 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 1024
418 #define EXPECTED_GHCB_SIZE PAGE_SIZE
420 static inline void __unused_size_checks(void)
422 BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE);
423 BUILD_BUG_ON(sizeof(struct sev_es_save_area) != EXPECTED_SEV_ES_SAVE_AREA_SIZE);
424 BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE);
425 BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE);
429 struct vmcb_control_area control;
430 struct vmcb_save_area save;
433 #define SVM_CPUID_FUNC 0x8000000a
435 #define SVM_VM_CR_SVM_DISABLE 4
437 #define SVM_SELECTOR_S_SHIFT 4
438 #define SVM_SELECTOR_DPL_SHIFT 5
439 #define SVM_SELECTOR_P_SHIFT 7
440 #define SVM_SELECTOR_AVL_SHIFT 8
441 #define SVM_SELECTOR_L_SHIFT 9
442 #define SVM_SELECTOR_DB_SHIFT 10
443 #define SVM_SELECTOR_G_SHIFT 11
445 #define SVM_SELECTOR_TYPE_MASK (0xf)
446 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
447 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
448 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
449 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
450 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
451 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
452 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
454 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
455 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
456 #define SVM_SELECTOR_CODE_MASK (1 << 3)
458 #define SVM_EVTINJ_VEC_MASK 0xff
460 #define SVM_EVTINJ_TYPE_SHIFT 8
461 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
463 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
464 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
465 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
466 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
468 #define SVM_EVTINJ_VALID (1 << 31)
469 #define SVM_EVTINJ_VALID_ERR (1 << 11)
471 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
472 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
474 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
475 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
476 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
477 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
479 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
480 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
482 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
483 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
484 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
486 #define SVM_EXITINFO_REG_MASK 0x0F
488 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
490 /* GHCB Accessor functions */
492 #define GHCB_BITMAP_IDX(field) \
493 (offsetof(struct sev_es_save_area, field) / sizeof(u64))
495 #define DEFINE_GHCB_ACCESSORS(field) \
496 static inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \
498 return test_bit(GHCB_BITMAP_IDX(field), \
499 (unsigned long *)&ghcb->save.valid_bitmap); \
502 static inline u64 ghcb_get_##field(struct ghcb *ghcb) \
504 return ghcb->save.field; \
507 static inline u64 ghcb_get_##field##_if_valid(struct ghcb *ghcb) \
509 return ghcb_##field##_is_valid(ghcb) ? ghcb->save.field : 0; \
512 static inline void ghcb_set_##field(struct ghcb *ghcb, u64 value) \
514 __set_bit(GHCB_BITMAP_IDX(field), \
515 (unsigned long *)&ghcb->save.valid_bitmap); \
516 ghcb->save.field = value; \
519 DEFINE_GHCB_ACCESSORS(cpl)
520 DEFINE_GHCB_ACCESSORS(rip)
521 DEFINE_GHCB_ACCESSORS(rsp)
522 DEFINE_GHCB_ACCESSORS(rax)
523 DEFINE_GHCB_ACCESSORS(rcx)
524 DEFINE_GHCB_ACCESSORS(rdx)
525 DEFINE_GHCB_ACCESSORS(rbx)
526 DEFINE_GHCB_ACCESSORS(rbp)
527 DEFINE_GHCB_ACCESSORS(rsi)
528 DEFINE_GHCB_ACCESSORS(rdi)
529 DEFINE_GHCB_ACCESSORS(r8)
530 DEFINE_GHCB_ACCESSORS(r9)
531 DEFINE_GHCB_ACCESSORS(r10)
532 DEFINE_GHCB_ACCESSORS(r11)
533 DEFINE_GHCB_ACCESSORS(r12)
534 DEFINE_GHCB_ACCESSORS(r13)
535 DEFINE_GHCB_ACCESSORS(r14)
536 DEFINE_GHCB_ACCESSORS(r15)
537 DEFINE_GHCB_ACCESSORS(sw_exit_code)
538 DEFINE_GHCB_ACCESSORS(sw_exit_info_1)
539 DEFINE_GHCB_ACCESSORS(sw_exit_info_2)
540 DEFINE_GHCB_ACCESSORS(sw_scratch)
541 DEFINE_GHCB_ACCESSORS(xcr0)