arch/x86/kernel/cpu/common.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* cpu_feature_enabled() cannot be used this early */
   3 #define USE_EARLY_PGTABLE_L5
   4
   5 #include <linux/memblock.h>
   6 #include <linux/linkage.h>
   7 #include <linux/bitops.h>
   8 #include <linux/kernel.h>
   9 #include <linux/export.h>
  10 #include <linux/percpu.h>
  11 #include <linux/string.h>
  12 #include <linux/ctype.h>
  13 #include <linux/delay.h>
  14 #include <linux/sched/mm.h>
  15 #include <linux/sched/clock.h>
  16 #include <linux/sched/task.h>
  17 #include <linux/sched/smt.h>
  18 #include <linux/init.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/kgdb.h>
  21 #include <linux/mem_encrypt.h>
  22 #include <linux/smp.h>
  23 #include <linux/cpu.h>
  24 #include <linux/io.h>
  25 #include <linux/syscore_ops.h>
  26 #include <linux/pgtable.h>
  27 #include <linux/stackprotector.h>
  28 #include <linux/utsname.h>
  29
  30 #include <asm/alternative.h>
  31 #include <asm/cmdline.h>
  32 #include <asm/perf_event.h>
  33 #include <asm/mmu_context.h>
  34 #include <asm/doublefault.h>
  35 #include <asm/archrandom.h>
  36 #include <asm/hypervisor.h>
  37 #include <asm/processor.h>
  38 #include <asm/tlbflush.h>
  39 #include <asm/debugreg.h>
  40 #include <asm/sections.h>
  41 #include <asm/vsyscall.h>
  42 #include <linux/topology.h>
  43 #include <linux/cpumask.h>
  44 #include <linux/atomic.h>
  45 #include <asm/proto.h>
  46 #include <asm/setup.h>
  47 #include <asm/apic.h>
  48 #include <asm/desc.h>
  49 #include <asm/fpu/api.h>
  50 #include <asm/mtrr.h>
  51 #include <asm/hwcap2.h>
  52 #include <linux/numa.h>
  53 #include <asm/numa.h>
  54 #include <asm/asm.h>
  55 #include <asm/bugs.h>
  56 #include <asm/cpu.h>
  57 #include <asm/mce.h>
  58 #include <asm/msr.h>
  59 #include <asm/cacheinfo.h>
  60 #include <asm/memtype.h>
  61 #include <asm/microcode.h>
  62 #include <asm/intel-family.h>
  63 #include <asm/cpu_device_id.h>
  64 #include <asm/uv/uv.h>
  65 #include <asm/ia32.h>
  66 #include <asm/set_memory.h>
  67 #include <asm/traps.h>
  68 #include <asm/sev.h>
  69 #include <asm/tdx.h>
  70
  71 #include "cpu.h"
  72
  73 u32 elf_hwcap2 __read_mostly;
  74
  75 /* Number of siblings per CPU package */
  76 unsigned int smp_num_siblings __ro_after_init = 1;
  77 EXPORT_SYMBOL(smp_num_siblings);
  78
  79 unsigned int __max_dies_per_package __ro_after_init = 1;
  80 EXPORT_SYMBOL(__max_dies_per_package);
  81
  82 unsigned int __max_logical_packages __ro_after_init = 1;
  83 EXPORT_SYMBOL(__max_logical_packages);
  84
  85 static struct ppin_info {
  86         int     feature;
  87         int     msr_ppin_ctl;
  88         int     msr_ppin;
  89 } ppin_info[] = {
  90         [X86_VENDOR_INTEL] = {
  91                 .feature = X86_FEATURE_INTEL_PPIN,
  92                 .msr_ppin_ctl = MSR_PPIN_CTL,
  93                 .msr_ppin = MSR_PPIN
  94         },
  95         [X86_VENDOR_AMD] = {
  96                 .feature = X86_FEATURE_AMD_PPIN,
  97                 .msr_ppin_ctl = MSR_AMD_PPIN_CTL,
  98                 .msr_ppin = MSR_AMD_PPIN
  99         },
 100 };
 101
 102 static const struct x86_cpu_id ppin_cpuids[] = {
 103         X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]),
 104         X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]),
 105
 106         /* Legacy models without CPUID enumeration */
 107         X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]),
 108         X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &ppin_info[X86_VENDOR_INTEL]),
 109         X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]),
 110         X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]),
 111         X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]),
 112         X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]),
 113         X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]),
 114         X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]),
 115         X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &ppin_info[X86_VENDOR_INTEL]),
 116         X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]),
 117         X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]),
 118
 119         {}
 120 };
 121
 122 static void ppin_init(struct cpuinfo_x86 *c)
 123 {
 124         const struct x86_cpu_id *id;
 125         unsigned long long val;
 126         struct ppin_info *info;
 127
 128         id = x86_match_cpu(ppin_cpuids);
 129         if (!id)
 130                 return;
 131
 132         /*
 133          * Testing the presence of the MSR is not enough. Need to check
 134          * that the PPIN_CTL allows reading of the PPIN.
 135          */
 136         info = (struct ppin_info *)id->driver_data;
 137
 138         if (rdmsrl_safe(info->msr_ppin_ctl, &val))
 139                 goto clear_ppin;
 140
 141         if ((val & 3UL) == 1UL) {
 142                 /* PPIN locked in disabled mode */
 143                 goto clear_ppin;
 144         }
 145
 146         /* If PPIN is disabled, try to enable */
 147         if (!(val & 2UL)) {
 148                 wrmsrl_safe(info->msr_ppin_ctl,  val | 2UL);
 149                 rdmsrl_safe(info->msr_ppin_ctl, &val);
 150         }
 151
 152         /* Is the enable bit set? */
 153         if (val & 2UL) {
 154                 c->ppin = __rdmsr(info->msr_ppin);
 155                 set_cpu_cap(c, info->feature);
 156                 return;
 157         }
 158
 159 clear_ppin:
 160         clear_cpu_cap(c, info->feature);
 161 }
 162
 163 static void default_init(struct cpuinfo_x86 *c)
 164 {
 165 #ifdef CONFIG_X86_64
 166         cpu_detect_cache_sizes(c);
 167 #else
 168         /* Not much we can do here... */
 169         /* Check if at least it has cpuid */
 170         if (c->cpuid_level == -1) {
 171                 /* No cpuid. It must be an ancient CPU */
 172                 if (c->x86 == 4)
 173                         strcpy(c->x86_model_id, "486");
 174                 else if (c->x86 == 3)
 175                         strcpy(c->x86_model_id, "386");
 176         }
 177 #endif
 178 }
 179
 180 static const struct cpu_dev default_cpu = {
 181         .c_init         = default_init,
 182         .c_vendor       = "Unknown",
 183         .c_x86_vendor   = X86_VENDOR_UNKNOWN,
 184 };
 185
 186 static const struct cpu_dev *this_cpu = &default_cpu;
 187
 188 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
 189 #ifdef CONFIG_X86_64
 190         /*
 191          * We need valid kernel segments for data and code in long mode too
 192          * IRET will check the segment types  kkeil 2000/10/28
 193          * Also sysret mandates a special GDT layout
 194          *
 195          * TLS descriptors are currently at a different place compared to i386.
 196          * Hopefully nobody expects them at a fixed place (Wine?)
 197          */
 198         [GDT_ENTRY_KERNEL32_CS]         = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff),
 199         [GDT_ENTRY_KERNEL_CS]           = GDT_ENTRY_INIT(DESC_CODE64, 0, 0xfffff),
 200         [GDT_ENTRY_KERNEL_DS]           = GDT_ENTRY_INIT(DESC_DATA64, 0, 0xfffff),
 201         [GDT_ENTRY_DEFAULT_USER32_CS]   = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff),
 202         [GDT_ENTRY_DEFAULT_USER_DS]     = GDT_ENTRY_INIT(DESC_DATA64 | DESC_USER, 0, 0xfffff),
 203         [GDT_ENTRY_DEFAULT_USER_CS]     = GDT_ENTRY_INIT(DESC_CODE64 | DESC_USER, 0, 0xfffff),
 204 #else
 205         [GDT_ENTRY_KERNEL_CS]           = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff),
 206         [GDT_ENTRY_KERNEL_DS]           = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff),
 207         [GDT_ENTRY_DEFAULT_USER_CS]     = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff),
 208         [GDT_ENTRY_DEFAULT_USER_DS]     = GDT_ENTRY_INIT(DESC_DATA32 | DESC_USER, 0, 0xfffff),
 209         /*
 210          * Segments used for calling PnP BIOS have byte granularity.
 211          * They code segments and data segments have fixed 64k limits,
 212          * the transfer segment sizes are set at run time.
 213          */
 214         [GDT_ENTRY_PNPBIOS_CS32]        = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff),
 215         [GDT_ENTRY_PNPBIOS_CS16]        = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff),
 216         [GDT_ENTRY_PNPBIOS_DS]          = GDT_ENTRY_INIT(DESC_DATA16, 0, 0xffff),
 217         [GDT_ENTRY_PNPBIOS_TS1]         = GDT_ENTRY_INIT(DESC_DATA16, 0, 0),
 218         [GDT_ENTRY_PNPBIOS_TS2]         = GDT_ENTRY_INIT(DESC_DATA16, 0, 0),
 219         /*
 220          * The APM segments have byte granularity and their bases
 221          * are set at run time.  All have 64k limits.
 222          */
 223         [GDT_ENTRY_APMBIOS_BASE]        = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff),
 224         [GDT_ENTRY_APMBIOS_BASE+1]      = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff),
 225         [GDT_ENTRY_APMBIOS_BASE+2]      = GDT_ENTRY_INIT(DESC_DATA32_BIOS, 0, 0xffff),
 226
 227         [GDT_ENTRY_ESPFIX_SS]           = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff),
 228         [GDT_ENTRY_PERCPU]              = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff),
 229 #endif
 230 } };
 231 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
 232
 233 #ifdef CONFIG_X86_64
 234 static int __init x86_nopcid_setup(char *s)
 235 {
 236         /* nopcid doesn't accept parameters */
 237         if (s)
 238                 return -EINVAL;
 239
 240         /* do not emit a message if the feature is not present */
 241         if (!boot_cpu_has(X86_FEATURE_PCID))
 242                 return 0;
 243
 244         setup_clear_cpu_cap(X86_FEATURE_PCID);
 245         pr_info("nopcid: PCID feature disabled\n");
 246         return 0;
 247 }
 248 early_param("nopcid", x86_nopcid_setup);
 249 #endif
 250
 251 static int __init x86_noinvpcid_setup(char *s)
 252 {
 253         /* noinvpcid doesn't accept parameters */
 254         if (s)
 255                 return -EINVAL;
 256
 257         /* do not emit a message if the feature is not present */
 258         if (!boot_cpu_has(X86_FEATURE_INVPCID))
 259                 return 0;
 260
 261         setup_clear_cpu_cap(X86_FEATURE_INVPCID);
 262         pr_info("noinvpcid: INVPCID feature disabled\n");
 263         return 0;
 264 }
 265 early_param("noinvpcid", x86_noinvpcid_setup);
 266
 267 #ifdef CONFIG_X86_32
 268 static int cachesize_override = -1;
 269 static int disable_x86_serial_nr = 1;
 270
 271 static int __init cachesize_setup(char *str)
 272 {
 273         get_option(&str, &cachesize_override);
 274         return 1;
 275 }
 276 __setup("cachesize=", cachesize_setup);
 277
 278 /* Standard macro to see if a specific flag is changeable */
 279 static inline int flag_is_changeable_p(u32 flag)
 280 {
 281         u32 f1, f2;
 282
 283         /*
 284          * Cyrix and IDT cpus allow disabling of CPUID
 285          * so the code below may return different results
 286          * when it is executed before and after enabling
 287          * the CPUID. Add "volatile" to not allow gcc to
 288          * optimize the subsequent calls to this function.
 289          */
 290         asm volatile ("pushfl           \n\t"
 291                       "pushfl           \n\t"
 292                       "popl %0          \n\t"
 293                       "movl %0, %1      \n\t"
 294                       "xorl %2, %0      \n\t"
 295                       "pushl %0         \n\t"
 296                       "popfl            \n\t"
 297                       "pushfl           \n\t"
 298                       "popl %0          \n\t"
 299                       "popfl            \n\t"
 300
 301                       : "=&r" (f1), "=&r" (f2)
 302                       : "ir" (flag));
 303
 304         return ((f1^f2) & flag) != 0;
 305 }
 306
 307 /* Probe for the CPUID instruction */
 308 int have_cpuid_p(void)
 309 {
 310         return flag_is_changeable_p(X86_EFLAGS_ID);
 311 }
 312
 313 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
 314 {
 315         unsigned long lo, hi;
 316
 317         if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
 318                 return;
 319
 320         /* Disable processor serial number: */
 321
 322         rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
 323         lo |= 0x200000;
 324         wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
 325
 326         pr_notice("CPU serial number disabled.\n");
 327         clear_cpu_cap(c, X86_FEATURE_PN);
 328
 329         /* Disabling the serial number may affect the cpuid level */
 330         c->cpuid_level = cpuid_eax(0);
 331 }
 332
 333 static int __init x86_serial_nr_setup(char *s)
 334 {
 335         disable_x86_serial_nr = 0;
 336         return 1;
 337 }
 338 __setup("serialnumber", x86_serial_nr_setup);
 339 #else
 340 static inline int flag_is_changeable_p(u32 flag)
 341 {
 342         return 1;
 343 }
 344 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
 345 {
 346 }
 347 #endif
 348
 349 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
 350 {
 351         if (cpu_has(c, X86_FEATURE_SMEP))
 352                 cr4_set_bits(X86_CR4_SMEP);
 353 }
 354
 355 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
 356 {
 357         unsigned long eflags = native_save_fl();
 358
 359         /* This should have been cleared long ago */
 360         BUG_ON(eflags & X86_EFLAGS_AC);
 361
 362         if (cpu_has(c, X86_FEATURE_SMAP))
 363                 cr4_set_bits(X86_CR4_SMAP);
 364 }
 365
 366 static __always_inline void setup_umip(struct cpuinfo_x86 *c)
 367 {
 368         /* Check the boot processor, plus build option for UMIP. */
 369         if (!cpu_feature_enabled(X86_FEATURE_UMIP))
 370                 goto out;
 371
 372         /* Check the current processor's cpuid bits. */
 373         if (!cpu_has(c, X86_FEATURE_UMIP))
 374                 goto out;
 375
 376         cr4_set_bits(X86_CR4_UMIP);
 377
 378         pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
 379
 380         return;
 381
 382 out:
 383         /*
 384          * Make sure UMIP is disabled in case it was enabled in a
 385          * previous boot (e.g., via kexec).
 386          */
 387         cr4_clear_bits(X86_CR4_UMIP);
 388 }
 389
 390 /* These bits should not change their value after CPU init is finished. */
 391 static const unsigned long cr4_pinned_mask =
 392         X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP |
 393         X86_CR4_FSGSBASE | X86_CR4_CET;
 394 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning);
 395 static unsigned long cr4_pinned_bits __ro_after_init;
 396
 397 void native_write_cr0(unsigned long val)
 398 {
 399         unsigned long bits_missing = 0;
 400
 401 set_register:
 402         asm volatile("mov %0,%%cr0": "+r" (val) : : "memory");
 403
 404         if (static_branch_likely(&cr_pinning)) {
 405                 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) {
 406                         bits_missing = X86_CR0_WP;
 407                         val |= bits_missing;
 408                         goto set_register;
 409                 }
 410                 /* Warn after we've set the missing bits. */
 411                 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n");
 412         }
 413 }
 414 EXPORT_SYMBOL(native_write_cr0);
 415
 416 void __no_profile native_write_cr4(unsigned long val)
 417 {
 418         unsigned long bits_changed = 0;
 419
 420 set_register:
 421         asm volatile("mov %0,%%cr4": "+r" (val) : : "memory");
 422
 423         if (static_branch_likely(&cr_pinning)) {
 424                 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) {
 425                         bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits;
 426                         val = (val & ~cr4_pinned_mask) | cr4_pinned_bits;
 427                         goto set_register;
 428                 }
 429                 /* Warn after we've corrected the changed bits. */
 430                 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n",
 431                           bits_changed);
 432         }
 433 }
 434 #if IS_MODULE(CONFIG_LKDTM)
 435 EXPORT_SYMBOL_GPL(native_write_cr4);
 436 #endif
 437
 438 void cr4_update_irqsoff(unsigned long set, unsigned long clear)
 439 {
 440         unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
 441
 442         lockdep_assert_irqs_disabled();
 443
 444         newval = (cr4 & ~clear) | set;
 445         if (newval != cr4) {
 446                 this_cpu_write(cpu_tlbstate.cr4, newval);
 447                 __write_cr4(newval);
 448         }
 449 }
 450 EXPORT_SYMBOL(cr4_update_irqsoff);
 451
 452 /* Read the CR4 shadow. */
 453 unsigned long cr4_read_shadow(void)
 454 {
 455         return this_cpu_read(cpu_tlbstate.cr4);
 456 }
 457 EXPORT_SYMBOL_GPL(cr4_read_shadow);
 458
 459 void cr4_init(void)
 460 {
 461         unsigned long cr4 = __read_cr4();
 462
 463         if (boot_cpu_has(X86_FEATURE_PCID))
 464                 cr4 |= X86_CR4_PCIDE;
 465         if (static_branch_likely(&cr_pinning))
 466                 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits;
 467
 468         __write_cr4(cr4);
 469
 470         /* Initialize cr4 shadow for this CPU. */
 471         this_cpu_write(cpu_tlbstate.cr4, cr4);
 472 }
 473
 474 /*
 475  * Once CPU feature detection is finished (and boot params have been
 476  * parsed), record any of the sensitive CR bits that are set, and
 477  * enable CR pinning.
 478  */
 479 static void __init setup_cr_pinning(void)
 480 {
 481         cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask;
 482         static_key_enable(&cr_pinning.key);
 483 }
 484
 485 static __init int x86_nofsgsbase_setup(char *arg)
 486 {
 487         /* Require an exact match without trailing characters. */
 488         if (strlen(arg))
 489                 return 0;
 490
 491         /* Do not emit a message if the feature is not present. */
 492         if (!boot_cpu_has(X86_FEATURE_FSGSBASE))
 493                 return 1;
 494
 495         setup_clear_cpu_cap(X86_FEATURE_FSGSBASE);
 496         pr_info("FSGSBASE disabled via kernel command line\n");
 497         return 1;
 498 }
 499 __setup("nofsgsbase", x86_nofsgsbase_setup);
 500
 501 /*
 502  * Protection Keys are not available in 32-bit mode.
 503  */
 504 static bool pku_disabled;
 505
 506 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
 507 {
 508         if (c == &boot_cpu_data) {
 509                 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU))
 510                         return;
 511                 /*
 512                  * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid
 513                  * bit to be set.  Enforce it.
 514                  */
 515                 setup_force_cpu_cap(X86_FEATURE_OSPKE);
 516
 517         } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) {
 518                 return;
 519         }
 520
 521         cr4_set_bits(X86_CR4_PKE);
 522         /* Load the default PKRU value */
 523         pkru_write_default();
 524 }
 525
 526 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
 527 static __init int setup_disable_pku(char *arg)
 528 {
 529         /*
 530          * Do not clear the X86_FEATURE_PKU bit.  All of the
 531          * runtime checks are against OSPKE so clearing the
 532          * bit does nothing.
 533          *
 534          * This way, we will see "pku" in cpuinfo, but not
 535          * "ospke", which is exactly what we want.  It shows
 536          * that the CPU has PKU, but the OS has not enabled it.
 537          * This happens to be exactly how a system would look
 538          * if we disabled the config option.
 539          */
 540         pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
 541         pku_disabled = true;
 542         return 1;
 543 }
 544 __setup("nopku", setup_disable_pku);
 545 #endif
 546
 547 #ifdef CONFIG_X86_KERNEL_IBT
 548
 549 __noendbr u64 ibt_save(bool disable)
 550 {
 551         u64 msr = 0;
 552
 553         if (cpu_feature_enabled(X86_FEATURE_IBT)) {
 554                 rdmsrl(MSR_IA32_S_CET, msr);
 555                 if (disable)
 556                         wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN);
 557         }
 558
 559         return msr;
 560 }
 561
 562 __noendbr void ibt_restore(u64 save)
 563 {
 564         u64 msr;
 565
 566         if (cpu_feature_enabled(X86_FEATURE_IBT)) {
 567                 rdmsrl(MSR_IA32_S_CET, msr);
 568                 msr &= ~CET_ENDBR_EN;
 569                 msr |= (save & CET_ENDBR_EN);
 570                 wrmsrl(MSR_IA32_S_CET, msr);
 571         }
 572 }
 573
 574 #endif
 575
 576 static __always_inline void setup_cet(struct cpuinfo_x86 *c)
 577 {
 578         bool user_shstk, kernel_ibt;
 579
 580         if (!IS_ENABLED(CONFIG_X86_CET))
 581                 return;
 582
 583         kernel_ibt = HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT);
 584         user_shstk = cpu_feature_enabled(X86_FEATURE_SHSTK) &&
 585                      IS_ENABLED(CONFIG_X86_USER_SHADOW_STACK);
 586
 587         if (!kernel_ibt && !user_shstk)
 588                 return;
 589
 590         if (user_shstk)
 591                 set_cpu_cap(c, X86_FEATURE_USER_SHSTK);
 592
 593         if (kernel_ibt)
 594                 wrmsrl(MSR_IA32_S_CET, CET_ENDBR_EN);
 595         else
 596                 wrmsrl(MSR_IA32_S_CET, 0);
 597
 598         cr4_set_bits(X86_CR4_CET);
 599
 600         if (kernel_ibt && ibt_selftest()) {
 601                 pr_err("IBT selftest: Failed!\n");
 602                 wrmsrl(MSR_IA32_S_CET, 0);
 603                 setup_clear_cpu_cap(X86_FEATURE_IBT);
 604         }
 605 }
 606
 607 __noendbr void cet_disable(void)
 608 {
 609         if (!(cpu_feature_enabled(X86_FEATURE_IBT) ||
 610               cpu_feature_enabled(X86_FEATURE_SHSTK)))
 611                 return;
 612
 613         wrmsrl(MSR_IA32_S_CET, 0);
 614         wrmsrl(MSR_IA32_U_CET, 0);
 615 }
 616
 617 /*
 618  * Some CPU features depend on higher CPUID levels, which may not always
 619  * be available due to CPUID level capping or broken virtualization
 620  * software.  Add those features to this table to auto-disable them.
 621  */
 622 struct cpuid_dependent_feature {
 623         u32 feature;
 624         u32 level;
 625 };
 626
 627 static const struct cpuid_dependent_feature
 628 cpuid_dependent_features[] = {
 629         { X86_FEATURE_MWAIT,            0x00000005 },
 630         { X86_FEATURE_DCA,              0x00000009 },
 631         { X86_FEATURE_XSAVE,            0x0000000d },
 632         { 0, 0 }
 633 };
 634
 635 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
 636 {
 637         const struct cpuid_dependent_feature *df;
 638
 639         for (df = cpuid_dependent_features; df->feature; df++) {
 640
 641                 if (!cpu_has(c, df->feature))
 642                         continue;
 643                 /*
 644                  * Note: cpuid_level is set to -1 if unavailable, but
 645                  * extended_extended_level is set to 0 if unavailable
 646                  * and the legitimate extended levels are all negative
 647                  * when signed; hence the weird messing around with
 648                  * signs here...
 649                  */
 650                 if (!((s32)df->level < 0 ?
 651                      (u32)df->level > (u32)c->extended_cpuid_level :
 652                      (s32)df->level > (s32)c->cpuid_level))
 653                         continue;
 654
 655                 clear_cpu_cap(c, df->feature);
 656                 if (!warn)
 657                         continue;
 658
 659                 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
 660                         x86_cap_flag(df->feature), df->level);
 661         }
 662 }
 663
 664 /*
 665  * Naming convention should be: <Name> [(<Codename>)]
 666  * This table only is used unless init_<vendor>() below doesn't set it;
 667  * in particular, if CPUID levels 0x80000002..4 are supported, this
 668  * isn't used
 669  */
 670
 671 /* Look up CPU names by table lookup. */
 672 static const char *table_lookup_model(struct cpuinfo_x86 *c)
 673 {
 674 #ifdef CONFIG_X86_32
 675         const struct legacy_cpu_model_info *info;
 676
 677         if (c->x86_model >= 16)
 678                 return NULL;    /* Range check */
 679
 680         if (!this_cpu)
 681                 return NULL;
 682
 683         info = this_cpu->legacy_models;
 684
 685         while (info->family) {
 686                 if (info->family == c->x86)
 687                         return info->model_names[c->x86_model];
 688                 info++;
 689         }
 690 #endif
 691         return NULL;            /* Not found */
 692 }
 693
 694 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
 695 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
 696 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
 697
 698 #ifdef CONFIG_X86_32
 699 /* The 32-bit entry code needs to find cpu_entry_area. */
 700 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
 701 #endif
 702
 703 /* Load the original GDT from the per-cpu structure */
 704 void load_direct_gdt(int cpu)
 705 {
 706         struct desc_ptr gdt_descr;
 707
 708         gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
 709         gdt_descr.size = GDT_SIZE - 1;
 710         load_gdt(&gdt_descr);
 711 }
 712 EXPORT_SYMBOL_GPL(load_direct_gdt);
 713
 714 /* Load a fixmap remapping of the per-cpu GDT */
 715 void load_fixmap_gdt(int cpu)
 716 {
 717         struct desc_ptr gdt_descr;
 718
 719         gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
 720         gdt_descr.size = GDT_SIZE - 1;
 721         load_gdt(&gdt_descr);
 722 }
 723 EXPORT_SYMBOL_GPL(load_fixmap_gdt);
 724
 725 /**
 726  * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base
 727  * @cpu:        The CPU number for which this is invoked
 728  *
 729  * Invoked during early boot to switch from early GDT and early per CPU to
 730  * the direct GDT and the runtime per CPU area. On 32-bit the percpu base
 731  * switch is implicit by loading the direct GDT. On 64bit this requires
 732  * to update GSBASE.
 733  */
 734 void __init switch_gdt_and_percpu_base(int cpu)
 735 {
 736         load_direct_gdt(cpu);
 737
 738 #ifdef CONFIG_X86_64
 739         /*
 740          * No need to load %gs. It is already correct.
 741          *
 742          * Writing %gs on 64bit would zero GSBASE which would make any per
 743          * CPU operation up to the point of the wrmsrl() fault.
 744          *
 745          * Set GSBASE to the new offset. Until the wrmsrl() happens the
 746          * early mapping is still valid. That means the GSBASE update will
 747          * lose any prior per CPU data which was not copied over in
 748          * setup_per_cpu_areas().
 749          *
 750          * This works even with stackprotector enabled because the
 751          * per CPU stack canary is 0 in both per CPU areas.
 752          */
 753         wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));
 754 #else
 755         /*
 756          * %fs is already set to __KERNEL_PERCPU, but after switching GDT
 757          * it is required to load FS again so that the 'hidden' part is
 758          * updated from the new GDT. Up to this point the early per CPU
 759          * translation is active. Any content of the early per CPU data
 760          * which was not copied over in setup_per_cpu_areas() is lost.
 761          */
 762         loadsegment(fs, __KERNEL_PERCPU);
 763 #endif
 764 }
 765
 766 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
 767
 768 static void get_model_name(struct cpuinfo_x86 *c)
 769 {
 770         unsigned int *v;
 771         char *p, *q, *s;
 772
 773         if (c->extended_cpuid_level < 0x80000004)
 774                 return;
 775
 776         v = (unsigned int *)c->x86_model_id;
 777         cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
 778         cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
 779         cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
 780         c->x86_model_id[48] = 0;
 781
 782         /* Trim whitespace */
 783         p = q = s = &c->x86_model_id[0];
 784
 785         while (*p == ' ')
 786                 p++;
 787
 788         while (*p) {
 789                 /* Note the last non-whitespace index */
 790                 if (!isspace(*p))
 791                         s = q;
 792
 793                 *q++ = *p++;
 794         }
 795
 796         *(s + 1) = '\0';
 797 }
 798
 799 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
 800 {
 801         unsigned int n, dummy, ebx, ecx, edx, l2size;
 802
 803         n = c->extended_cpuid_level;
 804
 805         if (n >= 0x80000005) {
 806                 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
 807                 c->x86_cache_size = (ecx>>24) + (edx>>24);
 808 #ifdef CONFIG_X86_64
 809                 /* On K8 L1 TLB is inclusive, so don't count it */
 810                 c->x86_tlbsize = 0;
 811 #endif
 812         }
 813
 814         if (n < 0x80000006)     /* Some chips just has a large L1. */
 815                 return;
 816
 817         cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
 818         l2size = ecx >> 16;
 819
 820 #ifdef CONFIG_X86_64
 821         c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
 822 #else
 823         /* do processor-specific cache resizing */
 824         if (this_cpu->legacy_cache_size)
 825                 l2size = this_cpu->legacy_cache_size(c, l2size);
 826
 827         /* Allow user to override all this if necessary. */
 828         if (cachesize_override != -1)
 829                 l2size = cachesize_override;
 830
 831         if (l2size == 0)
 832                 return;         /* Again, no L2 cache is possible */
 833 #endif
 834
 835         c->x86_cache_size = l2size;
 836 }
 837
 838 u16 __read_mostly tlb_lli_4k[NR_INFO];
 839 u16 __read_mostly tlb_lli_2m[NR_INFO];
 840 u16 __read_mostly tlb_lli_4m[NR_INFO];
 841 u16 __read_mostly tlb_lld_4k[NR_INFO];
 842 u16 __read_mostly tlb_lld_2m[NR_INFO];
 843 u16 __read_mostly tlb_lld_4m[NR_INFO];
 844 u16 __read_mostly tlb_lld_1g[NR_INFO];
 845
 846 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
 847 {
 848         if (this_cpu->c_detect_tlb)
 849                 this_cpu->c_detect_tlb(c);
 850
 851         pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
 852                 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
 853                 tlb_lli_4m[ENTRIES]);
 854
 855         pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
 856                 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
 857                 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
 858 }
 859
 860 static void get_cpu_vendor(struct cpuinfo_x86 *c)
 861 {
 862         char *v = c->x86_vendor_id;
 863         int i;
 864
 865         for (i = 0; i < X86_VENDOR_NUM; i++) {
 866                 if (!cpu_devs[i])
 867                         break;
 868
 869                 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
 870                     (cpu_devs[i]->c_ident[1] &&
 871                      !strcmp(v, cpu_devs[i]->c_ident[1]))) {
 872
 873                         this_cpu = cpu_devs[i];
 874                         c->x86_vendor = this_cpu->c_x86_vendor;
 875                         return;
 876                 }
 877         }
 878
 879         pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
 880                     "CPU: Your system may be unstable.\n", v);
 881
 882         c->x86_vendor = X86_VENDOR_UNKNOWN;
 883         this_cpu = &default_cpu;
 884 }
 885
 886 void cpu_detect(struct cpuinfo_x86 *c)
 887 {
 888         /* Get vendor name */
 889         cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
 890               (unsigned int *)&c->x86_vendor_id[0],
 891               (unsigned int *)&c->x86_vendor_id[8],
 892               (unsigned int *)&c->x86_vendor_id[4]);
 893
 894         c->x86 = 4;
 895         /* Intel-defined flags: level 0x00000001 */
 896         if (c->cpuid_level >= 0x00000001) {
 897                 u32 junk, tfms, cap0, misc;
 898
 899                 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
 900                 c->x86          = x86_family(tfms);
 901                 c->x86_model    = x86_model(tfms);
 902                 c->x86_stepping = x86_stepping(tfms);
 903
 904                 if (cap0 & (1<<19)) {
 905                         c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
 906                         c->x86_cache_alignment = c->x86_clflush_size;
 907                 }
 908         }
 909 }
 910
 911 static void apply_forced_caps(struct cpuinfo_x86 *c)
 912 {
 913         int i;
 914
 915         for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
 916                 c->x86_capability[i] &= ~cpu_caps_cleared[i];
 917                 c->x86_capability[i] |= cpu_caps_set[i];
 918         }
 919 }
 920
 921 static void init_speculation_control(struct cpuinfo_x86 *c)
 922 {
 923         /*
 924          * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
 925          * and they also have a different bit for STIBP support. Also,
 926          * a hypervisor might have set the individual AMD bits even on
 927          * Intel CPUs, for finer-grained selection of what's available.
 928          */
 929         if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
 930                 set_cpu_cap(c, X86_FEATURE_IBRS);
 931                 set_cpu_cap(c, X86_FEATURE_IBPB);
 932                 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
 933         }
 934
 935         if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
 936                 set_cpu_cap(c, X86_FEATURE_STIBP);
 937
 938         if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
 939             cpu_has(c, X86_FEATURE_VIRT_SSBD))
 940                 set_cpu_cap(c, X86_FEATURE_SSBD);
 941
 942         if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
 943                 set_cpu_cap(c, X86_FEATURE_IBRS);
 944                 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
 945         }
 946
 947         if (cpu_has(c, X86_FEATURE_AMD_IBPB))
 948                 set_cpu_cap(c, X86_FEATURE_IBPB);
 949
 950         if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
 951                 set_cpu_cap(c, X86_FEATURE_STIBP);
 952                 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
 953         }
 954
 955         if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
 956                 set_cpu_cap(c, X86_FEATURE_SSBD);
 957                 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
 958                 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
 959         }
 960 }
 961
 962 void get_cpu_cap(struct cpuinfo_x86 *c)
 963 {
 964         u32 eax, ebx, ecx, edx;
 965
 966         /* Intel-defined flags: level 0x00000001 */
 967         if (c->cpuid_level >= 0x00000001) {
 968                 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
 969
 970                 c->x86_capability[CPUID_1_ECX] = ecx;
 971                 c->x86_capability[CPUID_1_EDX] = edx;
 972         }
 973
 974         /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
 975         if (c->cpuid_level >= 0x00000006)
 976                 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
 977
 978         /* Additional Intel-defined flags: level 0x00000007 */
 979         if (c->cpuid_level >= 0x00000007) {
 980                 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
 981                 c->x86_capability[CPUID_7_0_EBX] = ebx;
 982                 c->x86_capability[CPUID_7_ECX] = ecx;
 983                 c->x86_capability[CPUID_7_EDX] = edx;
 984
 985                 /* Check valid sub-leaf index before accessing it */
 986                 if (eax >= 1) {
 987                         cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
 988                         c->x86_capability[CPUID_7_1_EAX] = eax;
 989                 }
 990         }
 991
 992         /* Extended state features: level 0x0000000d */
 993         if (c->cpuid_level >= 0x0000000d) {
 994                 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
 995
 996                 c->x86_capability[CPUID_D_1_EAX] = eax;
 997         }
 998
 999         /* AMD-defined flags: level 0x80000001 */
1000         eax = cpuid_eax(0x80000000);
1001         c->extended_cpuid_level = eax;
1002
1003         if ((eax & 0xffff0000) == 0x80000000) {
1004                 if (eax >= 0x80000001) {
1005                         cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
1006
1007                         c->x86_capability[CPUID_8000_0001_ECX] = ecx;
1008                         c->x86_capability[CPUID_8000_0001_EDX] = edx;
1009                 }
1010         }
1011
1012         if (c->extended_cpuid_level >= 0x80000007) {
1013                 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
1014
1015                 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
1016                 c->x86_power = edx;
1017         }
1018
1019         if (c->extended_cpuid_level >= 0x80000008) {
1020                 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
1021                 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
1022         }
1023
1024         if (c->extended_cpuid_level >= 0x8000000a)
1025                 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
1026
1027         if (c->extended_cpuid_level >= 0x8000001f)
1028                 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f);
1029
1030         if (c->extended_cpuid_level >= 0x80000021)
1031                 c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021);
1032
1033         init_scattered_cpuid_features(c);
1034         init_speculation_control(c);
1035
1036         /*
1037          * Clear/Set all flags overridden by options, after probe.
1038          * This needs to happen each time we re-probe, which may happen
1039          * several times during CPU initialization.
1040          */
1041         apply_forced_caps(c);
1042 }
1043
1044 void get_cpu_address_sizes(struct cpuinfo_x86 *c)
1045 {
1046         u32 eax, ebx, ecx, edx;
1047         bool vp_bits_from_cpuid = true;
1048
1049         if (!cpu_has(c, X86_FEATURE_CPUID) ||
1050             (c->extended_cpuid_level < 0x80000008))
1051                 vp_bits_from_cpuid = false;
1052
1053         if (vp_bits_from_cpuid) {
1054                 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
1055
1056                 c->x86_virt_bits = (eax >> 8) & 0xff;
1057                 c->x86_phys_bits = eax & 0xff;
1058         } else {
1059                 if (IS_ENABLED(CONFIG_X86_64)) {
1060                         c->x86_clflush_size = 64;
1061                         c->x86_phys_bits = 36;
1062                         c->x86_virt_bits = 48;
1063                 } else {
1064                         c->x86_clflush_size = 32;
1065                         c->x86_virt_bits = 32;
1066                         c->x86_phys_bits = 32;
1067
1068                         if (cpu_has(c, X86_FEATURE_PAE) ||
1069                             cpu_has(c, X86_FEATURE_PSE36))
1070                                 c->x86_phys_bits = 36;
1071                 }
1072         }
1073         c->x86_cache_bits = c->x86_phys_bits;
1074         c->x86_cache_alignment = c->x86_clflush_size;
1075 }
1076
1077 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
1078 {
1079 #ifdef CONFIG_X86_32
1080         int i;
1081
1082         /*
1083          * First of all, decide if this is a 486 or higher
1084          * It's a 486 if we can modify the AC flag
1085          */
1086         if (flag_is_changeable_p(X86_EFLAGS_AC))
1087                 c->x86 = 4;
1088         else
1089                 c->x86 = 3;
1090
1091         for (i = 0; i < X86_VENDOR_NUM; i++)
1092                 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
1093                         c->x86_vendor_id[0] = 0;
1094                         cpu_devs[i]->c_identify(c);
1095                         if (c->x86_vendor_id[0]) {
1096                                 get_cpu_vendor(c);
1097                                 break;
1098                         }
1099                 }
1100 #endif
1101 }
1102
1103 #define NO_SPECULATION          BIT(0)
1104 #define NO_MELTDOWN             BIT(1)
1105 #define NO_SSB                  BIT(2)
1106 #define NO_L1TF                 BIT(3)
1107 #define NO_MDS                  BIT(4)
1108 #define MSBDS_ONLY              BIT(5)
1109 #define NO_SWAPGS               BIT(6)
1110 #define NO_ITLB_MULTIHIT        BIT(7)
1111 #define NO_SPECTRE_V2           BIT(8)
1112 #define NO_MMIO                 BIT(9)
1113 #define NO_EIBRS_PBRSB          BIT(10)
1114
1115 #define VULNWL(vendor, family, model, whitelist)        \
1116         X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
1117
1118 #define VULNWL_INTEL(model, whitelist)          \
1119         VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
1120
1121 #define VULNWL_AMD(family, whitelist)           \
1122         VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1123
1124 #define VULNWL_HYGON(family, whitelist)         \
1125         VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1126
1127 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
1128         VULNWL(ANY,     4, X86_MODEL_ANY,       NO_SPECULATION),
1129         VULNWL(CENTAUR, 5, X86_MODEL_ANY,       NO_SPECULATION),
1130         VULNWL(INTEL,   5, X86_MODEL_ANY,       NO_SPECULATION),
1131         VULNWL(NSC,     5, X86_MODEL_ANY,       NO_SPECULATION),
1132         VULNWL(VORTEX,  5, X86_MODEL_ANY,       NO_SPECULATION),
1133         VULNWL(VORTEX,  6, X86_MODEL_ANY,       NO_SPECULATION),
1134
1135         /* Intel Family 6 */
1136         VULNWL_INTEL(TIGERLAKE,                 NO_MMIO),
1137         VULNWL_INTEL(TIGERLAKE_L,               NO_MMIO),
1138         VULNWL_INTEL(ALDERLAKE,                 NO_MMIO),
1139         VULNWL_INTEL(ALDERLAKE_L,               NO_MMIO),
1140
1141         VULNWL_INTEL(ATOM_SALTWELL,             NO_SPECULATION | NO_ITLB_MULTIHIT),
1142         VULNWL_INTEL(ATOM_SALTWELL_TABLET,      NO_SPECULATION | NO_ITLB_MULTIHIT),
1143         VULNWL_INTEL(ATOM_SALTWELL_MID,         NO_SPECULATION | NO_ITLB_MULTIHIT),
1144         VULNWL_INTEL(ATOM_BONNELL,              NO_SPECULATION | NO_ITLB_MULTIHIT),
1145         VULNWL_INTEL(ATOM_BONNELL_MID,          NO_SPECULATION | NO_ITLB_MULTIHIT),
1146
1147         VULNWL_INTEL(ATOM_SILVERMONT,           NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1148         VULNWL_INTEL(ATOM_SILVERMONT_D,         NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1149         VULNWL_INTEL(ATOM_SILVERMONT_MID,       NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1150         VULNWL_INTEL(ATOM_AIRMONT,              NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1151         VULNWL_INTEL(XEON_PHI_KNL,              NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1152         VULNWL_INTEL(XEON_PHI_KNM,              NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1153
1154         VULNWL_INTEL(CORE_YONAH,                NO_SSB),
1155
1156         VULNWL_INTEL(ATOM_AIRMONT_MID,          NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1157         VULNWL_INTEL(ATOM_AIRMONT_NP,           NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1158
1159         VULNWL_INTEL(ATOM_GOLDMONT,             NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1160         VULNWL_INTEL(ATOM_GOLDMONT_D,           NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1161         VULNWL_INTEL(ATOM_GOLDMONT_PLUS,        NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB),
1162
1163         /*
1164          * Technically, swapgs isn't serializing on AMD (despite it previously
1165          * being documented as such in the APM).  But according to AMD, %gs is
1166          * updated non-speculatively, and the issuing of %gs-relative memory
1167          * operands will be blocked until the %gs update completes, which is
1168          * good enough for our purposes.
1169          */
1170
1171         VULNWL_INTEL(ATOM_TREMONT,              NO_EIBRS_PBRSB),
1172         VULNWL_INTEL(ATOM_TREMONT_L,            NO_EIBRS_PBRSB),
1173         VULNWL_INTEL(ATOM_TREMONT_D,            NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB),
1174
1175         /* AMD Family 0xf - 0x12 */
1176         VULNWL_AMD(0x0f,        NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1177         VULNWL_AMD(0x10,        NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1178         VULNWL_AMD(0x11,        NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1179         VULNWL_AMD(0x12,        NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1180
1181         /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1182         VULNWL_AMD(X86_FAMILY_ANY,      NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB),
1183         VULNWL_HYGON(X86_FAMILY_ANY,    NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB),
1184
1185         /* Zhaoxin Family 7 */
1186         VULNWL(CENTAUR, 7, X86_MODEL_ANY,       NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO),
1187         VULNWL(ZHAOXIN, 7, X86_MODEL_ANY,       NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO),
1188         {}
1189 };
1190
1191 #define VULNBL(vendor, family, model, blacklist)        \
1192         X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist)
1193
1194 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues)                   \
1195         X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6,             \
1196                                             INTEL_FAM6_##model, steppings, \
1197                                             X86_FEATURE_ANY, issues)
1198
1199 #define VULNBL_AMD(family, blacklist)           \
1200         VULNBL(AMD, family, X86_MODEL_ANY, blacklist)
1201
1202 #define VULNBL_HYGON(family, blacklist)         \
1203         VULNBL(HYGON, family, X86_MODEL_ANY, blacklist)
1204
1205 #define SRBDS           BIT(0)
1206 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */
1207 #define MMIO            BIT(1)
1208 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */
1209 #define MMIO_SBDS       BIT(2)
1210 /* CPU is affected by RETbleed, speculating where you would not expect it */
1211 #define RETBLEED        BIT(3)
1212 /* CPU is affected by SMT (cross-thread) return predictions */
1213 #define SMT_RSB         BIT(4)
1214 /* CPU is affected by SRSO */
1215 #define SRSO            BIT(5)
1216 /* CPU is affected by GDS */
1217 #define GDS             BIT(6)
1218
1219 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
1220         VULNBL_INTEL_STEPPINGS(IVYBRIDGE,       X86_STEPPING_ANY,               SRBDS),
1221         VULNBL_INTEL_STEPPINGS(HASWELL,         X86_STEPPING_ANY,               SRBDS),
1222         VULNBL_INTEL_STEPPINGS(HASWELL_L,       X86_STEPPING_ANY,               SRBDS),
1223         VULNBL_INTEL_STEPPINGS(HASWELL_G,       X86_STEPPING_ANY,               SRBDS),
1224         VULNBL_INTEL_STEPPINGS(HASWELL_X,       X86_STEPPING_ANY,               MMIO),
1225         VULNBL_INTEL_STEPPINGS(BROADWELL_D,     X86_STEPPING_ANY,               MMIO),
1226         VULNBL_INTEL_STEPPINGS(BROADWELL_G,     X86_STEPPING_ANY,               SRBDS),
1227         VULNBL_INTEL_STEPPINGS(BROADWELL_X,     X86_STEPPING_ANY,               MMIO),
1228         VULNBL_INTEL_STEPPINGS(BROADWELL,       X86_STEPPING_ANY,               SRBDS),
1229         VULNBL_INTEL_STEPPINGS(SKYLAKE_X,       X86_STEPPING_ANY,               MMIO | RETBLEED | GDS),
1230         VULNBL_INTEL_STEPPINGS(SKYLAKE_L,       X86_STEPPING_ANY,               MMIO | RETBLEED | GDS | SRBDS),
1231         VULNBL_INTEL_STEPPINGS(SKYLAKE,         X86_STEPPING_ANY,               MMIO | RETBLEED | GDS | SRBDS),
1232         VULNBL_INTEL_STEPPINGS(KABYLAKE_L,      X86_STEPPING_ANY,               MMIO | RETBLEED | GDS | SRBDS),
1233         VULNBL_INTEL_STEPPINGS(KABYLAKE,        X86_STEPPING_ANY,               MMIO | RETBLEED | GDS | SRBDS),
1234         VULNBL_INTEL_STEPPINGS(CANNONLAKE_L,    X86_STEPPING_ANY,               RETBLEED),
1235         VULNBL_INTEL_STEPPINGS(ICELAKE_L,       X86_STEPPING_ANY,               MMIO | MMIO_SBDS | RETBLEED | GDS),
1236         VULNBL_INTEL_STEPPINGS(ICELAKE_D,       X86_STEPPING_ANY,               MMIO | GDS),
1237         VULNBL_INTEL_STEPPINGS(ICELAKE_X,       X86_STEPPING_ANY,               MMIO | GDS),
1238         VULNBL_INTEL_STEPPINGS(COMETLAKE,       X86_STEPPING_ANY,               MMIO | MMIO_SBDS | RETBLEED | GDS),
1239         VULNBL_INTEL_STEPPINGS(COMETLAKE_L,     X86_STEPPINGS(0x0, 0x0),        MMIO | RETBLEED),
1240         VULNBL_INTEL_STEPPINGS(COMETLAKE_L,     X86_STEPPING_ANY,               MMIO | MMIO_SBDS | RETBLEED | GDS),
1241         VULNBL_INTEL_STEPPINGS(TIGERLAKE_L,     X86_STEPPING_ANY,               GDS),
1242         VULNBL_INTEL_STEPPINGS(TIGERLAKE,       X86_STEPPING_ANY,               GDS),
1243         VULNBL_INTEL_STEPPINGS(LAKEFIELD,       X86_STEPPING_ANY,               MMIO | MMIO_SBDS | RETBLEED),
1244         VULNBL_INTEL_STEPPINGS(ROCKETLAKE,      X86_STEPPING_ANY,               MMIO | RETBLEED | GDS),
1245         VULNBL_INTEL_STEPPINGS(ATOM_TREMONT,    X86_STEPPING_ANY,               MMIO | MMIO_SBDS),
1246         VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_D,  X86_STEPPING_ANY,               MMIO),
1247         VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L,  X86_STEPPING_ANY,               MMIO | MMIO_SBDS),
1248
1249         VULNBL_AMD(0x15, RETBLEED),
1250         VULNBL_AMD(0x16, RETBLEED),
1251         VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO),
1252         VULNBL_HYGON(0x18, RETBLEED | SMT_RSB | SRSO),
1253         VULNBL_AMD(0x19, SRSO),
1254         {}
1255 };
1256
1257 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which)
1258 {
1259         const struct x86_cpu_id *m = x86_match_cpu(table);
1260
1261         return m && !!(m->driver_data & which);
1262 }
1263
1264 u64 x86_read_arch_cap_msr(void)
1265 {
1266         u64 ia32_cap = 0;
1267
1268         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1269                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
1270
1271         return ia32_cap;
1272 }
1273
1274 static bool arch_cap_mmio_immune(u64 ia32_cap)
1275 {
1276         return (ia32_cap & ARCH_CAP_FBSDP_NO &&
1277                 ia32_cap & ARCH_CAP_PSDP_NO &&
1278                 ia32_cap & ARCH_CAP_SBDR_SSDP_NO);
1279 }
1280
1281 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1282 {
1283         u64 ia32_cap = x86_read_arch_cap_msr();
1284
1285         /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1286         if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) &&
1287             !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO))
1288                 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);
1289
1290         if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION))
1291                 return;
1292
1293         setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1294
1295         if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2))
1296                 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1297
1298         if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) &&
1299             !(ia32_cap & ARCH_CAP_SSB_NO) &&
1300            !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1301                 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1302
1303         /*
1304          * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature
1305          * flag and protect from vendor-specific bugs via the whitelist.
1306          */
1307         if ((ia32_cap & ARCH_CAP_IBRS_ALL) || cpu_has(c, X86_FEATURE_AUTOIBRS)) {
1308                 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1309                 if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) &&
1310                     !(ia32_cap & ARCH_CAP_PBRSB_NO))
1311                         setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB);
1312         }
1313
1314         if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) &&
1315             !(ia32_cap & ARCH_CAP_MDS_NO)) {
1316                 setup_force_cpu_bug(X86_BUG_MDS);
1317                 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY))
1318                         setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
1319         }
1320
1321         if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS))
1322                 setup_force_cpu_bug(X86_BUG_SWAPGS);
1323
1324         /*
1325          * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1326          *      - TSX is supported or
1327          *      - TSX_CTRL is present
1328          *
1329          * TSX_CTRL check is needed for cases when TSX could be disabled before
1330          * the kernel boot e.g. kexec.
1331          * TSX_CTRL check alone is not sufficient for cases when the microcode
1332          * update is not present or running as guest that don't get TSX_CTRL.
1333          */
1334         if (!(ia32_cap & ARCH_CAP_TAA_NO) &&
1335             (cpu_has(c, X86_FEATURE_RTM) ||
1336              (ia32_cap & ARCH_CAP_TSX_CTRL_MSR)))
1337                 setup_force_cpu_bug(X86_BUG_TAA);
1338
1339         /*
1340          * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
1341          * in the vulnerability blacklist.
1342          *
1343          * Some of the implications and mitigation of Shared Buffers Data
1344          * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as
1345          * SRBDS.
1346          */
1347         if ((cpu_has(c, X86_FEATURE_RDRAND) ||
1348              cpu_has(c, X86_FEATURE_RDSEED)) &&
1349             cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS))
1350                     setup_force_cpu_bug(X86_BUG_SRBDS);
1351
1352         /*
1353          * Processor MMIO Stale Data bug enumeration
1354          *
1355          * Affected CPU list is generally enough to enumerate the vulnerability,
1356          * but for virtualization case check for ARCH_CAP MSR bits also, VMM may
1357          * not want the guest to enumerate the bug.
1358          *
1359          * Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist,
1360          * nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits.
1361          */
1362         if (!arch_cap_mmio_immune(ia32_cap)) {
1363                 if (cpu_matches(cpu_vuln_blacklist, MMIO))
1364                         setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA);
1365                 else if (!cpu_matches(cpu_vuln_whitelist, NO_MMIO))
1366                         setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN);
1367         }
1368
1369         if (!cpu_has(c, X86_FEATURE_BTC_NO)) {
1370                 if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (ia32_cap & ARCH_CAP_RSBA))
1371                         setup_force_cpu_bug(X86_BUG_RETBLEED);
1372         }
1373
1374         if (cpu_matches(cpu_vuln_blacklist, SMT_RSB))
1375                 setup_force_cpu_bug(X86_BUG_SMT_RSB);
1376
1377         if (!cpu_has(c, X86_FEATURE_SRSO_NO)) {
1378                 if (cpu_matches(cpu_vuln_blacklist, SRSO))
1379                         setup_force_cpu_bug(X86_BUG_SRSO);
1380         }
1381
1382         /*
1383          * Check if CPU is vulnerable to GDS. If running in a virtual machine on
1384          * an affected processor, the VMM may have disabled the use of GATHER by
1385          * disabling AVX2. The only way to do this in HW is to clear XCR0[2],
1386          * which means that AVX will be disabled.
1387          */
1388         if (cpu_matches(cpu_vuln_blacklist, GDS) && !(ia32_cap & ARCH_CAP_GDS_NO) &&
1389             boot_cpu_has(X86_FEATURE_AVX))
1390                 setup_force_cpu_bug(X86_BUG_GDS);
1391
1392         if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))
1393                 return;
1394
1395         /* Rogue Data Cache Load? No! */
1396         if (ia32_cap & ARCH_CAP_RDCL_NO)
1397                 return;
1398
1399         setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1400
1401         if (cpu_matches(cpu_vuln_whitelist, NO_L1TF))
1402                 return;
1403
1404         setup_force_cpu_bug(X86_BUG_L1TF);
1405 }
1406
1407 /*
1408  * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1409  * unfortunately, that's not true in practice because of early VIA
1410  * chips and (more importantly) broken virtualizers that are not easy
1411  * to detect. In the latter case it doesn't even *fail* reliably, so
1412  * probing for it doesn't even work. Disable it completely on 32-bit
1413  * unless we can find a reliable way to detect all the broken cases.
1414  * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1415  */
1416 static void detect_nopl(void)
1417 {
1418 #ifdef CONFIG_X86_32
1419         setup_clear_cpu_cap(X86_FEATURE_NOPL);
1420 #else
1421         setup_force_cpu_cap(X86_FEATURE_NOPL);
1422 #endif
1423 }
1424
1425 /*
1426  * We parse cpu parameters early because fpu__init_system() is executed
1427  * before parse_early_param().
1428  */
1429 static void __init cpu_parse_early_param(void)
1430 {
1431         char arg[128];
1432         char *argptr = arg, *opt;
1433         int arglen, taint = 0;
1434
1435 #ifdef CONFIG_X86_32
1436         if (cmdline_find_option_bool(boot_command_line, "no387"))
1437 #ifdef CONFIG_MATH_EMULATION
1438                 setup_clear_cpu_cap(X86_FEATURE_FPU);
1439 #else
1440                 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n");
1441 #endif
1442
1443         if (cmdline_find_option_bool(boot_command_line, "nofxsr"))
1444                 setup_clear_cpu_cap(X86_FEATURE_FXSR);
1445 #endif
1446
1447         if (cmdline_find_option_bool(boot_command_line, "noxsave"))
1448                 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
1449
1450         if (cmdline_find_option_bool(boot_command_line, "noxsaveopt"))
1451                 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
1452
1453         if (cmdline_find_option_bool(boot_command_line, "noxsaves"))
1454                 setup_clear_cpu_cap(X86_FEATURE_XSAVES);
1455
1456         if (cmdline_find_option_bool(boot_command_line, "nousershstk"))
1457                 setup_clear_cpu_cap(X86_FEATURE_USER_SHSTK);
1458
1459         arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg));
1460         if (arglen <= 0)
1461                 return;
1462
1463         pr_info("Clearing CPUID bits:");
1464
1465         while (argptr) {
1466                 bool found __maybe_unused = false;
1467                 unsigned int bit;
1468
1469                 opt = strsep(&argptr, ",");
1470
1471                 /*
1472                  * Handle naked numbers first for feature flags which don't
1473                  * have names.
1474                  */
1475                 if (!kstrtouint(opt, 10, &bit)) {
1476                         if (bit < NCAPINTS * 32) {
1477
1478                                 /* empty-string, i.e., ""-defined feature flags */
1479                                 if (!x86_cap_flags[bit])
1480                                         pr_cont(" " X86_CAP_FMT_NUM, x86_cap_flag_num(bit));
1481                                 else
1482                                         pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit));
1483
1484                                 setup_clear_cpu_cap(bit);
1485                                 taint++;
1486                         }
1487                         /*
1488                          * The assumption is that there are no feature names with only
1489                          * numbers in the name thus go to the next argument.
1490                          */
1491                         continue;
1492                 }
1493
1494                 for (bit = 0; bit < 32 * NCAPINTS; bit++) {
1495                         if (!x86_cap_flag(bit))
1496                                 continue;
1497
1498                         if (strcmp(x86_cap_flag(bit), opt))
1499                                 continue;
1500
1501                         pr_cont(" %s", opt);
1502                         setup_clear_cpu_cap(bit);
1503                         taint++;
1504                         found = true;
1505                         break;
1506                 }
1507
1508                 if (!found)
1509                         pr_cont(" (unknown: %s)", opt);
1510         }
1511         pr_cont("\n");
1512
1513         if (taint)
1514                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1515 }
1516
1517 /*
1518  * Do minimum CPU detection early.
1519  * Fields really needed: vendor, cpuid_level, family, model, mask,
1520  * cache alignment.
1521  * The others are not touched to avoid unwanted side effects.
1522  *
1523  * WARNING: this function is only called on the boot CPU.  Don't add code
1524  * here that is supposed to run on all CPUs.
1525  */
1526 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1527 {
1528         memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1529         c->extended_cpuid_level = 0;
1530
1531         if (!have_cpuid_p())
1532                 identify_cpu_without_cpuid(c);
1533
1534         /* cyrix could have cpuid enabled via c_identify()*/
1535         if (have_cpuid_p()) {
1536                 cpu_detect(c);
1537                 get_cpu_vendor(c);
1538                 get_cpu_cap(c);
1539                 setup_force_cpu_cap(X86_FEATURE_CPUID);
1540                 cpu_parse_early_param();
1541
1542                 cpu_init_topology(c);
1543
1544                 if (this_cpu->c_early_init)
1545                         this_cpu->c_early_init(c);
1546
1547                 c->cpu_index = 0;
1548                 filter_cpuid_features(c, false);
1549
1550                 if (this_cpu->c_bsp_init)
1551                         this_cpu->c_bsp_init(c);
1552         } else {
1553                 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1554                 cpu_init_topology(c);
1555         }
1556
1557         get_cpu_address_sizes(c);
1558
1559         setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1560
1561         cpu_set_bug_bits(c);
1562
1563         sld_setup(c);
1564
1565 #ifdef CONFIG_X86_32
1566         /*
1567          * Regardless of whether PCID is enumerated, the SDM says
1568          * that it can't be enabled in 32-bit mode.
1569          */
1570         setup_clear_cpu_cap(X86_FEATURE_PCID);
1571 #endif
1572
1573         /*
1574          * Later in the boot process pgtable_l5_enabled() relies on
1575          * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1576          * enabled by this point we need to clear the feature bit to avoid
1577          * false-positives at the later stage.
1578          *
1579          * pgtable_l5_enabled() can be false here for several reasons:
1580          *  - 5-level paging is disabled compile-time;
1581          *  - it's 32-bit kernel;
1582          *  - machine doesn't support 5-level paging;
1583          *  - user specified 'no5lvl' in kernel command line.
1584          */
1585         if (!pgtable_l5_enabled())
1586                 setup_clear_cpu_cap(X86_FEATURE_LA57);
1587
1588         detect_nopl();
1589 }
1590
1591 void __init early_cpu_init(void)
1592 {
1593         const struct cpu_dev *const *cdev;
1594         int count = 0;
1595
1596 #ifdef CONFIG_PROCESSOR_SELECT
1597         pr_info("KERNEL supported cpus:\n");
1598 #endif
1599
1600         for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1601                 const struct cpu_dev *cpudev = *cdev;
1602
1603                 if (count >= X86_VENDOR_NUM)
1604                         break;
1605                 cpu_devs[count] = cpudev;
1606                 count++;
1607
1608 #ifdef CONFIG_PROCESSOR_SELECT
1609                 {
1610                         unsigned int j;
1611
1612                         for (j = 0; j < 2; j++) {
1613                                 if (!cpudev->c_ident[j])
1614                                         continue;
1615                                 pr_info("  %s %s\n", cpudev->c_vendor,
1616                                         cpudev->c_ident[j]);
1617                         }
1618                 }
1619 #endif
1620         }
1621         early_identify_cpu(&boot_cpu_data);
1622 }
1623
1624 static bool detect_null_seg_behavior(void)
1625 {
1626         /*
1627          * Empirically, writing zero to a segment selector on AMD does
1628          * not clear the base, whereas writing zero to a segment
1629          * selector on Intel does clear the base.  Intel's behavior
1630          * allows slightly faster context switches in the common case
1631          * where GS is unused by the prev and next threads.
1632          *
1633          * Since neither vendor documents this anywhere that I can see,
1634          * detect it directly instead of hard-coding the choice by
1635          * vendor.
1636          *
1637          * I've designated AMD's behavior as the "bug" because it's
1638          * counterintuitive and less friendly.
1639          */
1640
1641         unsigned long old_base, tmp;
1642         rdmsrl(MSR_FS_BASE, old_base);
1643         wrmsrl(MSR_FS_BASE, 1);
1644         loadsegment(fs, 0);
1645         rdmsrl(MSR_FS_BASE, tmp);
1646         wrmsrl(MSR_FS_BASE, old_base);
1647         return tmp == 0;
1648 }
1649
1650 void check_null_seg_clears_base(struct cpuinfo_x86 *c)
1651 {
1652         /* BUG_NULL_SEG is only relevant with 64bit userspace */
1653         if (!IS_ENABLED(CONFIG_X86_64))
1654                 return;
1655
1656         if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE))
1657                 return;
1658
1659         /*
1660          * CPUID bit above wasn't set. If this kernel is still running
1661          * as a HV guest, then the HV has decided not to advertize
1662          * that CPUID bit for whatever reason.  For example, one
1663          * member of the migration pool might be vulnerable.  Which
1664          * means, the bug is present: set the BUG flag and return.
1665          */
1666         if (cpu_has(c, X86_FEATURE_HYPERVISOR)) {
1667                 set_cpu_bug(c, X86_BUG_NULL_SEG);
1668                 return;
1669         }
1670
1671         /*
1672          * Zen2 CPUs also have this behaviour, but no CPUID bit.
1673          * 0x18 is the respective family for Hygon.
1674          */
1675         if ((c->x86 == 0x17 || c->x86 == 0x18) &&
1676             detect_null_seg_behavior())
1677                 return;
1678
1679         /* All the remaining ones are affected */
1680         set_cpu_bug(c, X86_BUG_NULL_SEG);
1681 }
1682
1683 static void generic_identify(struct cpuinfo_x86 *c)
1684 {
1685         c->extended_cpuid_level = 0;
1686
1687         if (!have_cpuid_p())
1688                 identify_cpu_without_cpuid(c);
1689
1690         /* cyrix could have cpuid enabled via c_identify()*/
1691         if (!have_cpuid_p())
1692                 return;
1693
1694         cpu_detect(c);
1695
1696         get_cpu_vendor(c);
1697
1698         get_cpu_cap(c);
1699
1700         get_cpu_address_sizes(c);
1701
1702         get_model_name(c); /* Default name */
1703
1704         /*
1705          * ESPFIX is a strange bug.  All real CPUs have it.  Paravirt
1706          * systems that run Linux at CPL > 0 may or may not have the
1707          * issue, but, even if they have the issue, there's absolutely
1708          * nothing we can do about it because we can't use the real IRET
1709          * instruction.
1710          *
1711          * NB: For the time being, only 32-bit kernels support
1712          * X86_BUG_ESPFIX as such.  64-bit kernels directly choose
1713          * whether to apply espfix using paravirt hooks.  If any
1714          * non-paravirt system ever shows up that does *not* have the
1715          * ESPFIX issue, we can change this.
1716          */
1717 #ifdef CONFIG_X86_32
1718         set_cpu_bug(c, X86_BUG_ESPFIX);
1719 #endif
1720 }
1721
1722 /*
1723  * This does the hard work of actually picking apart the CPU stuff...
1724  */
1725 static void identify_cpu(struct cpuinfo_x86 *c)
1726 {
1727         int i;
1728
1729         c->loops_per_jiffy = loops_per_jiffy;
1730         c->x86_cache_size = 0;
1731         c->x86_vendor = X86_VENDOR_UNKNOWN;
1732         c->x86_model = c->x86_stepping = 0;     /* So far unknown... */
1733         c->x86_vendor_id[0] = '\0'; /* Unset */
1734         c->x86_model_id[0] = '\0';  /* Unset */
1735         c->x86_max_cores = 1;
1736 #ifdef CONFIG_X86_64
1737         c->x86_clflush_size = 64;
1738         c->x86_phys_bits = 36;
1739         c->x86_virt_bits = 48;
1740 #else
1741         c->cpuid_level = -1;    /* CPUID not detected */
1742         c->x86_clflush_size = 32;
1743         c->x86_phys_bits = 32;
1744         c->x86_virt_bits = 32;
1745 #endif
1746         c->x86_cache_alignment = c->x86_clflush_size;
1747         memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1748 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
1749         memset(&c->vmx_capability, 0, sizeof(c->vmx_capability));
1750 #endif
1751
1752         generic_identify(c);
1753
1754         cpu_parse_topology(c);
1755
1756         if (this_cpu->c_identify)
1757                 this_cpu->c_identify(c);
1758
1759         /* Clear/Set all flags overridden by options, after probe */
1760         apply_forced_caps(c);
1761
1762         /*
1763          * Set default APIC and TSC_DEADLINE MSR fencing flag. AMD and
1764          * Hygon will clear it in ->c_init() below.
1765          */
1766         set_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE);
1767
1768         /*
1769          * Vendor-specific initialization.  In this section we
1770          * canonicalize the feature flags, meaning if there are
1771          * features a certain CPU supports which CPUID doesn't
1772          * tell us, CPUID claiming incorrect flags, or other bugs,
1773          * we handle them here.
1774          *
1775          * At the end of this section, c->x86_capability better
1776          * indicate the features this CPU genuinely supports!
1777          */
1778         if (this_cpu->c_init)
1779                 this_cpu->c_init(c);
1780
1781         /* Disable the PN if appropriate */
1782         squash_the_stupid_serial_number(c);
1783
1784         /* Set up SMEP/SMAP/UMIP */
1785         setup_smep(c);
1786         setup_smap(c);
1787         setup_umip(c);
1788
1789         /* Enable FSGSBASE instructions if available. */
1790         if (cpu_has(c, X86_FEATURE_FSGSBASE)) {
1791                 cr4_set_bits(X86_CR4_FSGSBASE);
1792                 elf_hwcap2 |= HWCAP2_FSGSBASE;
1793         }
1794
1795         /*
1796          * The vendor-specific functions might have changed features.
1797          * Now we do "generic changes."
1798          */
1799
1800         /* Filter out anything that depends on CPUID levels we don't have */
1801         filter_cpuid_features(c, true);
1802
1803         /* If the model name is still unset, do table lookup. */
1804         if (!c->x86_model_id[0]) {
1805                 const char *p;
1806                 p = table_lookup_model(c);
1807                 if (p)
1808                         strcpy(c->x86_model_id, p);
1809                 else
1810                         /* Last resort... */
1811                         sprintf(c->x86_model_id, "%02x/%02x",
1812                                 c->x86, c->x86_model);
1813         }
1814
1815         x86_init_rdrand(c);
1816         setup_pku(c);
1817         setup_cet(c);
1818
1819         /*
1820          * Clear/Set all flags overridden by options, need do it
1821          * before following smp all cpus cap AND.
1822          */
1823         apply_forced_caps(c);
1824
1825         /*
1826          * On SMP, boot_cpu_data holds the common feature set between
1827          * all CPUs; so make sure that we indicate which features are
1828          * common between the CPUs.  The first time this routine gets
1829          * executed, c == &boot_cpu_data.
1830          */
1831         if (c != &boot_cpu_data) {
1832                 /* AND the already accumulated flags with these */
1833                 for (i = 0; i < NCAPINTS; i++)
1834                         boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1835
1836                 /* OR, i.e. replicate the bug flags */
1837                 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1838                         c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1839         }
1840
1841         ppin_init(c);
1842
1843         /* Init Machine Check Exception if available. */
1844         mcheck_cpu_init(c);
1845
1846         select_idle_routine(c);
1847
1848 #ifdef CONFIG_NUMA
1849         numa_add_cpu(smp_processor_id());
1850 #endif
1851 }
1852
1853 /*
1854  * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1855  * on 32-bit kernels:
1856  */
1857 #ifdef CONFIG_X86_32
1858 void enable_sep_cpu(void)
1859 {
1860         struct tss_struct *tss;
1861         int cpu;
1862
1863         if (!boot_cpu_has(X86_FEATURE_SEP))
1864                 return;
1865
1866         cpu = get_cpu();
1867         tss = &per_cpu(cpu_tss_rw, cpu);
1868
1869         /*
1870          * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1871          * see the big comment in struct x86_hw_tss's definition.
1872          */
1873
1874         tss->x86_tss.ss1 = __KERNEL_CS;
1875         wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1876         wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1877         wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1878
1879         put_cpu();
1880 }
1881 #endif
1882
1883 static __init void identify_boot_cpu(void)
1884 {
1885         identify_cpu(&boot_cpu_data);
1886         if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT))
1887                 pr_info("CET detected: Indirect Branch Tracking enabled\n");
1888 #ifdef CONFIG_X86_32
1889         enable_sep_cpu();
1890 #endif
1891         cpu_detect_tlb(&boot_cpu_data);
1892         setup_cr_pinning();
1893
1894         tsx_init();
1895         tdx_init();
1896         lkgs_init();
1897 }
1898
1899 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1900 {
1901         BUG_ON(c == &boot_cpu_data);
1902         identify_cpu(c);
1903 #ifdef CONFIG_X86_32
1904         enable_sep_cpu();
1905 #endif
1906         x86_spec_ctrl_setup_ap();
1907         update_srbds_msr();
1908         if (boot_cpu_has_bug(X86_BUG_GDS))
1909                 update_gds_msr();
1910
1911         tsx_ap_init();
1912 }
1913
1914 void print_cpu_info(struct cpuinfo_x86 *c)
1915 {
1916         const char *vendor = NULL;
1917
1918         if (c->x86_vendor < X86_VENDOR_NUM) {
1919                 vendor = this_cpu->c_vendor;
1920         } else {
1921                 if (c->cpuid_level >= 0)
1922                         vendor = c->x86_vendor_id;
1923         }
1924
1925         if (vendor && !strstr(c->x86_model_id, vendor))
1926                 pr_cont("%s ", vendor);
1927
1928         if (c->x86_model_id[0])
1929                 pr_cont("%s", c->x86_model_id);
1930         else
1931                 pr_cont("%d86", c->x86);
1932
1933         pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1934
1935         if (c->x86_stepping || c->cpuid_level >= 0)
1936                 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
1937         else
1938                 pr_cont(")\n");
1939 }
1940
1941 /*
1942  * clearcpuid= was already parsed in cpu_parse_early_param().  This dummy
1943  * function prevents it from becoming an environment variable for init.
1944  */
1945 static __init int setup_clearcpuid(char *arg)
1946 {
1947         return 1;
1948 }
1949 __setup("clearcpuid=", setup_clearcpuid);
1950
1951 DEFINE_PER_CPU_ALIGNED(struct pcpu_hot, pcpu_hot) = {
1952         .current_task   = &init_task,
1953         .preempt_count  = INIT_PREEMPT_COUNT,
1954         .top_of_stack   = TOP_OF_INIT_STACK,
1955 };
1956 EXPORT_PER_CPU_SYMBOL(pcpu_hot);
1957
1958 #ifdef CONFIG_X86_64
1959 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data,
1960                      fixed_percpu_data) __aligned(PAGE_SIZE) __visible;
1961 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data);
1962
1963 static void wrmsrl_cstar(unsigned long val)
1964 {
1965         /*
1966          * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR
1967          * is so far ignored by the CPU, but raises a #VE trap in a TDX
1968          * guest. Avoid the pointless write on all Intel CPUs.
1969          */
1970         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
1971                 wrmsrl(MSR_CSTAR, val);
1972 }
1973
1974 /* May not be marked __init: used by software suspend */
1975 void syscall_init(void)
1976 {
1977         wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1978         wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1979
1980         if (ia32_enabled()) {
1981                 wrmsrl_cstar((unsigned long)entry_SYSCALL_compat);
1982                 /*
1983                  * This only works on Intel CPUs.
1984                  * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1985                  * This does not cause SYSENTER to jump to the wrong location, because
1986                  * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1987                  */
1988                 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1989                 wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
1990                             (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
1991                 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1992         } else {
1993                 wrmsrl_cstar((unsigned long)entry_SYSCALL32_ignore);
1994                 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1995                 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1996                 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1997         }
1998
1999         /*
2000          * Flags to clear on syscall; clear as much as possible
2001          * to minimize user space-kernel interference.
2002          */
2003         wrmsrl(MSR_SYSCALL_MASK,
2004                X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF|
2005                X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF|
2006                X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF|
2007                X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF|
2008                X86_EFLAGS_AC|X86_EFLAGS_ID);
2009 }
2010
2011 #else   /* CONFIG_X86_64 */
2012
2013 #ifdef CONFIG_STACKPROTECTOR
2014 DEFINE_PER_CPU(unsigned long, __stack_chk_guard);
2015 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard);
2016 #endif
2017
2018 #endif  /* CONFIG_X86_64 */
2019
2020 /*
2021  * Clear all 6 debug registers:
2022  */
2023 static void clear_all_debug_regs(void)
2024 {
2025         int i;
2026
2027         for (i = 0; i < 8; i++) {
2028                 /* Ignore db4, db5 */
2029                 if ((i == 4) || (i == 5))
2030                         continue;
2031
2032                 set_debugreg(0, i);
2033         }
2034 }
2035
2036 #ifdef CONFIG_KGDB
2037 /*
2038  * Restore debug regs if using kgdbwait and you have a kernel debugger
2039  * connection established.
2040  */
2041 static void dbg_restore_debug_regs(void)
2042 {
2043         if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
2044                 arch_kgdb_ops.correct_hw_break();
2045 }
2046 #else /* ! CONFIG_KGDB */
2047 #define dbg_restore_debug_regs()
2048 #endif /* ! CONFIG_KGDB */
2049
2050 static inline void setup_getcpu(int cpu)
2051 {
2052         unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu));
2053         struct desc_struct d = { };
2054
2055         if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID))
2056                 wrmsr(MSR_TSC_AUX, cpudata, 0);
2057
2058         /* Store CPU and node number in limit. */
2059         d.limit0 = cpudata;
2060         d.limit1 = cpudata >> 16;
2061
2062         d.type = 5;             /* RO data, expand down, accessed */
2063         d.dpl = 3;              /* Visible to user code */
2064         d.s = 1;                /* Not a system segment */
2065         d.p = 1;                /* Present */
2066         d.d = 1;                /* 32-bit */
2067
2068         write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S);
2069 }
2070
2071 #ifdef CONFIG_X86_64
2072 static inline void tss_setup_ist(struct tss_struct *tss)
2073 {
2074         /* Set up the per-CPU TSS IST stacks */
2075         tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
2076         tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
2077         tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
2078         tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
2079         /* Only mapped when SEV-ES is active */
2080         tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC);
2081 }
2082 #else /* CONFIG_X86_64 */
2083 static inline void tss_setup_ist(struct tss_struct *tss) { }
2084 #endif /* !CONFIG_X86_64 */
2085
2086 static inline void tss_setup_io_bitmap(struct tss_struct *tss)
2087 {
2088         tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID;
2089
2090 #ifdef CONFIG_X86_IOPL_IOPERM
2091         tss->io_bitmap.prev_max = 0;
2092         tss->io_bitmap.prev_sequence = 0;
2093         memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap));
2094         /*
2095          * Invalidate the extra array entry past the end of the all
2096          * permission bitmap as required by the hardware.
2097          */
2098         tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL;
2099 #endif
2100 }
2101
2102 /*
2103  * Setup everything needed to handle exceptions from the IDT, including the IST
2104  * exceptions which use paranoid_entry().
2105  */
2106 void cpu_init_exception_handling(void)
2107 {
2108         struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
2109         int cpu = raw_smp_processor_id();
2110
2111         /* paranoid_entry() gets the CPU number from the GDT */
2112         setup_getcpu(cpu);
2113
2114         /* IST vectors need TSS to be set up. */
2115         tss_setup_ist(tss);
2116         tss_setup_io_bitmap(tss);
2117         set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
2118
2119         load_TR_desc();
2120
2121         /* GHCB needs to be setup to handle #VC. */
2122         setup_ghcb();
2123
2124         /* Finally load the IDT */
2125         load_current_idt();
2126 }
2127
2128 /*
2129  * cpu_init() initializes state that is per-CPU. Some data is already
2130  * initialized (naturally) in the bootstrap process, such as the GDT.  We
2131  * reload it nevertheless, this function acts as a 'CPU state barrier',
2132  * nothing should get across.
2133  */
2134 void cpu_init(void)
2135 {
2136         struct task_struct *cur = current;
2137         int cpu = raw_smp_processor_id();
2138
2139 #ifdef CONFIG_NUMA
2140         if (this_cpu_read(numa_node) == 0 &&
2141             early_cpu_to_node(cpu) != NUMA_NO_NODE)
2142                 set_numa_node(early_cpu_to_node(cpu));
2143 #endif
2144         pr_debug("Initializing CPU#%d\n", cpu);
2145
2146         if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) ||
2147             boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE))
2148                 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
2149
2150         if (IS_ENABLED(CONFIG_X86_64)) {
2151                 loadsegment(fs, 0);
2152                 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
2153                 syscall_init();
2154
2155                 wrmsrl(MSR_FS_BASE, 0);
2156                 wrmsrl(MSR_KERNEL_GS_BASE, 0);
2157                 barrier();
2158
2159                 x2apic_setup();
2160         }
2161
2162         mmgrab(&init_mm);
2163         cur->active_mm = &init_mm;
2164         BUG_ON(cur->mm);
2165         initialize_tlbstate_and_flush();
2166         enter_lazy_tlb(&init_mm, cur);
2167
2168         /*
2169          * sp0 points to the entry trampoline stack regardless of what task
2170          * is running.
2171          */
2172         load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
2173
2174         load_mm_ldt(&init_mm);
2175
2176         clear_all_debug_regs();
2177         dbg_restore_debug_regs();
2178
2179         doublefault_init_cpu_tss();
2180
2181         if (is_uv_system())
2182                 uv_cpu_init();
2183
2184         load_fixmap_gdt(cpu);
2185 }
2186
2187 #ifdef CONFIG_MICROCODE_LATE_LOADING
2188 /**
2189  * store_cpu_caps() - Store a snapshot of CPU capabilities
2190  * @curr_info: Pointer where to store it
2191  *
2192  * Returns: None
2193  */
2194 void store_cpu_caps(struct cpuinfo_x86 *curr_info)
2195 {
2196         /* Reload CPUID max function as it might've changed. */
2197         curr_info->cpuid_level = cpuid_eax(0);
2198
2199         /* Copy all capability leafs and pick up the synthetic ones. */
2200         memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability,
2201                sizeof(curr_info->x86_capability));
2202
2203         /* Get the hardware CPUID leafs */
2204         get_cpu_cap(curr_info);
2205 }
2206
2207 /**
2208  * microcode_check() - Check if any CPU capabilities changed after an update.
2209  * @prev_info:  CPU capabilities stored before an update.
2210  *
2211  * The microcode loader calls this upon late microcode load to recheck features,
2212  * only when microcode has been updated. Caller holds and CPU hotplug lock.
2213  *
2214  * Return: None
2215  */
2216 void microcode_check(struct cpuinfo_x86 *prev_info)
2217 {
2218         struct cpuinfo_x86 curr_info;
2219
2220         perf_check_microcode();
2221
2222         amd_check_microcode();
2223
2224         store_cpu_caps(&curr_info);
2225
2226         if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability,
2227                     sizeof(prev_info->x86_capability)))
2228                 return;
2229
2230         pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
2231         pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
2232 }
2233 #endif
2234
2235 /*
2236  * Invoked from core CPU hotplug code after hotplug operations
2237  */
2238 void arch_smt_update(void)
2239 {
2240         /* Handle the speculative execution misfeatures */
2241         cpu_bugs_smt_update();
2242         /* Check whether IPI broadcasting can be enabled */
2243         apic_smt_update();
2244 }
2245
2246 void __init arch_cpu_finalize_init(void)
2247 {
2248         identify_boot_cpu();
2249
2250         /*
2251          * identify_boot_cpu() initialized SMT support information, let the
2252          * core code know.
2253          */
2254         cpu_smt_set_num_threads(smp_num_siblings, smp_num_siblings);
2255
2256         if (!IS_ENABLED(CONFIG_SMP)) {
2257                 pr_info("CPU: ");
2258                 print_cpu_info(&boot_cpu_data);
2259         }
2260
2261         cpu_select_mitigations();
2262
2263         arch_smt_update();
2264
2265         if (IS_ENABLED(CONFIG_X86_32)) {
2266                 /*
2267                  * Check whether this is a real i386 which is not longer
2268                  * supported and fixup the utsname.
2269                  */
2270                 if (boot_cpu_data.x86 < 4)
2271                         panic("Kernel requires i486+ for 'invlpg' and other features");
2272
2273                 init_utsname()->machine[1] =
2274                         '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
2275         }
2276
2277         /*
2278          * Must be before alternatives because it might set or clear
2279          * feature bits.
2280          */
2281         fpu__init_system();
2282         fpu__init_cpu();
2283
2284         alternative_instructions();
2285
2286         if (IS_ENABLED(CONFIG_X86_64)) {
2287                 /*
2288                  * Make sure the first 2MB area is not mapped by huge pages
2289                  * There are typically fixed size MTRRs in there and overlapping
2290                  * MTRRs into large pages causes slow downs.
2291                  *
2292                  * Right now we don't do that with gbpages because there seems
2293                  * very little benefit for that case.
2294                  */
2295                 if (!direct_gbpages)
2296                         set_memory_4k((unsigned long)__va(0), 1);
2297         } else {
2298                 fpu__init_check_bugs();
2299         }
2300
2301         /*
2302          * This needs to be called before any devices perform DMA
2303          * operations that might use the SWIOTLB bounce buffers. It will
2304          * mark the bounce buffers as decrypted so that their usage will
2305          * not cause "plain-text" data to be decrypted when accessed. It
2306          * must be called after late_time_init() so that Hyper-V x86/x64
2307          * hypercalls work when the SWIOTLB bounce buffers are decrypted.
2308          */
2309         mem_encrypt_init();
2310 }