1 // SPDX-License-Identifier: GPL-2.0-only
3 * AMD Memory Encryption Support
5 * Copyright (C) 2019 SUSE
7 * Author: Joerg Roedel <jroedel@suse.de>
10 #define pr_fmt(fmt) "SEV: " fmt
12 #include <linux/sched/debug.h> /* For show_regs() */
13 #include <linux/percpu-defs.h>
14 #include <linux/cc_platform.h>
15 #include <linux/printk.h>
16 #include <linux/mm_types.h>
17 #include <linux/set_memory.h>
18 #include <linux/memblock.h>
19 #include <linux/kernel.h>
21 #include <linux/cpumask.h>
22 #include <linux/efi.h>
23 #include <linux/platform_device.h>
26 #include <asm/cpu_entry_area.h>
27 #include <asm/stacktrace.h>
29 #include <asm/insn-eval.h>
30 #include <asm/fpu/xcr.h>
31 #include <asm/processor.h>
32 #include <asm/realmode.h>
33 #include <asm/setup.h>
34 #include <asm/traps.h>
39 #include <asm/cpuid.h>
40 #include <asm/cmdline.h>
42 #define DR7_RESET_VALUE 0x400
44 /* AP INIT values as documented in the APM2 section "Processor Initialization State" */
45 #define AP_INIT_CS_LIMIT 0xffff
46 #define AP_INIT_DS_LIMIT 0xffff
47 #define AP_INIT_LDTR_LIMIT 0xffff
48 #define AP_INIT_GDTR_LIMIT 0xffff
49 #define AP_INIT_IDTR_LIMIT 0xffff
50 #define AP_INIT_TR_LIMIT 0xffff
51 #define AP_INIT_RFLAGS_DEFAULT 0x2
52 #define AP_INIT_DR6_DEFAULT 0xffff0ff0
53 #define AP_INIT_GPAT_DEFAULT 0x0007040600070406ULL
54 #define AP_INIT_XCR0_DEFAULT 0x1
55 #define AP_INIT_X87_FTW_DEFAULT 0x5555
56 #define AP_INIT_X87_FCW_DEFAULT 0x0040
57 #define AP_INIT_CR0_DEFAULT 0x60000010
58 #define AP_INIT_MXCSR_DEFAULT 0x1f80
60 /* For early boot hypervisor communication in SEV-ES enabled guests */
61 static struct ghcb boot_ghcb_page __bss_decrypted __aligned(PAGE_SIZE);
64 * Needs to be in the .data section because we need it NULL before bss is
67 static struct ghcb *boot_ghcb __section(".data");
69 /* Bitmap of SEV features supported by the hypervisor */
70 static u64 sev_hv_features __ro_after_init;
72 /* #VC handler runtime per-CPU data */
73 struct sev_es_runtime_data {
74 struct ghcb ghcb_page;
77 * Reserve one page per CPU as backup storage for the unencrypted GHCB.
78 * It is needed when an NMI happens while the #VC handler uses the real
79 * GHCB, and the NMI handler itself is causing another #VC exception. In
80 * that case the GHCB content of the first handler needs to be backed up
83 struct ghcb backup_ghcb;
86 * Mark the per-cpu GHCBs as in-use to detect nested #VC exceptions.
87 * There is no need for it to be atomic, because nothing is written to
88 * the GHCB between the read and the write of ghcb_active. So it is safe
89 * to use it when a nested #VC exception happens before the write.
91 * This is necessary for example in the #VC->NMI->#VC case when the NMI
92 * happens while the first #VC handler uses the GHCB. When the NMI code
93 * raises a second #VC handler it might overwrite the contents of the
94 * GHCB written by the first handler. To avoid this the content of the
95 * GHCB is saved and restored when the GHCB is detected to be in use
99 bool backup_ghcb_active;
102 * Cached DR7 value - write it on DR7 writes and return it on reads.
103 * That value will never make it to the real hardware DR7 as debugging
104 * is currently unsupported in SEV-ES guests.
113 static DEFINE_PER_CPU(struct sev_es_runtime_data*, runtime_data);
114 DEFINE_STATIC_KEY_FALSE(sev_es_enable_key);
116 static DEFINE_PER_CPU(struct sev_es_save_area *, sev_vmsa);
123 static struct sev_config sev_cfg __read_mostly;
125 static __always_inline bool on_vc_stack(struct pt_regs *regs)
127 unsigned long sp = regs->sp;
129 /* User-mode RSP is not trusted */
133 /* SYSCALL gap still has user-mode RSP */
134 if (ip_within_syscall_gap(regs))
137 return ((sp >= __this_cpu_ist_bottom_va(VC)) && (sp < __this_cpu_ist_top_va(VC)));
141 * This function handles the case when an NMI is raised in the #VC
142 * exception handler entry code, before the #VC handler has switched off
143 * its IST stack. In this case, the IST entry for #VC must be adjusted,
144 * so that any nested #VC exception will not overwrite the stack
145 * contents of the interrupted #VC handler.
147 * The IST entry is adjusted unconditionally so that it can be also be
148 * unconditionally adjusted back in __sev_es_ist_exit(). Otherwise a
149 * nested sev_es_ist_exit() call may adjust back the IST entry too
152 * The __sev_es_ist_enter() and __sev_es_ist_exit() functions always run
153 * on the NMI IST stack, as they are only called from NMI handling code
156 void noinstr __sev_es_ist_enter(struct pt_regs *regs)
158 unsigned long old_ist, new_ist;
160 /* Read old IST entry */
161 new_ist = old_ist = __this_cpu_read(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC]);
164 * If NMI happened while on the #VC IST stack, set the new IST
165 * value below regs->sp, so that the interrupted stack frame is
166 * not overwritten by subsequent #VC exceptions.
168 if (on_vc_stack(regs))
172 * Reserve additional 8 bytes and store old IST value so this
173 * adjustment can be unrolled in __sev_es_ist_exit().
175 new_ist -= sizeof(old_ist);
176 *(unsigned long *)new_ist = old_ist;
178 /* Set new IST entry */
179 this_cpu_write(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC], new_ist);
182 void noinstr __sev_es_ist_exit(void)
187 ist = __this_cpu_read(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC]);
189 if (WARN_ON(ist == __this_cpu_ist_top_va(VC)))
192 /* Read back old IST entry and write it to the TSS */
193 this_cpu_write(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC], *(unsigned long *)ist);
197 * Nothing shall interrupt this code path while holding the per-CPU
198 * GHCB. The backup GHCB is only for NMIs interrupting this path.
200 * Callers must disable local interrupts around it.
202 static noinstr struct ghcb *__sev_get_ghcb(struct ghcb_state *state)
204 struct sev_es_runtime_data *data;
207 WARN_ON(!irqs_disabled());
209 data = this_cpu_read(runtime_data);
210 ghcb = &data->ghcb_page;
212 if (unlikely(data->ghcb_active)) {
213 /* GHCB is already in use - save its contents */
215 if (unlikely(data->backup_ghcb_active)) {
217 * Backup-GHCB is also already in use. There is no way
218 * to continue here so just kill the machine. To make
219 * panic() work, mark GHCBs inactive so that messages
220 * can be printed out.
222 data->ghcb_active = false;
223 data->backup_ghcb_active = false;
225 instrumentation_begin();
226 panic("Unable to handle #VC exception! GHCB and Backup GHCB are already in use");
227 instrumentation_end();
230 /* Mark backup_ghcb active before writing to it */
231 data->backup_ghcb_active = true;
233 state->ghcb = &data->backup_ghcb;
235 /* Backup GHCB content */
236 *state->ghcb = *ghcb;
239 data->ghcb_active = true;
245 static inline u64 sev_es_rd_ghcb_msr(void)
247 return __rdmsr(MSR_AMD64_SEV_ES_GHCB);
250 static __always_inline void sev_es_wr_ghcb_msr(u64 val)
255 high = (u32)(val >> 32);
257 native_wrmsr(MSR_AMD64_SEV_ES_GHCB, low, high);
260 static int vc_fetch_insn_kernel(struct es_em_ctxt *ctxt,
261 unsigned char *buffer)
263 return copy_from_kernel_nofault(buffer, (unsigned char *)ctxt->regs->ip, MAX_INSN_SIZE);
266 static enum es_result __vc_decode_user_insn(struct es_em_ctxt *ctxt)
268 char buffer[MAX_INSN_SIZE];
271 insn_bytes = insn_fetch_from_user_inatomic(ctxt->regs, buffer);
272 if (insn_bytes == 0) {
273 /* Nothing could be copied */
274 ctxt->fi.vector = X86_TRAP_PF;
275 ctxt->fi.error_code = X86_PF_INSTR | X86_PF_USER;
276 ctxt->fi.cr2 = ctxt->regs->ip;
278 } else if (insn_bytes == -EINVAL) {
279 /* Effective RIP could not be calculated */
280 ctxt->fi.vector = X86_TRAP_GP;
281 ctxt->fi.error_code = 0;
286 if (!insn_decode_from_regs(&ctxt->insn, ctxt->regs, buffer, insn_bytes))
287 return ES_DECODE_FAILED;
289 if (ctxt->insn.immediate.got)
292 return ES_DECODE_FAILED;
295 static enum es_result __vc_decode_kern_insn(struct es_em_ctxt *ctxt)
297 char buffer[MAX_INSN_SIZE];
300 res = vc_fetch_insn_kernel(ctxt, buffer);
302 ctxt->fi.vector = X86_TRAP_PF;
303 ctxt->fi.error_code = X86_PF_INSTR;
304 ctxt->fi.cr2 = ctxt->regs->ip;
308 ret = insn_decode(&ctxt->insn, buffer, MAX_INSN_SIZE, INSN_MODE_64);
310 return ES_DECODE_FAILED;
315 static enum es_result vc_decode_insn(struct es_em_ctxt *ctxt)
317 if (user_mode(ctxt->regs))
318 return __vc_decode_user_insn(ctxt);
320 return __vc_decode_kern_insn(ctxt);
323 static enum es_result vc_write_mem(struct es_em_ctxt *ctxt,
324 char *dst, char *buf, size_t size)
326 unsigned long error_code = X86_PF_PROT | X86_PF_WRITE;
329 * This function uses __put_user() independent of whether kernel or user
330 * memory is accessed. This works fine because __put_user() does no
331 * sanity checks of the pointer being accessed. All that it does is
332 * to report when the access failed.
334 * Also, this function runs in atomic context, so __put_user() is not
335 * allowed to sleep. The page-fault handler detects that it is running
336 * in atomic context and will not try to take mmap_sem and handle the
337 * fault, so additional pagefault_enable()/disable() calls are not
340 * The access can't be done via copy_to_user() here because
341 * vc_write_mem() must not use string instructions to access unsafe
342 * memory. The reason is that MOVS is emulated by the #VC handler by
343 * splitting the move up into a read and a write and taking a nested #VC
344 * exception on whatever of them is the MMIO access. Using string
345 * instructions here would cause infinite nesting.
350 u8 __user *target = (u8 __user *)dst;
353 if (__put_user(d1, target))
359 u16 __user *target = (u16 __user *)dst;
362 if (__put_user(d2, target))
368 u32 __user *target = (u32 __user *)dst;
371 if (__put_user(d4, target))
377 u64 __user *target = (u64 __user *)dst;
380 if (__put_user(d8, target))
385 WARN_ONCE(1, "%s: Invalid size: %zu\n", __func__, size);
386 return ES_UNSUPPORTED;
392 if (user_mode(ctxt->regs))
393 error_code |= X86_PF_USER;
395 ctxt->fi.vector = X86_TRAP_PF;
396 ctxt->fi.error_code = error_code;
397 ctxt->fi.cr2 = (unsigned long)dst;
402 static enum es_result vc_read_mem(struct es_em_ctxt *ctxt,
403 char *src, char *buf, size_t size)
405 unsigned long error_code = X86_PF_PROT;
408 * This function uses __get_user() independent of whether kernel or user
409 * memory is accessed. This works fine because __get_user() does no
410 * sanity checks of the pointer being accessed. All that it does is
411 * to report when the access failed.
413 * Also, this function runs in atomic context, so __get_user() is not
414 * allowed to sleep. The page-fault handler detects that it is running
415 * in atomic context and will not try to take mmap_sem and handle the
416 * fault, so additional pagefault_enable()/disable() calls are not
419 * The access can't be done via copy_from_user() here because
420 * vc_read_mem() must not use string instructions to access unsafe
421 * memory. The reason is that MOVS is emulated by the #VC handler by
422 * splitting the move up into a read and a write and taking a nested #VC
423 * exception on whatever of them is the MMIO access. Using string
424 * instructions here would cause infinite nesting.
429 u8 __user *s = (u8 __user *)src;
431 if (__get_user(d1, s))
438 u16 __user *s = (u16 __user *)src;
440 if (__get_user(d2, s))
447 u32 __user *s = (u32 __user *)src;
449 if (__get_user(d4, s))
456 u64 __user *s = (u64 __user *)src;
457 if (__get_user(d8, s))
463 WARN_ONCE(1, "%s: Invalid size: %zu\n", __func__, size);
464 return ES_UNSUPPORTED;
470 if (user_mode(ctxt->regs))
471 error_code |= X86_PF_USER;
473 ctxt->fi.vector = X86_TRAP_PF;
474 ctxt->fi.error_code = error_code;
475 ctxt->fi.cr2 = (unsigned long)src;
480 static enum es_result vc_slow_virt_to_phys(struct ghcb *ghcb, struct es_em_ctxt *ctxt,
481 unsigned long vaddr, phys_addr_t *paddr)
483 unsigned long va = (unsigned long)vaddr;
489 pgd = __va(read_cr3_pa());
490 pgd = &pgd[pgd_index(va)];
491 pte = lookup_address_in_pgd(pgd, va, &level);
493 ctxt->fi.vector = X86_TRAP_PF;
494 ctxt->fi.cr2 = vaddr;
495 ctxt->fi.error_code = 0;
497 if (user_mode(ctxt->regs))
498 ctxt->fi.error_code |= X86_PF_USER;
503 if (WARN_ON_ONCE(pte_val(*pte) & _PAGE_ENC))
504 /* Emulated MMIO to/from encrypted memory not supported */
505 return ES_UNSUPPORTED;
507 pa = (phys_addr_t)pte_pfn(*pte) << PAGE_SHIFT;
508 pa |= va & ~page_level_mask(level);
515 /* Include code shared with pre-decompression boot stage */
516 #include "sev-shared.c"
518 static noinstr void __sev_put_ghcb(struct ghcb_state *state)
520 struct sev_es_runtime_data *data;
523 WARN_ON(!irqs_disabled());
525 data = this_cpu_read(runtime_data);
526 ghcb = &data->ghcb_page;
529 /* Restore GHCB from Backup */
530 *ghcb = *state->ghcb;
531 data->backup_ghcb_active = false;
535 * Invalidate the GHCB so a VMGEXIT instruction issued
536 * from userspace won't appear to be valid.
538 vc_ghcb_invalidate(ghcb);
539 data->ghcb_active = false;
543 void noinstr __sev_es_nmi_complete(void)
545 struct ghcb_state state;
548 ghcb = __sev_get_ghcb(&state);
550 vc_ghcb_invalidate(ghcb);
551 ghcb_set_sw_exit_code(ghcb, SVM_VMGEXIT_NMI_COMPLETE);
552 ghcb_set_sw_exit_info_1(ghcb, 0);
553 ghcb_set_sw_exit_info_2(ghcb, 0);
555 sev_es_wr_ghcb_msr(__pa_nodebug(ghcb));
558 __sev_put_ghcb(&state);
561 static u64 get_jump_table_addr(void)
563 struct ghcb_state state;
568 local_irq_save(flags);
570 ghcb = __sev_get_ghcb(&state);
572 vc_ghcb_invalidate(ghcb);
573 ghcb_set_sw_exit_code(ghcb, SVM_VMGEXIT_AP_JUMP_TABLE);
574 ghcb_set_sw_exit_info_1(ghcb, SVM_VMGEXIT_GET_AP_JUMP_TABLE);
575 ghcb_set_sw_exit_info_2(ghcb, 0);
577 sev_es_wr_ghcb_msr(__pa(ghcb));
580 if (ghcb_sw_exit_info_1_is_valid(ghcb) &&
581 ghcb_sw_exit_info_2_is_valid(ghcb))
582 ret = ghcb->save.sw_exit_info_2;
584 __sev_put_ghcb(&state);
586 local_irq_restore(flags);
591 static void pvalidate_pages(unsigned long vaddr, unsigned int npages, bool validate)
593 unsigned long vaddr_end;
596 vaddr = vaddr & PAGE_MASK;
597 vaddr_end = vaddr + (npages << PAGE_SHIFT);
599 while (vaddr < vaddr_end) {
600 rc = pvalidate(vaddr, RMP_PG_SIZE_4K, validate);
601 if (WARN(rc, "Failed to validate address 0x%lx ret %d", vaddr, rc))
602 sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PVALIDATE);
604 vaddr = vaddr + PAGE_SIZE;
608 static void __init early_set_pages_state(unsigned long paddr, unsigned int npages, enum psc_op op)
610 unsigned long paddr_end;
613 paddr = paddr & PAGE_MASK;
614 paddr_end = paddr + (npages << PAGE_SHIFT);
616 while (paddr < paddr_end) {
618 * Use the MSR protocol because this function can be called before
619 * the GHCB is established.
621 sev_es_wr_ghcb_msr(GHCB_MSR_PSC_REQ_GFN(paddr >> PAGE_SHIFT, op));
624 val = sev_es_rd_ghcb_msr();
626 if (WARN(GHCB_RESP_CODE(val) != GHCB_MSR_PSC_RESP,
627 "Wrong PSC response code: 0x%x\n",
628 (unsigned int)GHCB_RESP_CODE(val)))
631 if (WARN(GHCB_MSR_PSC_RESP_VAL(val),
632 "Failed to change page state to '%s' paddr 0x%lx error 0x%llx\n",
633 op == SNP_PAGE_STATE_PRIVATE ? "private" : "shared",
634 paddr, GHCB_MSR_PSC_RESP_VAL(val)))
637 paddr = paddr + PAGE_SIZE;
643 sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PSC);
646 void __init early_snp_set_memory_private(unsigned long vaddr, unsigned long paddr,
649 if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP))
653 * Ask the hypervisor to mark the memory pages as private in the RMP
656 early_set_pages_state(paddr, npages, SNP_PAGE_STATE_PRIVATE);
658 /* Validate the memory pages after they've been added in the RMP table. */
659 pvalidate_pages(vaddr, npages, true);
662 void __init early_snp_set_memory_shared(unsigned long vaddr, unsigned long paddr,
665 if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP))
668 /* Invalidate the memory pages before they are marked shared in the RMP table. */
669 pvalidate_pages(vaddr, npages, false);
671 /* Ask hypervisor to mark the memory pages shared in the RMP table. */
672 early_set_pages_state(paddr, npages, SNP_PAGE_STATE_SHARED);
675 void __init snp_prep_memory(unsigned long paddr, unsigned int sz, enum psc_op op)
677 unsigned long vaddr, npages;
679 vaddr = (unsigned long)__va(paddr);
680 npages = PAGE_ALIGN(sz) >> PAGE_SHIFT;
682 if (op == SNP_PAGE_STATE_PRIVATE)
683 early_snp_set_memory_private(vaddr, paddr, npages);
684 else if (op == SNP_PAGE_STATE_SHARED)
685 early_snp_set_memory_shared(vaddr, paddr, npages);
687 WARN(1, "invalid memory op %d\n", op);
690 static int vmgexit_psc(struct snp_psc_desc *desc)
692 int cur_entry, end_entry, ret = 0;
693 struct snp_psc_desc *data;
694 struct ghcb_state state;
695 struct es_em_ctxt ctxt;
700 * __sev_get_ghcb() needs to run with IRQs disabled because it is using
703 local_irq_save(flags);
705 ghcb = __sev_get_ghcb(&state);
711 /* Copy the input desc into GHCB shared buffer */
712 data = (struct snp_psc_desc *)ghcb->shared_buffer;
713 memcpy(ghcb->shared_buffer, desc, min_t(int, GHCB_SHARED_BUF_SIZE, sizeof(*desc)));
716 * As per the GHCB specification, the hypervisor can resume the guest
717 * before processing all the entries. Check whether all the entries
718 * are processed. If not, then keep retrying. Note, the hypervisor
719 * will update the data memory directly to indicate the status, so
720 * reference the data->hdr everywhere.
722 * The strategy here is to wait for the hypervisor to change the page
723 * state in the RMP table before guest accesses the memory pages. If the
724 * page state change was not successful, then later memory access will
727 cur_entry = data->hdr.cur_entry;
728 end_entry = data->hdr.end_entry;
730 while (data->hdr.cur_entry <= data->hdr.end_entry) {
731 ghcb_set_sw_scratch(ghcb, (u64)__pa(data));
733 /* This will advance the shared buffer data points to. */
734 ret = sev_es_ghcb_hv_call(ghcb, true, &ctxt, SVM_VMGEXIT_PSC, 0, 0);
737 * Page State Change VMGEXIT can pass error code through
740 if (WARN(ret || ghcb->save.sw_exit_info_2,
741 "SNP: PSC failed ret=%d exit_info_2=%llx\n",
742 ret, ghcb->save.sw_exit_info_2)) {
747 /* Verify that reserved bit is not set */
748 if (WARN(data->hdr.reserved, "Reserved bit is set in the PSC header\n")) {
754 * Sanity check that entry processing is not going backwards.
755 * This will happen only if hypervisor is tricking us.
757 if (WARN(data->hdr.end_entry > end_entry || cur_entry > data->hdr.cur_entry,
758 "SNP: PSC processing going backward, end_entry %d (got %d) cur_entry %d (got %d)\n",
759 end_entry, data->hdr.end_entry, cur_entry, data->hdr.cur_entry)) {
766 __sev_put_ghcb(&state);
769 local_irq_restore(flags);
774 static void __set_pages_state(struct snp_psc_desc *data, unsigned long vaddr,
775 unsigned long vaddr_end, int op)
785 memset(data, 0, sizeof(*data));
788 while (vaddr < vaddr_end) {
789 if (is_vmalloc_addr((void *)vaddr))
790 pfn = vmalloc_to_pfn((void *)vaddr);
792 pfn = __pa(vaddr) >> PAGE_SHIFT;
799 * Current SNP implementation doesn't keep track of the RMP page
800 * size so use 4K for simplicity.
802 e->pagesize = RMP_PG_SIZE_4K;
804 vaddr = vaddr + PAGE_SIZE;
809 if (vmgexit_psc(data))
810 sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PSC);
813 static void set_pages_state(unsigned long vaddr, unsigned int npages, int op)
815 unsigned long vaddr_end, next_vaddr;
816 struct snp_psc_desc *desc;
818 desc = kmalloc(sizeof(*desc), GFP_KERNEL_ACCOUNT);
820 panic("SNP: failed to allocate memory for PSC descriptor\n");
822 vaddr = vaddr & PAGE_MASK;
823 vaddr_end = vaddr + (npages << PAGE_SHIFT);
825 while (vaddr < vaddr_end) {
826 /* Calculate the last vaddr that fits in one struct snp_psc_desc. */
827 next_vaddr = min_t(unsigned long, vaddr_end,
828 (VMGEXIT_PSC_MAX_ENTRY * PAGE_SIZE) + vaddr);
830 __set_pages_state(desc, vaddr, next_vaddr, op);
838 void snp_set_memory_shared(unsigned long vaddr, unsigned int npages)
840 if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP))
843 pvalidate_pages(vaddr, npages, false);
845 set_pages_state(vaddr, npages, SNP_PAGE_STATE_SHARED);
848 void snp_set_memory_private(unsigned long vaddr, unsigned int npages)
850 if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP))
853 set_pages_state(vaddr, npages, SNP_PAGE_STATE_PRIVATE);
855 pvalidate_pages(vaddr, npages, true);
858 static int snp_set_vmsa(void *va, bool vmsa)
863 * Running at VMPL0 allows the kernel to change the VMSA bit for a page
864 * using the RMPADJUST instruction. However, for the instruction to
865 * succeed it must target the permissions of a lesser privileged
866 * (higher numbered) VMPL level, so use VMPL1 (refer to the RMPADJUST
867 * instruction in the AMD64 APM Volume 3).
871 attrs |= RMPADJUST_VMSA_PAGE_BIT;
873 return rmpadjust((unsigned long)va, RMP_PG_SIZE_4K, attrs);
876 #define __ATTR_BASE (SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK)
877 #define INIT_CS_ATTRIBS (__ATTR_BASE | SVM_SELECTOR_READ_MASK | SVM_SELECTOR_CODE_MASK)
878 #define INIT_DS_ATTRIBS (__ATTR_BASE | SVM_SELECTOR_WRITE_MASK)
880 #define INIT_LDTR_ATTRIBS (SVM_SELECTOR_P_MASK | 2)
881 #define INIT_TR_ATTRIBS (SVM_SELECTOR_P_MASK | 3)
883 static void *snp_alloc_vmsa_page(void)
888 * Allocate VMSA page to work around the SNP erratum where the CPU will
889 * incorrectly signal an RMP violation #PF if a large page (2MB or 1GB)
890 * collides with the RMP entry of VMSA page. The recommended workaround
891 * is to not use a large page.
893 * Allocate an 8k page which is also 8k-aligned.
895 p = alloc_pages(GFP_KERNEL_ACCOUNT | __GFP_ZERO, 1);
901 /* Free the first 4k. This page may be 2M/1G aligned and cannot be used. */
904 return page_address(p + 1);
907 static void snp_cleanup_vmsa(struct sev_es_save_area *vmsa)
911 err = snp_set_vmsa(vmsa, false);
913 pr_err("clear VMSA page failed (%u), leaking page\n", err);
915 free_page((unsigned long)vmsa);
918 static int wakeup_cpu_via_vmgexit(int apic_id, unsigned long start_ip)
920 struct sev_es_save_area *cur_vmsa, *vmsa;
921 struct ghcb_state state;
929 * The hypervisor SNP feature support check has happened earlier, just check
930 * the AP_CREATION one here.
932 if (!(sev_hv_features & GHCB_HV_FT_SNP_AP_CREATION))
936 * Verify the desired start IP against the known trampoline start IP
937 * to catch any future new trampolines that may be introduced that
938 * would require a new protected guest entry point.
940 if (WARN_ONCE(start_ip != real_mode_header->trampoline_start,
941 "Unsupported SNP start_ip: %lx\n", start_ip))
944 /* Override start_ip with known protected guest start IP */
945 start_ip = real_mode_header->sev_es_trampoline_start;
947 /* Find the logical CPU for the APIC ID */
948 for_each_present_cpu(cpu) {
949 if (arch_match_cpu_phys_id(cpu, apic_id))
952 if (cpu >= nr_cpu_ids)
955 cur_vmsa = per_cpu(sev_vmsa, cpu);
958 * A new VMSA is created each time because there is no guarantee that
959 * the current VMSA is the kernels or that the vCPU is not running. If
960 * an attempt was done to use the current VMSA with a running vCPU, a
961 * #VMEXIT of that vCPU would wipe out all of the settings being done
964 vmsa = (struct sev_es_save_area *)snp_alloc_vmsa_page();
968 /* CR4 should maintain the MCE value */
969 cr4 = native_read_cr4() & X86_CR4_MCE;
971 /* Set the CS value based on the start_ip converted to a SIPI vector */
972 sipi_vector = (start_ip >> 12);
973 vmsa->cs.base = sipi_vector << 12;
974 vmsa->cs.limit = AP_INIT_CS_LIMIT;
975 vmsa->cs.attrib = INIT_CS_ATTRIBS;
976 vmsa->cs.selector = sipi_vector << 8;
978 /* Set the RIP value based on start_ip */
979 vmsa->rip = start_ip & 0xfff;
981 /* Set AP INIT defaults as documented in the APM */
982 vmsa->ds.limit = AP_INIT_DS_LIMIT;
983 vmsa->ds.attrib = INIT_DS_ATTRIBS;
989 vmsa->gdtr.limit = AP_INIT_GDTR_LIMIT;
990 vmsa->ldtr.limit = AP_INIT_LDTR_LIMIT;
991 vmsa->ldtr.attrib = INIT_LDTR_ATTRIBS;
992 vmsa->idtr.limit = AP_INIT_IDTR_LIMIT;
993 vmsa->tr.limit = AP_INIT_TR_LIMIT;
994 vmsa->tr.attrib = INIT_TR_ATTRIBS;
997 vmsa->cr0 = AP_INIT_CR0_DEFAULT;
998 vmsa->dr7 = DR7_RESET_VALUE;
999 vmsa->dr6 = AP_INIT_DR6_DEFAULT;
1000 vmsa->rflags = AP_INIT_RFLAGS_DEFAULT;
1001 vmsa->g_pat = AP_INIT_GPAT_DEFAULT;
1002 vmsa->xcr0 = AP_INIT_XCR0_DEFAULT;
1003 vmsa->mxcsr = AP_INIT_MXCSR_DEFAULT;
1004 vmsa->x87_ftw = AP_INIT_X87_FTW_DEFAULT;
1005 vmsa->x87_fcw = AP_INIT_X87_FCW_DEFAULT;
1007 /* SVME must be set. */
1008 vmsa->efer = EFER_SVME;
1011 * Set the SNP-specific fields for this VMSA:
1013 * SEV_FEATURES (matches the SEV STATUS MSR right shifted 2 bits)
1016 vmsa->sev_features = sev_status >> 2;
1018 /* Switch the page over to a VMSA page now that it is initialized */
1019 ret = snp_set_vmsa(vmsa, true);
1021 pr_err("set VMSA page failed (%u)\n", ret);
1022 free_page((unsigned long)vmsa);
1027 /* Issue VMGEXIT AP Creation NAE event */
1028 local_irq_save(flags);
1030 ghcb = __sev_get_ghcb(&state);
1032 vc_ghcb_invalidate(ghcb);
1033 ghcb_set_rax(ghcb, vmsa->sev_features);
1034 ghcb_set_sw_exit_code(ghcb, SVM_VMGEXIT_AP_CREATION);
1035 ghcb_set_sw_exit_info_1(ghcb, ((u64)apic_id << 32) | SVM_VMGEXIT_AP_CREATE);
1036 ghcb_set_sw_exit_info_2(ghcb, __pa(vmsa));
1038 sev_es_wr_ghcb_msr(__pa(ghcb));
1041 if (!ghcb_sw_exit_info_1_is_valid(ghcb) ||
1042 lower_32_bits(ghcb->save.sw_exit_info_1)) {
1043 pr_err("SNP AP Creation error\n");
1047 __sev_put_ghcb(&state);
1049 local_irq_restore(flags);
1051 /* Perform cleanup if there was an error */
1053 snp_cleanup_vmsa(vmsa);
1057 /* Free up any previous VMSA page */
1059 snp_cleanup_vmsa(cur_vmsa);
1061 /* Record the current VMSA page */
1062 per_cpu(sev_vmsa, cpu) = vmsa;
1067 void snp_set_wakeup_secondary_cpu(void)
1069 if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP))
1073 * Always set this override if SNP is enabled. This makes it the
1074 * required method to start APs under SNP. If the hypervisor does
1075 * not support AP creation, then no APs will be started.
1077 apic->wakeup_secondary_cpu = wakeup_cpu_via_vmgexit;
1080 int sev_es_setup_ap_jump_table(struct real_mode_header *rmh)
1082 u16 startup_cs, startup_ip;
1083 phys_addr_t jump_table_pa;
1084 u64 jump_table_addr;
1085 u16 __iomem *jump_table;
1087 jump_table_addr = get_jump_table_addr();
1089 /* On UP guests there is no jump table so this is not a failure */
1090 if (!jump_table_addr)
1093 /* Check if AP Jump Table is page-aligned */
1094 if (jump_table_addr & ~PAGE_MASK)
1097 jump_table_pa = jump_table_addr & PAGE_MASK;
1099 startup_cs = (u16)(rmh->trampoline_start >> 4);
1100 startup_ip = (u16)(rmh->sev_es_trampoline_start -
1101 rmh->trampoline_start);
1103 jump_table = ioremap_encrypted(jump_table_pa, PAGE_SIZE);
1107 writew(startup_ip, &jump_table[0]);
1108 writew(startup_cs, &jump_table[1]);
1110 iounmap(jump_table);
1116 * This is needed by the OVMF UEFI firmware which will use whatever it finds in
1117 * the GHCB MSR as its GHCB to talk to the hypervisor. So make sure the per-cpu
1118 * runtime GHCBs used by the kernel are also mapped in the EFI page-table.
1120 int __init sev_es_efi_map_ghcbs(pgd_t *pgd)
1122 struct sev_es_runtime_data *data;
1123 unsigned long address, pflags;
1127 if (!cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT))
1130 pflags = _PAGE_NX | _PAGE_RW;
1132 for_each_possible_cpu(cpu) {
1133 data = per_cpu(runtime_data, cpu);
1135 address = __pa(&data->ghcb_page);
1136 pfn = address >> PAGE_SHIFT;
1138 if (kernel_map_pages_in_pgd(pgd, pfn, address, 1, pflags))
1145 static enum es_result vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
1147 struct pt_regs *regs = ctxt->regs;
1151 /* Is it a WRMSR? */
1152 exit_info_1 = (ctxt->insn.opcode.bytes[1] == 0x30) ? 1 : 0;
1154 ghcb_set_rcx(ghcb, regs->cx);
1156 ghcb_set_rax(ghcb, regs->ax);
1157 ghcb_set_rdx(ghcb, regs->dx);
1160 ret = sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_MSR,
1163 if ((ret == ES_OK) && (!exit_info_1)) {
1164 regs->ax = ghcb->save.rax;
1165 regs->dx = ghcb->save.rdx;
1171 static void snp_register_per_cpu_ghcb(void)
1173 struct sev_es_runtime_data *data;
1176 data = this_cpu_read(runtime_data);
1177 ghcb = &data->ghcb_page;
1179 snp_register_ghcb_early(__pa(ghcb));
1182 void setup_ghcb(void)
1184 if (!cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT))
1187 /* First make sure the hypervisor talks a supported protocol. */
1188 if (!sev_es_negotiate_protocol())
1189 sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_GEN_REQ);
1192 * Check whether the runtime #VC exception handler is active. It uses
1193 * the per-CPU GHCB page which is set up by sev_es_init_vc_handling().
1195 * If SNP is active, register the per-CPU GHCB page so that the runtime
1196 * exception handler can use it.
1198 if (initial_vc_handler == (unsigned long)kernel_exc_vmm_communication) {
1199 if (cc_platform_has(CC_ATTR_GUEST_SEV_SNP))
1200 snp_register_per_cpu_ghcb();
1206 * Clear the boot_ghcb. The first exception comes in before the bss
1207 * section is cleared.
1209 memset(&boot_ghcb_page, 0, PAGE_SIZE);
1211 /* Alright - Make the boot-ghcb public */
1212 boot_ghcb = &boot_ghcb_page;
1214 /* SNP guest requires that GHCB GPA must be registered. */
1215 if (cc_platform_has(CC_ATTR_GUEST_SEV_SNP))
1216 snp_register_ghcb_early(__pa(&boot_ghcb_page));
1219 #ifdef CONFIG_HOTPLUG_CPU
1220 static void sev_es_ap_hlt_loop(void)
1222 struct ghcb_state state;
1225 ghcb = __sev_get_ghcb(&state);
1228 vc_ghcb_invalidate(ghcb);
1229 ghcb_set_sw_exit_code(ghcb, SVM_VMGEXIT_AP_HLT_LOOP);
1230 ghcb_set_sw_exit_info_1(ghcb, 0);
1231 ghcb_set_sw_exit_info_2(ghcb, 0);
1233 sev_es_wr_ghcb_msr(__pa(ghcb));
1236 /* Wakeup signal? */
1237 if (ghcb_sw_exit_info_2_is_valid(ghcb) &&
1238 ghcb->save.sw_exit_info_2)
1242 __sev_put_ghcb(&state);
1246 * Play_dead handler when running under SEV-ES. This is needed because
1247 * the hypervisor can't deliver an SIPI request to restart the AP.
1248 * Instead the kernel has to issue a VMGEXIT to halt the VCPU until the
1249 * hypervisor wakes it up again.
1251 static void sev_es_play_dead(void)
1255 /* IRQs now disabled */
1257 sev_es_ap_hlt_loop();
1260 * If we get here, the VCPU was woken up again. Jump to CPU
1261 * startup code to get it back online.
1265 #else /* CONFIG_HOTPLUG_CPU */
1266 #define sev_es_play_dead native_play_dead
1267 #endif /* CONFIG_HOTPLUG_CPU */
1270 static void __init sev_es_setup_play_dead(void)
1272 smp_ops.play_dead = sev_es_play_dead;
1275 static inline void sev_es_setup_play_dead(void) { }
1278 static void __init alloc_runtime_data(int cpu)
1280 struct sev_es_runtime_data *data;
1282 data = memblock_alloc(sizeof(*data), PAGE_SIZE);
1284 panic("Can't allocate SEV-ES runtime data");
1286 per_cpu(runtime_data, cpu) = data;
1289 static void __init init_ghcb(int cpu)
1291 struct sev_es_runtime_data *data;
1294 data = per_cpu(runtime_data, cpu);
1296 err = early_set_memory_decrypted((unsigned long)&data->ghcb_page,
1297 sizeof(data->ghcb_page));
1299 panic("Can't map GHCBs unencrypted");
1301 memset(&data->ghcb_page, 0, sizeof(data->ghcb_page));
1303 data->ghcb_active = false;
1304 data->backup_ghcb_active = false;
1307 void __init sev_es_init_vc_handling(void)
1311 BUILD_BUG_ON(offsetof(struct sev_es_runtime_data, ghcb_page) % PAGE_SIZE);
1313 if (!cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT))
1316 if (!sev_es_check_cpu_features())
1317 panic("SEV-ES CPU Features missing");
1320 * SNP is supported in v2 of the GHCB spec which mandates support for HV
1323 if (cc_platform_has(CC_ATTR_GUEST_SEV_SNP)) {
1324 sev_hv_features = get_hv_features();
1326 if (!(sev_hv_features & GHCB_HV_FT_SNP))
1327 sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SNP_UNSUPPORTED);
1330 /* Enable SEV-ES special handling */
1331 static_branch_enable(&sev_es_enable_key);
1333 /* Initialize per-cpu GHCB pages */
1334 for_each_possible_cpu(cpu) {
1335 alloc_runtime_data(cpu);
1339 sev_es_setup_play_dead();
1341 /* Secondary CPUs use the runtime #VC handler */
1342 initial_vc_handler = (unsigned long)kernel_exc_vmm_communication;
1345 static void __init vc_early_forward_exception(struct es_em_ctxt *ctxt)
1347 int trapnr = ctxt->fi.vector;
1349 if (trapnr == X86_TRAP_PF)
1350 native_write_cr2(ctxt->fi.cr2);
1352 ctxt->regs->orig_ax = ctxt->fi.error_code;
1353 do_early_exception(ctxt->regs, trapnr);
1356 static long *vc_insn_get_rm(struct es_em_ctxt *ctxt)
1361 reg_array = (long *)ctxt->regs;
1362 offset = insn_get_modrm_rm_off(&ctxt->insn, ctxt->regs);
1367 offset /= sizeof(long);
1369 return reg_array + offset;
1371 static enum es_result vc_do_mmio(struct ghcb *ghcb, struct es_em_ctxt *ctxt,
1372 unsigned int bytes, bool read)
1374 u64 exit_code, exit_info_1, exit_info_2;
1375 unsigned long ghcb_pa = __pa(ghcb);
1380 ref = insn_get_addr_ref(&ctxt->insn, ctxt->regs);
1381 if (ref == (void __user *)-1L)
1382 return ES_UNSUPPORTED;
1384 exit_code = read ? SVM_VMGEXIT_MMIO_READ : SVM_VMGEXIT_MMIO_WRITE;
1386 res = vc_slow_virt_to_phys(ghcb, ctxt, (unsigned long)ref, &paddr);
1388 if (res == ES_EXCEPTION && !read)
1389 ctxt->fi.error_code |= X86_PF_WRITE;
1394 exit_info_1 = paddr;
1395 /* Can never be greater than 8 */
1396 exit_info_2 = bytes;
1398 ghcb_set_sw_scratch(ghcb, ghcb_pa + offsetof(struct ghcb, shared_buffer));
1400 return sev_es_ghcb_hv_call(ghcb, true, ctxt, exit_code, exit_info_1, exit_info_2);
1404 * The MOVS instruction has two memory operands, which raises the
1405 * problem that it is not known whether the access to the source or the
1406 * destination caused the #VC exception (and hence whether an MMIO read
1407 * or write operation needs to be emulated).
1409 * Instead of playing games with walking page-tables and trying to guess
1410 * whether the source or destination is an MMIO range, split the move
1411 * into two operations, a read and a write with only one memory operand.
1412 * This will cause a nested #VC exception on the MMIO address which can
1415 * This implementation has the benefit that it also supports MOVS where
1416 * source _and_ destination are MMIO regions.
1418 * It will slow MOVS on MMIO down a lot, but in SEV-ES guests it is a
1419 * rare operation. If it turns out to be a performance problem the split
1420 * operations can be moved to memcpy_fromio() and memcpy_toio().
1422 static enum es_result vc_handle_mmio_movs(struct es_em_ctxt *ctxt,
1425 unsigned long ds_base, es_base;
1426 unsigned char *src, *dst;
1427 unsigned char buffer[8];
1432 ds_base = insn_get_seg_base(ctxt->regs, INAT_SEG_REG_DS);
1433 es_base = insn_get_seg_base(ctxt->regs, INAT_SEG_REG_ES);
1435 if (ds_base == -1L || es_base == -1L) {
1436 ctxt->fi.vector = X86_TRAP_GP;
1437 ctxt->fi.error_code = 0;
1438 return ES_EXCEPTION;
1441 src = ds_base + (unsigned char *)ctxt->regs->si;
1442 dst = es_base + (unsigned char *)ctxt->regs->di;
1444 ret = vc_read_mem(ctxt, src, buffer, bytes);
1448 ret = vc_write_mem(ctxt, dst, buffer, bytes);
1452 if (ctxt->regs->flags & X86_EFLAGS_DF)
1457 ctxt->regs->si += off;
1458 ctxt->regs->di += off;
1460 rep = insn_has_rep_prefix(&ctxt->insn);
1462 ctxt->regs->cx -= 1;
1464 if (!rep || ctxt->regs->cx == 0)
1470 static enum es_result vc_handle_mmio(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
1472 struct insn *insn = &ctxt->insn;
1473 unsigned int bytes = 0;
1474 enum mmio_type mmio;
1479 mmio = insn_decode_mmio(insn, &bytes);
1480 if (mmio == MMIO_DECODE_FAILED)
1481 return ES_DECODE_FAILED;
1483 if (mmio != MMIO_WRITE_IMM && mmio != MMIO_MOVS) {
1484 reg_data = insn_get_modrm_reg_ptr(insn, ctxt->regs);
1486 return ES_DECODE_FAILED;
1491 memcpy(ghcb->shared_buffer, reg_data, bytes);
1492 ret = vc_do_mmio(ghcb, ctxt, bytes, false);
1494 case MMIO_WRITE_IMM:
1495 memcpy(ghcb->shared_buffer, insn->immediate1.bytes, bytes);
1496 ret = vc_do_mmio(ghcb, ctxt, bytes, false);
1499 ret = vc_do_mmio(ghcb, ctxt, bytes, true);
1503 /* Zero-extend for 32-bit operation */
1507 memcpy(reg_data, ghcb->shared_buffer, bytes);
1509 case MMIO_READ_ZERO_EXTEND:
1510 ret = vc_do_mmio(ghcb, ctxt, bytes, true);
1514 /* Zero extend based on operand size */
1515 memset(reg_data, 0, insn->opnd_bytes);
1516 memcpy(reg_data, ghcb->shared_buffer, bytes);
1518 case MMIO_READ_SIGN_EXTEND:
1519 ret = vc_do_mmio(ghcb, ctxt, bytes, true);
1524 u8 *val = (u8 *)ghcb->shared_buffer;
1526 sign_byte = (*val & 0x80) ? 0xff : 0x00;
1528 u16 *val = (u16 *)ghcb->shared_buffer;
1530 sign_byte = (*val & 0x8000) ? 0xff : 0x00;
1533 /* Sign extend based on operand size */
1534 memset(reg_data, sign_byte, insn->opnd_bytes);
1535 memcpy(reg_data, ghcb->shared_buffer, bytes);
1538 ret = vc_handle_mmio_movs(ctxt, bytes);
1541 ret = ES_UNSUPPORTED;
1548 static enum es_result vc_handle_dr7_write(struct ghcb *ghcb,
1549 struct es_em_ctxt *ctxt)
1551 struct sev_es_runtime_data *data = this_cpu_read(runtime_data);
1552 long val, *reg = vc_insn_get_rm(ctxt);
1556 return ES_DECODE_FAILED;
1560 /* Upper 32 bits must be written as zeroes */
1562 ctxt->fi.vector = X86_TRAP_GP;
1563 ctxt->fi.error_code = 0;
1564 return ES_EXCEPTION;
1567 /* Clear out other reserved bits and set bit 10 */
1568 val = (val & 0xffff23ffL) | BIT(10);
1570 /* Early non-zero writes to DR7 are not supported */
1571 if (!data && (val & ~DR7_RESET_VALUE))
1572 return ES_UNSUPPORTED;
1574 /* Using a value of 0 for ExitInfo1 means RAX holds the value */
1575 ghcb_set_rax(ghcb, val);
1576 ret = sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_WRITE_DR7, 0, 0);
1586 static enum es_result vc_handle_dr7_read(struct ghcb *ghcb,
1587 struct es_em_ctxt *ctxt)
1589 struct sev_es_runtime_data *data = this_cpu_read(runtime_data);
1590 long *reg = vc_insn_get_rm(ctxt);
1593 return ES_DECODE_FAILED;
1598 *reg = DR7_RESET_VALUE;
1603 static enum es_result vc_handle_wbinvd(struct ghcb *ghcb,
1604 struct es_em_ctxt *ctxt)
1606 return sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_WBINVD, 0, 0);
1609 static enum es_result vc_handle_rdpmc(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
1613 ghcb_set_rcx(ghcb, ctxt->regs->cx);
1615 ret = sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_RDPMC, 0, 0);
1619 if (!(ghcb_rax_is_valid(ghcb) && ghcb_rdx_is_valid(ghcb)))
1620 return ES_VMM_ERROR;
1622 ctxt->regs->ax = ghcb->save.rax;
1623 ctxt->regs->dx = ghcb->save.rdx;
1628 static enum es_result vc_handle_monitor(struct ghcb *ghcb,
1629 struct es_em_ctxt *ctxt)
1632 * Treat it as a NOP and do not leak a physical address to the
1638 static enum es_result vc_handle_mwait(struct ghcb *ghcb,
1639 struct es_em_ctxt *ctxt)
1641 /* Treat the same as MONITOR/MONITORX */
1645 static enum es_result vc_handle_vmmcall(struct ghcb *ghcb,
1646 struct es_em_ctxt *ctxt)
1650 ghcb_set_rax(ghcb, ctxt->regs->ax);
1651 ghcb_set_cpl(ghcb, user_mode(ctxt->regs) ? 3 : 0);
1653 if (x86_platform.hyper.sev_es_hcall_prepare)
1654 x86_platform.hyper.sev_es_hcall_prepare(ghcb, ctxt->regs);
1656 ret = sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_VMMCALL, 0, 0);
1660 if (!ghcb_rax_is_valid(ghcb))
1661 return ES_VMM_ERROR;
1663 ctxt->regs->ax = ghcb->save.rax;
1666 * Call sev_es_hcall_finish() after regs->ax is already set.
1667 * This allows the hypervisor handler to overwrite it again if
1670 if (x86_platform.hyper.sev_es_hcall_finish &&
1671 !x86_platform.hyper.sev_es_hcall_finish(ghcb, ctxt->regs))
1672 return ES_VMM_ERROR;
1677 static enum es_result vc_handle_trap_ac(struct ghcb *ghcb,
1678 struct es_em_ctxt *ctxt)
1681 * Calling ecx_alignment_check() directly does not work, because it
1682 * enables IRQs and the GHCB is active. Forward the exception and call
1683 * it later from vc_forward_exception().
1685 ctxt->fi.vector = X86_TRAP_AC;
1686 ctxt->fi.error_code = 0;
1687 return ES_EXCEPTION;
1690 static enum es_result vc_handle_exitcode(struct es_em_ctxt *ctxt,
1692 unsigned long exit_code)
1694 enum es_result result;
1696 switch (exit_code) {
1697 case SVM_EXIT_READ_DR7:
1698 result = vc_handle_dr7_read(ghcb, ctxt);
1700 case SVM_EXIT_WRITE_DR7:
1701 result = vc_handle_dr7_write(ghcb, ctxt);
1703 case SVM_EXIT_EXCP_BASE + X86_TRAP_AC:
1704 result = vc_handle_trap_ac(ghcb, ctxt);
1706 case SVM_EXIT_RDTSC:
1707 case SVM_EXIT_RDTSCP:
1708 result = vc_handle_rdtsc(ghcb, ctxt, exit_code);
1710 case SVM_EXIT_RDPMC:
1711 result = vc_handle_rdpmc(ghcb, ctxt);
1714 pr_err_ratelimited("#VC exception for INVD??? Seriously???\n");
1715 result = ES_UNSUPPORTED;
1717 case SVM_EXIT_CPUID:
1718 result = vc_handle_cpuid(ghcb, ctxt);
1721 result = vc_handle_ioio(ghcb, ctxt);
1724 result = vc_handle_msr(ghcb, ctxt);
1726 case SVM_EXIT_VMMCALL:
1727 result = vc_handle_vmmcall(ghcb, ctxt);
1729 case SVM_EXIT_WBINVD:
1730 result = vc_handle_wbinvd(ghcb, ctxt);
1732 case SVM_EXIT_MONITOR:
1733 result = vc_handle_monitor(ghcb, ctxt);
1735 case SVM_EXIT_MWAIT:
1736 result = vc_handle_mwait(ghcb, ctxt);
1739 result = vc_handle_mmio(ghcb, ctxt);
1743 * Unexpected #VC exception
1745 result = ES_UNSUPPORTED;
1751 static __always_inline void vc_forward_exception(struct es_em_ctxt *ctxt)
1753 long error_code = ctxt->fi.error_code;
1754 int trapnr = ctxt->fi.vector;
1756 ctxt->regs->orig_ax = ctxt->fi.error_code;
1760 exc_general_protection(ctxt->regs, error_code);
1763 exc_invalid_op(ctxt->regs);
1766 write_cr2(ctxt->fi.cr2);
1767 exc_page_fault(ctxt->regs, error_code);
1770 exc_alignment_check(ctxt->regs, error_code);
1773 pr_emerg("Unsupported exception in #VC instruction emulation - can't continue\n");
1778 static __always_inline bool is_vc2_stack(unsigned long sp)
1780 return (sp >= __this_cpu_ist_bottom_va(VC2) && sp < __this_cpu_ist_top_va(VC2));
1783 static __always_inline bool vc_from_invalid_context(struct pt_regs *regs)
1785 unsigned long sp, prev_sp;
1787 sp = (unsigned long)regs;
1791 * If the code was already executing on the VC2 stack when the #VC
1792 * happened, let it proceed to the normal handling routine. This way the
1793 * code executing on the VC2 stack can cause #VC exceptions to get handled.
1795 return is_vc2_stack(sp) && !is_vc2_stack(prev_sp);
1798 static bool vc_raw_handle_exception(struct pt_regs *regs, unsigned long error_code)
1800 struct ghcb_state state;
1801 struct es_em_ctxt ctxt;
1802 enum es_result result;
1806 ghcb = __sev_get_ghcb(&state);
1808 vc_ghcb_invalidate(ghcb);
1809 result = vc_init_em_ctxt(&ctxt, regs, error_code);
1811 if (result == ES_OK)
1812 result = vc_handle_exitcode(&ctxt, ghcb, error_code);
1814 __sev_put_ghcb(&state);
1816 /* Done - now check the result */
1819 vc_finish_insn(&ctxt);
1821 case ES_UNSUPPORTED:
1822 pr_err_ratelimited("Unsupported exit-code 0x%02lx in #VC exception (IP: 0x%lx)\n",
1823 error_code, regs->ip);
1827 pr_err_ratelimited("Failure in communication with VMM (exit-code 0x%02lx IP: 0x%lx)\n",
1828 error_code, regs->ip);
1831 case ES_DECODE_FAILED:
1832 pr_err_ratelimited("Failed to decode instruction (exit-code 0x%02lx IP: 0x%lx)\n",
1833 error_code, regs->ip);
1837 vc_forward_exception(&ctxt);
1843 pr_emerg("Unknown result in %s():%d\n", __func__, result);
1845 * Emulating the instruction which caused the #VC exception
1846 * failed - can't continue so print debug information
1854 static __always_inline bool vc_is_db(unsigned long error_code)
1856 return error_code == SVM_EXIT_EXCP_BASE + X86_TRAP_DB;
1860 * Runtime #VC exception handler when raised from kernel mode. Runs in NMI mode
1861 * and will panic when an error happens.
1863 DEFINE_IDTENTRY_VC_KERNEL(exc_vmm_communication)
1865 irqentry_state_t irq_state;
1868 * With the current implementation it is always possible to switch to a
1869 * safe stack because #VC exceptions only happen at known places, like
1870 * intercepted instructions or accesses to MMIO areas/IO ports. They can
1871 * also happen with code instrumentation when the hypervisor intercepts
1872 * #DB, but the critical paths are forbidden to be instrumented, so #DB
1873 * exceptions currently also only happen in safe places.
1875 * But keep this here in case the noinstr annotations are violated due
1878 if (unlikely(vc_from_invalid_context(regs))) {
1879 instrumentation_begin();
1880 panic("Can't handle #VC exception from unsupported context\n");
1881 instrumentation_end();
1885 * Handle #DB before calling into !noinstr code to avoid recursive #DB.
1887 if (vc_is_db(error_code)) {
1892 irq_state = irqentry_nmi_enter(regs);
1894 instrumentation_begin();
1896 if (!vc_raw_handle_exception(regs, error_code)) {
1897 /* Show some debug info */
1900 /* Ask hypervisor to sev_es_terminate */
1901 sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_GEN_REQ);
1903 /* If that fails and we get here - just panic */
1904 panic("Returned from Terminate-Request to Hypervisor\n");
1907 instrumentation_end();
1908 irqentry_nmi_exit(regs, irq_state);
1912 * Runtime #VC exception handler when raised from user mode. Runs in IRQ mode
1913 * and will kill the current task with SIGBUS when an error happens.
1915 DEFINE_IDTENTRY_VC_USER(exc_vmm_communication)
1918 * Handle #DB before calling into !noinstr code to avoid recursive #DB.
1920 if (vc_is_db(error_code)) {
1921 noist_exc_debug(regs);
1925 irqentry_enter_from_user_mode(regs);
1926 instrumentation_begin();
1928 if (!vc_raw_handle_exception(regs, error_code)) {
1930 * Do not kill the machine if user-space triggered the
1931 * exception. Send SIGBUS instead and let user-space deal with
1934 force_sig_fault(SIGBUS, BUS_OBJERR, (void __user *)0);
1937 instrumentation_end();
1938 irqentry_exit_to_user_mode(regs);
1941 bool __init handle_vc_boot_ghcb(struct pt_regs *regs)
1943 unsigned long exit_code = regs->orig_ax;
1944 struct es_em_ctxt ctxt;
1945 enum es_result result;
1947 vc_ghcb_invalidate(boot_ghcb);
1949 result = vc_init_em_ctxt(&ctxt, regs, exit_code);
1950 if (result == ES_OK)
1951 result = vc_handle_exitcode(&ctxt, boot_ghcb, exit_code);
1953 /* Done - now check the result */
1956 vc_finish_insn(&ctxt);
1958 case ES_UNSUPPORTED:
1959 early_printk("PANIC: Unsupported exit-code 0x%02lx in early #VC exception (IP: 0x%lx)\n",
1960 exit_code, regs->ip);
1963 early_printk("PANIC: Failure in communication with VMM (exit-code 0x%02lx IP: 0x%lx)\n",
1964 exit_code, regs->ip);
1966 case ES_DECODE_FAILED:
1967 early_printk("PANIC: Failed to decode instruction (exit-code 0x%02lx IP: 0x%lx)\n",
1968 exit_code, regs->ip);
1971 vc_early_forward_exception(&ctxt);
1985 sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_GEN_REQ);
1989 * Initial set up of SNP relies on information provided by the
1990 * Confidential Computing blob, which can be passed to the kernel
1991 * in the following ways, depending on how it is booted:
1993 * - when booted via the boot/decompress kernel:
1996 * - when booted directly by firmware/bootloader (e.g. CONFIG_PVH):
1997 * - via a setup_data entry, as defined by the Linux Boot Protocol
1999 * Scan for the blob in that order.
2001 static __init struct cc_blob_sev_info *find_cc_blob(struct boot_params *bp)
2003 struct cc_blob_sev_info *cc_info;
2005 /* Boot kernel would have passed the CC blob via boot_params. */
2006 if (bp->cc_blob_address) {
2007 cc_info = (struct cc_blob_sev_info *)(unsigned long)bp->cc_blob_address;
2012 * If kernel was booted directly, without the use of the
2013 * boot/decompression kernel, the CC blob may have been passed via
2014 * setup_data instead.
2016 cc_info = find_cc_blob_setup_data(bp);
2021 if (cc_info->magic != CC_BLOB_SEV_HDR_MAGIC)
2027 bool __init snp_init(struct boot_params *bp)
2029 struct cc_blob_sev_info *cc_info;
2034 cc_info = find_cc_blob(bp);
2038 setup_cpuid_table(cc_info);
2041 * The CC blob will be used later to access the secrets page. Cache
2042 * it here like the boot kernel does.
2044 bp->cc_blob_address = (u32)(unsigned long)cc_info;
2049 void __init snp_abort(void)
2051 sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SNP_UNSUPPORTED);
2054 static void dump_cpuid_table(void)
2056 const struct snp_cpuid_table *cpuid_table = snp_cpuid_get_table();
2059 pr_info("count=%d reserved=0x%x reserved2=0x%llx\n",
2060 cpuid_table->count, cpuid_table->__reserved1, cpuid_table->__reserved2);
2062 for (i = 0; i < SNP_CPUID_COUNT_MAX; i++) {
2063 const struct snp_cpuid_fn *fn = &cpuid_table->fn[i];
2065 pr_info("index=%3d fn=0x%08x subfn=0x%08x: eax=0x%08x ebx=0x%08x ecx=0x%08x edx=0x%08x xcr0_in=0x%016llx xss_in=0x%016llx reserved=0x%016llx\n",
2066 i, fn->eax_in, fn->ecx_in, fn->eax, fn->ebx, fn->ecx,
2067 fn->edx, fn->xcr0_in, fn->xss_in, fn->__reserved);
2072 * It is useful from an auditing/testing perspective to provide an easy way
2073 * for the guest owner to know that the CPUID table has been initialized as
2074 * expected, but that initialization happens too early in boot to print any
2075 * sort of indicator, and there's not really any other good place to do it,
2078 static int __init report_cpuid_table(void)
2080 const struct snp_cpuid_table *cpuid_table = snp_cpuid_get_table();
2082 if (!cpuid_table->count)
2085 pr_info("Using SNP CPUID table, %d entries present.\n",
2086 cpuid_table->count);
2093 arch_initcall(report_cpuid_table);
2095 static int __init init_sev_config(char *str)
2099 while ((s = strsep(&str, ","))) {
2100 if (!strcmp(s, "debug")) {
2101 sev_cfg.debug = true;
2105 pr_info("SEV command-line option '%s' was not recognized\n", s);
2110 __setup("sev=", init_sev_config);
2112 int snp_issue_guest_request(u64 exit_code, struct snp_req_data *input, unsigned long *fw_err)
2114 struct ghcb_state state;
2115 struct es_em_ctxt ctxt;
2116 unsigned long flags;
2120 if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP))
2127 * __sev_get_ghcb() needs to run with IRQs disabled because it is using
2130 local_irq_save(flags);
2132 ghcb = __sev_get_ghcb(&state);
2138 vc_ghcb_invalidate(ghcb);
2140 if (exit_code == SVM_VMGEXIT_EXT_GUEST_REQUEST) {
2141 ghcb_set_rax(ghcb, input->data_gpa);
2142 ghcb_set_rbx(ghcb, input->data_npages);
2145 ret = sev_es_ghcb_hv_call(ghcb, true, &ctxt, exit_code, input->req_gpa, input->resp_gpa);
2149 if (ghcb->save.sw_exit_info_2) {
2150 /* Number of expected pages are returned in RBX */
2151 if (exit_code == SVM_VMGEXIT_EXT_GUEST_REQUEST &&
2152 ghcb->save.sw_exit_info_2 == SNP_GUEST_REQ_INVALID_LEN)
2153 input->data_npages = ghcb_get_rbx(ghcb);
2155 *fw_err = ghcb->save.sw_exit_info_2;
2161 __sev_put_ghcb(&state);
2163 local_irq_restore(flags);
2167 EXPORT_SYMBOL_GPL(snp_issue_guest_request);
2169 static struct platform_device sev_guest_device = {
2170 .name = "sev-guest",
2174 static u64 get_secrets_page(void)
2176 u64 pa_data = boot_params.cc_blob_address;
2177 struct cc_blob_sev_info info;
2181 * The CC blob contains the address of the secrets page, check if the
2187 map = early_memremap(pa_data, sizeof(info));
2188 memcpy(&info, map, sizeof(info));
2189 early_memunmap(map, sizeof(info));
2191 /* smoke-test the secrets page passed */
2192 if (!info.secrets_phys || info.secrets_len != PAGE_SIZE)
2195 return info.secrets_phys;
2198 static int __init snp_init_platform_device(void)
2200 struct sev_guest_platform_data data;
2203 if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP))
2206 gpa = get_secrets_page();
2210 data.secrets_gpa = gpa;
2211 if (platform_device_add_data(&sev_guest_device, &data, sizeof(data)))
2214 if (platform_device_register(&sev_guest_device))
2217 pr_info("SNP guest platform device initialized.\n");
2220 device_initcall(snp_init_platform_device);