1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * x86 SMP booting functions
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/export.h>
45 #include <linux/sched.h>
46 #include <linux/sched/topology.h>
47 #include <linux/sched/hotplug.h>
48 #include <linux/sched/task_stack.h>
49 #include <linux/percpu.h>
50 #include <linux/memblock.h>
51 #include <linux/err.h>
52 #include <linux/nmi.h>
53 #include <linux/tboot.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
56 #include <linux/kexec.h>
57 #include <linux/numa.h>
58 #include <linux/pgtable.h>
59 #include <linux/overflow.h>
60 #include <linux/stackprotector.h>
61 #include <linux/cpuhotplug.h>
62 #include <linux/mc146818rtc.h>
65 #include <asm/cacheinfo.h>
69 #include <asm/realmode.h>
72 #include <asm/tlbflush.h>
74 #include <asm/mwait.h>
76 #include <asm/io_apic.h>
77 #include <asm/fpu/api.h>
78 #include <asm/setup.h>
79 #include <asm/uv/uv.h>
80 #include <asm/microcode.h>
81 #include <asm/i8259.h>
83 #include <asm/qspinlock.h>
84 #include <asm/intel-family.h>
85 #include <asm/cpu_device_id.h>
86 #include <asm/spec-ctrl.h>
87 #include <asm/hw_irq.h>
88 #include <asm/stackprotector.h>
90 #include <asm/spec-ctrl.h>
92 /* representing HT siblings of each logical CPU */
93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
94 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
96 /* representing HT and core siblings of each logical CPU */
97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
98 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
100 /* representing HT, core, and die siblings of each logical CPU */
101 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
102 EXPORT_PER_CPU_SYMBOL(cpu_die_map);
104 /* Per CPU bogomips and other parameters */
105 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
106 EXPORT_PER_CPU_SYMBOL(cpu_info);
108 /* CPUs which are the primary SMT threads */
109 struct cpumask __cpu_primary_thread_mask __read_mostly;
111 /* Representing CPUs for which sibling maps can be computed */
112 static cpumask_var_t cpu_sibling_setup_mask;
114 struct mwait_cpu_dead {
115 unsigned int control;
119 #define CPUDEAD_MWAIT_WAIT 0xDEADBEEF
120 #define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD
123 * Cache line aligned data for mwait_play_dead(). Separate on purpose so
124 * that it's unlikely to be touched by other CPUs.
126 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead);
128 /* Maximum number of SMT threads on any online core */
129 int __read_mostly __max_smt_threads = 1;
131 /* Flag to indicate if a complete sched domain rebuild is required */
132 bool x86_topology_update;
134 int arch_update_cpu_topology(void)
136 int retval = x86_topology_update;
138 x86_topology_update = false;
142 static unsigned int smpboot_warm_reset_vector_count;
144 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
148 spin_lock_irqsave(&rtc_lock, flags);
149 if (!smpboot_warm_reset_vector_count++) {
150 CMOS_WRITE(0xa, 0xf);
151 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4;
152 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf;
154 spin_unlock_irqrestore(&rtc_lock, flags);
157 static inline void smpboot_restore_warm_reset_vector(void)
162 * Paranoid: Set warm reset code and vector here back
165 spin_lock_irqsave(&rtc_lock, flags);
166 if (!--smpboot_warm_reset_vector_count) {
168 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
170 spin_unlock_irqrestore(&rtc_lock, flags);
174 /* Run the next set of setup steps for the upcoming CPU */
175 static void ap_starting(void)
177 int cpuid = smp_processor_id();
179 /* Mop up eventual mwait_play_dead() wreckage */
180 this_cpu_write(mwait_cpu_dead.status, 0);
181 this_cpu_write(mwait_cpu_dead.control, 0);
184 * If woken up by an INIT in an 82489DX configuration the alive
185 * synchronization guarantees that the CPU does not reach this
186 * point before an INIT_deassert IPI reaches the local APIC, so it
187 * is now safe to touch the local APIC.
189 * Set up this CPU, first the APIC, which is probably redundant on
194 /* Save the processor parameters. */
195 smp_store_cpu_info(cpuid);
198 * The topology information must be up to date before
199 * notify_cpu_starting().
201 set_cpu_sibling_map(cpuid);
203 ap_init_aperfmperf();
205 pr_debug("Stack at about %p\n", &cpuid);
210 * This runs the AP through all the cpuhp states to its target
211 * state CPUHP_ONLINE.
213 notify_cpu_starting(cpuid);
216 static void ap_calibrate_delay(void)
219 * Calibrate the delay loop and update loops_per_jiffy in cpu_data.
220 * smp_store_cpu_info() stored a value that is close but not as
221 * accurate as the value just calculated.
223 * As this is invoked after the TSC synchronization check,
224 * calibrate_delay_is_known() will skip the calibration routine
225 * when TSC is synchronized across sockets.
228 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy;
232 * Activate a secondary processor.
234 static void notrace start_secondary(void *unused)
237 * Don't put *anything* except direct CPU state initialization
238 * before cpu_init(), SMP booting is too fragile that we want to
239 * limit the things done here to the most necessary things.
244 * 32-bit specific. 64-bit reaches this code with the correct page
245 * table established. Yet another historical divergence.
247 if (IS_ENABLED(CONFIG_X86_32)) {
248 /* switch away from the initial page table */
249 load_cr3(swapper_pg_dir);
253 cpu_init_exception_handling();
256 * Load the microcode before reaching the AP alive synchronization
257 * point below so it is not part of the full per CPU serialized
258 * bringup part when "parallel" bringup is enabled.
260 * That's even safe when hyperthreading is enabled in the CPU as
261 * the core code starts the primary threads first and leaves the
262 * secondary threads waiting for SIPI. Loading microcode on
263 * physical cores concurrently is a safe operation.
265 * This covers both the Intel specific issue that concurrent
266 * microcode loading on SMT siblings must be prohibited and the
267 * vendor independent issue`that microcode loading which changes
268 * CPUID, MSRs etc. must be strictly serialized to maintain
269 * software state correctness.
274 * Synchronization point with the hotplug core. Sets this CPUs
275 * synchronization state to ALIVE and spin-waits for the control CPU to
276 * release this CPU for further bringup.
278 cpuhp_ap_sync_alive();
282 rcutree_report_cpu_starting(raw_smp_processor_id());
283 x86_cpuinit.early_percpu_clock_init();
287 /* Check TSC synchronization with the control CPU. */
288 check_tsc_sync_target();
291 * Calibrate the delay loop after the TSC synchronization check.
292 * This allows to skip the calibration when TSC is synchronized
295 ap_calibrate_delay();
297 speculative_store_bypass_ht_init();
300 * Lock vector_lock, set CPU online and bring the vector
301 * allocator online. Online must be set with vector_lock held
302 * to prevent a concurrent irq setup/teardown from seeing a
303 * half valid vector space.
306 set_cpu_online(smp_processor_id(), true);
308 unlock_vector_lock();
309 x86_platform.nmi_init();
311 /* enable local interrupts */
314 x86_cpuinit.setup_percpu_clockev();
317 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
320 static void __init smp_store_boot_cpu_info(void)
322 struct cpuinfo_x86 *c = &cpu_data(0);
325 c->initialized = true;
329 * The bootstrap kernel entry code has set these up. Save them for
332 void smp_store_cpu_info(int id)
334 struct cpuinfo_x86 *c = &cpu_data(id);
336 /* Copy boot_cpu_data only on the first bringup */
341 * During boot time, CPU0 has this setup already. Save the info when
344 identify_secondary_cpu(c);
345 c->initialized = true;
349 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
351 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
353 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
357 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
359 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
361 return !WARN_ONCE(!topology_same_node(c, o),
362 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
363 "[node: %d != %d]. Ignoring dependency.\n",
364 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
367 #define link_mask(mfunc, c1, c2) \
369 cpumask_set_cpu((c1), mfunc(c2)); \
370 cpumask_set_cpu((c2), mfunc(c1)); \
373 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
375 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
376 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
378 if (c->topo.pkg_id == o->topo.pkg_id &&
379 c->topo.die_id == o->topo.die_id &&
380 c->topo.amd_node_id == o->topo.amd_node_id &&
381 per_cpu_llc_id(cpu1) == per_cpu_llc_id(cpu2)) {
382 if (c->topo.core_id == o->topo.core_id)
383 return topology_sane(c, o, "smt");
385 if ((c->topo.cu_id != 0xff) &&
386 (o->topo.cu_id != 0xff) &&
387 (c->topo.cu_id == o->topo.cu_id))
388 return topology_sane(c, o, "smt");
391 } else if (c->topo.pkg_id == o->topo.pkg_id &&
392 c->topo.die_id == o->topo.die_id &&
393 c->topo.core_id == o->topo.core_id) {
394 return topology_sane(c, o, "smt");
400 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
402 if (c->topo.pkg_id != o->topo.pkg_id || c->topo.die_id != o->topo.die_id)
405 if (cpu_feature_enabled(X86_FEATURE_TOPOEXT) && topology_amd_nodes_per_pkg() > 1)
406 return c->topo.amd_node_id == o->topo.amd_node_id;
411 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
413 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
415 /* If the arch didn't set up l2c_id, fall back to SMT */
416 if (per_cpu_l2c_id(cpu1) == BAD_APICID)
417 return match_smt(c, o);
419 /* Do not match if L2 cache id does not match: */
420 if (per_cpu_l2c_id(cpu1) != per_cpu_l2c_id(cpu2))
423 return topology_sane(c, o, "l2c");
427 * Unlike the other levels, we do not enforce keeping a
428 * multicore group inside a NUMA node. If this happens, we will
429 * discard the MC level of the topology later.
431 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
433 if (c->topo.pkg_id == o->topo.pkg_id)
439 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs.
441 * Any Intel CPU that has multiple nodes per package and does not
442 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology.
444 * When in SNC mode, these CPUs enumerate an LLC that is shared
445 * by multiple NUMA nodes. The LLC is shared for off-package data
446 * access but private to the NUMA node (half of the package) for
447 * on-package access. CPUID (the source of the information about
448 * the LLC) can only enumerate the cache as shared or unshared,
449 * but not this particular configuration.
452 static const struct x86_cpu_id intel_cod_cpu[] = {
453 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */
454 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */
455 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */
459 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
461 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu);
462 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
463 bool intel_snc = id && id->driver_data;
465 /* Do not match if we do not have a valid APICID for cpu: */
466 if (per_cpu_llc_id(cpu1) == BAD_APICID)
469 /* Do not match if LLC id does not match: */
470 if (per_cpu_llc_id(cpu1) != per_cpu_llc_id(cpu2))
474 * Allow the SNC topology without warning. Return of false
475 * means 'c' does not share the LLC of 'o'. This will be
476 * reflected to userspace.
478 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc)
481 return topology_sane(c, o, "llc");
485 static inline int x86_sched_itmt_flags(void)
487 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
490 #ifdef CONFIG_SCHED_MC
491 static int x86_core_flags(void)
493 return cpu_core_flags() | x86_sched_itmt_flags();
496 #ifdef CONFIG_SCHED_SMT
497 static int x86_smt_flags(void)
499 return cpu_smt_flags();
502 #ifdef CONFIG_SCHED_CLUSTER
503 static int x86_cluster_flags(void)
505 return cpu_cluster_flags() | x86_sched_itmt_flags();
509 static int x86_die_flags(void)
511 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
512 return x86_sched_itmt_flags();
518 * Set if a package/die has multiple NUMA nodes inside.
519 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
520 * Sub-NUMA Clustering have this.
522 static bool x86_has_numa_in_package;
524 static struct sched_domain_topology_level x86_topology[6];
526 static void __init build_sched_topology(void)
530 #ifdef CONFIG_SCHED_SMT
531 x86_topology[i++] = (struct sched_domain_topology_level){
532 cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT)
535 #ifdef CONFIG_SCHED_CLUSTER
536 x86_topology[i++] = (struct sched_domain_topology_level){
537 cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS)
540 #ifdef CONFIG_SCHED_MC
541 x86_topology[i++] = (struct sched_domain_topology_level){
542 cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC)
546 * When there is NUMA topology inside the package skip the PKG domain
547 * since the NUMA domains will auto-magically create the right spanning
548 * domains based on the SLIT.
550 if (!x86_has_numa_in_package) {
551 x86_topology[i++] = (struct sched_domain_topology_level){
552 cpu_cpu_mask, x86_die_flags, SD_INIT_NAME(PKG)
557 * There must be one trailing NULL entry left.
559 BUG_ON(i >= ARRAY_SIZE(x86_topology)-1);
561 set_sched_topology(x86_topology);
564 void set_cpu_sibling_map(int cpu)
566 bool has_smt = __max_threads_per_core > 1;
567 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
568 struct cpuinfo_x86 *c = &cpu_data(cpu);
569 struct cpuinfo_x86 *o;
572 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
575 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
576 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
577 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu));
578 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
579 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
584 for_each_cpu(i, cpu_sibling_setup_mask) {
587 if (match_pkg(c, o) && !topology_same_node(c, o))
588 x86_has_numa_in_package = true;
590 if ((i == cpu) || (has_smt && match_smt(c, o)))
591 link_mask(topology_sibling_cpumask, cpu, i);
593 if ((i == cpu) || (has_mp && match_llc(c, o)))
594 link_mask(cpu_llc_shared_mask, cpu, i);
596 if ((i == cpu) || (has_mp && match_l2c(c, o)))
597 link_mask(cpu_l2c_shared_mask, cpu, i);
599 if ((i == cpu) || (has_mp && match_die(c, o)))
600 link_mask(topology_die_cpumask, cpu, i);
603 threads = cpumask_weight(topology_sibling_cpumask(cpu));
604 if (threads > __max_smt_threads)
605 __max_smt_threads = threads;
607 for_each_cpu(i, topology_sibling_cpumask(cpu))
608 cpu_data(i).smt_active = threads > 1;
611 * This needs a separate iteration over the cpus because we rely on all
612 * topology_sibling_cpumask links to be set-up.
614 for_each_cpu(i, cpu_sibling_setup_mask) {
617 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
618 link_mask(topology_core_cpumask, cpu, i);
621 * Does this new cpu bringup a new core?
625 * for each core in package, increment
626 * the booted_cores for this new cpu
629 topology_sibling_cpumask(i)) == i)
632 * increment the core count for all
633 * the other cpus in this package
636 cpu_data(i).booted_cores++;
637 } else if (i != cpu && !c->booted_cores)
638 c->booted_cores = cpu_data(i).booted_cores;
643 /* maps the cpu to the sched domain representing multi-core */
644 const struct cpumask *cpu_coregroup_mask(int cpu)
646 return cpu_llc_shared_mask(cpu);
649 const struct cpumask *cpu_clustergroup_mask(int cpu)
651 return cpu_l2c_shared_mask(cpu);
653 EXPORT_SYMBOL_GPL(cpu_clustergroup_mask);
655 static void impress_friends(void)
658 unsigned long bogosum = 0;
660 * Allow the user to impress friends.
662 pr_debug("Before bogomips\n");
663 for_each_online_cpu(cpu)
664 bogosum += cpu_data(cpu).loops_per_jiffy;
666 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
669 (bogosum/(5000/HZ))%100);
671 pr_debug("Before bogocount - setting activated=1\n");
675 * The Multiprocessor Specification 1.4 (1997) example code suggests
676 * that there should be a 10ms delay between the BSP asserting INIT
677 * and de-asserting INIT, when starting a remote processor.
678 * But that slows boot and resume on modern processors, which include
679 * many cores and don't require that delay.
681 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
682 * Modern processor families are quirked to remove the delay entirely.
684 #define UDELAY_10MS_DEFAULT 10000
686 static unsigned int init_udelay = UINT_MAX;
688 static int __init cpu_init_udelay(char *str)
690 get_option(&str, &init_udelay);
694 early_param("cpu_init_udelay", cpu_init_udelay);
696 static void __init smp_quirk_init_udelay(void)
698 /* if cmdline changed it from default, leave it alone */
699 if (init_udelay != UINT_MAX)
702 /* if modern processor, use no delay */
703 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
704 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
705 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
709 /* else, use legacy delay */
710 init_udelay = UDELAY_10MS_DEFAULT;
714 * Wake up AP by INIT, INIT, STARTUP sequence.
716 static void send_init_sequence(u32 phys_apicid)
718 int maxlvt = lapic_get_maxlvt();
720 /* Be paranoid about clearing APIC errors. */
721 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
722 /* Due to the Pentium erratum 3AP. */
724 apic_write(APIC_ESR, 0);
728 /* Assert INIT on the target CPU */
729 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid);
730 safe_apic_wait_icr_idle();
734 /* Deassert INIT on the target CPU */
735 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
736 safe_apic_wait_icr_idle();
740 * Wake up AP by INIT, INIT, STARTUP sequence.
742 static int wakeup_secondary_cpu_via_init(u32 phys_apicid, unsigned long start_eip)
744 unsigned long send_status = 0, accept_status = 0;
745 int num_starts, j, maxlvt;
748 maxlvt = lapic_get_maxlvt();
749 send_init_sequence(phys_apicid);
754 * Should we send STARTUP IPIs ?
756 * Determine this based on the APIC version.
757 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
759 if (APIC_INTEGRATED(boot_cpu_apic_version))
765 * Run STARTUP IPI loop.
767 pr_debug("#startup loops: %d\n", num_starts);
769 for (j = 1; j <= num_starts; j++) {
770 pr_debug("Sending STARTUP #%d\n", j);
771 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
772 apic_write(APIC_ESR, 0);
774 pr_debug("After apic_write\n");
781 /* Boot on the stack */
782 /* Kick the second */
783 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
787 * Give the other CPU some time to accept the IPI.
789 if (init_udelay == 0)
794 pr_debug("Startup point 1\n");
796 pr_debug("Waiting for send to finish...\n");
797 send_status = safe_apic_wait_icr_idle();
800 * Give the other CPU some time to accept the IPI.
802 if (init_udelay == 0)
807 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
808 apic_write(APIC_ESR, 0);
809 accept_status = (apic_read(APIC_ESR) & 0xEF);
810 if (send_status || accept_status)
813 pr_debug("After Startup\n");
816 pr_err("APIC never delivered???\n");
818 pr_err("APIC delivery error (%lx)\n", accept_status);
821 return (send_status | accept_status);
824 /* reduce the number of lines printed when booting a large cpu count system */
825 static void announce_cpu(int cpu, int apicid)
827 static int width, node_width, first = 1;
828 static int current_node = NUMA_NO_NODE;
829 int node = early_cpu_to_node(cpu);
832 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
835 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
837 if (system_state < SYSTEM_RUNNING) {
839 pr_info("x86: Booting SMP configuration:\n");
841 if (node != current_node) {
842 if (current_node > (-1))
846 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
847 node_width - num_digits(node), " ", node);
850 /* Add padding for the BSP */
852 pr_cont("%*s", width + 1, " ");
855 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
857 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
861 int common_cpu_up(unsigned int cpu, struct task_struct *idle)
865 /* Just in case we booted with a single CPU. */
866 alternatives_enable_smp();
868 per_cpu(pcpu_hot.current_task, cpu) = idle;
869 cpu_init_stack_canary(cpu, idle);
871 /* Initialize the interrupt stack(s) */
872 ret = irq_init_percpu_irqstack(cpu);
877 /* Stack for startup_32 can be just as for start_secondary onwards */
878 per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle);
884 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
885 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
886 * Returns zero if startup was successfully sent, else error code from
887 * ->wakeup_secondary_cpu.
889 static int do_boot_cpu(u32 apicid, int cpu, struct task_struct *idle)
891 unsigned long start_ip = real_mode_header->trampoline_start;
895 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */
896 if (apic->wakeup_secondary_cpu_64)
897 start_ip = real_mode_header->trampoline_start64;
899 idle->thread.sp = (unsigned long)task_pt_regs(idle);
900 initial_code = (unsigned long)start_secondary;
902 if (IS_ENABLED(CONFIG_X86_32)) {
903 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
904 initial_stack = idle->thread.sp;
905 } else if (!(smpboot_control & STARTUP_PARALLEL_MASK)) {
906 smpboot_control = cpu;
909 /* Enable the espfix hack for this CPU */
912 /* So we see what's up */
913 announce_cpu(cpu, apicid);
916 * This grunge runs the startup process for
917 * the targeted processor.
919 if (x86_platform.legacy.warm_reset) {
921 pr_debug("Setting warm reset code and vector.\n");
923 smpboot_setup_warm_reset_vector(start_ip);
925 * Be paranoid about clearing APIC errors.
927 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
928 apic_write(APIC_ESR, 0);
936 * Wake up a CPU in difference cases:
937 * - Use a method from the APIC driver if one defined, with wakeup
938 * straight to 64-bit mode preferred over wakeup to RM.
940 * - Use an INIT boot APIC message
942 if (apic->wakeup_secondary_cpu_64)
943 ret = apic->wakeup_secondary_cpu_64(apicid, start_ip);
944 else if (apic->wakeup_secondary_cpu)
945 ret = apic->wakeup_secondary_cpu(apicid, start_ip);
947 ret = wakeup_secondary_cpu_via_init(apicid, start_ip);
949 /* If the wakeup mechanism failed, cleanup the warm reset vector */
951 arch_cpuhp_cleanup_kick_cpu(cpu);
955 int native_kick_ap(unsigned int cpu, struct task_struct *tidle)
957 u32 apicid = apic->cpu_present_to_apicid(cpu);
960 lockdep_assert_irqs_enabled();
962 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
964 if (apicid == BAD_APICID || !apic_id_valid(apicid)) {
965 pr_err("CPU %u has invalid APIC ID %x. Aborting bringup\n", cpu, apicid);
969 if (!test_bit(apicid, phys_cpu_present_map)) {
970 pr_err("CPU %u APIC ID %x is not present. Aborting bringup\n", cpu, apicid);
975 * Save current MTRR state in case it was changed since early boot
976 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
980 /* the FPU context is blank, nobody can own it */
981 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
983 err = common_cpu_up(cpu, tidle);
987 err = do_boot_cpu(apicid, cpu, tidle);
989 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
994 int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle)
996 return smp_ops.kick_ap_alive(cpu, tidle);
999 void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu)
1001 /* Cleanup possible dangling ends... */
1002 if (smp_ops.kick_ap_alive == native_kick_ap && x86_platform.legacy.warm_reset)
1003 smpboot_restore_warm_reset_vector();
1006 void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu)
1008 if (smp_ops.cleanup_dead_cpu)
1009 smp_ops.cleanup_dead_cpu(cpu);
1011 if (system_state == SYSTEM_RUNNING)
1012 pr_info("CPU %u is now offline\n", cpu);
1015 void arch_cpuhp_sync_state_poll(void)
1017 if (smp_ops.poll_sync_state)
1018 smp_ops.poll_sync_state();
1022 * arch_disable_smp_support() - Disables SMP support for x86 at boottime
1024 void __init arch_disable_smp_support(void)
1026 disable_ioapic_support();
1030 * Fall back to non SMP mode after errors.
1032 * RED-PEN audit/test this more. I bet there is more state messed up here.
1034 static __init void disable_smp(void)
1036 pr_info("SMP disabled\n");
1038 disable_ioapic_support();
1039 topology_reset_possible_cpus_up();
1041 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1042 cpumask_set_cpu(0, topology_core_cpumask(0));
1043 cpumask_set_cpu(0, topology_die_cpumask(0));
1046 static void __init smp_cpu_index_default(void)
1049 struct cpuinfo_x86 *c;
1051 for_each_possible_cpu(i) {
1053 /* mark all to hotplug */
1054 c->cpu_index = nr_cpu_ids;
1058 void __init smp_prepare_cpus_common(void)
1062 smp_cpu_index_default();
1065 * Setup boot CPU information
1067 smp_store_boot_cpu_info(); /* Final full version of the data */
1070 for_each_possible_cpu(i) {
1071 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1072 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1073 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL);
1074 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1075 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL);
1078 set_cpu_sibling_map(0);
1081 #ifdef CONFIG_X86_64
1082 /* Establish whether parallel bringup can be supported. */
1083 bool __init arch_cpuhp_init_parallel_bringup(void)
1085 if (!x86_cpuinit.parallel_bringup) {
1086 pr_info("Parallel CPU startup disabled by the platform\n");
1090 smpboot_control = STARTUP_READ_APICID;
1091 pr_debug("Parallel CPU startup enabled: 0x%08x\n", smpboot_control);
1097 * Prepare for SMP bootup.
1098 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1099 * for common interface support.
1101 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1103 smp_prepare_cpus_common();
1105 switch (apic_intr_mode) {
1107 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1110 case APIC_SYMMETRIC_IO_NO_ROUTING:
1112 /* Setup local timer */
1113 x86_init.timers.setup_percpu_clockev();
1115 case APIC_VIRTUAL_WIRE:
1116 case APIC_SYMMETRIC_IO:
1120 /* Setup local timer */
1121 x86_init.timers.setup_percpu_clockev();
1124 print_cpu_info(&cpu_data(0));
1128 smp_quirk_init_udelay();
1130 speculative_store_bypass_ht_init();
1132 snp_set_wakeup_secondary_cpu();
1135 void arch_thaw_secondary_cpus_begin(void)
1137 set_cache_aps_delayed_init(true);
1140 void arch_thaw_secondary_cpus_end(void)
1146 * Early setup to make printk work.
1148 void __init native_smp_prepare_boot_cpu(void)
1150 int me = smp_processor_id();
1152 /* SMP handles this from setup_per_cpu_areas() */
1153 if (!IS_ENABLED(CONFIG_SMP))
1154 switch_gdt_and_percpu_base(me);
1156 native_pv_lock_init();
1159 void __init native_smp_cpus_done(unsigned int max_cpus)
1161 pr_debug("Boot done\n");
1163 build_sched_topology();
1169 /* correctly size the local cpu masks */
1170 void __init setup_cpu_local_masks(void)
1172 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
1175 #ifdef CONFIG_HOTPLUG_CPU
1177 /* Recompute SMT state for all CPUs on offline */
1178 static void recompute_smt_state(void)
1180 int max_threads, cpu;
1183 for_each_online_cpu (cpu) {
1184 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1186 if (threads > max_threads)
1187 max_threads = threads;
1189 __max_smt_threads = max_threads;
1192 static void remove_siblinginfo(int cpu)
1195 struct cpuinfo_x86 *c = &cpu_data(cpu);
1197 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1198 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1200 * last thread sibling in this cpu core going down
1202 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1203 cpu_data(sibling).booted_cores--;
1206 for_each_cpu(sibling, topology_die_cpumask(cpu))
1207 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1209 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) {
1210 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1211 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1)
1212 cpu_data(sibling).smt_active = false;
1215 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1216 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1217 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu))
1218 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling));
1219 cpumask_clear(cpu_llc_shared_mask(cpu));
1220 cpumask_clear(cpu_l2c_shared_mask(cpu));
1221 cpumask_clear(topology_sibling_cpumask(cpu));
1222 cpumask_clear(topology_core_cpumask(cpu));
1223 cpumask_clear(topology_die_cpumask(cpu));
1224 c->topo.core_id = 0;
1225 c->booted_cores = 0;
1226 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1227 recompute_smt_state();
1230 static void remove_cpu_from_maps(int cpu)
1232 set_cpu_online(cpu, false);
1233 numa_remove_cpu(cpu);
1236 void cpu_disable_common(void)
1238 int cpu = smp_processor_id();
1240 remove_siblinginfo(cpu);
1242 /* It's now safe to remove this processor from the online map */
1244 remove_cpu_from_maps(cpu);
1245 unlock_vector_lock();
1250 int native_cpu_disable(void)
1254 ret = lapic_can_unplug_cpu();
1258 cpu_disable_common();
1261 * Disable the local APIC. Otherwise IPI broadcasts will reach
1262 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1265 * Disabling the APIC must happen after cpu_disable_common()
1266 * which invokes fixup_irqs().
1268 * Disabling the APIC preserves already set bits in IRR, but
1269 * an interrupt arriving after disabling the local APIC does not
1270 * set the corresponding IRR bit.
1272 * fixup_irqs() scans IRR for set bits so it can raise a not
1273 * yet handled interrupt on the new destination CPU via an IPI
1274 * but obviously it can't do so for IRR bits which are not set.
1275 * IOW, interrupts arriving after disabling the local APIC will
1278 apic_soft_disable();
1283 void play_dead_common(void)
1287 cpuhp_ap_report_dead();
1289 local_irq_disable();
1293 * We need to flush the caches before going to sleep, lest we have
1294 * dirty data in our caches when we come back up.
1296 static inline void mwait_play_dead(void)
1298 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead);
1299 unsigned int eax, ebx, ecx, edx;
1300 unsigned int highest_cstate = 0;
1301 unsigned int highest_subcstate = 0;
1304 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1305 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1307 if (!this_cpu_has(X86_FEATURE_MWAIT))
1309 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1311 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1314 eax = CPUID_MWAIT_LEAF;
1316 native_cpuid(&eax, &ebx, &ecx, &edx);
1319 * eax will be 0 if EDX enumeration is not valid.
1320 * Initialized below to cstate, sub_cstate value when EDX is valid.
1322 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1325 edx >>= MWAIT_SUBSTATE_SIZE;
1326 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1327 if (edx & MWAIT_SUBSTATE_MASK) {
1329 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1332 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1333 (highest_subcstate - 1);
1336 /* Set up state for the kexec() hack below */
1337 md->status = CPUDEAD_MWAIT_WAIT;
1338 md->control = CPUDEAD_MWAIT_WAIT;
1344 * The CLFLUSH is a workaround for erratum AAI65 for
1345 * the Xeon 7400 series. It's not clear it is actually
1346 * needed, but it should be harmless in either case.
1347 * The WBINVD is insufficient due to the spurious-wakeup
1348 * case where we return around the loop.
1353 __monitor(md, 0, 0);
1357 if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) {
1359 * Kexec is about to happen. Don't go back into mwait() as
1360 * the kexec kernel might overwrite text and data including
1361 * page tables and stack. So mwait() would resume when the
1362 * monitor cache line is written to and then the CPU goes
1363 * south due to overwritten text, page tables and stack.
1365 * Note: This does _NOT_ protect against a stray MCE, NMI,
1366 * SMI. They will resume execution at the instruction
1367 * following the HLT instruction and run into the problem
1368 * which this is trying to prevent.
1370 WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT);
1378 * Kick all "offline" CPUs out of mwait on kexec(). See comment in
1379 * mwait_play_dead().
1381 void smp_kick_mwait_play_dead(void)
1383 u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT;
1384 struct mwait_cpu_dead *md;
1385 unsigned int cpu, i;
1387 for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) {
1388 md = per_cpu_ptr(&mwait_cpu_dead, cpu);
1390 /* Does it sit in mwait_play_dead() ? */
1391 if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT)
1394 /* Wait up to 5ms */
1395 for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) {
1396 /* Bring it out of mwait */
1397 WRITE_ONCE(md->control, newstate);
1401 if (READ_ONCE(md->status) != newstate)
1402 pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu);
1406 void __noreturn hlt_play_dead(void)
1408 if (__this_cpu_read(cpu_info.x86) >= 4)
1416 * native_play_dead() is essentially a __noreturn function, but it can't
1417 * be marked as such as the compiler may complain about it.
1419 void native_play_dead(void)
1421 if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
1422 __update_spec_ctrl(0);
1425 tboot_shutdown(TB_SHUTDOWN_WFS);
1428 if (cpuidle_play_dead())
1432 #else /* ... !CONFIG_HOTPLUG_CPU */
1433 int native_cpu_disable(void)
1438 void native_play_dead(void)