1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * x86 SMP booting functions
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/export.h>
45 #include <linux/sched.h>
46 #include <linux/sched/topology.h>
47 #include <linux/sched/hotplug.h>
48 #include <linux/sched/task_stack.h>
49 #include <linux/percpu.h>
50 #include <linux/memblock.h>
51 #include <linux/err.h>
52 #include <linux/nmi.h>
53 #include <linux/tboot.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
56 #include <linux/kexec.h>
57 #include <linux/numa.h>
58 #include <linux/pgtable.h>
59 #include <linux/overflow.h>
60 #include <linux/stackprotector.h>
61 #include <linux/cpuhotplug.h>
62 #include <linux/mc146818rtc.h>
65 #include <asm/cacheinfo.h>
69 #include <asm/realmode.h>
72 #include <asm/tlbflush.h>
74 #include <asm/mwait.h>
76 #include <asm/io_apic.h>
77 #include <asm/fpu/api.h>
78 #include <asm/setup.h>
79 #include <asm/uv/uv.h>
80 #include <asm/microcode.h>
81 #include <asm/i8259.h>
83 #include <asm/qspinlock.h>
84 #include <asm/intel-family.h>
85 #include <asm/cpu_device_id.h>
86 #include <asm/spec-ctrl.h>
87 #include <asm/hw_irq.h>
88 #include <asm/stackprotector.h>
90 #include <asm/spec-ctrl.h>
92 /* representing HT siblings of each logical CPU */
93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
94 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
96 /* representing HT and core siblings of each logical CPU */
97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
98 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
100 /* representing HT, core, and die siblings of each logical CPU */
101 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
102 EXPORT_PER_CPU_SYMBOL(cpu_die_map);
104 /* Per CPU bogomips and other parameters */
105 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
106 EXPORT_PER_CPU_SYMBOL(cpu_info);
108 /* CPUs which are the primary SMT threads */
109 struct cpumask __cpu_primary_thread_mask __read_mostly;
111 /* Representing CPUs for which sibling maps can be computed */
112 static cpumask_var_t cpu_sibling_setup_mask;
114 struct mwait_cpu_dead {
115 unsigned int control;
119 #define CPUDEAD_MWAIT_WAIT 0xDEADBEEF
120 #define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD
123 * Cache line aligned data for mwait_play_dead(). Separate on purpose so
124 * that it's unlikely to be touched by other CPUs.
126 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead);
128 /* Logical package management. */
129 struct logical_maps {
136 /* Temporary workaround until the full topology mechanics is in place */
137 static DEFINE_PER_CPU_READ_MOSTLY(struct logical_maps, logical_maps) = {
138 .phys_pkg_id = U32_MAX,
139 .phys_die_id = U32_MAX,
142 unsigned int __max_logical_packages __read_mostly;
143 EXPORT_SYMBOL(__max_logical_packages);
144 static unsigned int logical_packages __read_mostly;
145 static unsigned int logical_die __read_mostly;
147 /* Maximum number of SMT threads on any online core */
148 int __read_mostly __max_smt_threads = 1;
150 /* Flag to indicate if a complete sched domain rebuild is required */
151 bool x86_topology_update;
153 int arch_update_cpu_topology(void)
155 int retval = x86_topology_update;
157 x86_topology_update = false;
161 static unsigned int smpboot_warm_reset_vector_count;
163 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
167 spin_lock_irqsave(&rtc_lock, flags);
168 if (!smpboot_warm_reset_vector_count++) {
169 CMOS_WRITE(0xa, 0xf);
170 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4;
171 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf;
173 spin_unlock_irqrestore(&rtc_lock, flags);
176 static inline void smpboot_restore_warm_reset_vector(void)
181 * Paranoid: Set warm reset code and vector here back
184 spin_lock_irqsave(&rtc_lock, flags);
185 if (!--smpboot_warm_reset_vector_count) {
187 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
189 spin_unlock_irqrestore(&rtc_lock, flags);
193 /* Run the next set of setup steps for the upcoming CPU */
194 static void ap_starting(void)
196 int cpuid = smp_processor_id();
198 /* Mop up eventual mwait_play_dead() wreckage */
199 this_cpu_write(mwait_cpu_dead.status, 0);
200 this_cpu_write(mwait_cpu_dead.control, 0);
203 * If woken up by an INIT in an 82489DX configuration the alive
204 * synchronization guarantees that the CPU does not reach this
205 * point before an INIT_deassert IPI reaches the local APIC, so it
206 * is now safe to touch the local APIC.
208 * Set up this CPU, first the APIC, which is probably redundant on
213 /* Save the processor parameters. */
214 smp_store_cpu_info(cpuid);
217 * The topology information must be up to date before
218 * notify_cpu_starting().
220 set_cpu_sibling_map(cpuid);
222 ap_init_aperfmperf();
224 pr_debug("Stack at about %p\n", &cpuid);
229 * This runs the AP through all the cpuhp states to its target
230 * state CPUHP_ONLINE.
232 notify_cpu_starting(cpuid);
235 static void ap_calibrate_delay(void)
238 * Calibrate the delay loop and update loops_per_jiffy in cpu_data.
239 * smp_store_cpu_info() stored a value that is close but not as
240 * accurate as the value just calculated.
242 * As this is invoked after the TSC synchronization check,
243 * calibrate_delay_is_known() will skip the calibration routine
244 * when TSC is synchronized across sockets.
247 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy;
251 * Activate a secondary processor.
253 static void notrace start_secondary(void *unused)
256 * Don't put *anything* except direct CPU state initialization
257 * before cpu_init(), SMP booting is too fragile that we want to
258 * limit the things done here to the most necessary things.
263 * 32-bit specific. 64-bit reaches this code with the correct page
264 * table established. Yet another historical divergence.
266 if (IS_ENABLED(CONFIG_X86_32)) {
267 /* switch away from the initial page table */
268 load_cr3(swapper_pg_dir);
272 cpu_init_exception_handling();
275 * Load the microcode before reaching the AP alive synchronization
276 * point below so it is not part of the full per CPU serialized
277 * bringup part when "parallel" bringup is enabled.
279 * That's even safe when hyperthreading is enabled in the CPU as
280 * the core code starts the primary threads first and leaves the
281 * secondary threads waiting for SIPI. Loading microcode on
282 * physical cores concurrently is a safe operation.
284 * This covers both the Intel specific issue that concurrent
285 * microcode loading on SMT siblings must be prohibited and the
286 * vendor independent issue`that microcode loading which changes
287 * CPUID, MSRs etc. must be strictly serialized to maintain
288 * software state correctness.
293 * Synchronization point with the hotplug core. Sets this CPUs
294 * synchronization state to ALIVE and spin-waits for the control CPU to
295 * release this CPU for further bringup.
297 cpuhp_ap_sync_alive();
301 rcutree_report_cpu_starting(raw_smp_processor_id());
302 x86_cpuinit.early_percpu_clock_init();
306 /* Check TSC synchronization with the control CPU. */
307 check_tsc_sync_target();
310 * Calibrate the delay loop after the TSC synchronization check.
311 * This allows to skip the calibration when TSC is synchronized
314 ap_calibrate_delay();
316 speculative_store_bypass_ht_init();
319 * Lock vector_lock, set CPU online and bring the vector
320 * allocator online. Online must be set with vector_lock held
321 * to prevent a concurrent irq setup/teardown from seeing a
322 * half valid vector space.
325 set_cpu_online(smp_processor_id(), true);
327 unlock_vector_lock();
328 x86_platform.nmi_init();
330 /* enable local interrupts */
333 x86_cpuinit.setup_percpu_clockev();
336 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
340 * topology_phys_to_logical_pkg - Map a physical package id to a logical
341 * @phys_pkg: The physical package id to map
343 * Returns logical package id or -1 if not found
345 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
349 for_each_possible_cpu(cpu) {
350 if (per_cpu(logical_maps.phys_pkg_id, cpu) == phys_pkg)
351 return per_cpu(logical_maps.logical_pkg_id, cpu);
355 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
358 * topology_phys_to_logical_die - Map a physical die id to logical
359 * @die_id: The physical die id to map
360 * @cur_cpu: The CPU for which the mapping is done
362 * Returns logical die id or -1 if not found
364 static int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu)
366 int cpu, proc_id = cpu_data(cur_cpu).topo.pkg_id;
368 for_each_possible_cpu(cpu) {
369 if (per_cpu(logical_maps.phys_pkg_id, cpu) == proc_id &&
370 per_cpu(logical_maps.phys_die_id, cpu) == die_id)
371 return per_cpu(logical_maps.logical_die_id, cpu);
377 * topology_update_package_map - Update the physical to logical package map
378 * @pkg: The physical package id as retrieved via CPUID
379 * @cpu: The cpu for which this is updated
381 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
385 /* Already available somewhere? */
386 new = topology_phys_to_logical_pkg(pkg);
390 new = logical_packages++;
392 pr_info("CPU %u Converting physical %u to logical package %u\n",
396 per_cpu(logical_maps.phys_pkg_id, cpu) = pkg;
397 per_cpu(logical_maps.logical_pkg_id, cpu) = new;
398 cpu_data(cpu).topo.logical_pkg_id = new;
402 * topology_update_die_map - Update the physical to logical die map
403 * @die: The die id as retrieved via CPUID
404 * @cpu: The cpu for which this is updated
406 int topology_update_die_map(unsigned int die, unsigned int cpu)
410 /* Already available somewhere? */
411 new = topology_phys_to_logical_die(die, cpu);
417 pr_info("CPU %u Converting physical %u to logical die %u\n",
421 per_cpu(logical_maps.phys_die_id, cpu) = die;
422 per_cpu(logical_maps.logical_die_id, cpu) = new;
423 cpu_data(cpu).topo.logical_die_id = new;
427 static void __init smp_store_boot_cpu_info(void)
429 int id = 0; /* CPU 0 */
430 struct cpuinfo_x86 *c = &cpu_data(id);
434 topology_update_package_map(c->topo.pkg_id, id);
435 topology_update_die_map(c->topo.die_id, id);
436 c->initialized = true;
440 * The bootstrap kernel entry code has set these up. Save them for
443 void smp_store_cpu_info(int id)
445 struct cpuinfo_x86 *c = &cpu_data(id);
447 /* Copy boot_cpu_data only on the first bringup */
452 * During boot time, CPU0 has this setup already. Save the info when
455 identify_secondary_cpu(c);
456 c->initialized = true;
460 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
462 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
464 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
468 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
470 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
472 return !WARN_ONCE(!topology_same_node(c, o),
473 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
474 "[node: %d != %d]. Ignoring dependency.\n",
475 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
478 #define link_mask(mfunc, c1, c2) \
480 cpumask_set_cpu((c1), mfunc(c2)); \
481 cpumask_set_cpu((c2), mfunc(c1)); \
484 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
486 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
487 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
489 if (c->topo.pkg_id == o->topo.pkg_id &&
490 c->topo.die_id == o->topo.die_id &&
491 c->topo.amd_node_id == o->topo.amd_node_id &&
492 per_cpu_llc_id(cpu1) == per_cpu_llc_id(cpu2)) {
493 if (c->topo.core_id == o->topo.core_id)
494 return topology_sane(c, o, "smt");
496 if ((c->topo.cu_id != 0xff) &&
497 (o->topo.cu_id != 0xff) &&
498 (c->topo.cu_id == o->topo.cu_id))
499 return topology_sane(c, o, "smt");
502 } else if (c->topo.pkg_id == o->topo.pkg_id &&
503 c->topo.die_id == o->topo.die_id &&
504 c->topo.core_id == o->topo.core_id) {
505 return topology_sane(c, o, "smt");
511 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
513 if (c->topo.pkg_id != o->topo.pkg_id || c->topo.die_id != o->topo.die_id)
516 if (cpu_feature_enabled(X86_FEATURE_TOPOEXT) && topology_amd_nodes_per_pkg() > 1)
517 return c->topo.amd_node_id == o->topo.amd_node_id;
522 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
524 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
526 /* If the arch didn't set up l2c_id, fall back to SMT */
527 if (per_cpu_l2c_id(cpu1) == BAD_APICID)
528 return match_smt(c, o);
530 /* Do not match if L2 cache id does not match: */
531 if (per_cpu_l2c_id(cpu1) != per_cpu_l2c_id(cpu2))
534 return topology_sane(c, o, "l2c");
538 * Unlike the other levels, we do not enforce keeping a
539 * multicore group inside a NUMA node. If this happens, we will
540 * discard the MC level of the topology later.
542 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
544 if (c->topo.pkg_id == o->topo.pkg_id)
550 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs.
552 * Any Intel CPU that has multiple nodes per package and does not
553 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology.
555 * When in SNC mode, these CPUs enumerate an LLC that is shared
556 * by multiple NUMA nodes. The LLC is shared for off-package data
557 * access but private to the NUMA node (half of the package) for
558 * on-package access. CPUID (the source of the information about
559 * the LLC) can only enumerate the cache as shared or unshared,
560 * but not this particular configuration.
563 static const struct x86_cpu_id intel_cod_cpu[] = {
564 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */
565 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */
566 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */
570 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
572 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu);
573 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
574 bool intel_snc = id && id->driver_data;
576 /* Do not match if we do not have a valid APICID for cpu: */
577 if (per_cpu_llc_id(cpu1) == BAD_APICID)
580 /* Do not match if LLC id does not match: */
581 if (per_cpu_llc_id(cpu1) != per_cpu_llc_id(cpu2))
585 * Allow the SNC topology without warning. Return of false
586 * means 'c' does not share the LLC of 'o'. This will be
587 * reflected to userspace.
589 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc)
592 return topology_sane(c, o, "llc");
596 static inline int x86_sched_itmt_flags(void)
598 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
601 #ifdef CONFIG_SCHED_MC
602 static int x86_core_flags(void)
604 return cpu_core_flags() | x86_sched_itmt_flags();
607 #ifdef CONFIG_SCHED_SMT
608 static int x86_smt_flags(void)
610 return cpu_smt_flags();
613 #ifdef CONFIG_SCHED_CLUSTER
614 static int x86_cluster_flags(void)
616 return cpu_cluster_flags() | x86_sched_itmt_flags();
620 static int x86_die_flags(void)
622 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
623 return x86_sched_itmt_flags();
629 * Set if a package/die has multiple NUMA nodes inside.
630 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
631 * Sub-NUMA Clustering have this.
633 static bool x86_has_numa_in_package;
635 static struct sched_domain_topology_level x86_topology[6];
637 static void __init build_sched_topology(void)
641 #ifdef CONFIG_SCHED_SMT
642 x86_topology[i++] = (struct sched_domain_topology_level){
643 cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT)
646 #ifdef CONFIG_SCHED_CLUSTER
647 x86_topology[i++] = (struct sched_domain_topology_level){
648 cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS)
651 #ifdef CONFIG_SCHED_MC
652 x86_topology[i++] = (struct sched_domain_topology_level){
653 cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC)
657 * When there is NUMA topology inside the package skip the PKG domain
658 * since the NUMA domains will auto-magically create the right spanning
659 * domains based on the SLIT.
661 if (!x86_has_numa_in_package) {
662 x86_topology[i++] = (struct sched_domain_topology_level){
663 cpu_cpu_mask, x86_die_flags, SD_INIT_NAME(PKG)
668 * There must be one trailing NULL entry left.
670 BUG_ON(i >= ARRAY_SIZE(x86_topology)-1);
672 set_sched_topology(x86_topology);
675 void set_cpu_sibling_map(int cpu)
677 bool has_smt = smp_num_siblings > 1;
678 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
679 struct cpuinfo_x86 *c = &cpu_data(cpu);
680 struct cpuinfo_x86 *o;
683 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
686 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
687 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
688 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu));
689 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
690 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
695 for_each_cpu(i, cpu_sibling_setup_mask) {
698 if (match_pkg(c, o) && !topology_same_node(c, o))
699 x86_has_numa_in_package = true;
701 if ((i == cpu) || (has_smt && match_smt(c, o)))
702 link_mask(topology_sibling_cpumask, cpu, i);
704 if ((i == cpu) || (has_mp && match_llc(c, o)))
705 link_mask(cpu_llc_shared_mask, cpu, i);
707 if ((i == cpu) || (has_mp && match_l2c(c, o)))
708 link_mask(cpu_l2c_shared_mask, cpu, i);
710 if ((i == cpu) || (has_mp && match_die(c, o)))
711 link_mask(topology_die_cpumask, cpu, i);
714 threads = cpumask_weight(topology_sibling_cpumask(cpu));
715 if (threads > __max_smt_threads)
716 __max_smt_threads = threads;
718 for_each_cpu(i, topology_sibling_cpumask(cpu))
719 cpu_data(i).smt_active = threads > 1;
722 * This needs a separate iteration over the cpus because we rely on all
723 * topology_sibling_cpumask links to be set-up.
725 for_each_cpu(i, cpu_sibling_setup_mask) {
728 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
729 link_mask(topology_core_cpumask, cpu, i);
732 * Does this new cpu bringup a new core?
736 * for each core in package, increment
737 * the booted_cores for this new cpu
740 topology_sibling_cpumask(i)) == i)
743 * increment the core count for all
744 * the other cpus in this package
747 cpu_data(i).booted_cores++;
748 } else if (i != cpu && !c->booted_cores)
749 c->booted_cores = cpu_data(i).booted_cores;
754 /* maps the cpu to the sched domain representing multi-core */
755 const struct cpumask *cpu_coregroup_mask(int cpu)
757 return cpu_llc_shared_mask(cpu);
760 const struct cpumask *cpu_clustergroup_mask(int cpu)
762 return cpu_l2c_shared_mask(cpu);
764 EXPORT_SYMBOL_GPL(cpu_clustergroup_mask);
766 static void impress_friends(void)
769 unsigned long bogosum = 0;
771 * Allow the user to impress friends.
773 pr_debug("Before bogomips\n");
774 for_each_online_cpu(cpu)
775 bogosum += cpu_data(cpu).loops_per_jiffy;
777 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
780 (bogosum/(5000/HZ))%100);
782 pr_debug("Before bogocount - setting activated=1\n");
786 * The Multiprocessor Specification 1.4 (1997) example code suggests
787 * that there should be a 10ms delay between the BSP asserting INIT
788 * and de-asserting INIT, when starting a remote processor.
789 * But that slows boot and resume on modern processors, which include
790 * many cores and don't require that delay.
792 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
793 * Modern processor families are quirked to remove the delay entirely.
795 #define UDELAY_10MS_DEFAULT 10000
797 static unsigned int init_udelay = UINT_MAX;
799 static int __init cpu_init_udelay(char *str)
801 get_option(&str, &init_udelay);
805 early_param("cpu_init_udelay", cpu_init_udelay);
807 static void __init smp_quirk_init_udelay(void)
809 /* if cmdline changed it from default, leave it alone */
810 if (init_udelay != UINT_MAX)
813 /* if modern processor, use no delay */
814 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
815 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
816 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
820 /* else, use legacy delay */
821 init_udelay = UDELAY_10MS_DEFAULT;
825 * Wake up AP by INIT, INIT, STARTUP sequence.
827 static void send_init_sequence(u32 phys_apicid)
829 int maxlvt = lapic_get_maxlvt();
831 /* Be paranoid about clearing APIC errors. */
832 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
833 /* Due to the Pentium erratum 3AP. */
835 apic_write(APIC_ESR, 0);
839 /* Assert INIT on the target CPU */
840 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid);
841 safe_apic_wait_icr_idle();
845 /* Deassert INIT on the target CPU */
846 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
847 safe_apic_wait_icr_idle();
851 * Wake up AP by INIT, INIT, STARTUP sequence.
853 static int wakeup_secondary_cpu_via_init(u32 phys_apicid, unsigned long start_eip)
855 unsigned long send_status = 0, accept_status = 0;
856 int num_starts, j, maxlvt;
859 maxlvt = lapic_get_maxlvt();
860 send_init_sequence(phys_apicid);
865 * Should we send STARTUP IPIs ?
867 * Determine this based on the APIC version.
868 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
870 if (APIC_INTEGRATED(boot_cpu_apic_version))
876 * Run STARTUP IPI loop.
878 pr_debug("#startup loops: %d\n", num_starts);
880 for (j = 1; j <= num_starts; j++) {
881 pr_debug("Sending STARTUP #%d\n", j);
882 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
883 apic_write(APIC_ESR, 0);
885 pr_debug("After apic_write\n");
892 /* Boot on the stack */
893 /* Kick the second */
894 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
898 * Give the other CPU some time to accept the IPI.
900 if (init_udelay == 0)
905 pr_debug("Startup point 1\n");
907 pr_debug("Waiting for send to finish...\n");
908 send_status = safe_apic_wait_icr_idle();
911 * Give the other CPU some time to accept the IPI.
913 if (init_udelay == 0)
918 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
919 apic_write(APIC_ESR, 0);
920 accept_status = (apic_read(APIC_ESR) & 0xEF);
921 if (send_status || accept_status)
924 pr_debug("After Startup\n");
927 pr_err("APIC never delivered???\n");
929 pr_err("APIC delivery error (%lx)\n", accept_status);
932 return (send_status | accept_status);
935 /* reduce the number of lines printed when booting a large cpu count system */
936 static void announce_cpu(int cpu, int apicid)
938 static int width, node_width, first = 1;
939 static int current_node = NUMA_NO_NODE;
940 int node = early_cpu_to_node(cpu);
943 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
946 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
948 if (system_state < SYSTEM_RUNNING) {
950 pr_info("x86: Booting SMP configuration:\n");
952 if (node != current_node) {
953 if (current_node > (-1))
957 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
958 node_width - num_digits(node), " ", node);
961 /* Add padding for the BSP */
963 pr_cont("%*s", width + 1, " ");
966 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
968 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
972 int common_cpu_up(unsigned int cpu, struct task_struct *idle)
976 /* Just in case we booted with a single CPU. */
977 alternatives_enable_smp();
979 per_cpu(pcpu_hot.current_task, cpu) = idle;
980 cpu_init_stack_canary(cpu, idle);
982 /* Initialize the interrupt stack(s) */
983 ret = irq_init_percpu_irqstack(cpu);
988 /* Stack for startup_32 can be just as for start_secondary onwards */
989 per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle);
995 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
996 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
997 * Returns zero if startup was successfully sent, else error code from
998 * ->wakeup_secondary_cpu.
1000 static int do_boot_cpu(u32 apicid, int cpu, struct task_struct *idle)
1002 unsigned long start_ip = real_mode_header->trampoline_start;
1005 #ifdef CONFIG_X86_64
1006 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */
1007 if (apic->wakeup_secondary_cpu_64)
1008 start_ip = real_mode_header->trampoline_start64;
1010 idle->thread.sp = (unsigned long)task_pt_regs(idle);
1011 initial_code = (unsigned long)start_secondary;
1013 if (IS_ENABLED(CONFIG_X86_32)) {
1014 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
1015 initial_stack = idle->thread.sp;
1016 } else if (!(smpboot_control & STARTUP_PARALLEL_MASK)) {
1017 smpboot_control = cpu;
1020 /* Enable the espfix hack for this CPU */
1021 init_espfix_ap(cpu);
1023 /* So we see what's up */
1024 announce_cpu(cpu, apicid);
1027 * This grunge runs the startup process for
1028 * the targeted processor.
1030 if (x86_platform.legacy.warm_reset) {
1032 pr_debug("Setting warm reset code and vector.\n");
1034 smpboot_setup_warm_reset_vector(start_ip);
1036 * Be paranoid about clearing APIC errors.
1038 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1039 apic_write(APIC_ESR, 0);
1040 apic_read(APIC_ESR);
1047 * Wake up a CPU in difference cases:
1048 * - Use a method from the APIC driver if one defined, with wakeup
1049 * straight to 64-bit mode preferred over wakeup to RM.
1051 * - Use an INIT boot APIC message
1053 if (apic->wakeup_secondary_cpu_64)
1054 ret = apic->wakeup_secondary_cpu_64(apicid, start_ip);
1055 else if (apic->wakeup_secondary_cpu)
1056 ret = apic->wakeup_secondary_cpu(apicid, start_ip);
1058 ret = wakeup_secondary_cpu_via_init(apicid, start_ip);
1060 /* If the wakeup mechanism failed, cleanup the warm reset vector */
1062 arch_cpuhp_cleanup_kick_cpu(cpu);
1066 int native_kick_ap(unsigned int cpu, struct task_struct *tidle)
1068 u32 apicid = apic->cpu_present_to_apicid(cpu);
1071 lockdep_assert_irqs_enabled();
1073 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1075 if (apicid == BAD_APICID || !apic_id_valid(apicid)) {
1076 pr_err("CPU %u has invalid APIC ID %x. Aborting bringup\n", cpu, apicid);
1080 if (!test_bit(apicid, phys_cpu_present_map)) {
1081 pr_err("CPU %u APIC ID %x is not present. Aborting bringup\n", cpu, apicid);
1086 * Save current MTRR state in case it was changed since early boot
1087 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1091 /* the FPU context is blank, nobody can own it */
1092 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1094 err = common_cpu_up(cpu, tidle);
1098 err = do_boot_cpu(apicid, cpu, tidle);
1100 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1105 int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle)
1107 return smp_ops.kick_ap_alive(cpu, tidle);
1110 void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu)
1112 /* Cleanup possible dangling ends... */
1113 if (smp_ops.kick_ap_alive == native_kick_ap && x86_platform.legacy.warm_reset)
1114 smpboot_restore_warm_reset_vector();
1117 void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu)
1119 if (smp_ops.cleanup_dead_cpu)
1120 smp_ops.cleanup_dead_cpu(cpu);
1122 if (system_state == SYSTEM_RUNNING)
1123 pr_info("CPU %u is now offline\n", cpu);
1126 void arch_cpuhp_sync_state_poll(void)
1128 if (smp_ops.poll_sync_state)
1129 smp_ops.poll_sync_state();
1133 * arch_disable_smp_support() - Disables SMP support for x86 at boottime
1135 void __init arch_disable_smp_support(void)
1137 disable_ioapic_support();
1141 * Fall back to non SMP mode after errors.
1143 * RED-PEN audit/test this more. I bet there is more state messed up here.
1145 static __init void disable_smp(void)
1147 pr_info("SMP disabled\n");
1149 disable_ioapic_support();
1150 topology_reset_possible_cpus_up();
1152 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1153 cpumask_set_cpu(0, topology_core_cpumask(0));
1154 cpumask_set_cpu(0, topology_die_cpumask(0));
1157 static void __init smp_cpu_index_default(void)
1160 struct cpuinfo_x86 *c;
1162 for_each_possible_cpu(i) {
1164 /* mark all to hotplug */
1165 c->cpu_index = nr_cpu_ids;
1169 void __init smp_prepare_cpus_common(void)
1173 smp_cpu_index_default();
1176 * Setup boot CPU information
1178 smp_store_boot_cpu_info(); /* Final full version of the data */
1181 for_each_possible_cpu(i) {
1182 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1183 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1184 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL);
1185 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1186 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL);
1189 set_cpu_sibling_map(0);
1192 #ifdef CONFIG_X86_64
1193 /* Establish whether parallel bringup can be supported. */
1194 bool __init arch_cpuhp_init_parallel_bringup(void)
1196 if (!x86_cpuinit.parallel_bringup) {
1197 pr_info("Parallel CPU startup disabled by the platform\n");
1201 smpboot_control = STARTUP_READ_APICID;
1202 pr_debug("Parallel CPU startup enabled: 0x%08x\n", smpboot_control);
1208 * Prepare for SMP bootup.
1209 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1210 * for common interface support.
1212 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1214 smp_prepare_cpus_common();
1216 switch (apic_intr_mode) {
1218 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1221 case APIC_SYMMETRIC_IO_NO_ROUTING:
1223 /* Setup local timer */
1224 x86_init.timers.setup_percpu_clockev();
1226 case APIC_VIRTUAL_WIRE:
1227 case APIC_SYMMETRIC_IO:
1231 /* Setup local timer */
1232 x86_init.timers.setup_percpu_clockev();
1235 print_cpu_info(&cpu_data(0));
1239 smp_quirk_init_udelay();
1241 speculative_store_bypass_ht_init();
1243 snp_set_wakeup_secondary_cpu();
1246 void arch_thaw_secondary_cpus_begin(void)
1248 set_cache_aps_delayed_init(true);
1251 void arch_thaw_secondary_cpus_end(void)
1257 * Early setup to make printk work.
1259 void __init native_smp_prepare_boot_cpu(void)
1261 int me = smp_processor_id();
1263 /* SMP handles this from setup_per_cpu_areas() */
1264 if (!IS_ENABLED(CONFIG_SMP))
1265 switch_gdt_and_percpu_base(me);
1267 native_pv_lock_init();
1270 void __init calculate_max_logical_packages(void)
1275 * Today neither Intel nor AMD support heterogeneous systems so
1276 * extrapolate the boot cpu's data to all packages.
1278 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1279 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
1280 pr_info("Max logical packages: %u\n", __max_logical_packages);
1283 void __init native_smp_cpus_done(unsigned int max_cpus)
1285 pr_debug("Boot done\n");
1287 calculate_max_logical_packages();
1288 build_sched_topology();
1294 /* correctly size the local cpu masks */
1295 void __init setup_cpu_local_masks(void)
1297 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
1300 #ifdef CONFIG_HOTPLUG_CPU
1302 /* Recompute SMT state for all CPUs on offline */
1303 static void recompute_smt_state(void)
1305 int max_threads, cpu;
1308 for_each_online_cpu (cpu) {
1309 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1311 if (threads > max_threads)
1312 max_threads = threads;
1314 __max_smt_threads = max_threads;
1317 static void remove_siblinginfo(int cpu)
1320 struct cpuinfo_x86 *c = &cpu_data(cpu);
1322 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1323 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1325 * last thread sibling in this cpu core going down
1327 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1328 cpu_data(sibling).booted_cores--;
1331 for_each_cpu(sibling, topology_die_cpumask(cpu))
1332 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1334 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) {
1335 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1336 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1)
1337 cpu_data(sibling).smt_active = false;
1340 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1341 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1342 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu))
1343 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling));
1344 cpumask_clear(cpu_llc_shared_mask(cpu));
1345 cpumask_clear(cpu_l2c_shared_mask(cpu));
1346 cpumask_clear(topology_sibling_cpumask(cpu));
1347 cpumask_clear(topology_core_cpumask(cpu));
1348 cpumask_clear(topology_die_cpumask(cpu));
1349 c->topo.core_id = 0;
1350 c->booted_cores = 0;
1351 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1352 recompute_smt_state();
1355 static void remove_cpu_from_maps(int cpu)
1357 set_cpu_online(cpu, false);
1358 numa_remove_cpu(cpu);
1361 void cpu_disable_common(void)
1363 int cpu = smp_processor_id();
1365 remove_siblinginfo(cpu);
1367 /* It's now safe to remove this processor from the online map */
1369 remove_cpu_from_maps(cpu);
1370 unlock_vector_lock();
1375 int native_cpu_disable(void)
1379 ret = lapic_can_unplug_cpu();
1383 cpu_disable_common();
1386 * Disable the local APIC. Otherwise IPI broadcasts will reach
1387 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1390 * Disabling the APIC must happen after cpu_disable_common()
1391 * which invokes fixup_irqs().
1393 * Disabling the APIC preserves already set bits in IRR, but
1394 * an interrupt arriving after disabling the local APIC does not
1395 * set the corresponding IRR bit.
1397 * fixup_irqs() scans IRR for set bits so it can raise a not
1398 * yet handled interrupt on the new destination CPU via an IPI
1399 * but obviously it can't do so for IRR bits which are not set.
1400 * IOW, interrupts arriving after disabling the local APIC will
1403 apic_soft_disable();
1408 void play_dead_common(void)
1412 cpuhp_ap_report_dead();
1414 local_irq_disable();
1418 * We need to flush the caches before going to sleep, lest we have
1419 * dirty data in our caches when we come back up.
1421 static inline void mwait_play_dead(void)
1423 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead);
1424 unsigned int eax, ebx, ecx, edx;
1425 unsigned int highest_cstate = 0;
1426 unsigned int highest_subcstate = 0;
1429 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1430 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1432 if (!this_cpu_has(X86_FEATURE_MWAIT))
1434 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1436 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1439 eax = CPUID_MWAIT_LEAF;
1441 native_cpuid(&eax, &ebx, &ecx, &edx);
1444 * eax will be 0 if EDX enumeration is not valid.
1445 * Initialized below to cstate, sub_cstate value when EDX is valid.
1447 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1450 edx >>= MWAIT_SUBSTATE_SIZE;
1451 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1452 if (edx & MWAIT_SUBSTATE_MASK) {
1454 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1457 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1458 (highest_subcstate - 1);
1461 /* Set up state for the kexec() hack below */
1462 md->status = CPUDEAD_MWAIT_WAIT;
1463 md->control = CPUDEAD_MWAIT_WAIT;
1469 * The CLFLUSH is a workaround for erratum AAI65 for
1470 * the Xeon 7400 series. It's not clear it is actually
1471 * needed, but it should be harmless in either case.
1472 * The WBINVD is insufficient due to the spurious-wakeup
1473 * case where we return around the loop.
1478 __monitor(md, 0, 0);
1482 if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) {
1484 * Kexec is about to happen. Don't go back into mwait() as
1485 * the kexec kernel might overwrite text and data including
1486 * page tables and stack. So mwait() would resume when the
1487 * monitor cache line is written to and then the CPU goes
1488 * south due to overwritten text, page tables and stack.
1490 * Note: This does _NOT_ protect against a stray MCE, NMI,
1491 * SMI. They will resume execution at the instruction
1492 * following the HLT instruction and run into the problem
1493 * which this is trying to prevent.
1495 WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT);
1503 * Kick all "offline" CPUs out of mwait on kexec(). See comment in
1504 * mwait_play_dead().
1506 void smp_kick_mwait_play_dead(void)
1508 u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT;
1509 struct mwait_cpu_dead *md;
1510 unsigned int cpu, i;
1512 for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) {
1513 md = per_cpu_ptr(&mwait_cpu_dead, cpu);
1515 /* Does it sit in mwait_play_dead() ? */
1516 if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT)
1519 /* Wait up to 5ms */
1520 for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) {
1521 /* Bring it out of mwait */
1522 WRITE_ONCE(md->control, newstate);
1526 if (READ_ONCE(md->status) != newstate)
1527 pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu);
1531 void __noreturn hlt_play_dead(void)
1533 if (__this_cpu_read(cpu_info.x86) >= 4)
1541 * native_play_dead() is essentially a __noreturn function, but it can't
1542 * be marked as such as the compiler may complain about it.
1544 void native_play_dead(void)
1546 if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
1547 __update_spec_ctrl(0);
1550 tboot_shutdown(TB_SHUTDOWN_WFS);
1553 if (cpuidle_play_dead())
1557 #else /* ... !CONFIG_HOTPLUG_CPU */
1558 int native_cpu_disable(void)
1563 void native_play_dead(void)