arch/x86/kvm/svm/svm.h

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * AMD SVM support
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *   Avi Kivity   <avi@qumranet.com>
  13  */
  14
  15 #ifndef __SVM_SVM_H
  16 #define __SVM_SVM_H
  17
  18 #include <linux/kvm_types.h>
  19 #include <linux/kvm_host.h>
  20
  21 #include <asm/svm.h>
  22
  23 static const u32 host_save_user_msrs[] = {
  24 #ifdef CONFIG_X86_64
  25         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  26         MSR_FS_BASE,
  27 #endif
  28         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  29         MSR_TSC_AUX,
  30 };
  31
  32 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  33
  34 #define MAX_DIRECT_ACCESS_MSRS  15
  35 #define MSRPM_OFFSETS   16
  36 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  37 extern bool npt_enabled;
  38
  39 enum {
  40         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
  41                             pause filter count */
  42         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
  43         VMCB_ASID,       /* ASID */
  44         VMCB_INTR,       /* int_ctl, int_vector */
  45         VMCB_NPT,        /* npt_en, nCR3, gPAT */
  46         VMCB_CR,         /* CR0, CR3, CR4, EFER */
  47         VMCB_DR,         /* DR6, DR7 */
  48         VMCB_DT,         /* GDT, IDT */
  49         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
  50         VMCB_CR2,        /* CR2 only */
  51         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
  52         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
  53                           * AVIC PHYSICAL_TABLE pointer,
  54                           * AVIC LOGICAL_TABLE pointer
  55                           */
  56         VMCB_DIRTY_MAX,
  57 };
  58
  59 /* TPR and CR2 are always written before VMRUN */
  60 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
  61
  62 struct kvm_sev_info {
  63         bool active;            /* SEV enabled guest */
  64         bool es_active;         /* SEV-ES enabled guest */
  65         unsigned int asid;      /* ASID used for this guest */
  66         unsigned int handle;    /* SEV firmware handle */
  67         int fd;                 /* SEV device fd */
  68         unsigned long pages_locked; /* Number of pages locked */
  69         struct list_head regions_list;  /* List of registered regions */
  70 };
  71
  72 struct kvm_svm {
  73         struct kvm kvm;
  74
  75         /* Struct members for AVIC */
  76         u32 avic_vm_id;
  77         struct page *avic_logical_id_table_page;
  78         struct page *avic_physical_id_table_page;
  79         struct hlist_node hnode;
  80
  81         struct kvm_sev_info sev_info;
  82 };
  83
  84 struct kvm_vcpu;
  85
  86 struct svm_nested_state {
  87         struct vmcb *hsave;
  88         u64 hsave_msr;
  89         u64 vm_cr_msr;
  90         u64 vmcb12_gpa;
  91
  92         /* These are the merged vectors */
  93         u32 *msrpm;
  94
  95         /* A VMRUN has started but has not yet been performed, so
  96          * we cannot inject a nested vmexit yet.  */
  97         bool nested_run_pending;
  98
  99         /* cache for control fields of the guest */
 100         struct vmcb_control_area ctl;
 101
 102         bool initialized;
 103 };
 104
 105 struct vcpu_svm {
 106         struct kvm_vcpu vcpu;
 107         struct vmcb *vmcb;
 108         unsigned long vmcb_pa;
 109         struct svm_cpu_data *svm_data;
 110         u32 asid;
 111         uint64_t asid_generation;
 112         uint64_t sysenter_esp;
 113         uint64_t sysenter_eip;
 114         uint64_t tsc_aux;
 115
 116         u64 msr_decfg;
 117
 118         u64 next_rip;
 119
 120         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 121         struct {
 122                 u16 fs;
 123                 u16 gs;
 124                 u16 ldt;
 125                 u64 gs_base;
 126         } host;
 127
 128         u64 spec_ctrl;
 129         /*
 130          * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
 131          * translated into the appropriate L2_CFG bits on the host to
 132          * perform speculative control.
 133          */
 134         u64 virt_spec_ctrl;
 135
 136         u32 *msrpm;
 137
 138         ulong nmi_iret_rip;
 139
 140         struct svm_nested_state nested;
 141
 142         bool nmi_singlestep;
 143         u64 nmi_singlestep_guest_rflags;
 144
 145         unsigned int3_injected;
 146         unsigned long int3_rip;
 147
 148         /* cached guest cpuid flags for faster access */
 149         bool nrips_enabled      : 1;
 150
 151         u32 ldr_reg;
 152         u32 dfr_reg;
 153         struct page *avic_backing_page;
 154         u64 *avic_physical_id_cache;
 155         bool avic_is_running;
 156
 157         /*
 158          * Per-vcpu list of struct amd_svm_iommu_ir:
 159          * This is used mainly to store interrupt remapping information used
 160          * when update the vcpu affinity. This avoids the need to scan for
 161          * IRTE and try to match ga_tag in the IOMMU driver.
 162          */
 163         struct list_head ir_list;
 164         spinlock_t ir_list_lock;
 165
 166         /* Save desired MSR intercept (read: pass-through) state */
 167         struct {
 168                 DECLARE_BITMAP(read, MAX_DIRECT_ACCESS_MSRS);
 169                 DECLARE_BITMAP(write, MAX_DIRECT_ACCESS_MSRS);
 170         } shadow_msr_intercept;
 171
 172         /* SEV-ES support */
 173         struct vmcb_save_area *vmsa;
 174         struct ghcb *ghcb;
 175 };
 176
 177 struct svm_cpu_data {
 178         int cpu;
 179
 180         u64 asid_generation;
 181         u32 max_asid;
 182         u32 next_asid;
 183         u32 min_asid;
 184         struct kvm_ldttss_desc *tss_desc;
 185
 186         struct page *save_area;
 187         struct vmcb *current_vmcb;
 188
 189         /* index = sev_asid, value = vmcb pointer */
 190         struct vmcb **sev_vmcbs;
 191 };
 192
 193 DECLARE_PER_CPU(struct svm_cpu_data *, svm_data);
 194
 195 void recalc_intercepts(struct vcpu_svm *svm);
 196
 197 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
 198 {
 199         return container_of(kvm, struct kvm_svm, kvm);
 200 }
 201
 202 static inline bool sev_guest(struct kvm *kvm)
 203 {
 204 #ifdef CONFIG_KVM_AMD_SEV
 205         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 206
 207         return sev->active;
 208 #else
 209         return false;
 210 #endif
 211 }
 212
 213 static inline bool sev_es_guest(struct kvm *kvm)
 214 {
 215 #ifdef CONFIG_KVM_AMD_SEV
 216         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 217
 218         return sev_guest(kvm) && sev->es_active;
 219 #else
 220         return false;
 221 #endif
 222 }
 223
 224 static inline void vmcb_mark_all_dirty(struct vmcb *vmcb)
 225 {
 226         vmcb->control.clean = 0;
 227 }
 228
 229 static inline void vmcb_mark_all_clean(struct vmcb *vmcb)
 230 {
 231         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 232                                & ~VMCB_ALWAYS_DIRTY_MASK;
 233 }
 234
 235 static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit)
 236 {
 237         vmcb->control.clean &= ~(1 << bit);
 238 }
 239
 240 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 241 {
 242         return container_of(vcpu, struct vcpu_svm, vcpu);
 243 }
 244
 245 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 246 {
 247         if (is_guest_mode(&svm->vcpu))
 248                 return svm->nested.hsave;
 249         else
 250                 return svm->vmcb;
 251 }
 252
 253 static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit)
 254 {
 255         WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
 256         __set_bit(bit, (unsigned long *)&control->intercepts);
 257 }
 258
 259 static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit)
 260 {
 261         WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
 262         __clear_bit(bit, (unsigned long *)&control->intercepts);
 263 }
 264
 265 static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit)
 266 {
 267         WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
 268         return test_bit(bit, (unsigned long *)&control->intercepts);
 269 }
 270
 271 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 272 {
 273         struct vmcb *vmcb = get_host_vmcb(svm);
 274
 275         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_READ);
 276         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_READ);
 277         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_READ);
 278         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_READ);
 279         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_READ);
 280         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_READ);
 281         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_READ);
 282         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ);
 283         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_WRITE);
 284         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_WRITE);
 285         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_WRITE);
 286         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_WRITE);
 287         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_WRITE);
 288         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_WRITE);
 289         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE);
 290         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE);
 291
 292         recalc_intercepts(svm);
 293 }
 294
 295 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 296 {
 297         struct vmcb *vmcb = get_host_vmcb(svm);
 298
 299         vmcb->control.intercepts[INTERCEPT_DR] = 0;
 300
 301         recalc_intercepts(svm);
 302 }
 303
 304 static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit)
 305 {
 306         struct vmcb *vmcb = get_host_vmcb(svm);
 307
 308         WARN_ON_ONCE(bit >= 32);
 309         vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);
 310
 311         recalc_intercepts(svm);
 312 }
 313
 314 static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit)
 315 {
 316         struct vmcb *vmcb = get_host_vmcb(svm);
 317
 318         WARN_ON_ONCE(bit >= 32);
 319         vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);
 320
 321         recalc_intercepts(svm);
 322 }
 323
 324 static inline void svm_set_intercept(struct vcpu_svm *svm, int bit)
 325 {
 326         struct vmcb *vmcb = get_host_vmcb(svm);
 327
 328         vmcb_set_intercept(&vmcb->control, bit);
 329
 330         recalc_intercepts(svm);
 331 }
 332
 333 static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit)
 334 {
 335         struct vmcb *vmcb = get_host_vmcb(svm);
 336
 337         vmcb_clr_intercept(&vmcb->control, bit);
 338
 339         recalc_intercepts(svm);
 340 }
 341
 342 static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit)
 343 {
 344         return vmcb_is_intercept(&svm->vmcb->control, bit);
 345 }
 346
 347 static inline bool vgif_enabled(struct vcpu_svm *svm)
 348 {
 349         return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
 350 }
 351
 352 static inline void enable_gif(struct vcpu_svm *svm)
 353 {
 354         if (vgif_enabled(svm))
 355                 svm->vmcb->control.int_ctl |= V_GIF_MASK;
 356         else
 357                 svm->vcpu.arch.hflags |= HF_GIF_MASK;
 358 }
 359
 360 static inline void disable_gif(struct vcpu_svm *svm)
 361 {
 362         if (vgif_enabled(svm))
 363                 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
 364         else
 365                 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 366 }
 367
 368 static inline bool gif_set(struct vcpu_svm *svm)
 369 {
 370         if (vgif_enabled(svm))
 371                 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
 372         else
 373                 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 374 }
 375
 376 /* svm.c */
 377 #define MSR_CR3_LEGACY_RESERVED_MASK            0xfe7U
 378 #define MSR_CR3_LEGACY_PAE_RESERVED_MASK        0x7U
 379 #define MSR_CR3_LONG_MBZ_MASK                   0xfff0000000000000U
 380 #define MSR_INVALID                             0xffffffffU
 381
 382 extern int sev;
 383 extern int sev_es;
 384
 385 u32 svm_msrpm_offset(u32 msr);
 386 u32 *svm_vcpu_alloc_msrpm(void);
 387 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm);
 388 void svm_vcpu_free_msrpm(u32 *msrpm);
 389
 390 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer);
 391 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 392 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
 393 void svm_flush_tlb(struct kvm_vcpu *vcpu);
 394 void disable_nmi_singlestep(struct vcpu_svm *svm);
 395 bool svm_smi_blocked(struct kvm_vcpu *vcpu);
 396 bool svm_nmi_blocked(struct kvm_vcpu *vcpu);
 397 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu);
 398 void svm_set_gif(struct vcpu_svm *svm, bool value);
 399
 400 /* nested.c */
 401
 402 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
 403 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
 404 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
 405
 406 static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu)
 407 {
 408         struct vcpu_svm *svm = to_svm(vcpu);
 409
 410         return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK);
 411 }
 412
 413 static inline bool nested_exit_on_smi(struct vcpu_svm *svm)
 414 {
 415         return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SMI);
 416 }
 417
 418 static inline bool nested_exit_on_intr(struct vcpu_svm *svm)
 419 {
 420         return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_INTR);
 421 }
 422
 423 static inline bool nested_exit_on_nmi(struct vcpu_svm *svm)
 424 {
 425         return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_NMI);
 426 }
 427
 428 int enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
 429                          struct vmcb *nested_vmcb);
 430 void svm_leave_nested(struct vcpu_svm *svm);
 431 void svm_free_nested(struct vcpu_svm *svm);
 432 int svm_allocate_nested(struct vcpu_svm *svm);
 433 int nested_svm_vmrun(struct vcpu_svm *svm);
 434 void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb);
 435 int nested_svm_vmexit(struct vcpu_svm *svm);
 436 int nested_svm_exit_handled(struct vcpu_svm *svm);
 437 int nested_svm_check_permissions(struct vcpu_svm *svm);
 438 int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 439                                bool has_error_code, u32 error_code);
 440 int nested_svm_exit_special(struct vcpu_svm *svm);
 441 void sync_nested_vmcb_control(struct vcpu_svm *svm);
 442
 443 extern struct kvm_x86_nested_ops svm_nested_ops;
 444
 445 /* avic.c */
 446
 447 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 448 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT                 31
 449 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 450
 451 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 452 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 453 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 454 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 455
 456 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 457
 458 extern int avic;
 459
 460 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 461 {
 462         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 463         vmcb_mark_dirty(svm->vmcb, VMCB_AVIC);
 464 }
 465
 466 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 467 {
 468         struct vcpu_svm *svm = to_svm(vcpu);
 469         u64 *entry = svm->avic_physical_id_cache;
 470
 471         if (!entry)
 472                 return false;
 473
 474         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 475 }
 476
 477 int avic_ga_log_notifier(u32 ga_tag);
 478 void avic_vm_destroy(struct kvm *kvm);
 479 int avic_vm_init(struct kvm *kvm);
 480 void avic_init_vmcb(struct vcpu_svm *svm);
 481 void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate);
 482 int avic_incomplete_ipi_interception(struct vcpu_svm *svm);
 483 int avic_unaccelerated_access_interception(struct vcpu_svm *svm);
 484 int avic_init_vcpu(struct vcpu_svm *svm);
 485 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
 486 void avic_vcpu_put(struct kvm_vcpu *vcpu);
 487 void avic_post_state_restore(struct kvm_vcpu *vcpu);
 488 void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
 489 void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu);
 490 bool svm_check_apicv_inhibit_reasons(ulong bit);
 491 void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate);
 492 void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap);
 493 void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr);
 494 void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr);
 495 int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec);
 496 bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu);
 497 int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
 498                        uint32_t guest_irq, bool set);
 499 void svm_vcpu_blocking(struct kvm_vcpu *vcpu);
 500 void svm_vcpu_unblocking(struct kvm_vcpu *vcpu);
 501
 502 /* sev.c */
 503
 504 extern unsigned int max_sev_asid;
 505
 506 static inline bool svm_sev_enabled(void)
 507 {
 508         return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
 509 }
 510
 511 void sev_vm_destroy(struct kvm *kvm);
 512 int svm_mem_enc_op(struct kvm *kvm, void __user *argp);
 513 int svm_register_enc_region(struct kvm *kvm,
 514                             struct kvm_enc_region *range);
 515 int svm_unregister_enc_region(struct kvm *kvm,
 516                               struct kvm_enc_region *range);
 517 void pre_sev_run(struct vcpu_svm *svm, int cpu);
 518 void __init sev_hardware_setup(void);
 519 void sev_hardware_teardown(void);
 520 void sev_free_vcpu(struct kvm_vcpu *vcpu);
 521
 522 #endif