drivers/cxl/acpi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright(c) 2021 Intel Corporation. All rights reserved. */
   3 #include <linux/platform_device.h>
   4 #include <linux/module.h>
   5 #include <linux/device.h>
   6 #include <linux/kernel.h>
   7 #include <linux/acpi.h>
   8 #include <linux/pci.h>
   9 #include <linux/node.h>
  10 #include <asm/div64.h>
  11 #include "cxlpci.h"
  12 #include "cxl.h"
  13
  14 #define CXL_RCRB_SIZE   SZ_8K
  15
  16 struct cxl_cxims_data {
  17         int nr_maps;
  18         u64 xormaps[] __counted_by(nr_maps);
  19 };
  20
  21 static const guid_t acpi_cxl_qtg_id_guid =
  22         GUID_INIT(0xF365F9A6, 0xA7DE, 0x4071,
  23                   0xA6, 0x6A, 0xB4, 0x0C, 0x0B, 0x4F, 0x8E, 0x52);
  24
  25 /*
  26  * Find a targets entry (n) in the host bridge interleave list.
  27  * CXL Specification 3.0 Table 9-22
  28  */
  29 static int cxl_xor_calc_n(u64 hpa, struct cxl_cxims_data *cximsd, int iw,
  30                           int ig)
  31 {
  32         int i = 0, n = 0;
  33         u8 eiw;
  34
  35         /* IW: 2,4,6,8,12,16 begin building 'n' using xormaps */
  36         if (iw != 3) {
  37                 for (i = 0; i < cximsd->nr_maps; i++)
  38                         n |= (hweight64(hpa & cximsd->xormaps[i]) & 1) << i;
  39         }
  40         /* IW: 3,6,12 add a modulo calculation to 'n' */
  41         if (!is_power_of_2(iw)) {
  42                 if (ways_to_eiw(iw, &eiw))
  43                         return -1;
  44                 hpa &= GENMASK_ULL(51, eiw + ig);
  45                 n |= do_div(hpa, 3) << i;
  46         }
  47         return n;
  48 }
  49
  50 static struct cxl_dport *cxl_hb_xor(struct cxl_root_decoder *cxlrd, int pos)
  51 {
  52         struct cxl_cxims_data *cximsd = cxlrd->platform_data;
  53         struct cxl_switch_decoder *cxlsd = &cxlrd->cxlsd;
  54         struct cxl_decoder *cxld = &cxlsd->cxld;
  55         int ig = cxld->interleave_granularity;
  56         int iw = cxld->interleave_ways;
  57         int n = 0;
  58         u64 hpa;
  59
  60         if (dev_WARN_ONCE(&cxld->dev,
  61                           cxld->interleave_ways != cxlsd->nr_targets,
  62                           "misconfigured root decoder\n"))
  63                 return NULL;
  64
  65         hpa = cxlrd->res->start + pos * ig;
  66
  67         /* Entry (n) is 0 for no interleave (iw == 1) */
  68         if (iw != 1)
  69                 n = cxl_xor_calc_n(hpa, cximsd, iw, ig);
  70
  71         if (n < 0)
  72                 return NULL;
  73
  74         return cxlrd->cxlsd.target[n];
  75 }
  76
  77 struct cxl_cxims_context {
  78         struct device *dev;
  79         struct cxl_root_decoder *cxlrd;
  80 };
  81
  82 static int cxl_parse_cxims(union acpi_subtable_headers *header, void *arg,
  83                            const unsigned long end)
  84 {
  85         struct acpi_cedt_cxims *cxims = (struct acpi_cedt_cxims *)header;
  86         struct cxl_cxims_context *ctx = arg;
  87         struct cxl_root_decoder *cxlrd = ctx->cxlrd;
  88         struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
  89         struct device *dev = ctx->dev;
  90         struct cxl_cxims_data *cximsd;
  91         unsigned int hbig, nr_maps;
  92         int rc;
  93
  94         rc = eig_to_granularity(cxims->hbig, &hbig);
  95         if (rc)
  96                 return rc;
  97
  98         /* Does this CXIMS entry apply to the given CXL Window? */
  99         if (hbig != cxld->interleave_granularity)
 100                 return 0;
 101
 102         /* IW 1,3 do not use xormaps and skip this parsing entirely */
 103         if (is_power_of_2(cxld->interleave_ways))
 104                 /* 2, 4, 8, 16 way */
 105                 nr_maps = ilog2(cxld->interleave_ways);
 106         else
 107                 /* 6, 12 way */
 108                 nr_maps = ilog2(cxld->interleave_ways / 3);
 109
 110         if (cxims->nr_xormaps < nr_maps) {
 111                 dev_dbg(dev, "CXIMS nr_xormaps[%d] expected[%d]\n",
 112                         cxims->nr_xormaps, nr_maps);
 113                 return -ENXIO;
 114         }
 115
 116         cximsd = devm_kzalloc(dev, struct_size(cximsd, xormaps, nr_maps),
 117                               GFP_KERNEL);
 118         if (!cximsd)
 119                 return -ENOMEM;
 120         cximsd->nr_maps = nr_maps;
 121         memcpy(cximsd->xormaps, cxims->xormap_list,
 122                nr_maps * sizeof(*cximsd->xormaps));
 123         cxlrd->platform_data = cximsd;
 124
 125         return 0;
 126 }
 127
 128 static unsigned long cfmws_to_decoder_flags(int restrictions)
 129 {
 130         unsigned long flags = CXL_DECODER_F_ENABLE;
 131
 132         if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2)
 133                 flags |= CXL_DECODER_F_TYPE2;
 134         if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3)
 135                 flags |= CXL_DECODER_F_TYPE3;
 136         if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE)
 137                 flags |= CXL_DECODER_F_RAM;
 138         if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM)
 139                 flags |= CXL_DECODER_F_PMEM;
 140         if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED)
 141                 flags |= CXL_DECODER_F_LOCK;
 142
 143         return flags;
 144 }
 145
 146 static int cxl_acpi_cfmws_verify(struct device *dev,
 147                                  struct acpi_cedt_cfmws *cfmws)
 148 {
 149         int rc, expected_len;
 150         unsigned int ways;
 151
 152         if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO &&
 153             cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
 154                 dev_err(dev, "CFMWS Unknown Interleave Arithmetic: %d\n",
 155                         cfmws->interleave_arithmetic);
 156                 return -EINVAL;
 157         }
 158
 159         if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) {
 160                 dev_err(dev, "CFMWS Base HPA not 256MB aligned\n");
 161                 return -EINVAL;
 162         }
 163
 164         if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) {
 165                 dev_err(dev, "CFMWS Window Size not 256MB aligned\n");
 166                 return -EINVAL;
 167         }
 168
 169         rc = eiw_to_ways(cfmws->interleave_ways, &ways);
 170         if (rc) {
 171                 dev_err(dev, "CFMWS Interleave Ways (%d) invalid\n",
 172                         cfmws->interleave_ways);
 173                 return -EINVAL;
 174         }
 175
 176         expected_len = struct_size(cfmws, interleave_targets, ways);
 177
 178         if (cfmws->header.length < expected_len) {
 179                 dev_err(dev, "CFMWS length %d less than expected %d\n",
 180                         cfmws->header.length, expected_len);
 181                 return -EINVAL;
 182         }
 183
 184         if (cfmws->header.length > expected_len)
 185                 dev_dbg(dev, "CFMWS length %d greater than expected %d\n",
 186                         cfmws->header.length, expected_len);
 187
 188         return 0;
 189 }
 190
 191 /*
 192  * Note, @dev must be the first member, see 'struct cxl_chbs_context'
 193  * and mock_acpi_table_parse_cedt()
 194  */
 195 struct cxl_cfmws_context {
 196         struct device *dev;
 197         struct cxl_port *root_port;
 198         struct resource *cxl_res;
 199         int id;
 200 };
 201
 202 /**
 203  * cxl_acpi_evaluate_qtg_dsm - Retrieve QTG ids via ACPI _DSM
 204  * @handle: ACPI handle
 205  * @coord: performance access coordinates
 206  * @entries: number of QTG IDs to return
 207  * @qos_class: int array provided by caller to return QTG IDs
 208  *
 209  * Return: number of QTG IDs returned, or -errno for errors
 210  *
 211  * Issue QTG _DSM with accompanied bandwidth and latency data in order to get
 212  * the QTG IDs that are suitable for the performance point in order of most
 213  * suitable to least suitable. Write back array of QTG IDs and return the
 214  * actual number of QTG IDs written back.
 215  */
 216 static int
 217 cxl_acpi_evaluate_qtg_dsm(acpi_handle handle, struct access_coordinate *coord,
 218                           int entries, int *qos_class)
 219 {
 220         union acpi_object *out_obj, *out_buf, *obj;
 221         union acpi_object in_array[4] = {
 222                 [0].integer = { ACPI_TYPE_INTEGER, coord->read_latency },
 223                 [1].integer = { ACPI_TYPE_INTEGER, coord->write_latency },
 224                 [2].integer = { ACPI_TYPE_INTEGER, coord->read_bandwidth },
 225                 [3].integer = { ACPI_TYPE_INTEGER, coord->write_bandwidth },
 226         };
 227         union acpi_object in_obj = {
 228                 .package = {
 229                         .type = ACPI_TYPE_PACKAGE,
 230                         .count = 4,
 231                         .elements = in_array,
 232                 },
 233         };
 234         int count, pkg_entries, i;
 235         u16 max_qtg;
 236         int rc;
 237
 238         if (!entries)
 239                 return -EINVAL;
 240
 241         out_obj = acpi_evaluate_dsm(handle, &acpi_cxl_qtg_id_guid, 1, 1, &in_obj);
 242         if (!out_obj)
 243                 return -ENXIO;
 244
 245         if (out_obj->type != ACPI_TYPE_PACKAGE) {
 246                 rc = -ENXIO;
 247                 goto out;
 248         }
 249
 250         /* Check Max QTG ID */
 251         obj = &out_obj->package.elements[0];
 252         if (obj->type != ACPI_TYPE_INTEGER) {
 253                 rc = -ENXIO;
 254                 goto out;
 255         }
 256
 257         max_qtg = obj->integer.value;
 258
 259         /* It's legal to have 0 QTG entries */
 260         pkg_entries = out_obj->package.count;
 261         if (pkg_entries <= 1) {
 262                 rc = 0;
 263                 goto out;
 264         }
 265
 266         /* Retrieve QTG IDs package */
 267         obj = &out_obj->package.elements[1];
 268         if (obj->type != ACPI_TYPE_PACKAGE) {
 269                 rc = -ENXIO;
 270                 goto out;
 271         }
 272
 273         pkg_entries = obj->package.count;
 274         count = min(entries, pkg_entries);
 275         for (i = 0; i < count; i++) {
 276                 u16 qtg_id;
 277
 278                 out_buf = &obj->package.elements[i];
 279                 if (out_buf->type != ACPI_TYPE_INTEGER) {
 280                         rc = -ENXIO;
 281                         goto out;
 282                 }
 283
 284                 qtg_id = out_buf->integer.value;
 285                 if (qtg_id > max_qtg)
 286                         pr_warn("QTG ID %u greater than MAX %u\n",
 287                                 qtg_id, max_qtg);
 288
 289                 qos_class[i] = qtg_id;
 290         }
 291         rc = count;
 292
 293 out:
 294         ACPI_FREE(out_obj);
 295         return rc;
 296 }
 297
 298 static int cxl_acpi_qos_class(struct cxl_root *cxl_root,
 299                               struct access_coordinate *coord, int entries,
 300                               int *qos_class)
 301 {
 302         struct device *dev = cxl_root->port.uport_dev;
 303         acpi_handle handle;
 304
 305         if (!dev_is_platform(dev))
 306                 return -ENODEV;
 307
 308         handle = ACPI_HANDLE(dev);
 309         if (!handle)
 310                 return -ENODEV;
 311
 312         return cxl_acpi_evaluate_qtg_dsm(handle, coord, entries, qos_class);
 313 }
 314
 315 static const struct cxl_root_ops acpi_root_ops = {
 316         .qos_class = cxl_acpi_qos_class,
 317 };
 318
 319 static int __cxl_parse_cfmws(struct acpi_cedt_cfmws *cfmws,
 320                              struct cxl_cfmws_context *ctx)
 321 {
 322         int target_map[CXL_DECODER_MAX_INTERLEAVE];
 323         struct cxl_port *root_port = ctx->root_port;
 324         struct resource *cxl_res = ctx->cxl_res;
 325         struct cxl_cxims_context cxims_ctx;
 326         struct cxl_root_decoder *cxlrd;
 327         struct device *dev = ctx->dev;
 328         cxl_calc_hb_fn cxl_calc_hb;
 329         struct cxl_decoder *cxld;
 330         unsigned int ways, i, ig;
 331         struct resource *res;
 332         int rc;
 333
 334         rc = cxl_acpi_cfmws_verify(dev, cfmws);
 335         if (rc) {
 336                 dev_err(dev, "CFMWS range %#llx-%#llx not registered\n",
 337                         cfmws->base_hpa,
 338                         cfmws->base_hpa + cfmws->window_size - 1);
 339                 return rc;
 340         }
 341
 342         rc = eiw_to_ways(cfmws->interleave_ways, &ways);
 343         if (rc)
 344                 return rc;
 345         rc = eig_to_granularity(cfmws->granularity, &ig);
 346         if (rc)
 347                 return rc;
 348         for (i = 0; i < ways; i++)
 349                 target_map[i] = cfmws->interleave_targets[i];
 350
 351         res = kzalloc(sizeof(*res), GFP_KERNEL);
 352         if (!res)
 353                 return -ENOMEM;
 354
 355         res->name = kasprintf(GFP_KERNEL, "CXL Window %d", ctx->id++);
 356         if (!res->name)
 357                 goto err_name;
 358
 359         res->start = cfmws->base_hpa;
 360         res->end = cfmws->base_hpa + cfmws->window_size - 1;
 361         res->flags = IORESOURCE_MEM;
 362
 363         /* add to the local resource tracking to establish a sort order */
 364         rc = insert_resource(cxl_res, res);
 365         if (rc)
 366                 goto err_insert;
 367
 368         if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_MODULO)
 369                 cxl_calc_hb = cxl_hb_modulo;
 370         else
 371                 cxl_calc_hb = cxl_hb_xor;
 372
 373         cxlrd = cxl_root_decoder_alloc(root_port, ways, cxl_calc_hb);
 374         if (IS_ERR(cxlrd))
 375                 return PTR_ERR(cxlrd);
 376
 377         cxld = &cxlrd->cxlsd.cxld;
 378         cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);
 379         cxld->target_type = CXL_DECODER_HOSTONLYMEM;
 380         cxld->hpa_range = (struct range) {
 381                 .start = res->start,
 382                 .end = res->end,
 383         };
 384         cxld->interleave_ways = ways;
 385         /*
 386          * Minimize the x1 granularity to advertise support for any
 387          * valid region granularity
 388          */
 389         if (ways == 1)
 390                 ig = CXL_DECODER_MIN_GRANULARITY;
 391         cxld->interleave_granularity = ig;
 392
 393         if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
 394                 if (ways != 1 && ways != 3) {
 395                         cxims_ctx = (struct cxl_cxims_context) {
 396                                 .dev = dev,
 397                                 .cxlrd = cxlrd,
 398                         };
 399                         rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CXIMS,
 400                                                    cxl_parse_cxims, &cxims_ctx);
 401                         if (rc < 0)
 402                                 goto err_xormap;
 403                         if (!cxlrd->platform_data) {
 404                                 dev_err(dev, "No CXIMS for HBIG %u\n", ig);
 405                                 rc = -EINVAL;
 406                                 goto err_xormap;
 407                         }
 408                 }
 409         }
 410
 411         cxlrd->qos_class = cfmws->qtg_id;
 412
 413         rc = cxl_decoder_add(cxld, target_map);
 414 err_xormap:
 415         if (rc)
 416                 put_device(&cxld->dev);
 417         else
 418                 rc = cxl_decoder_autoremove(dev, cxld);
 419         return rc;
 420
 421 err_insert:
 422         kfree(res->name);
 423 err_name:
 424         kfree(res);
 425         return -ENOMEM;
 426 }
 427
 428 static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
 429                            const unsigned long end)
 430 {
 431         struct acpi_cedt_cfmws *cfmws = (struct acpi_cedt_cfmws *)header;
 432         struct cxl_cfmws_context *ctx = arg;
 433         struct device *dev = ctx->dev;
 434         int rc;
 435
 436         rc = __cxl_parse_cfmws(cfmws, ctx);
 437         if (rc)
 438                 dev_err(dev,
 439                         "Failed to add decode range: [%#llx - %#llx] (%d)\n",
 440                         cfmws->base_hpa,
 441                         cfmws->base_hpa + cfmws->window_size - 1, rc);
 442         else
 443                 dev_dbg(dev, "decode range: node: %d range [%#llx - %#llx]\n",
 444                         phys_to_target_node(cfmws->base_hpa), cfmws->base_hpa,
 445                         cfmws->base_hpa + cfmws->window_size - 1);
 446
 447         /* never fail cxl_acpi load for a single window failure */
 448         return 0;
 449 }
 450
 451 __mock struct acpi_device *to_cxl_host_bridge(struct device *host,
 452                                               struct device *dev)
 453 {
 454         struct acpi_device *adev = to_acpi_device(dev);
 455
 456         if (!acpi_pci_find_root(adev->handle))
 457                 return NULL;
 458
 459         if (strcmp(acpi_device_hid(adev), "ACPI0016") == 0)
 460                 return adev;
 461         return NULL;
 462 }
 463
 464 /* Note, @dev is used by mock_acpi_table_parse_cedt() */
 465 struct cxl_chbs_context {
 466         struct device *dev;
 467         unsigned long long uid;
 468         resource_size_t base;
 469         u32 cxl_version;
 470 };
 471
 472 static int cxl_get_chbs_iter(union acpi_subtable_headers *header, void *arg,
 473                              const unsigned long end)
 474 {
 475         struct cxl_chbs_context *ctx = arg;
 476         struct acpi_cedt_chbs *chbs;
 477
 478         if (ctx->base != CXL_RESOURCE_NONE)
 479                 return 0;
 480
 481         chbs = (struct acpi_cedt_chbs *) header;
 482
 483         if (ctx->uid != chbs->uid)
 484                 return 0;
 485
 486         ctx->cxl_version = chbs->cxl_version;
 487         if (!chbs->base)
 488                 return 0;
 489
 490         if (chbs->cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11 &&
 491             chbs->length != CXL_RCRB_SIZE)
 492                 return 0;
 493
 494         ctx->base = chbs->base;
 495
 496         return 0;
 497 }
 498
 499 static int cxl_get_chbs(struct device *dev, struct acpi_device *hb,
 500                         struct cxl_chbs_context *ctx)
 501 {
 502         unsigned long long uid;
 503         int rc;
 504
 505         rc = acpi_evaluate_integer(hb->handle, METHOD_NAME__UID, NULL, &uid);
 506         if (rc != AE_OK) {
 507                 dev_err(dev, "unable to retrieve _UID\n");
 508                 return -ENOENT;
 509         }
 510
 511         dev_dbg(dev, "UID found: %lld\n", uid);
 512         *ctx = (struct cxl_chbs_context) {
 513                 .dev = dev,
 514                 .uid = uid,
 515                 .base = CXL_RESOURCE_NONE,
 516                 .cxl_version = UINT_MAX,
 517         };
 518
 519         acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbs_iter, ctx);
 520
 521         return 0;
 522 }
 523
 524 static int get_genport_coordinates(struct device *dev, struct cxl_dport *dport)
 525 {
 526         struct acpi_device *hb = to_cxl_host_bridge(NULL, dev);
 527         u32 uid;
 528
 529         if (kstrtou32(acpi_device_uid(hb), 0, &uid))
 530                 return -EINVAL;
 531
 532         return acpi_get_genport_coordinates(uid, dport->coord);
 533 }
 534
 535 static int add_host_bridge_dport(struct device *match, void *arg)
 536 {
 537         int ret;
 538         acpi_status rc;
 539         struct device *bridge;
 540         struct cxl_dport *dport;
 541         struct cxl_chbs_context ctx;
 542         struct acpi_pci_root *pci_root;
 543         struct cxl_port *root_port = arg;
 544         struct device *host = root_port->dev.parent;
 545         struct acpi_device *hb = to_cxl_host_bridge(host, match);
 546
 547         if (!hb)
 548                 return 0;
 549
 550         rc = cxl_get_chbs(match, hb, &ctx);
 551         if (rc)
 552                 return rc;
 553
 554         if (ctx.cxl_version == UINT_MAX) {
 555                 dev_warn(match, "No CHBS found for Host Bridge (UID %lld)\n",
 556                          ctx.uid);
 557                 return 0;
 558         }
 559
 560         if (ctx.base == CXL_RESOURCE_NONE) {
 561                 dev_warn(match, "CHBS invalid for Host Bridge (UID %lld)\n",
 562                          ctx.uid);
 563                 return 0;
 564         }
 565
 566         pci_root = acpi_pci_find_root(hb->handle);
 567         bridge = pci_root->bus->bridge;
 568
 569         /*
 570          * In RCH mode, bind the component regs base to the dport. In
 571          * VH mode it will be bound to the CXL host bridge's port
 572          * object later in add_host_bridge_uport().
 573          */
 574         if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) {
 575                 dev_dbg(match, "RCRB found for UID %lld: %pa\n", ctx.uid,
 576                         &ctx.base);
 577                 dport = devm_cxl_add_rch_dport(root_port, bridge, ctx.uid,
 578                                                ctx.base);
 579         } else {
 580                 dport = devm_cxl_add_dport(root_port, bridge, ctx.uid,
 581                                            CXL_RESOURCE_NONE);
 582         }
 583
 584         if (IS_ERR(dport))
 585                 return PTR_ERR(dport);
 586
 587         ret = get_genport_coordinates(match, dport);
 588         if (ret)
 589                 dev_dbg(match, "Failed to get generic port perf coordinates.\n");
 590
 591         return 0;
 592 }
 593
 594 /*
 595  * A host bridge is a dport to a CFMWS decode and it is a uport to the
 596  * dport (PCIe Root Ports) in the host bridge.
 597  */
 598 static int add_host_bridge_uport(struct device *match, void *arg)
 599 {
 600         struct cxl_port *root_port = arg;
 601         struct device *host = root_port->dev.parent;
 602         struct acpi_device *hb = to_cxl_host_bridge(host, match);
 603         struct acpi_pci_root *pci_root;
 604         struct cxl_dport *dport;
 605         struct cxl_port *port;
 606         struct device *bridge;
 607         struct cxl_chbs_context ctx;
 608         resource_size_t component_reg_phys;
 609         int rc;
 610
 611         if (!hb)
 612                 return 0;
 613
 614         pci_root = acpi_pci_find_root(hb->handle);
 615         bridge = pci_root->bus->bridge;
 616         dport = cxl_find_dport_by_dev(root_port, bridge);
 617         if (!dport) {
 618                 dev_dbg(host, "host bridge expected and not found\n");
 619                 return 0;
 620         }
 621
 622         if (dport->rch) {
 623                 dev_info(bridge, "host supports CXL (restricted)\n");
 624                 return 0;
 625         }
 626
 627         rc = cxl_get_chbs(match, hb, &ctx);
 628         if (rc)
 629                 return rc;
 630
 631         if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) {
 632                 dev_warn(bridge,
 633                          "CXL CHBS version mismatch, skip port registration\n");
 634                 return 0;
 635         }
 636
 637         component_reg_phys = ctx.base;
 638         if (component_reg_phys != CXL_RESOURCE_NONE)
 639                 dev_dbg(match, "CHBCR found for UID %lld: %pa\n",
 640                         ctx.uid, &component_reg_phys);
 641
 642         rc = devm_cxl_register_pci_bus(host, bridge, pci_root->bus);
 643         if (rc)
 644                 return rc;
 645
 646         port = devm_cxl_add_port(host, bridge, component_reg_phys, dport);
 647         if (IS_ERR(port))
 648                 return PTR_ERR(port);
 649
 650         dev_info(bridge, "host supports CXL\n");
 651
 652         return 0;
 653 }
 654
 655 static int add_root_nvdimm_bridge(struct device *match, void *data)
 656 {
 657         struct cxl_decoder *cxld;
 658         struct cxl_port *root_port = data;
 659         struct cxl_nvdimm_bridge *cxl_nvb;
 660         struct device *host = root_port->dev.parent;
 661
 662         if (!is_root_decoder(match))
 663                 return 0;
 664
 665         cxld = to_cxl_decoder(match);
 666         if (!(cxld->flags & CXL_DECODER_F_PMEM))
 667                 return 0;
 668
 669         cxl_nvb = devm_cxl_add_nvdimm_bridge(host, root_port);
 670         if (IS_ERR(cxl_nvb)) {
 671                 dev_dbg(host, "failed to register pmem\n");
 672                 return PTR_ERR(cxl_nvb);
 673         }
 674         dev_dbg(host, "%s: add: %s\n", dev_name(&root_port->dev),
 675                 dev_name(&cxl_nvb->dev));
 676         return 1;
 677 }
 678
 679 static struct lock_class_key cxl_root_key;
 680
 681 static void cxl_acpi_lock_reset_class(void *dev)
 682 {
 683         device_lock_reset_class(dev);
 684 }
 685
 686 static void del_cxl_resource(struct resource *res)
 687 {
 688         kfree(res->name);
 689         kfree(res);
 690 }
 691
 692 static void cxl_set_public_resource(struct resource *priv, struct resource *pub)
 693 {
 694         priv->desc = (unsigned long) pub;
 695 }
 696
 697 static struct resource *cxl_get_public_resource(struct resource *priv)
 698 {
 699         return (struct resource *) priv->desc;
 700 }
 701
 702 static void remove_cxl_resources(void *data)
 703 {
 704         struct resource *res, *next, *cxl = data;
 705
 706         for (res = cxl->child; res; res = next) {
 707                 struct resource *victim = cxl_get_public_resource(res);
 708
 709                 next = res->sibling;
 710                 remove_resource(res);
 711
 712                 if (victim) {
 713                         remove_resource(victim);
 714                         kfree(victim);
 715                 }
 716
 717                 del_cxl_resource(res);
 718         }
 719 }
 720
 721 /**
 722  * add_cxl_resources() - reflect CXL fixed memory windows in iomem_resource
 723  * @cxl_res: A standalone resource tree where each CXL window is a sibling
 724  *
 725  * Walk each CXL window in @cxl_res and add it to iomem_resource potentially
 726  * expanding its boundaries to ensure that any conflicting resources become
 727  * children. If a window is expanded it may then conflict with a another window
 728  * entry and require the window to be truncated or trimmed. Consider this
 729  * situation:
 730  *
 731  * |-- "CXL Window 0" --||----- "CXL Window 1" -----|
 732  * |--------------- "System RAM" -------------|
 733  *
 734  * ...where platform firmware has established as System RAM resource across 2
 735  * windows, but has left some portion of window 1 for dynamic CXL region
 736  * provisioning. In this case "Window 0" will span the entirety of the "System
 737  * RAM" span, and "CXL Window 1" is truncated to the remaining tail past the end
 738  * of that "System RAM" resource.
 739  */
 740 static int add_cxl_resources(struct resource *cxl_res)
 741 {
 742         struct resource *res, *new, *next;
 743
 744         for (res = cxl_res->child; res; res = next) {
 745                 new = kzalloc(sizeof(*new), GFP_KERNEL);
 746                 if (!new)
 747                         return -ENOMEM;
 748                 new->name = res->name;
 749                 new->start = res->start;
 750                 new->end = res->end;
 751                 new->flags = IORESOURCE_MEM;
 752                 new->desc = IORES_DESC_CXL;
 753
 754                 /*
 755                  * Record the public resource in the private cxl_res tree for
 756                  * later removal.
 757                  */
 758                 cxl_set_public_resource(res, new);
 759
 760                 insert_resource_expand_to_fit(&iomem_resource, new);
 761
 762                 next = res->sibling;
 763                 while (next && resource_overlaps(new, next)) {
 764                         if (resource_contains(new, next)) {
 765                                 struct resource *_next = next->sibling;
 766
 767                                 remove_resource(next);
 768                                 del_cxl_resource(next);
 769                                 next = _next;
 770                         } else
 771                                 next->start = new->end + 1;
 772                 }
 773         }
 774         return 0;
 775 }
 776
 777 static int pair_cxl_resource(struct device *dev, void *data)
 778 {
 779         struct resource *cxl_res = data;
 780         struct resource *p;
 781
 782         if (!is_root_decoder(dev))
 783                 return 0;
 784
 785         for (p = cxl_res->child; p; p = p->sibling) {
 786                 struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev);
 787                 struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
 788                 struct resource res = {
 789                         .start = cxld->hpa_range.start,
 790                         .end = cxld->hpa_range.end,
 791                         .flags = IORESOURCE_MEM,
 792                 };
 793
 794                 if (resource_contains(p, &res)) {
 795                         cxlrd->res = cxl_get_public_resource(p);
 796                         break;
 797                 }
 798         }
 799
 800         return 0;
 801 }
 802
 803 static int cxl_acpi_probe(struct platform_device *pdev)
 804 {
 805         int rc;
 806         struct resource *cxl_res;
 807         struct cxl_root *cxl_root;
 808         struct cxl_port *root_port;
 809         struct device *host = &pdev->dev;
 810         struct acpi_device *adev = ACPI_COMPANION(host);
 811         struct cxl_cfmws_context ctx;
 812
 813         device_lock_set_class(&pdev->dev, &cxl_root_key);
 814         rc = devm_add_action_or_reset(&pdev->dev, cxl_acpi_lock_reset_class,
 815                                       &pdev->dev);
 816         if (rc)
 817                 return rc;
 818
 819         cxl_res = devm_kzalloc(host, sizeof(*cxl_res), GFP_KERNEL);
 820         if (!cxl_res)
 821                 return -ENOMEM;
 822         cxl_res->name = "CXL mem";
 823         cxl_res->start = 0;
 824         cxl_res->end = -1;
 825         cxl_res->flags = IORESOURCE_MEM;
 826
 827         cxl_root = devm_cxl_add_root(host, &acpi_root_ops);
 828         if (IS_ERR(cxl_root))
 829                 return PTR_ERR(cxl_root);
 830         root_port = &cxl_root->port;
 831
 832         rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
 833                               add_host_bridge_dport);
 834         if (rc < 0)
 835                 return rc;
 836
 837         rc = devm_add_action_or_reset(host, remove_cxl_resources, cxl_res);
 838         if (rc)
 839                 return rc;
 840
 841         ctx = (struct cxl_cfmws_context) {
 842                 .dev = host,
 843                 .root_port = root_port,
 844                 .cxl_res = cxl_res,
 845         };
 846         rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, cxl_parse_cfmws, &ctx);
 847         if (rc < 0)
 848                 return -ENXIO;
 849
 850         rc = add_cxl_resources(cxl_res);
 851         if (rc)
 852                 return rc;
 853
 854         /*
 855          * Populate the root decoders with their related iomem resource,
 856          * if present
 857          */
 858         device_for_each_child(&root_port->dev, cxl_res, pair_cxl_resource);
 859
 860         /*
 861          * Root level scanned with host-bridge as dports, now scan host-bridges
 862          * for their role as CXL uports to their CXL-capable PCIe Root Ports.
 863          */
 864         rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
 865                               add_host_bridge_uport);
 866         if (rc < 0)
 867                 return rc;
 868
 869         if (IS_ENABLED(CONFIG_CXL_PMEM))
 870                 rc = device_for_each_child(&root_port->dev, root_port,
 871                                            add_root_nvdimm_bridge);
 872         if (rc < 0)
 873                 return rc;
 874
 875         /* In case PCI is scanned before ACPI re-trigger memdev attach */
 876         cxl_bus_rescan();
 877         return 0;
 878 }
 879
 880 static const struct acpi_device_id cxl_acpi_ids[] = {
 881         { "ACPI0017" },
 882         { },
 883 };
 884 MODULE_DEVICE_TABLE(acpi, cxl_acpi_ids);
 885
 886 static const struct platform_device_id cxl_test_ids[] = {
 887         { "cxl_acpi" },
 888         { },
 889 };
 890 MODULE_DEVICE_TABLE(platform, cxl_test_ids);
 891
 892 static struct platform_driver cxl_acpi_driver = {
 893         .probe = cxl_acpi_probe,
 894         .driver = {
 895                 .name = KBUILD_MODNAME,
 896                 .acpi_match_table = cxl_acpi_ids,
 897         },
 898         .id_table = cxl_test_ids,
 899 };
 900
 901 static int __init cxl_acpi_init(void)
 902 {
 903         return platform_driver_register(&cxl_acpi_driver);
 904 }
 905
 906 static void __exit cxl_acpi_exit(void)
 907 {
 908         platform_driver_unregister(&cxl_acpi_driver);
 909         cxl_bus_drain();
 910 }
 911
 912 /* load before dax_hmem sees 'Soft Reserved' CXL ranges */
 913 subsys_initcall(cxl_acpi_init);
 914 module_exit(cxl_acpi_exit);
 915 MODULE_LICENSE("GPL v2");
 916 MODULE_IMPORT_NS(CXL);
 917 MODULE_IMPORT_NS(ACPI);