Merge tag 'sched-urgent-2024-03-24' of git://git.kernel.org/pub/scm/linux/kernel...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / display / dc / hwss / dcn32 / dcn32_hwseq.c
1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25
26
27 #include "dm_services.h"
28 #include "dm_helpers.h"
29 #include "core_types.h"
30 #include "resource.h"
31 #include "dccg.h"
32 #include "dce/dce_hwseq.h"
33 #include "dcn30/dcn30_cm_common.h"
34 #include "reg_helper.h"
35 #include "abm.h"
36 #include "hubp.h"
37 #include "dchubbub.h"
38 #include "timing_generator.h"
39 #include "opp.h"
40 #include "ipp.h"
41 #include "mpc.h"
42 #include "mcif_wb.h"
43 #include "dc_dmub_srv.h"
44 #include "link_hwss.h"
45 #include "dpcd_defs.h"
46 #include "dcn32_hwseq.h"
47 #include "clk_mgr.h"
48 #include "dsc.h"
49 #include "dcn20/dcn20_optc.h"
50 #include "dce/dmub_hw_lock_mgr.h"
51 #include "dcn32/dcn32_resource.h"
52 #include "link.h"
53 #include "../dcn20/dcn20_hwseq.h"
54 #include "dc_state_priv.h"
55
56 #define DC_LOGGER_INIT(logger)
57
58 #define CTX \
59         hws->ctx
60 #define REG(reg)\
61         hws->regs->reg
62 #define DC_LOGGER \
63         stream->ctx->logger
64
65
66 #undef FN
67 #define FN(reg_name, field_name) \
68         hws->shifts->field_name, hws->masks->field_name
69
70 void dcn32_dsc_pg_control(
71                 struct dce_hwseq *hws,
72                 unsigned int dsc_inst,
73                 bool power_on)
74 {
75         uint32_t power_gate = power_on ? 0 : 1;
76         uint32_t pwr_status = power_on ? 0 : 2;
77         uint32_t org_ip_request_cntl = 0;
78
79         if (hws->ctx->dc->debug.disable_dsc_power_gate)
80                 return;
81
82         if (!hws->ctx->dc->debug.enable_double_buffered_dsc_pg_support)
83                 return;
84
85         REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
86         if (org_ip_request_cntl == 0)
87                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
88
89         switch (dsc_inst) {
90         case 0: /* DSC0 */
91                 REG_UPDATE(DOMAIN16_PG_CONFIG,
92                                 DOMAIN_POWER_GATE, power_gate);
93
94                 REG_WAIT(DOMAIN16_PG_STATUS,
95                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
96                                 1, 1000);
97                 break;
98         case 1: /* DSC1 */
99                 REG_UPDATE(DOMAIN17_PG_CONFIG,
100                                 DOMAIN_POWER_GATE, power_gate);
101
102                 REG_WAIT(DOMAIN17_PG_STATUS,
103                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
104                                 1, 1000);
105                 break;
106         case 2: /* DSC2 */
107                 REG_UPDATE(DOMAIN18_PG_CONFIG,
108                                 DOMAIN_POWER_GATE, power_gate);
109
110                 REG_WAIT(DOMAIN18_PG_STATUS,
111                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
112                                 1, 1000);
113                 break;
114         case 3: /* DSC3 */
115                 REG_UPDATE(DOMAIN19_PG_CONFIG,
116                                 DOMAIN_POWER_GATE, power_gate);
117
118                 REG_WAIT(DOMAIN19_PG_STATUS,
119                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
120                                 1, 1000);
121                 break;
122         default:
123                 BREAK_TO_DEBUGGER();
124                 break;
125         }
126
127         if (org_ip_request_cntl == 0)
128                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
129 }
130
131
132 void dcn32_enable_power_gating_plane(
133         struct dce_hwseq *hws,
134         bool enable)
135 {
136         bool force_on = true; /* disable power gating */
137         uint32_t org_ip_request_cntl = 0;
138
139         if (enable)
140                 force_on = false;
141
142         REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
143         if (org_ip_request_cntl == 0)
144                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
145
146         /* DCHUBP0/1/2/3 */
147         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
148         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
149         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
150         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
151
152         /* DCS0/1/2/3 */
153         REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
154         REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
155         REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
156         REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
157
158         if (org_ip_request_cntl == 0)
159                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
160 }
161
162 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
163 {
164         uint32_t power_gate = power_on ? 0 : 1;
165         uint32_t pwr_status = power_on ? 0 : 2;
166
167         if (hws->ctx->dc->debug.disable_hubp_power_gate)
168                 return;
169
170         if (REG(DOMAIN0_PG_CONFIG) == 0)
171                 return;
172
173         switch (hubp_inst) {
174         case 0:
175                 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
176                 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
177                 break;
178         case 1:
179                 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
180                 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
181                 break;
182         case 2:
183                 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
184                 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
185                 break;
186         case 3:
187                 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
188                 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
189                 break;
190         default:
191                 BREAK_TO_DEBUGGER();
192                 break;
193         }
194 }
195
196 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc)
197 {
198         int i;
199
200     /* First, check no-memory-request case */
201         for (i = 0; i < dc->current_state->stream_count; i++) {
202                 if ((dc->current_state->stream_status[i].plane_count) &&
203                         (dc->current_state->streams[i]->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED))
204                         /* Fail eligibility on a visible stream */
205                         break;
206         }
207
208         if (i == dc->current_state->stream_count)
209                 return true;
210
211         return false;
212 }
213
214
215 /* This function loops through every surface that needs to be cached in CAB for SS,
216  * and calculates the total number of ways required to store all surfaces (primary,
217  * meta, cursor).
218  */
219 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)
220 {
221         int i;
222         uint32_t num_ways = 0;
223         uint32_t mall_ss_size_bytes = 0;
224
225         mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes;
226         // TODO add additional logic for PSR active stream exclusion optimization
227         // mall_ss_psr_active_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes;
228
229         // Include cursor size for CAB allocation
230         for (i = 0; i < dc->res_pool->pipe_count; i++) {
231                 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i];
232
233                 if (!pipe->stream || !pipe->plane_state)
234                         continue;
235
236                 mall_ss_size_bytes += dcn32_helper_calculate_mall_bytes_for_cursor(dc, pipe, false);
237         }
238
239         // Convert number of cache lines required to number of ways
240         if (dc->debug.force_mall_ss_num_ways > 0) {
241                 num_ways = dc->debug.force_mall_ss_num_ways;
242         } else {
243                 num_ways = dcn32_helper_mall_bytes_to_ways(dc, mall_ss_size_bytes);
244         }
245
246         return num_ways;
247 }
248
249 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)
250 {
251         union dmub_rb_cmd cmd;
252         uint8_t i;
253         uint32_t ways;
254         int j;
255         bool mall_ss_unsupported = false;
256         struct dc_plane_state *plane = NULL;
257
258         if (!dc->ctx->dmub_srv)
259                 return false;
260
261         for (i = 0; i < dc->current_state->stream_count; i++) {
262                 /* MALL SS messaging is not supported with PSR at this time */
263                 if (dc->current_state->streams[i] != NULL &&
264                                 dc->current_state->streams[i]->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED)
265                         return false;
266         }
267
268         if (enable) {
269                 if (dc->current_state) {
270
271                         /* 1. Check no memory request case for CAB.
272                          * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message
273                          */
274                         if (dcn32_check_no_memory_request_for_cab(dc)) {
275                                 /* Enable no-memory-requests case */
276                                 memset(&cmd, 0, sizeof(cmd));
277                                 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
278                                 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ;
279                                 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
280
281                                 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
282
283                                 return true;
284                         }
285
286                         /* 2. Check if all surfaces can fit in CAB.
287                          * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message
288                          * and configure HUBP's to fetch from MALL
289                          */
290                         ways = dcn32_calculate_cab_allocation(dc, dc->current_state);
291
292                         /* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo,
293                          * or TMZ surface, don't try to enter MALL.
294                          */
295                         for (i = 0; i < dc->current_state->stream_count; i++) {
296                                 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {
297                                         plane = dc->current_state->stream_status[i].plane_states[j];
298
299                                         if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO ||
300                                                         plane->address.tmz_surface) {
301                                                 mall_ss_unsupported = true;
302                                                 break;
303                                         }
304                                 }
305                                 if (mall_ss_unsupported)
306                                         break;
307                         }
308                         if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) {
309                                 memset(&cmd, 0, sizeof(cmd));
310                                 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
311                                 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;
312                                 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
313                                 cmd.cab.cab_alloc_ways = (uint8_t)ways;
314
315                                 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
316
317                                 return true;
318                         }
319
320                 }
321                 return false;
322         }
323
324         /* Disable CAB */
325         memset(&cmd, 0, sizeof(cmd));
326         cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
327         cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION;
328         cmd.cab.header.payload_bytes =
329                         sizeof(cmd.cab) - sizeof(cmd.cab.header);
330
331         dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
332
333         return true;
334 }
335
336 /* Send DMCUB message with SubVP pipe info
337  * - For each pipe in context, populate payload with required SubVP information
338  *   if the pipe is using SubVP for MCLK switch
339  * - This function must be called while the DMUB HW lock is acquired by driver
340  */
341 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context)
342 {
343         int i;
344         bool enable_subvp = false;
345
346         if (!dc->ctx || !dc->ctx->dmub_srv)
347                 return;
348
349         for (i = 0; i < dc->res_pool->pipe_count; i++) {
350                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
351
352                 if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) {
353                         // There is at least 1 SubVP pipe, so enable SubVP
354                         enable_subvp = true;
355                         break;
356                 }
357         }
358         dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp);
359 }
360
361 /* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and:
362  * 1. Any full update for any SubVP main pipe
363  * 2. Any immediate flip for any SubVP pipe
364  * 3. Any flip for DRR pipe
365  * 4. If SubVP was previously in use (i.e. in old context)
366  */
367 void dcn32_subvp_pipe_control_lock(struct dc *dc,
368                 struct dc_state *context,
369                 bool lock,
370                 bool should_lock_all_pipes,
371                 struct pipe_ctx *top_pipe_to_program,
372                 bool subvp_prev_use)
373 {
374         unsigned int i = 0;
375         bool subvp_immediate_flip = false;
376         bool subvp_in_use = false;
377         struct pipe_ctx *pipe;
378         enum mall_stream_type pipe_mall_type = SUBVP_NONE;
379
380         for (i = 0; i < dc->res_pool->pipe_count; i++) {
381                 pipe = &context->res_ctx.pipe_ctx[i];
382                 pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);
383
384                 if (pipe->stream && pipe->plane_state && pipe_mall_type == SUBVP_MAIN) {
385                         subvp_in_use = true;
386                         break;
387                 }
388         }
389
390         if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) {
391                 if (dc_state_get_pipe_subvp_type(context, top_pipe_to_program) == SUBVP_MAIN &&
392                                 top_pipe_to_program->plane_state->flip_immediate)
393                         subvp_immediate_flip = true;
394         }
395
396         // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared.
397         if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) {
398                 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
399
400                 if (!lock) {
401                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
402                                 pipe = &context->res_ctx.pipe_ctx[i];
403                                 if (pipe->stream && pipe->plane_state && pipe_mall_type == SUBVP_MAIN &&
404                                                 should_lock_all_pipes)
405                                         pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);
406                         }
407                 }
408
409                 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;
410                 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;
411                 hw_lock_cmd.bits.lock = lock;
412                 hw_lock_cmd.bits.should_release = !lock;
413                 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);
414         }
415 }
416
417 void dcn32_subvp_pipe_control_lock_fast(union block_sequence_params *params)
418 {
419         struct dc *dc = params->subvp_pipe_control_lock_fast_params.dc;
420         bool lock = params->subvp_pipe_control_lock_fast_params.lock;
421         bool subvp_immediate_flip = params->subvp_pipe_control_lock_fast_params.subvp_immediate_flip;
422
423         // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared.
424         if (subvp_immediate_flip) {
425                 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
426
427                 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;
428                 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;
429                 hw_lock_cmd.bits.lock = lock;
430                 hw_lock_cmd.bits.should_release = !lock;
431                 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);
432         }
433 }
434
435 bool dcn32_set_mpc_shaper_3dlut(
436         struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream)
437 {
438         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
439         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
440         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
441         bool result = false;
442
443         const struct pwl_params *shaper_lut = NULL;
444         //get the shaper lut params
445         if (stream->func_shaper) {
446                 if (stream->func_shaper->type == TF_TYPE_HWPWL)
447                         shaper_lut = &stream->func_shaper->pwl;
448                 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
449                         cm_helper_translate_curve_to_hw_format(stream->ctx,
450                                         stream->func_shaper,
451                                         &dpp_base->shaper_params, true);
452                         shaper_lut = &dpp_base->shaper_params;
453                 }
454         }
455
456         if (stream->lut3d_func &&
457                 stream->lut3d_func->state.bits.initialized == 1) {
458
459                 result = mpc->funcs->program_3dlut(mpc,
460                                                                 &stream->lut3d_func->lut_3d,
461                                                                 mpcc_id);
462
463                 result = mpc->funcs->program_shaper(mpc,
464                                                                 shaper_lut,
465                                                                 mpcc_id);
466         }
467
468         return result;
469 }
470
471 bool dcn32_set_mcm_luts(
472         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
473 {
474         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
475         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
476         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
477         bool result = true;
478         struct pwl_params *lut_params = NULL;
479
480         // 1D LUT
481         if (plane_state->blend_tf) {
482                 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
483                         lut_params = &plane_state->blend_tf->pwl;
484                 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
485                         cm3_helper_translate_curve_to_hw_format(plane_state->blend_tf,
486                                         &dpp_base->regamma_params, false);
487                         lut_params = &dpp_base->regamma_params;
488                 }
489         }
490         result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);
491         lut_params = NULL;
492
493         // Shaper
494         if (plane_state->in_shaper_func) {
495                 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
496                         lut_params = &plane_state->in_shaper_func->pwl;
497                 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
498                         // TODO: dpp_base replace
499                         ASSERT(false);
500                         cm3_helper_translate_curve_to_hw_format(plane_state->in_shaper_func,
501                                         &dpp_base->shaper_params, true);
502                         lut_params = &dpp_base->shaper_params;
503                 }
504         }
505
506         result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);
507
508         // 3D
509         if (plane_state->lut3d_func && plane_state->lut3d_func->state.bits.initialized == 1)
510                 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id);
511         else
512                 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id);
513
514         return result;
515 }
516
517 bool dcn32_set_input_transfer_func(struct dc *dc,
518                                 struct pipe_ctx *pipe_ctx,
519                                 const struct dc_plane_state *plane_state)
520 {
521         struct dce_hwseq *hws = dc->hwseq;
522         struct mpc *mpc = dc->res_pool->mpc;
523         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
524
525         enum dc_transfer_func_predefined tf;
526         bool result = true;
527         struct pwl_params *params = NULL;
528
529         if (mpc == NULL || plane_state == NULL)
530                 return false;
531
532         tf = TRANSFER_FUNCTION_UNITY;
533
534         if (plane_state->in_transfer_func &&
535                 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED)
536                 tf = plane_state->in_transfer_func->tf;
537
538         dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);
539
540         if (plane_state->in_transfer_func) {
541                 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL)
542                         params = &plane_state->in_transfer_func->pwl;
543                 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS &&
544                         cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func,
545                                         &dpp_base->degamma_params, false))
546                         params = &dpp_base->degamma_params;
547         }
548
549         dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
550
551         if (pipe_ctx->stream_res.opp &&
552                         pipe_ctx->stream_res.opp->ctx &&
553                         hws->funcs.set_mcm_luts)
554                 result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state);
555
556         return result;
557 }
558
559 bool dcn32_set_output_transfer_func(struct dc *dc,
560                                 struct pipe_ctx *pipe_ctx,
561                                 const struct dc_stream_state *stream)
562 {
563         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
564         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
565         struct pwl_params *params = NULL;
566         bool ret = false;
567
568         /* program OGAM or 3DLUT only for the top pipe*/
569         if (resource_is_pipe_type(pipe_ctx, OPP_HEAD)) {
570                 /*program shaper and 3dlut in MPC*/
571                 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);
572                 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
573                         if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
574                                 params = &stream->out_transfer_func->pwl;
575                         else if (pipe_ctx->stream->out_transfer_func->type ==
576                                         TF_TYPE_DISTRIBUTED_POINTS &&
577                                         cm3_helper_translate_curve_to_hw_format(
578                                         stream->out_transfer_func,
579                                         &mpc->blender_params, false))
580                                 params = &mpc->blender_params;
581                         /* there are no ROM LUTs in OUTGAM */
582                         if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
583                                 BREAK_TO_DEBUGGER();
584                 }
585         }
586
587         mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
588         return ret;
589 }
590
591 /* Program P-State force value according to if pipe is using SubVP / FPO or not:
592  * 1. Reset P-State force on all pipes first
593  * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB)
594  */
595 void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context)
596 {
597         int i;
598
599         /* Unforce p-state for each pipe if it is not FPO or SubVP.
600          * For FPO and SubVP, if it's already forced disallow, leave
601          * it as disallow.
602          */
603         for (i = 0; i < dc->res_pool->pipe_count; i++) {
604                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
605                 struct hubp *hubp = pipe->plane_res.hubp;
606
607                 if (!pipe->stream || !(dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN ||
608                     pipe->stream->fpo_in_use)) {
609                         if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
610                                 hubp->funcs->hubp_update_force_pstate_disallow(hubp, false);
611                         if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow)
612                                 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, false);
613                 }
614         }
615
616         /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false.
617          */
618         for (i = 0; i < dc->res_pool->pipe_count; i++) {
619                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
620                 struct hubp *hubp = pipe->plane_res.hubp;
621
622                 if (pipe->stream && (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN ||
623                                 pipe->stream->fpo_in_use)) {
624                         if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
625                                 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true);
626                         if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow)
627                                 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, true);
628                 }
629         }
630 }
631
632 /* Update MALL_SEL register based on if pipe / plane
633  * is a phantom pipe, main pipe, and if using MALL
634  * for SS.
635  */
636 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context)
637 {
638         int i;
639         unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context);
640         bool cache_cursor = false;
641
642         for (i = 0; i < dc->res_pool->pipe_count; i++) {
643                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
644                 struct hubp *hubp = pipe->plane_res.hubp;
645
646                 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {
647                         int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;
648
649                         switch (hubp->curs_attr.color_format) {
650                         case CURSOR_MODE_MONO:
651                                 cursor_size /= 2;
652                                 break;
653                         case CURSOR_MODE_COLOR_1BIT_AND:
654                         case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
655                         case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
656                                 cursor_size *= 4;
657                                 break;
658
659                         case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
660                         case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
661                         default:
662                                 cursor_size *= 8;
663                                 break;
664                         }
665
666                         if (cursor_size > 16384)
667                                 cache_cursor = true;
668
669                         if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {
670                                 hubp->funcs->hubp_update_mall_sel(hubp, 1, false);
671                         } else {
672                                 // MALL not supported with Stereo3D
673                                 hubp->funcs->hubp_update_mall_sel(hubp,
674                                         num_ways <= dc->caps.cache_num_ways &&
675                                         pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
676                                         pipe->plane_state->address.type !=  PLN_ADDR_TYPE_GRPH_STEREO &&
677                                         !pipe->plane_state->address.tmz_surface ? 2 : 0,
678                                                         cache_cursor);
679                         }
680                 }
681         }
682 }
683
684 /* Program the sub-viewport pipe configuration after the main / phantom pipes
685  * have been programmed in hardware.
686  * 1. Update force P-State for all the main pipes (disallow P-state)
687  * 2. Update MALL_SEL register
688  * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes
689  */
690 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context)
691 {
692         int i;
693         struct dce_hwseq *hws = dc->hwseq;
694
695         // Don't force p-state disallow -- can't block dummy p-state
696
697         // Update MALL_SEL register for each pipe
698         if (hws && hws->funcs.update_mall_sel)
699                 hws->funcs.update_mall_sel(dc, context);
700
701         // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes
702         for (i = 0; i < dc->res_pool->pipe_count; i++) {
703                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
704                 struct hubp *hubp = pipe->plane_res.hubp;
705
706                 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) {
707                         /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases
708                          *      - need to investigate single pipe MPO + SubVP case to
709                          *        see if CURSOR_REQ_MODE will be back to 1 for SubVP
710                          *        when it should be 0 for MPO
711                          */
712                         if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)
713                                 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true);
714                 }
715         }
716 }
717
718 static void dcn32_initialize_min_clocks(struct dc *dc)
719 {
720         struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk;
721
722         clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ;
723         clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000;
724         clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000;
725         clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000;
726         clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000;
727         clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
728         clocks->fclk_p_state_change_support = true;
729         clocks->p_state_change_support = true;
730         if (dc->debug.disable_boot_optimizations) {
731                 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000;
732         } else {
733                 /* Even though DPG_EN = 1 for the connected display, it still requires the
734                  * correct timing so we cannot set DISPCLK to min freq or it could cause
735                  * audio corruption. Read current DISPCLK from DENTIST and request the same
736                  * freq to ensure that the timing is valid and unchanged.
737                  */
738                 clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);
739         }
740
741         dc->clk_mgr->funcs->update_clocks(
742                         dc->clk_mgr,
743                         dc->current_state,
744                         true);
745 }
746
747 void dcn32_init_hw(struct dc *dc)
748 {
749         struct abm **abms = dc->res_pool->multiple_abms;
750         struct dce_hwseq *hws = dc->hwseq;
751         struct dc_bios *dcb = dc->ctx->dc_bios;
752         struct resource_pool *res_pool = dc->res_pool;
753         int i;
754         int edp_num;
755         uint32_t backlight = MAX_BACKLIGHT_LEVEL;
756         uint32_t user_level = MAX_BACKLIGHT_LEVEL;
757
758         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
759                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
760
761         // Initialize the dccg
762         if (res_pool->dccg->funcs->dccg_init)
763                 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
764
765         if (!dcb->funcs->is_accelerated_mode(dcb)) {
766                 hws->funcs.bios_golden_init(dc);
767                 hws->funcs.disable_vga(dc->hwseq);
768         }
769
770         // Set default OPTC memory power states
771         if (dc->debug.enable_mem_low_power.bits.optc) {
772                 // Shutdown when unassigned and light sleep in VBLANK
773                 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
774         }
775
776         if (dc->debug.enable_mem_low_power.bits.vga) {
777                 // Power down VGA memory
778                 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
779         }
780
781         if (dc->ctx->dc_bios->fw_info_valid) {
782                 res_pool->ref_clocks.xtalin_clock_inKhz =
783                                 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
784
785                 if (res_pool->dccg && res_pool->hubbub) {
786                         (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
787                                         dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
788                                         &res_pool->ref_clocks.dccg_ref_clock_inKhz);
789
790                         (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
791                                         res_pool->ref_clocks.dccg_ref_clock_inKhz,
792                                         &res_pool->ref_clocks.dchub_ref_clock_inKhz);
793                 } else {
794                         // Not all ASICs have DCCG sw component
795                         res_pool->ref_clocks.dccg_ref_clock_inKhz =
796                                         res_pool->ref_clocks.xtalin_clock_inKhz;
797                         res_pool->ref_clocks.dchub_ref_clock_inKhz =
798                                         res_pool->ref_clocks.xtalin_clock_inKhz;
799                 }
800         } else
801                 ASSERT_CRITICAL(false);
802
803         for (i = 0; i < dc->link_count; i++) {
804                 /* Power up AND update implementation according to the
805                  * required signal (which may be different from the
806                  * default signal on connector).
807                  */
808                 struct dc_link *link = dc->links[i];
809
810                 link->link_enc->funcs->hw_init(link->link_enc);
811
812                 /* Check for enabled DIG to identify enabled display */
813                 if (link->link_enc->funcs->is_dig_enabled &&
814                         link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
815                         link->link_status.link_active = true;
816                         link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
817                         if (link->link_enc->funcs->fec_is_active &&
818                                         link->link_enc->funcs->fec_is_active(link->link_enc))
819                                 link->fec_state = dc_link_fec_enabled;
820                 }
821         }
822
823         /* enable_power_gating_plane before dsc_pg_control because
824          * FORCEON = 1 with hw default value on bootup, resume from s3
825          */
826         if (hws->funcs.enable_power_gating_plane)
827                 hws->funcs.enable_power_gating_plane(dc->hwseq, true);
828
829         /* we want to turn off all dp displays before doing detection */
830         dc->link_srv->blank_all_dp_displays(dc);
831
832         /* If taking control over from VBIOS, we may want to optimize our first
833          * mode set, so we need to skip powering down pipes until we know which
834          * pipes we want to use.
835          * Otherwise, if taking control is not possible, we need to power
836          * everything down.
837          */
838         if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
839                 /* Disable boot optimizations means power down everything including PHY, DIG,
840                  * and OTG (i.e. the boot is not optimized because we do a full power down).
841                  */
842                 if (dc->hwss.enable_accelerated_mode && dc->debug.disable_boot_optimizations)
843                         dc->hwss.enable_accelerated_mode(dc, dc->current_state);
844                 else
845                         hws->funcs.init_pipes(dc, dc->current_state);
846
847                 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
848                         dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
849                                         !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
850
851                 dcn32_initialize_min_clocks(dc);
852
853                 /* On HW init, allow idle optimizations after pipes have been turned off.
854                  *
855                  * In certain D3 cases (i.e. BOCO / BOMACO) it's possible that hardware state
856                  * is reset (i.e. not in idle at the time hw init is called), but software state
857                  * still has idle_optimizations = true, so we must disable idle optimizations first
858                  * (i.e. set false), then re-enable (set true).
859                  */
860                 dc_allow_idle_optimizations(dc, false);
861                 dc_allow_idle_optimizations(dc, true);
862         }
863
864         /* In headless boot cases, DIG may be turned
865          * on which causes HW/SW discrepancies.
866          * To avoid this, power down hardware on boot
867          * if DIG is turned on and seamless boot not enabled
868          */
869         if (!dc->config.seamless_boot_edp_requested) {
870                 struct dc_link *edp_links[MAX_NUM_EDP];
871                 struct dc_link *edp_link;
872
873                 dc_get_edp_links(dc, edp_links, &edp_num);
874                 if (edp_num) {
875                         for (i = 0; i < edp_num; i++) {
876                                 edp_link = edp_links[i];
877                                 if (edp_link->link_enc->funcs->is_dig_enabled &&
878                                                 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
879                                                 dc->hwss.edp_backlight_control &&
880                                                 dc->hwss.power_down &&
881                                                 dc->hwss.edp_power_control) {
882                                         dc->hwss.edp_backlight_control(edp_link, false);
883                                         dc->hwss.power_down(dc);
884                                         dc->hwss.edp_power_control(edp_link, false);
885                                 }
886                         }
887                 } else {
888                         for (i = 0; i < dc->link_count; i++) {
889                                 struct dc_link *link = dc->links[i];
890
891                                 if (link->link_enc->funcs->is_dig_enabled &&
892                                                 link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
893                                                 dc->hwss.power_down) {
894                                         dc->hwss.power_down(dc);
895                                         break;
896                                 }
897
898                         }
899                 }
900         }
901
902         for (i = 0; i < res_pool->audio_count; i++) {
903                 struct audio *audio = res_pool->audios[i];
904
905                 audio->funcs->hw_init(audio);
906         }
907
908         for (i = 0; i < dc->link_count; i++) {
909                 struct dc_link *link = dc->links[i];
910
911                 if (link->panel_cntl) {
912                         backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
913                         user_level = link->panel_cntl->stored_backlight_registers.USER_LEVEL;
914                 }
915         }
916
917         for (i = 0; i < dc->res_pool->pipe_count; i++) {
918                 if (abms[i] != NULL && abms[i]->funcs != NULL)
919                         abms[i]->funcs->abm_init(abms[i], backlight, user_level);
920         }
921
922         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
923         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
924
925         if (!dc->debug.disable_clock_gate) {
926                 /* enable all DCN clock gating */
927                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
928
929                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
930
931                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
932         }
933
934         if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
935                 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
936
937         if (dc->clk_mgr->funcs->notify_wm_ranges)
938                 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
939
940         if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)
941                 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
942
943         if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
944                 dc->res_pool->hubbub->funcs->force_pstate_change_control(
945                                 dc->res_pool->hubbub, false, false);
946
947         if (dc->res_pool->hubbub->funcs->init_crb)
948                 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
949
950         if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)
951                 dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);
952
953         // Get DMCUB capabilities
954         if (dc->ctx->dmub_srv) {
955                 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);
956                 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
957                 dc->caps.dmub_caps.subvp_psr = dc->ctx->dmub_srv->dmub->feature_caps.subvp_psr_support;
958                 dc->caps.dmub_caps.gecc_enable = dc->ctx->dmub_srv->dmub->feature_caps.gecc_enable;
959                 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;
960
961                 if (dc->ctx->dmub_srv->dmub->fw_version <
962                     DMUB_FW_VERSION(7, 0, 35)) {
963                         dc->debug.force_disable_subvp = true;
964                         dc->debug.disable_fpo_optimizations = true;
965                 }
966         }
967 }
968
969 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
970                 int opp_cnt)
971 {
972         bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
973         int flow_ctrl_cnt;
974
975         if (opp_cnt >= 2)
976                 hblank_halved = true;
977
978         flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
979                         stream->timing.h_border_left -
980                         stream->timing.h_border_right;
981
982         if (hblank_halved)
983                 flow_ctrl_cnt /= 2;
984
985         /* ODM combine 4:1 case */
986         if (opp_cnt == 4)
987                 flow_ctrl_cnt /= 2;
988
989         return flow_ctrl_cnt;
990 }
991
992 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
993 {
994         struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
995         struct dc *dc = pipe_ctx->stream->ctx->dc;
996         struct dc_stream_state *stream = pipe_ctx->stream;
997         struct pipe_ctx *odm_pipe;
998         int opp_cnt = 1;
999         struct dccg *dccg = dc->res_pool->dccg;
1000         /* It has been found that when DSCCLK is lower than 16Mhz, we will get DCN
1001          * register access hung. When DSCCLk is based on refclk, DSCCLk is always a
1002          * fixed value higher than 16Mhz so the issue doesn't occur. When DSCCLK is
1003          * generated by DTO, DSCCLK would be based on 1/3 dispclk. For small timings
1004          * with DSC such as 480p60Hz, the dispclk could be low enough to trigger
1005          * this problem. We are implementing a workaround here to keep using dscclk
1006          * based on fixed value refclk when timing is smaller than 3x16Mhz (i.e
1007          * 48Mhz) pixel clock to avoid hitting this problem.
1008          */
1009         bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) &&
1010                         stream->timing.pix_clk_100hz > 480000;
1011
1012         ASSERT(dsc);
1013         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1014                 opp_cnt++;
1015
1016         if (enable) {
1017                 struct dsc_config dsc_cfg;
1018                 struct dsc_optc_config dsc_optc_cfg;
1019                 enum optc_dsc_mode optc_dsc_mode;
1020
1021                 /* Enable DSC hw block */
1022                 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
1023                 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
1024                 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
1025                 dsc_cfg.color_depth = stream->timing.display_color_depth;
1026                 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
1027                 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
1028                 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
1029                 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
1030
1031                 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
1032                 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
1033                 if (should_use_dto_dscclk)
1034                         dccg->funcs->set_dto_dscclk(dccg, dsc->inst);
1035                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1036                         struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
1037
1038                         ASSERT(odm_dsc);
1039                         odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
1040                         odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
1041                         if (should_use_dto_dscclk)
1042                                 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst);
1043                 }
1044                 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
1045                 dsc_cfg.pic_width *= opp_cnt;
1046
1047                 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
1048
1049                 /* Enable DSC in OPTC */
1050                 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
1051                 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
1052                                                         optc_dsc_mode,
1053                                                         dsc_optc_cfg.bytes_per_pixel,
1054                                                         dsc_optc_cfg.slice_width);
1055         } else {
1056                 /* disable DSC in OPTC */
1057                 pipe_ctx->stream_res.tg->funcs->set_dsc_config(
1058                                 pipe_ctx->stream_res.tg,
1059                                 OPTC_DSC_DISABLED, 0, 0);
1060
1061                 /* disable DSC block */
1062                 if (dccg->funcs->set_ref_dscclk)
1063                         dccg->funcs->set_ref_dscclk(dccg, pipe_ctx->stream_res.dsc->inst);
1064                 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
1065                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1066                         ASSERT(odm_pipe->stream_res.dsc);
1067                         if (dccg->funcs->set_ref_dscclk)
1068                                 dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst);
1069                         odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
1070                 }
1071         }
1072 }
1073
1074 /*
1075 * Given any pipe_ctx, return the total ODM combine factor, and optionally return
1076 * the OPPids which are used
1077 * */
1078 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
1079 {
1080         unsigned int opp_count = 1;
1081         struct pipe_ctx *odm_pipe;
1082
1083         /* First get to the top pipe */
1084         for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)
1085                 ;
1086
1087         /* First pipe is always used */
1088         if (opp_instances)
1089                 opp_instances[0] = odm_pipe->stream_res.opp->inst;
1090
1091         /* Find and count odm pipes, if any */
1092         for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1093                 if (opp_instances)
1094                         opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;
1095                 opp_count++;
1096         }
1097
1098         return opp_count;
1099 }
1100
1101 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
1102 {
1103         struct pipe_ctx *odm_pipe;
1104         int opp_cnt = 0;
1105         int opp_inst[MAX_PIPES] = {0};
1106         bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing));
1107         struct mpc_dwb_flow_control flow_control;
1108         struct mpc *mpc = dc->res_pool->mpc;
1109         int i;
1110
1111         opp_cnt = get_odm_config(pipe_ctx, opp_inst);
1112
1113         if (opp_cnt > 1)
1114                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
1115                                 pipe_ctx->stream_res.tg,
1116                                 opp_inst, opp_cnt,
1117                                 &pipe_ctx->stream->timing);
1118         else
1119                 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
1120                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1121
1122         rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
1123         flow_control.flow_ctrl_mode = 0;
1124         flow_control.flow_ctrl_cnt0 = 0x80;
1125         flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt);
1126         if (mpc->funcs->set_out_rate_control) {
1127                 for (i = 0; i < opp_cnt; ++i) {
1128                         mpc->funcs->set_out_rate_control(
1129                                         mpc, opp_inst[i],
1130                                         true,
1131                                         rate_control_2x_pclk,
1132                                         &flow_control);
1133                 }
1134         }
1135
1136         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1137                 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
1138                                 odm_pipe->stream_res.opp,
1139                                 true);
1140         }
1141
1142         if (pipe_ctx->stream_res.dsc) {
1143                 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
1144
1145                 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
1146
1147                 /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */
1148                 if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&
1149                                 current_pipe_ctx->next_odm_pipe->stream_res.dsc) {
1150                         struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc;
1151                         struct dccg *dccg = dc->res_pool->dccg;
1152
1153                         if (dccg->funcs->set_ref_dscclk)
1154                                 dccg->funcs->set_ref_dscclk(dccg, dsc->inst);
1155                         /* disconnect DSC block from stream */
1156                         dsc->funcs->dsc_disconnect(dsc);
1157                 }
1158         }
1159
1160         if (!resource_is_pipe_type(pipe_ctx, DPP_PIPE))
1161                 /*
1162                  * blank pattern is generated by OPP, reprogram blank pattern
1163                  * due to OPP count change
1164                  */
1165                 dc->hwseq->funcs.blank_pixel_data(dc, pipe_ctx, true);
1166 }
1167
1168 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
1169 {
1170         struct dc_stream_state *stream = pipe_ctx->stream;
1171         unsigned int odm_combine_factor = 0;
1172         bool two_pix_per_container = false;
1173
1174         two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);
1175         odm_combine_factor = get_odm_config(pipe_ctx, NULL);
1176
1177         if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1178                 *k1_div = PIXEL_RATE_DIV_BY_1;
1179                 *k2_div = PIXEL_RATE_DIV_BY_1;
1180         } else if (dc_is_hdmi_tmds_signal(stream->signal) || dc_is_dvi_signal(stream->signal)) {
1181                 *k1_div = PIXEL_RATE_DIV_BY_1;
1182                 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1183                         *k2_div = PIXEL_RATE_DIV_BY_2;
1184                 else
1185                         *k2_div = PIXEL_RATE_DIV_BY_4;
1186         } else if (dc_is_dp_signal(stream->signal) || dc_is_virtual_signal(stream->signal)) {
1187                 if (two_pix_per_container) {
1188                         *k1_div = PIXEL_RATE_DIV_BY_1;
1189                         *k2_div = PIXEL_RATE_DIV_BY_2;
1190                 } else {
1191                         *k1_div = PIXEL_RATE_DIV_BY_1;
1192                         *k2_div = PIXEL_RATE_DIV_BY_4;
1193                         if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
1194                                 *k2_div = PIXEL_RATE_DIV_BY_2;
1195                 }
1196         }
1197
1198         if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
1199                 ASSERT(false);
1200
1201         return odm_combine_factor;
1202 }
1203
1204 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
1205 {
1206         uint32_t pix_per_cycle = 1;
1207         uint32_t odm_combine_factor = 1;
1208
1209         if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc)
1210                 return;
1211
1212         odm_combine_factor = get_odm_config(pipe_ctx, NULL);
1213         if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1
1214                 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
1215                 pix_per_cycle = 2;
1216
1217         if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)
1218                 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,
1219                                 pix_per_cycle);
1220 }
1221
1222 void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context)
1223 {
1224         unsigned int i;
1225         struct pipe_ctx *pipe = NULL;
1226         bool otg_disabled[MAX_PIPES] = {false};
1227
1228         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1229                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1230
1231                 if (!resource_is_pipe_type(pipe, OTG_MASTER))
1232                         continue;
1233
1234                 if ((pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))
1235                         && dc_state_get_pipe_subvp_type(dc->current_state, pipe) != SUBVP_PHANTOM) {
1236                         pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);
1237                         reset_sync_context_for_pipe(dc, context, i);
1238                         otg_disabled[i] = true;
1239                 }
1240         }
1241
1242         hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);
1243
1244         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1245                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1246
1247                 if (otg_disabled[i])
1248                         pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
1249         }
1250 }
1251
1252 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,
1253                 struct dc_link_settings *link_settings)
1254 {
1255         struct encoder_unblank_param params = {0};
1256         struct dc_stream_state *stream = pipe_ctx->stream;
1257         struct dc_link *link = stream->link;
1258         struct dce_hwseq *hws = link->dc->hwseq;
1259         struct pipe_ctx *odm_pipe;
1260         uint32_t pix_per_cycle = 1;
1261
1262         params.opp_cnt = 1;
1263         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1264                 params.opp_cnt++;
1265
1266         /* only 3 items below are used by unblank */
1267         params.timing = pipe_ctx->stream->timing;
1268
1269         params.link_settings.link_rate = link_settings->link_rate;
1270
1271         if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1272                 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
1273                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(
1274                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
1275                                 pipe_ctx->stream_res.tg->inst);
1276         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1277                 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1
1278                         || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) {
1279                         params.timing.pix_clk_100hz /= 2;
1280                         pix_per_cycle = 2;
1281                 }
1282                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
1283                                 pipe_ctx->stream_res.stream_enc, pix_per_cycle > 1);
1284                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
1285         }
1286
1287         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP)
1288                 hws->funcs.edp_backlight_control(link, true);
1289 }
1290
1291 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)
1292 {
1293         struct dc *dc = pipe_ctx->stream->ctx->dc;
1294
1295         if (!is_h_timing_divisible_by_2(pipe_ctx->stream))
1296                 return false;
1297
1298         if (dc_is_dp_signal(pipe_ctx->stream->signal) && !dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) &&
1299                 dc->debug.enable_dp_dig_pixel_rate_div_policy)
1300                 return true;
1301         return false;
1302 }
1303
1304 static void apply_symclk_on_tx_off_wa(struct dc_link *link)
1305 {
1306         /* There are use cases where SYMCLK is referenced by OTG. For instance
1307          * for TMDS signal, OTG relies SYMCLK even if TX video output is off.
1308          * However current link interface will power off PHY when disabling link
1309          * output. This will turn off SYMCLK generated by PHY. The workaround is
1310          * to identify such case where SYMCLK is still in use by OTG when we
1311          * power off PHY. When this is detected, we will temporarily power PHY
1312          * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling
1313          * program_pix_clk interface. When OTG is disabled, we will then power
1314          * off PHY by calling disable link output again.
1315          *
1316          * In future dcn generations, we plan to rework transmitter control
1317          * interface so that we could have an option to set SYMCLK ON TX OFF
1318          * state in one step without this workaround
1319          */
1320
1321         struct dc *dc = link->ctx->dc;
1322         struct pipe_ctx *pipe_ctx = NULL;
1323         uint8_t i;
1324
1325         if (link->phy_state.symclk_ref_cnts.otg > 0) {
1326                 for (i = 0; i < MAX_PIPES; i++) {
1327                         pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1328                         if (resource_is_pipe_type(pipe_ctx, OPP_HEAD) && pipe_ctx->stream->link == link) {
1329                                 pipe_ctx->clock_source->funcs->program_pix_clk(
1330                                                 pipe_ctx->clock_source,
1331                                                 &pipe_ctx->stream_res.pix_clk_params,
1332                                                 dc->link_srv->dp_get_encoding_format(
1333                                                                 &pipe_ctx->link_config.dp_link_settings),
1334                                                 &pipe_ctx->pll_settings);
1335                                 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
1336                                 break;
1337                         }
1338                 }
1339         }
1340 }
1341
1342 void dcn32_disable_link_output(struct dc_link *link,
1343                 const struct link_resource *link_res,
1344                 enum signal_type signal)
1345 {
1346         struct dc *dc = link->ctx->dc;
1347         const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
1348         struct dmcu *dmcu = dc->res_pool->dmcu;
1349
1350         if (signal == SIGNAL_TYPE_EDP &&
1351                         link->dc->hwss.edp_backlight_control &&
1352                         !link->skip_implict_edp_power_control)
1353                 link->dc->hwss.edp_backlight_control(link, false);
1354         else if (dmcu != NULL && dmcu->funcs->lock_phy)
1355                 dmcu->funcs->lock_phy(dmcu);
1356
1357         link_hwss->disable_link_output(link, link_res, signal);
1358         link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
1359
1360         if (signal == SIGNAL_TYPE_EDP &&
1361                         link->dc->hwss.edp_backlight_control &&
1362                         !link->skip_implict_edp_power_control)
1363                 link->dc->hwss.edp_power_control(link, false);
1364         else if (dmcu != NULL && dmcu->funcs->lock_phy)
1365                 dmcu->funcs->unlock_phy(dmcu);
1366
1367         dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
1368
1369         apply_symclk_on_tx_off_wa(link);
1370 }
1371
1372 /* For SubVP the main pipe can have a viewport position change
1373  * without a full update. In this case we must also update the
1374  * viewport positions for the phantom pipe accordingly.
1375  */
1376 void dcn32_update_phantom_vp_position(struct dc *dc,
1377                 struct dc_state *context,
1378                 struct pipe_ctx *phantom_pipe)
1379 {
1380         uint32_t i;
1381         struct dc_plane_state *phantom_plane = phantom_pipe->plane_state;
1382
1383         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1384                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1385
1386                 if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN &&
1387                                 dc_state_get_paired_subvp_stream(context, pipe->stream) == phantom_pipe->stream) {
1388                         if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) {
1389
1390                                 phantom_plane->src_rect.x = pipe->plane_state->src_rect.x;
1391                                 phantom_plane->src_rect.y = pipe->plane_state->src_rect.y;
1392                                 phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x;
1393                                 phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x;
1394                                 phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y;
1395
1396                                 phantom_pipe->plane_state->update_flags.bits.position_change = 1;
1397                                 resource_build_scaling_params(phantom_pipe);
1398                                 return;
1399                         }
1400                 }
1401         }
1402 }
1403
1404 /* Treat the phantom pipe as if it needs to be fully enabled.
1405  * If the pipe was previously in use but not phantom, it would
1406  * have been disabled earlier in the sequence so we need to run
1407  * the full enable sequence.
1408  */
1409 void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe)
1410 {
1411         phantom_pipe->update_flags.raw = 0;
1412         if (resource_is_pipe_type(phantom_pipe, DPP_PIPE)) {
1413                 phantom_pipe->update_flags.bits.enable = 1;
1414                 phantom_pipe->update_flags.bits.mpcc = 1;
1415                 phantom_pipe->update_flags.bits.dppclk = 1;
1416                 phantom_pipe->update_flags.bits.hubp_interdependent = 1;
1417                 phantom_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1418                 phantom_pipe->update_flags.bits.gamut_remap = 1;
1419                 phantom_pipe->update_flags.bits.scaler = 1;
1420                 phantom_pipe->update_flags.bits.viewport = 1;
1421                 phantom_pipe->update_flags.bits.det_size = 1;
1422                 if (resource_is_pipe_type(phantom_pipe, OTG_MASTER)) {
1423                         phantom_pipe->update_flags.bits.odm = 1;
1424                         phantom_pipe->update_flags.bits.global_sync = 1;
1425                 }
1426         }
1427 }
1428
1429 bool dcn32_dsc_pg_status(
1430                 struct dce_hwseq *hws,
1431                 unsigned int dsc_inst)
1432 {
1433         uint32_t pwr_status = 0;
1434
1435         switch (dsc_inst) {
1436         case 0: /* DSC0 */
1437                 REG_GET(DOMAIN16_PG_STATUS,
1438                                 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1439                 break;
1440         case 1: /* DSC1 */
1441
1442                 REG_GET(DOMAIN17_PG_STATUS,
1443                                 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1444                 break;
1445         case 2: /* DSC2 */
1446                 REG_GET(DOMAIN18_PG_STATUS,
1447                                 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1448                 break;
1449         case 3: /* DSC3 */
1450                 REG_GET(DOMAIN19_PG_STATUS,
1451                                 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1452                 break;
1453         default:
1454                 BREAK_TO_DEBUGGER();
1455                 break;
1456         }
1457
1458         return pwr_status == 0;
1459 }
1460
1461 void dcn32_update_dsc_pg(struct dc *dc,
1462                 struct dc_state *context,
1463                 bool safe_to_disable)
1464 {
1465         struct dce_hwseq *hws = dc->hwseq;
1466         int i;
1467
1468         for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
1469                 struct display_stream_compressor *dsc = dc->res_pool->dscs[i];
1470                 bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst);
1471
1472                 if (context->res_ctx.is_dsc_acquired[i]) {
1473                         if (!is_dsc_ungated) {
1474                                 hws->funcs.dsc_pg_control(hws, dsc->inst, true);
1475                         }
1476                 } else if (safe_to_disable) {
1477                         if (is_dsc_ungated) {
1478                                 hws->funcs.dsc_pg_control(hws, dsc->inst, false);
1479                         }
1480                 }
1481         }
1482 }
1483
1484 void dcn32_disable_phantom_streams(struct dc *dc, struct dc_state *context)
1485 {
1486         struct dce_hwseq *hws = dc->hwseq;
1487         int i;
1488
1489         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1490                 struct pipe_ctx *pipe_ctx_old =
1491                         &dc->current_state->res_ctx.pipe_ctx[i];
1492                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1493
1494                 if (!pipe_ctx_old->stream)
1495                         continue;
1496
1497                 if (dc_state_get_pipe_subvp_type(dc->current_state, pipe_ctx_old) != SUBVP_PHANTOM)
1498                         continue;
1499
1500                 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
1501                         continue;
1502
1503                 if (!pipe_ctx->stream || pipe_need_reprogram(pipe_ctx_old, pipe_ctx) ||
1504                                 (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)) {
1505                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
1506
1507                         if (hws->funcs.reset_back_end_for_pipe)
1508                                 hws->funcs.reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
1509                         if (hws->funcs.enable_stream_gating)
1510                                 hws->funcs.enable_stream_gating(dc, pipe_ctx_old);
1511                         if (old_clk)
1512                                 old_clk->funcs->cs_power_down(old_clk);
1513                 }
1514         }
1515 }
1516
1517 void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context)
1518 {
1519         unsigned int i;
1520         enum dc_status status = DC_OK;
1521         struct dce_hwseq *hws = dc->hwseq;
1522
1523         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1524                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1525                 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1526
1527                 /* If an active, non-phantom pipe is being transitioned into a phantom
1528                  * pipe, wait for the double buffer update to complete first before we do
1529                  * ANY phantom pipe programming.
1530                  */
1531                 if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM &&
1532                                 old_pipe->stream && dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) != SUBVP_PHANTOM) {
1533                         old_pipe->stream_res.tg->funcs->wait_for_state(
1534                                         old_pipe->stream_res.tg,
1535                                         CRTC_STATE_VBLANK);
1536                         old_pipe->stream_res.tg->funcs->wait_for_state(
1537                                         old_pipe->stream_res.tg,
1538                                         CRTC_STATE_VACTIVE);
1539                 }
1540         }
1541         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1542                 struct pipe_ctx *pipe_ctx_old =
1543                                         &dc->current_state->res_ctx.pipe_ctx[i];
1544                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1545
1546                 if (pipe_ctx->stream == NULL)
1547                         continue;
1548
1549                 if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)
1550                         continue;
1551
1552                 if (pipe_ctx->stream == pipe_ctx_old->stream &&
1553                         pipe_ctx->stream->link->link_state_valid) {
1554                         continue;
1555                 }
1556
1557                 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
1558                         continue;
1559
1560                 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)
1561                         continue;
1562
1563                 if (hws->funcs.apply_single_controller_ctx_to_hw)
1564                         status = hws->funcs.apply_single_controller_ctx_to_hw(
1565                                         pipe_ctx,
1566                                         context,
1567                                         dc);
1568
1569                 ASSERT(status == DC_OK);
1570
1571 #ifdef CONFIG_DRM_AMD_DC_FP
1572                 if (hws->funcs.resync_fifo_dccg_dio)
1573                         hws->funcs.resync_fifo_dccg_dio(hws, dc, context);
1574 #endif
1575         }
1576 }
1577
1578 /* Blank pixel data during initialization */
1579 void dcn32_init_blank(
1580                 struct dc *dc,
1581                 struct timing_generator *tg)
1582 {
1583         struct dce_hwseq *hws = dc->hwseq;
1584         enum dc_color_space color_space;
1585         struct tg_color black_color = {0};
1586         struct output_pixel_processor *opp = NULL;
1587         struct output_pixel_processor *bottom_opp = NULL;
1588         uint32_t num_opps, opp_id_src0, opp_id_src1;
1589         uint32_t otg_active_width, otg_active_height;
1590         uint32_t i;
1591
1592         /* program opp dpg blank color */
1593         color_space = COLOR_SPACE_SRGB;
1594         color_space_to_black_color(dc, color_space, &black_color);
1595
1596         /* get the OTG active size */
1597         tg->funcs->get_otg_active_size(tg,
1598                         &otg_active_width,
1599                         &otg_active_height);
1600
1601         /* get the OPTC source */
1602         tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
1603
1604         if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) {
1605                 ASSERT(false);
1606                 return;
1607         }
1608
1609         for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
1610                 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) {
1611                         opp = dc->res_pool->opps[i];
1612                         break;
1613                 }
1614         }
1615
1616         if (num_opps == 2) {
1617                 otg_active_width = otg_active_width / 2;
1618
1619                 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) {
1620                         ASSERT(false);
1621                         return;
1622                 }
1623                 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
1624                         if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src1) {
1625                                 bottom_opp = dc->res_pool->opps[i];
1626                                 break;
1627                         }
1628                 }
1629         }
1630
1631         if (opp && opp->funcs->opp_set_disp_pattern_generator)
1632                 opp->funcs->opp_set_disp_pattern_generator(
1633                                 opp,
1634                                 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
1635                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
1636                                 COLOR_DEPTH_UNDEFINED,
1637                                 &black_color,
1638                                 otg_active_width,
1639                                 otg_active_height,
1640                                 0);
1641
1642         if (num_opps == 2) {
1643                 if (bottom_opp && bottom_opp->funcs->opp_set_disp_pattern_generator) {
1644                         bottom_opp->funcs->opp_set_disp_pattern_generator(
1645                                         bottom_opp,
1646                                         CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
1647                                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
1648                                         COLOR_DEPTH_UNDEFINED,
1649                                         &black_color,
1650                                         otg_active_width,
1651                                         otg_active_height,
1652                                         0);
1653                         hws->funcs.wait_for_blank_complete(bottom_opp);
1654                 }
1655         }
1656
1657         if (opp)
1658                 hws->funcs.wait_for_blank_complete(opp);
1659 }
1660
1661 void dcn32_blank_phantom(struct dc *dc,
1662                 struct timing_generator *tg,
1663                 int width,
1664                 int height)
1665 {
1666         struct dce_hwseq *hws = dc->hwseq;
1667         enum dc_color_space color_space;
1668         struct tg_color black_color = {0};
1669         struct output_pixel_processor *opp = NULL;
1670         uint32_t num_opps, opp_id_src0, opp_id_src1;
1671         uint32_t otg_active_width, otg_active_height;
1672         uint32_t i;
1673
1674         /* program opp dpg blank color */
1675         color_space = COLOR_SPACE_SRGB;
1676         color_space_to_black_color(dc, color_space, &black_color);
1677
1678         otg_active_width = width;
1679         otg_active_height = height;
1680
1681         /* get the OPTC source */
1682         tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
1683         ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);
1684
1685         for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
1686                 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) {
1687                         opp = dc->res_pool->opps[i];
1688                         break;
1689                 }
1690         }
1691
1692         if (opp && opp->funcs->opp_set_disp_pattern_generator)
1693                 opp->funcs->opp_set_disp_pattern_generator(
1694                                 opp,
1695                                 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
1696                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
1697                                 COLOR_DEPTH_UNDEFINED,
1698                                 &black_color,
1699                                 otg_active_width,
1700                                 otg_active_height,
1701                                 0);
1702
1703         if (tg->funcs->is_tg_enabled(tg))
1704                 hws->funcs.wait_for_blank_complete(opp);
1705 }
1706
1707 bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc,
1708                 const struct dc_state *cur_ctx,
1709                 const struct dc_state *new_ctx)
1710 {
1711         int i;
1712         const struct pipe_ctx *cur_pipe, *new_pipe;
1713         bool is_seamless = true;
1714
1715         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1716                 cur_pipe = &cur_ctx->res_ctx.pipe_ctx[i];
1717                 new_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1718
1719                 if (resource_is_pipe_type(cur_pipe, FREE_PIPE) ||
1720                                 resource_is_pipe_type(new_pipe, FREE_PIPE))
1721                         /* adding or removing free pipes is always seamless */
1722                         continue;
1723                 else if (resource_is_pipe_type(cur_pipe, OTG_MASTER)) {
1724                         if (resource_is_pipe_type(new_pipe, OTG_MASTER))
1725                                 if (cur_pipe->stream->stream_id == new_pipe->stream->stream_id)
1726                                 /* OTG master with the same stream is seamless */
1727                                         continue;
1728                 } else if (resource_is_pipe_type(cur_pipe, OPP_HEAD)) {
1729                         if (resource_is_pipe_type(new_pipe, OPP_HEAD)) {
1730                                 if (cur_pipe->stream_res.tg == new_pipe->stream_res.tg)
1731                                         /*
1732                                          * OPP heads sharing the same timing
1733                                          * generator is seamless
1734                                          */
1735                                         continue;
1736                         }
1737                 } else if (resource_is_pipe_type(cur_pipe, DPP_PIPE)) {
1738                         if (resource_is_pipe_type(new_pipe, DPP_PIPE)) {
1739                                 if (cur_pipe->stream_res.opp == new_pipe->stream_res.opp)
1740                                         /*
1741                                          * DPP pipes sharing the same OPP head is
1742                                          * seamless
1743                                          */
1744                                         continue;
1745                         }
1746                 }
1747
1748                 /*
1749                  * This pipe's transition doesn't fall under any seamless
1750                  * conditions
1751                  */
1752                 is_seamless = false;
1753                 break;
1754         }
1755
1756         return is_seamless;
1757 }
1758
1759 void dcn32_prepare_bandwidth(struct dc *dc,
1760         struct dc_state *context)
1761 {
1762         bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;
1763         /* Any transition into an FPO config should disable MCLK switching first to avoid
1764          * driver and FW P-State synchronization issues.
1765          */
1766         if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {
1767                 dc->optimized_required = true;
1768                 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
1769         }
1770
1771         if (dc->clk_mgr->dc_mode_softmax_enabled)
1772                 if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
1773                                 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
1774                         dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
1775
1776         dcn20_prepare_bandwidth(dc, context);
1777
1778         if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)
1779                 dc_dmub_srv_p_state_delegate(dc, false, context);
1780
1781         if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {
1782                 /* After disabling P-State, restore the original value to ensure we get the correct P-State
1783                  * on the next optimize.
1784                  */
1785                 context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support;
1786         }
1787 }
1788
1789 void dcn32_interdependent_update_lock(struct dc *dc,
1790                 struct dc_state *context, bool lock)
1791 {
1792         unsigned int i;
1793         struct pipe_ctx *pipe;
1794         struct timing_generator *tg;
1795
1796         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1797                 pipe = &context->res_ctx.pipe_ctx[i];
1798                 tg = pipe->stream_res.tg;
1799
1800                 if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
1801                                 !tg->funcs->is_tg_enabled(tg) ||
1802                                 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)
1803                         continue;
1804
1805                 if (lock)
1806                         dc->hwss.pipe_control_lock(dc, pipe, true);
1807                 else
1808                         dc->hwss.pipe_control_lock(dc, pipe, false);
1809         }
1810 }