drivers/gpu/drm/i915/display/intel_audio.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/component.h>
  25 #include <linux/kernel.h>
  26
  27 #include <drm/drm_edid.h>
  28 #include <drm/drm_eld.h>
  29 #include <drm/i915_component.h>
  30
  31 #include "i915_drv.h"
  32 #include "intel_atomic.h"
  33 #include "intel_audio.h"
  34 #include "intel_audio_regs.h"
  35 #include "intel_cdclk.h"
  36 #include "intel_crtc.h"
  37 #include "intel_de.h"
  38 #include "intel_display_types.h"
  39 #include "intel_lpe_audio.h"
  40
  41 /**
  42  * DOC: High Definition Audio over HDMI and Display Port
  43  *
  44  * The graphics and audio drivers together support High Definition Audio over
  45  * HDMI and Display Port. The audio programming sequences are divided into audio
  46  * codec and controller enable and disable sequences. The graphics driver
  47  * handles the audio codec sequences, while the audio driver handles the audio
  48  * controller sequences.
  49  *
  50  * The disable sequences must be performed before disabling the transcoder or
  51  * port. The enable sequences may only be performed after enabling the
  52  * transcoder and port, and after completed link training. Therefore the audio
  53  * enable/disable sequences are part of the modeset sequence.
  54  *
  55  * The codec and controller sequences could be done either parallel or serial,
  56  * but generally the ELDV/PD change in the codec sequence indicates to the audio
  57  * driver that the controller sequence should start. Indeed, most of the
  58  * co-operation between the graphics and audio drivers is handled via audio
  59  * related registers. (The notable exception is the power management, not
  60  * covered here.)
  61  *
  62  * The struct &i915_audio_component is used to interact between the graphics
  63  * and audio drivers. The struct &i915_audio_component_ops @ops in it is
  64  * defined in graphics driver and called in audio driver. The
  65  * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
  66  */
  67
  68 struct intel_audio_funcs {
  69         void (*audio_codec_enable)(struct intel_encoder *encoder,
  70                                    const struct intel_crtc_state *crtc_state,
  71                                    const struct drm_connector_state *conn_state);
  72         void (*audio_codec_disable)(struct intel_encoder *encoder,
  73                                     const struct intel_crtc_state *old_crtc_state,
  74                                     const struct drm_connector_state *old_conn_state);
  75         void (*audio_codec_get_config)(struct intel_encoder *encoder,
  76                                        struct intel_crtc_state *crtc_state);
  77 };
  78
  79 struct hdmi_aud_ncts {
  80         int sample_rate;
  81         int clock;
  82         int n;
  83         int cts;
  84 };
  85
  86 static const struct {
  87         int clock;
  88         u32 config;
  89 } hdmi_audio_clock[] = {
  90         { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
  91         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
  92         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
  93         { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
  94         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
  95         { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
  96         { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
  97         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
  98         { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
  99         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
 100         { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 },
 101         { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 },
 102         { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 },
 103         { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 },
 104 };
 105
 106 /* HDMI N/CTS table */
 107 #define TMDS_297M 297000
 108 #define TMDS_296M 296703
 109 #define TMDS_594M 594000
 110 #define TMDS_593M 593407
 111
 112 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = {
 113         { 32000, TMDS_296M, 5824, 421875 },
 114         { 32000, TMDS_297M, 3072, 222750 },
 115         { 32000, TMDS_593M, 5824, 843750 },
 116         { 32000, TMDS_594M, 3072, 445500 },
 117         { 44100, TMDS_296M, 4459, 234375 },
 118         { 44100, TMDS_297M, 4704, 247500 },
 119         { 44100, TMDS_593M, 8918, 937500 },
 120         { 44100, TMDS_594M, 9408, 990000 },
 121         { 88200, TMDS_296M, 8918, 234375 },
 122         { 88200, TMDS_297M, 9408, 247500 },
 123         { 88200, TMDS_593M, 17836, 937500 },
 124         { 88200, TMDS_594M, 18816, 990000 },
 125         { 176400, TMDS_296M, 17836, 234375 },
 126         { 176400, TMDS_297M, 18816, 247500 },
 127         { 176400, TMDS_593M, 35672, 937500 },
 128         { 176400, TMDS_594M, 37632, 990000 },
 129         { 48000, TMDS_296M, 5824, 281250 },
 130         { 48000, TMDS_297M, 5120, 247500 },
 131         { 48000, TMDS_593M, 5824, 562500 },
 132         { 48000, TMDS_594M, 6144, 594000 },
 133         { 96000, TMDS_296M, 11648, 281250 },
 134         { 96000, TMDS_297M, 10240, 247500 },
 135         { 96000, TMDS_593M, 11648, 562500 },
 136         { 96000, TMDS_594M, 12288, 594000 },
 137         { 192000, TMDS_296M, 23296, 281250 },
 138         { 192000, TMDS_297M, 20480, 247500 },
 139         { 192000, TMDS_593M, 23296, 562500 },
 140         { 192000, TMDS_594M, 24576, 594000 },
 141 };
 142
 143 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/
 144 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/
 145 #define TMDS_371M 371250
 146 #define TMDS_370M 370878
 147
 148 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = {
 149         { 32000, TMDS_370M, 5824, 527344 },
 150         { 32000, TMDS_371M, 6144, 556875 },
 151         { 44100, TMDS_370M, 8918, 585938 },
 152         { 44100, TMDS_371M, 4704, 309375 },
 153         { 88200, TMDS_370M, 17836, 585938 },
 154         { 88200, TMDS_371M, 9408, 309375 },
 155         { 176400, TMDS_370M, 35672, 585938 },
 156         { 176400, TMDS_371M, 18816, 309375 },
 157         { 48000, TMDS_370M, 11648, 703125 },
 158         { 48000, TMDS_371M, 5120, 309375 },
 159         { 96000, TMDS_370M, 23296, 703125 },
 160         { 96000, TMDS_371M, 10240, 309375 },
 161         { 192000, TMDS_370M, 46592, 703125 },
 162         { 192000, TMDS_371M, 20480, 309375 },
 163 };
 164
 165 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/
 166 #define TMDS_445_5M 445500
 167 #define TMDS_445M 445054
 168
 169 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
 170         { 32000, TMDS_445M, 5824, 632813 },
 171         { 32000, TMDS_445_5M, 4096, 445500 },
 172         { 44100, TMDS_445M, 8918, 703125 },
 173         { 44100, TMDS_445_5M, 4704, 371250 },
 174         { 88200, TMDS_445M, 17836, 703125 },
 175         { 88200, TMDS_445_5M, 9408, 371250 },
 176         { 176400, TMDS_445M, 35672, 703125 },
 177         { 176400, TMDS_445_5M, 18816, 371250 },
 178         { 48000, TMDS_445M, 5824, 421875 },
 179         { 48000, TMDS_445_5M, 5120, 371250 },
 180         { 96000, TMDS_445M, 11648, 421875 },
 181         { 96000, TMDS_445_5M, 10240, 371250 },
 182         { 192000, TMDS_445M, 23296, 421875 },
 183         { 192000, TMDS_445_5M, 20480, 371250 },
 184 };
 185
 186 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
 187 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
 188 {
 189         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 190         const struct drm_display_mode *adjusted_mode =
 191                 &crtc_state->hw.adjusted_mode;
 192         int i;
 193
 194         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
 195                 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
 196                         break;
 197         }
 198
 199         if (DISPLAY_VER(i915) < 12 && adjusted_mode->crtc_clock > 148500)
 200                 i = ARRAY_SIZE(hdmi_audio_clock);
 201
 202         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
 203                 drm_dbg_kms(&i915->drm,
 204                             "HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
 205                             adjusted_mode->crtc_clock);
 206                 i = 1;
 207         }
 208
 209         drm_dbg_kms(&i915->drm,
 210                     "Configuring HDMI audio for pixel clock %d (0x%08x)\n",
 211                     hdmi_audio_clock[i].clock,
 212                     hdmi_audio_clock[i].config);
 213
 214         return hdmi_audio_clock[i].config;
 215 }
 216
 217 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,
 218                                    int rate)
 219 {
 220         const struct hdmi_aud_ncts *hdmi_ncts_table;
 221         int i, size;
 222
 223         if (crtc_state->pipe_bpp == 36) {
 224                 hdmi_ncts_table = hdmi_aud_ncts_36bpp;
 225                 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp);
 226         } else if (crtc_state->pipe_bpp == 30) {
 227                 hdmi_ncts_table = hdmi_aud_ncts_30bpp;
 228                 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp);
 229         } else {
 230                 hdmi_ncts_table = hdmi_aud_ncts_24bpp;
 231                 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp);
 232         }
 233
 234         for (i = 0; i < size; i++) {
 235                 if (rate == hdmi_ncts_table[i].sample_rate &&
 236                     crtc_state->port_clock == hdmi_ncts_table[i].clock) {
 237                         return hdmi_ncts_table[i].n;
 238                 }
 239         }
 240         return 0;
 241 }
 242
 243 /* ELD buffer size in dwords */
 244 static int g4x_eld_buffer_size(struct drm_i915_private *i915)
 245 {
 246         u32 tmp;
 247
 248         tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
 249
 250         return REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp);
 251 }
 252
 253 static void g4x_audio_codec_get_config(struct intel_encoder *encoder,
 254                                        struct intel_crtc_state *crtc_state)
 255 {
 256         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 257         u32 *eld = (u32 *)crtc_state->eld;
 258         int eld_buffer_size, len, i;
 259         u32 tmp;
 260
 261         tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
 262         if ((tmp & G4X_ELD_VALID) == 0)
 263                 return;
 264
 265         intel_de_rmw(i915, G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK, 0);
 266
 267         eld_buffer_size = g4x_eld_buffer_size(i915);
 268         len = min_t(int, sizeof(crtc_state->eld) / 4, eld_buffer_size);
 269
 270         for (i = 0; i < len; i++)
 271                 eld[i] = intel_de_read(i915, G4X_HDMIW_HDMIEDID);
 272 }
 273
 274 static void g4x_audio_codec_disable(struct intel_encoder *encoder,
 275                                     const struct intel_crtc_state *old_crtc_state,
 276                                     const struct drm_connector_state *old_conn_state)
 277 {
 278         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 279         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 280
 281         /* Invalidate ELD */
 282         intel_de_rmw(i915, G4X_AUD_CNTL_ST,
 283                      G4X_ELD_VALID, 0);
 284
 285         intel_crtc_wait_for_next_vblank(crtc);
 286         intel_crtc_wait_for_next_vblank(crtc);
 287 }
 288
 289 static void g4x_audio_codec_enable(struct intel_encoder *encoder,
 290                                    const struct intel_crtc_state *crtc_state,
 291                                    const struct drm_connector_state *conn_state)
 292 {
 293         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 294         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 295         const u32 *eld = (const u32 *)crtc_state->eld;
 296         int eld_buffer_size, len, i;
 297
 298         intel_crtc_wait_for_next_vblank(crtc);
 299
 300         intel_de_rmw(i915, G4X_AUD_CNTL_ST,
 301                      G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK, 0);
 302
 303         eld_buffer_size = g4x_eld_buffer_size(i915);
 304         len = min(drm_eld_size(crtc_state->eld) / 4, eld_buffer_size);
 305
 306         for (i = 0; i < len; i++)
 307                 intel_de_write(i915, G4X_HDMIW_HDMIEDID, eld[i]);
 308         for (; i < eld_buffer_size; i++)
 309                 intel_de_write(i915, G4X_HDMIW_HDMIEDID, 0);
 310
 311         drm_WARN_ON(&i915->drm,
 312                     (intel_de_read(i915, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0);
 313
 314         intel_de_rmw(i915, G4X_AUD_CNTL_ST,
 315                      0, G4X_ELD_VALID);
 316 }
 317
 318 static void
 319 hsw_dp_audio_config_update(struct intel_encoder *encoder,
 320                            const struct intel_crtc_state *crtc_state)
 321 {
 322         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 323         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 324
 325         /* Enable time stamps. Let HW calculate Maud/Naud values */
 326         intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder),
 327                      AUD_CONFIG_N_VALUE_INDEX |
 328                      AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK |
 329                      AUD_CONFIG_UPPER_N_MASK |
 330                      AUD_CONFIG_LOWER_N_MASK |
 331                      AUD_CONFIG_N_PROG_ENABLE,
 332                      AUD_CONFIG_N_VALUE_INDEX);
 333
 334 }
 335
 336 static void
 337 hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
 338                              const struct intel_crtc_state *crtc_state)
 339 {
 340         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 341         struct i915_audio_component *acomp = i915->display.audio.component;
 342         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 343         enum port port = encoder->port;
 344         int n, rate;
 345         u32 tmp;
 346
 347         rate = acomp ? acomp->aud_sample_rate[port] : 0;
 348
 349         tmp = intel_de_read(i915, HSW_AUD_CFG(cpu_transcoder));
 350         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 351         tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
 352         tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 353         tmp |= audio_config_hdmi_pixel_clock(crtc_state);
 354
 355         n = audio_config_hdmi_get_n(crtc_state, rate);
 356         if (n != 0) {
 357                 drm_dbg_kms(&i915->drm, "using N %d\n", n);
 358
 359                 tmp &= ~AUD_CONFIG_N_MASK;
 360                 tmp |= AUD_CONFIG_N(n);
 361                 tmp |= AUD_CONFIG_N_PROG_ENABLE;
 362         } else {
 363                 drm_dbg_kms(&i915->drm, "using automatic N\n");
 364         }
 365
 366         intel_de_write(i915, HSW_AUD_CFG(cpu_transcoder), tmp);
 367
 368         /*
 369          * Let's disable "Enable CTS or M Prog bit"
 370          * and let HW calculate the value
 371          */
 372         tmp = intel_de_read(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
 373         tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
 374         tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
 375         intel_de_write(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
 376 }
 377
 378 static void
 379 hsw_audio_config_update(struct intel_encoder *encoder,
 380                         const struct intel_crtc_state *crtc_state)
 381 {
 382         if (intel_crtc_has_dp_encoder(crtc_state))
 383                 hsw_dp_audio_config_update(encoder, crtc_state);
 384         else
 385                 hsw_hdmi_audio_config_update(encoder, crtc_state);
 386 }
 387
 388 static void hsw_audio_codec_disable(struct intel_encoder *encoder,
 389                                     const struct intel_crtc_state *old_crtc_state,
 390                                     const struct drm_connector_state *old_conn_state)
 391 {
 392         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 393         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 394         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 395
 396         mutex_lock(&i915->display.audio.mutex);
 397
 398         /* Disable timestamps */
 399         intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder),
 400                      AUD_CONFIG_N_VALUE_INDEX |
 401                      AUD_CONFIG_UPPER_N_MASK |
 402                      AUD_CONFIG_LOWER_N_MASK,
 403                      AUD_CONFIG_N_PROG_ENABLE |
 404                      (intel_crtc_has_dp_encoder(old_crtc_state) ?
 405                       AUD_CONFIG_N_VALUE_INDEX : 0));
 406
 407         /* Invalidate ELD */
 408         intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
 409                      AUDIO_ELD_VALID(cpu_transcoder), 0);
 410
 411         intel_crtc_wait_for_next_vblank(crtc);
 412         intel_crtc_wait_for_next_vblank(crtc);
 413
 414         /* Disable audio presence detect */
 415         intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
 416                      AUDIO_OUTPUT_ENABLE(cpu_transcoder), 0);
 417
 418         mutex_unlock(&i915->display.audio.mutex);
 419 }
 420
 421 static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
 422                                            const struct intel_crtc_state *crtc_state)
 423 {
 424         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 425         unsigned int link_clks_available, link_clks_required;
 426         unsigned int tu_data, tu_line, link_clks_active;
 427         unsigned int h_active, h_total, hblank_delta, pixel_clk;
 428         unsigned int fec_coeff, cdclk, vdsc_bppx16;
 429         unsigned int link_clk, lanes;
 430         unsigned int hblank_rise;
 431
 432         h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 433         h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
 434         pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
 435         vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16;
 436         cdclk = i915->display.cdclk.hw.cdclk;
 437         /* fec= 0.972261, using rounding multiplier of 1000000 */
 438         fec_coeff = 972261;
 439         link_clk = crtc_state->port_clock;
 440         lanes = crtc_state->lane_count;
 441
 442         drm_dbg_kms(&i915->drm,
 443                     "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " BPP_X16_FMT " cdclk = %u\n",
 444                     h_active, link_clk, lanes, BPP_X16_ARGS(vdsc_bppx16), cdclk);
 445
 446         if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk))
 447                 return 0;
 448
 449         link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28;
 450         link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2);
 451
 452         if (link_clks_available > link_clks_required)
 453                 hblank_delta = 32;
 454         else
 455                 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk),
 456                                                   mul_u32_u32(link_clk, cdclk));
 457
 458         tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000),
 459                             mul_u32_u32(link_clk * lanes * 16, fec_coeff));
 460         tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff),
 461                             mul_u32_u32(64 * pixel_clk, 1000000));
 462         link_clks_active  = (tu_line - 1) * 64 + tu_data;
 463
 464         hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_clk;
 465
 466         return h_active - hblank_rise + hblank_delta;
 467 }
 468
 469 static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state)
 470 {
 471         unsigned int h_active, h_total, pixel_clk;
 472         unsigned int link_clk, lanes;
 473
 474         h_active = crtc_state->hw.adjusted_mode.hdisplay;
 475         h_total = crtc_state->hw.adjusted_mode.htotal;
 476         pixel_clk = crtc_state->hw.adjusted_mode.clock;
 477         link_clk = crtc_state->port_clock;
 478         lanes = crtc_state->lane_count;
 479
 480         return ((h_total - h_active) * link_clk - 12 * pixel_clk) /
 481                 (pixel_clk * (48 / lanes + 2));
 482 }
 483
 484 static void enable_audio_dsc_wa(struct intel_encoder *encoder,
 485                                 const struct intel_crtc_state *crtc_state)
 486 {
 487         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 488         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 489         unsigned int hblank_early_prog, samples_room;
 490         unsigned int val;
 491
 492         if (DISPLAY_VER(i915) < 11)
 493                 return;
 494
 495         val = intel_de_read(i915, AUD_CONFIG_BE);
 496
 497         if (DISPLAY_VER(i915) == 11)
 498                 val |= HBLANK_EARLY_ENABLE_ICL(cpu_transcoder);
 499         else if (DISPLAY_VER(i915) >= 12)
 500                 val |= HBLANK_EARLY_ENABLE_TGL(cpu_transcoder);
 501
 502         if (crtc_state->dsc.compression_enable &&
 503             crtc_state->hw.adjusted_mode.hdisplay >= 3840 &&
 504             crtc_state->hw.adjusted_mode.vdisplay >= 2160) {
 505                 /* Get hblank early enable value required */
 506                 val &= ~HBLANK_START_COUNT_MASK(cpu_transcoder);
 507                 hblank_early_prog = calc_hblank_early_prog(encoder, crtc_state);
 508                 if (hblank_early_prog < 32)
 509                         val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_32);
 510                 else if (hblank_early_prog < 64)
 511                         val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_64);
 512                 else if (hblank_early_prog < 96)
 513                         val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_96);
 514                 else
 515                         val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_128);
 516
 517                 /* Get samples room value required */
 518                 val &= ~NUMBER_SAMPLES_PER_LINE_MASK(cpu_transcoder);
 519                 samples_room = calc_samples_room(crtc_state);
 520                 if (samples_room < 3)
 521                         val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, samples_room);
 522                 else /* Program 0 i.e "All Samples available in buffer" */
 523                         val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, 0x0);
 524         }
 525
 526         intel_de_write(i915, AUD_CONFIG_BE, val);
 527 }
 528
 529 static void hsw_audio_codec_enable(struct intel_encoder *encoder,
 530                                    const struct intel_crtc_state *crtc_state,
 531                                    const struct drm_connector_state *conn_state)
 532 {
 533         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 534         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 535         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 536
 537         mutex_lock(&i915->display.audio.mutex);
 538
 539         /* Enable Audio WA for 4k DSC usecases */
 540         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))
 541                 enable_audio_dsc_wa(encoder, crtc_state);
 542
 543         /* Enable audio presence detect */
 544         intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
 545                      0, AUDIO_OUTPUT_ENABLE(cpu_transcoder));
 546
 547         intel_crtc_wait_for_next_vblank(crtc);
 548
 549         /* Invalidate ELD */
 550         intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
 551                      AUDIO_ELD_VALID(cpu_transcoder), 0);
 552
 553         /*
 554          * The audio componenent is used to convey the ELD
 555          * instead using of the hardware ELD buffer.
 556          */
 557
 558         /* Enable timestamps */
 559         hsw_audio_config_update(encoder, crtc_state);
 560
 561         mutex_unlock(&i915->display.audio.mutex);
 562 }
 563
 564 struct ibx_audio_regs {
 565         i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
 566 };
 567
 568 static void ibx_audio_regs_init(struct drm_i915_private *i915,
 569                                 enum pipe pipe,
 570                                 struct ibx_audio_regs *regs)
 571 {
 572         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
 573                 regs->hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
 574                 regs->aud_config = VLV_AUD_CFG(pipe);
 575                 regs->aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
 576                 regs->aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 577         } else if (HAS_PCH_CPT(i915)) {
 578                 regs->hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
 579                 regs->aud_config = CPT_AUD_CFG(pipe);
 580                 regs->aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
 581                 regs->aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
 582         } else if (HAS_PCH_IBX(i915)) {
 583                 regs->hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
 584                 regs->aud_config = IBX_AUD_CFG(pipe);
 585                 regs->aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
 586                 regs->aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
 587         }
 588 }
 589
 590 static void ibx_audio_codec_disable(struct intel_encoder *encoder,
 591                                     const struct intel_crtc_state *old_crtc_state,
 592                                     const struct drm_connector_state *old_conn_state)
 593 {
 594         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 595         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 596         enum port port = encoder->port;
 597         enum pipe pipe = crtc->pipe;
 598         struct ibx_audio_regs regs;
 599
 600         if (drm_WARN_ON(&i915->drm, port == PORT_A))
 601                 return;
 602
 603         ibx_audio_regs_init(i915, pipe, &regs);
 604
 605         mutex_lock(&i915->display.audio.mutex);
 606
 607         /* Disable timestamps */
 608         intel_de_rmw(i915, regs.aud_config,
 609                      AUD_CONFIG_N_VALUE_INDEX |
 610                      AUD_CONFIG_UPPER_N_MASK |
 611                      AUD_CONFIG_LOWER_N_MASK,
 612                      AUD_CONFIG_N_PROG_ENABLE |
 613                      (intel_crtc_has_dp_encoder(old_crtc_state) ?
 614                       AUD_CONFIG_N_VALUE_INDEX : 0));
 615
 616         /* Invalidate ELD */
 617         intel_de_rmw(i915, regs.aud_cntrl_st2,
 618                      IBX_ELD_VALID(port), 0);
 619
 620         mutex_unlock(&i915->display.audio.mutex);
 621
 622         intel_crtc_wait_for_next_vblank(crtc);
 623         intel_crtc_wait_for_next_vblank(crtc);
 624 }
 625
 626 static void ibx_audio_codec_enable(struct intel_encoder *encoder,
 627                                    const struct intel_crtc_state *crtc_state,
 628                                    const struct drm_connector_state *conn_state)
 629 {
 630         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 631         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 632         enum port port = encoder->port;
 633         enum pipe pipe = crtc->pipe;
 634         struct ibx_audio_regs regs;
 635
 636         if (drm_WARN_ON(&i915->drm, port == PORT_A))
 637                 return;
 638
 639         intel_crtc_wait_for_next_vblank(crtc);
 640
 641         ibx_audio_regs_init(i915, pipe, &regs);
 642
 643         mutex_lock(&i915->display.audio.mutex);
 644
 645         /* Invalidate ELD */
 646         intel_de_rmw(i915, regs.aud_cntrl_st2,
 647                      IBX_ELD_VALID(port), 0);
 648
 649         /*
 650          * The audio componenent is used to convey the ELD
 651          * instead using of the hardware ELD buffer.
 652          */
 653
 654         /* Enable timestamps */
 655         intel_de_rmw(i915, regs.aud_config,
 656                      AUD_CONFIG_N_VALUE_INDEX |
 657                      AUD_CONFIG_N_PROG_ENABLE |
 658                      AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK,
 659                      (intel_crtc_has_dp_encoder(crtc_state) ?
 660                       AUD_CONFIG_N_VALUE_INDEX :
 661                       audio_config_hdmi_pixel_clock(crtc_state)));
 662
 663         mutex_unlock(&i915->display.audio.mutex);
 664 }
 665
 666 void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state)
 667 {
 668         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 669         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 670         enum transcoder trans = crtc_state->cpu_transcoder;
 671
 672         if (HAS_DP20(i915))
 673                 intel_de_rmw(i915, AUD_DP_2DOT0_CTRL(trans), AUD_ENABLE_SDP_SPLIT,
 674                              crtc_state->sdp_split_enable ? AUD_ENABLE_SDP_SPLIT : 0);
 675 }
 676
 677 bool intel_audio_compute_config(struct intel_encoder *encoder,
 678                                 struct intel_crtc_state *crtc_state,
 679                                 struct drm_connector_state *conn_state)
 680 {
 681         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 682         struct drm_connector *connector = conn_state->connector;
 683         const struct drm_display_mode *adjusted_mode =
 684                 &crtc_state->hw.adjusted_mode;
 685
 686         if (!connector->eld[0]) {
 687                 drm_dbg_kms(&i915->drm,
 688                             "Bogus ELD on [CONNECTOR:%d:%s]\n",
 689                             connector->base.id, connector->name);
 690                 return false;
 691         }
 692
 693         BUILD_BUG_ON(sizeof(crtc_state->eld) != sizeof(connector->eld));
 694         memcpy(crtc_state->eld, connector->eld, sizeof(crtc_state->eld));
 695
 696         crtc_state->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
 697
 698         return true;
 699 }
 700
 701 /**
 702  * intel_audio_codec_enable - Enable the audio codec for HD audio
 703  * @encoder: encoder on which to enable audio
 704  * @crtc_state: pointer to the current crtc state.
 705  * @conn_state: pointer to the current connector state.
 706  *
 707  * The enable sequences may only be performed after enabling the transcoder and
 708  * port, and after completed link training.
 709  */
 710 void intel_audio_codec_enable(struct intel_encoder *encoder,
 711                               const struct intel_crtc_state *crtc_state,
 712                               const struct drm_connector_state *conn_state)
 713 {
 714         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 715         struct i915_audio_component *acomp = i915->display.audio.component;
 716         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 717         struct intel_connector *connector = to_intel_connector(conn_state->connector);
 718         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 719         struct intel_audio_state *audio_state;
 720         enum port port = encoder->port;
 721
 722         if (!crtc_state->has_audio)
 723                 return;
 724
 725         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Enable audio codec on [CRTC:%d:%s], %u bytes ELD\n",
 726                     connector->base.base.id, connector->base.name,
 727                     encoder->base.base.id, encoder->base.name,
 728                     crtc->base.base.id, crtc->base.name,
 729                     drm_eld_size(crtc_state->eld));
 730
 731         if (i915->display.funcs.audio)
 732                 i915->display.funcs.audio->audio_codec_enable(encoder,
 733                                                               crtc_state,
 734                                                               conn_state);
 735
 736         mutex_lock(&i915->display.audio.mutex);
 737
 738         audio_state = &i915->display.audio.state[cpu_transcoder];
 739
 740         audio_state->encoder = encoder;
 741         BUILD_BUG_ON(sizeof(audio_state->eld) != sizeof(crtc_state->eld));
 742         memcpy(audio_state->eld, crtc_state->eld, sizeof(audio_state->eld));
 743
 744         mutex_unlock(&i915->display.audio.mutex);
 745
 746         if (acomp && acomp->base.audio_ops &&
 747             acomp->base.audio_ops->pin_eld_notify) {
 748                 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */
 749                 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
 750                         cpu_transcoder = -1;
 751                 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
 752                                                       (int)port, (int)cpu_transcoder);
 753         }
 754
 755         intel_lpe_audio_notify(i915, cpu_transcoder, port, crtc_state->eld,
 756                                crtc_state->port_clock,
 757                                intel_crtc_has_dp_encoder(crtc_state));
 758 }
 759
 760 /**
 761  * intel_audio_codec_disable - Disable the audio codec for HD audio
 762  * @encoder: encoder on which to disable audio
 763  * @old_crtc_state: pointer to the old crtc state.
 764  * @old_conn_state: pointer to the old connector state.
 765  *
 766  * The disable sequences must be performed before disabling the transcoder or
 767  * port.
 768  */
 769 void intel_audio_codec_disable(struct intel_encoder *encoder,
 770                                const struct intel_crtc_state *old_crtc_state,
 771                                const struct drm_connector_state *old_conn_state)
 772 {
 773         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 774         struct i915_audio_component *acomp = i915->display.audio.component;
 775         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 776         struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
 777         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 778         struct intel_audio_state *audio_state;
 779         enum port port = encoder->port;
 780
 781         if (!old_crtc_state->has_audio)
 782                 return;
 783
 784         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Disable audio codec on [CRTC:%d:%s]\n",
 785                     connector->base.base.id, connector->base.name,
 786                     encoder->base.base.id, encoder->base.name,
 787                     crtc->base.base.id, crtc->base.name);
 788
 789         if (i915->display.funcs.audio)
 790                 i915->display.funcs.audio->audio_codec_disable(encoder,
 791                                                                old_crtc_state,
 792                                                                old_conn_state);
 793
 794         mutex_lock(&i915->display.audio.mutex);
 795
 796         audio_state = &i915->display.audio.state[cpu_transcoder];
 797
 798         audio_state->encoder = NULL;
 799         memset(audio_state->eld, 0, sizeof(audio_state->eld));
 800
 801         mutex_unlock(&i915->display.audio.mutex);
 802
 803         if (acomp && acomp->base.audio_ops &&
 804             acomp->base.audio_ops->pin_eld_notify) {
 805                 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */
 806                 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
 807                         cpu_transcoder = -1;
 808                 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
 809                                                       (int)port, (int)cpu_transcoder);
 810         }
 811
 812         intel_lpe_audio_notify(i915, cpu_transcoder, port, NULL, 0, false);
 813 }
 814
 815 static void intel_acomp_get_config(struct intel_encoder *encoder,
 816                                    struct intel_crtc_state *crtc_state)
 817 {
 818         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 819         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 820         struct intel_audio_state *audio_state;
 821
 822         mutex_lock(&i915->display.audio.mutex);
 823
 824         audio_state = &i915->display.audio.state[cpu_transcoder];
 825
 826         if (audio_state->encoder)
 827                 memcpy(crtc_state->eld, audio_state->eld, sizeof(audio_state->eld));
 828
 829         mutex_unlock(&i915->display.audio.mutex);
 830 }
 831
 832 void intel_audio_codec_get_config(struct intel_encoder *encoder,
 833                                   struct intel_crtc_state *crtc_state)
 834 {
 835         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 836
 837         if (!crtc_state->has_audio)
 838                 return;
 839
 840         if (i915->display.funcs.audio)
 841                 i915->display.funcs.audio->audio_codec_get_config(encoder, crtc_state);
 842 }
 843
 844 static const struct intel_audio_funcs g4x_audio_funcs = {
 845         .audio_codec_enable = g4x_audio_codec_enable,
 846         .audio_codec_disable = g4x_audio_codec_disable,
 847         .audio_codec_get_config = g4x_audio_codec_get_config,
 848 };
 849
 850 static const struct intel_audio_funcs ibx_audio_funcs = {
 851         .audio_codec_enable = ibx_audio_codec_enable,
 852         .audio_codec_disable = ibx_audio_codec_disable,
 853         .audio_codec_get_config = intel_acomp_get_config,
 854 };
 855
 856 static const struct intel_audio_funcs hsw_audio_funcs = {
 857         .audio_codec_enable = hsw_audio_codec_enable,
 858         .audio_codec_disable = hsw_audio_codec_disable,
 859         .audio_codec_get_config = intel_acomp_get_config,
 860 };
 861
 862 /**
 863  * intel_audio_hooks_init - Set up chip specific audio hooks
 864  * @i915: device private
 865  */
 866 void intel_audio_hooks_init(struct drm_i915_private *i915)
 867 {
 868         if (IS_G4X(i915))
 869                 i915->display.funcs.audio = &g4x_audio_funcs;
 870         else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915) ||
 871                  HAS_PCH_CPT(i915) || HAS_PCH_IBX(i915))
 872                 i915->display.funcs.audio = &ibx_audio_funcs;
 873         else if (IS_HASWELL(i915) || DISPLAY_VER(i915) >= 8)
 874                 i915->display.funcs.audio = &hsw_audio_funcs;
 875 }
 876
 877 struct aud_ts_cdclk_m_n {
 878         u8 m;
 879         u16 n;
 880 };
 881
 882 void intel_audio_cdclk_change_pre(struct drm_i915_private *i915)
 883 {
 884         if (DISPLAY_VER(i915) >= 13)
 885                 intel_de_rmw(i915, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0);
 886 }
 887
 888 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts)
 889 {
 890         aud_ts->m = 60;
 891         aud_ts->n = cdclk * aud_ts->m / 24000;
 892 }
 893
 894 void intel_audio_cdclk_change_post(struct drm_i915_private *i915)
 895 {
 896         struct aud_ts_cdclk_m_n aud_ts;
 897
 898         if (DISPLAY_VER(i915) >= 13) {
 899                 get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts);
 900
 901                 intel_de_write(i915, AUD_TS_CDCLK_N, aud_ts.n);
 902                 intel_de_write(i915, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN);
 903                 drm_dbg_kms(&i915->drm, "aud_ts_cdclk set to M=%u, N=%u\n", aud_ts.m, aud_ts.n);
 904         }
 905 }
 906
 907 static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state,
 908                                         struct intel_crtc *crtc,
 909                                         bool enable)
 910 {
 911         struct intel_cdclk_state *cdclk_state;
 912         int ret;
 913
 914         /* need to hold at least one crtc lock for the global state */
 915         ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx);
 916         if (ret)
 917                 return ret;
 918
 919         cdclk_state = intel_atomic_get_cdclk_state(state);
 920         if (IS_ERR(cdclk_state))
 921                 return PTR_ERR(cdclk_state);
 922
 923         cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0;
 924
 925         return drm_atomic_commit(&state->base);
 926 }
 927
 928 static void glk_force_audio_cdclk(struct drm_i915_private *i915,
 929                                   bool enable)
 930 {
 931         struct drm_modeset_acquire_ctx ctx;
 932         struct drm_atomic_state *state;
 933         struct intel_crtc *crtc;
 934         int ret;
 935
 936         crtc = intel_first_crtc(i915);
 937         if (!crtc)
 938                 return;
 939
 940         drm_modeset_acquire_init(&ctx, 0);
 941         state = drm_atomic_state_alloc(&i915->drm);
 942         if (drm_WARN_ON(&i915->drm, !state))
 943                 return;
 944
 945         state->acquire_ctx = &ctx;
 946         to_intel_atomic_state(state)->internal = true;
 947
 948 retry:
 949         ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc,
 950                                            enable);
 951         if (ret == -EDEADLK) {
 952                 drm_atomic_state_clear(state);
 953                 drm_modeset_backoff(&ctx);
 954                 goto retry;
 955         }
 956
 957         drm_WARN_ON(&i915->drm, ret);
 958
 959         drm_atomic_state_put(state);
 960
 961         drm_modeset_drop_locks(&ctx);
 962         drm_modeset_acquire_fini(&ctx);
 963 }
 964
 965 static unsigned long i915_audio_component_get_power(struct device *kdev)
 966 {
 967         struct drm_i915_private *i915 = kdev_to_i915(kdev);
 968         intel_wakeref_t ret;
 969
 970         /* Catch potential impedance mismatches before they occur! */
 971         BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long));
 972
 973         ret = intel_display_power_get(i915, POWER_DOMAIN_AUDIO_PLAYBACK);
 974
 975         if (i915->display.audio.power_refcount++ == 0) {
 976                 if (DISPLAY_VER(i915) >= 9) {
 977                         intel_de_write(i915, AUD_FREQ_CNTRL,
 978                                        i915->display.audio.freq_cntrl);
 979                         drm_dbg_kms(&i915->drm,
 980                                     "restored AUD_FREQ_CNTRL to 0x%x\n",
 981                                     i915->display.audio.freq_cntrl);
 982                 }
 983
 984                 /* Force CDCLK to 2*BCLK as long as we need audio powered. */
 985                 if (IS_GEMINILAKE(i915))
 986                         glk_force_audio_cdclk(i915, true);
 987
 988                 if (DISPLAY_VER(i915) >= 10)
 989                         intel_de_rmw(i915, AUD_PIN_BUF_CTL,
 990                                      0, AUD_PIN_BUF_ENABLE);
 991         }
 992
 993         return ret;
 994 }
 995
 996 static void i915_audio_component_put_power(struct device *kdev,
 997                                            unsigned long cookie)
 998 {
 999         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1000
1001         /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
1002         if (--i915->display.audio.power_refcount == 0)
1003                 if (IS_GEMINILAKE(i915))
1004                         glk_force_audio_cdclk(i915, false);
1005
1006         intel_display_power_put(i915, POWER_DOMAIN_AUDIO_PLAYBACK, cookie);
1007 }
1008
1009 static void i915_audio_component_codec_wake_override(struct device *kdev,
1010                                                      bool enable)
1011 {
1012         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1013         unsigned long cookie;
1014
1015         if (DISPLAY_VER(i915) < 9)
1016                 return;
1017
1018         cookie = i915_audio_component_get_power(kdev);
1019
1020         /*
1021          * Enable/disable generating the codec wake signal, overriding the
1022          * internal logic to generate the codec wake to controller.
1023          */
1024         intel_de_rmw(i915, HSW_AUD_CHICKENBIT,
1025                      SKL_AUD_CODEC_WAKE_SIGNAL, 0);
1026         usleep_range(1000, 1500);
1027
1028         if (enable) {
1029                 intel_de_rmw(i915, HSW_AUD_CHICKENBIT,
1030                              0, SKL_AUD_CODEC_WAKE_SIGNAL);
1031                 usleep_range(1000, 1500);
1032         }
1033
1034         i915_audio_component_put_power(kdev, cookie);
1035 }
1036
1037 /* Get CDCLK in kHz  */
1038 static int i915_audio_component_get_cdclk_freq(struct device *kdev)
1039 {
1040         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1041
1042         if (drm_WARN_ON_ONCE(&i915->drm, !HAS_DDI(i915)))
1043                 return -ENODEV;
1044
1045         return i915->display.cdclk.hw.cdclk;
1046 }
1047
1048 /*
1049  * get the intel audio state according to the parameter port and cpu_transcoder
1050  * MST & (cpu_transcoder >= 0): return the audio.state[cpu_transcoder].encoder],
1051  *   when port is matched
1052  * MST & (cpu_transcoder < 0): this is invalid
1053  * Non-MST & (cpu_transcoder >= 0): only cpu_transcoder = 0 (the first device entry)
1054  *   will get the right intel_encoder with port matched
1055  * Non-MST & (cpu_transcoder < 0): get the right intel_encoder with port matched
1056  */
1057 static struct intel_audio_state *find_audio_state(struct drm_i915_private *i915,
1058                                                   int port, int cpu_transcoder)
1059 {
1060         /* MST */
1061         if (cpu_transcoder >= 0) {
1062                 struct intel_audio_state *audio_state;
1063                 struct intel_encoder *encoder;
1064
1065                 if (drm_WARN_ON(&i915->drm,
1066                                 cpu_transcoder >= ARRAY_SIZE(i915->display.audio.state)))
1067                         return NULL;
1068
1069                 audio_state = &i915->display.audio.state[cpu_transcoder];
1070                 encoder = audio_state->encoder;
1071
1072                 if (encoder && encoder->port == port &&
1073                     encoder->type == INTEL_OUTPUT_DP_MST)
1074                         return audio_state;
1075         }
1076
1077         /* Non-MST */
1078         if (cpu_transcoder > 0)
1079                 return NULL;
1080
1081         for_each_cpu_transcoder(i915, cpu_transcoder) {
1082                 struct intel_audio_state *audio_state;
1083                 struct intel_encoder *encoder;
1084
1085                 audio_state = &i915->display.audio.state[cpu_transcoder];
1086                 encoder = audio_state->encoder;
1087
1088                 if (encoder && encoder->port == port &&
1089                     encoder->type != INTEL_OUTPUT_DP_MST)
1090                         return audio_state;
1091         }
1092
1093         return NULL;
1094 }
1095
1096 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
1097                                                 int cpu_transcoder, int rate)
1098 {
1099         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1100         struct i915_audio_component *acomp = i915->display.audio.component;
1101         const struct intel_audio_state *audio_state;
1102         struct intel_encoder *encoder;
1103         struct intel_crtc *crtc;
1104         unsigned long cookie;
1105         int err = 0;
1106
1107         if (!HAS_DDI(i915))
1108                 return 0;
1109
1110         cookie = i915_audio_component_get_power(kdev);
1111         mutex_lock(&i915->display.audio.mutex);
1112
1113         audio_state = find_audio_state(i915, port, cpu_transcoder);
1114         if (!audio_state) {
1115                 drm_dbg_kms(&i915->drm, "Not valid for port %c\n", port_name(port));
1116                 err = -ENODEV;
1117                 goto unlock;
1118         }
1119
1120         encoder = audio_state->encoder;
1121
1122         /* FIXME stop using the legacy crtc pointer */
1123         crtc = to_intel_crtc(encoder->base.crtc);
1124
1125         /* port must be valid now, otherwise the cpu_transcoder will be invalid */
1126         acomp->aud_sample_rate[port] = rate;
1127
1128         /* FIXME get rid of the crtc->config stuff */
1129         hsw_audio_config_update(encoder, crtc->config);
1130
1131  unlock:
1132         mutex_unlock(&i915->display.audio.mutex);
1133         i915_audio_component_put_power(kdev, cookie);
1134         return err;
1135 }
1136
1137 static int i915_audio_component_get_eld(struct device *kdev, int port,
1138                                         int cpu_transcoder, bool *enabled,
1139                                         unsigned char *buf, int max_bytes)
1140 {
1141         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1142         const struct intel_audio_state *audio_state;
1143         int ret = 0;
1144
1145         mutex_lock(&i915->display.audio.mutex);
1146
1147         audio_state = find_audio_state(i915, port, cpu_transcoder);
1148         if (!audio_state) {
1149                 drm_dbg_kms(&i915->drm, "Not valid for port %c\n", port_name(port));
1150                 mutex_unlock(&i915->display.audio.mutex);
1151                 return -EINVAL;
1152         }
1153
1154         *enabled = audio_state->encoder != NULL;
1155         if (*enabled) {
1156                 const u8 *eld = audio_state->eld;
1157
1158                 ret = drm_eld_size(eld);
1159                 memcpy(buf, eld, min(max_bytes, ret));
1160         }
1161
1162         mutex_unlock(&i915->display.audio.mutex);
1163         return ret;
1164 }
1165
1166 static const struct drm_audio_component_ops i915_audio_component_ops = {
1167         .owner          = THIS_MODULE,
1168         .get_power      = i915_audio_component_get_power,
1169         .put_power      = i915_audio_component_put_power,
1170         .codec_wake_override = i915_audio_component_codec_wake_override,
1171         .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
1172         .sync_audio_rate = i915_audio_component_sync_audio_rate,
1173         .get_eld        = i915_audio_component_get_eld,
1174 };
1175
1176 static int i915_audio_component_bind(struct device *i915_kdev,
1177                                      struct device *hda_kdev, void *data)
1178 {
1179         struct i915_audio_component *acomp = data;
1180         struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
1181         int i;
1182
1183         if (drm_WARN_ON(&i915->drm, acomp->base.ops || acomp->base.dev))
1184                 return -EEXIST;
1185
1186         if (drm_WARN_ON(&i915->drm,
1187                         !device_link_add(hda_kdev, i915_kdev,
1188                                          DL_FLAG_STATELESS)))
1189                 return -ENOMEM;
1190
1191         drm_modeset_lock_all(&i915->drm);
1192         acomp->base.ops = &i915_audio_component_ops;
1193         acomp->base.dev = i915_kdev;
1194         BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
1195         for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
1196                 acomp->aud_sample_rate[i] = 0;
1197         i915->display.audio.component = acomp;
1198         drm_modeset_unlock_all(&i915->drm);
1199
1200         return 0;
1201 }
1202
1203 static void i915_audio_component_unbind(struct device *i915_kdev,
1204                                         struct device *hda_kdev, void *data)
1205 {
1206         struct i915_audio_component *acomp = data;
1207         struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
1208
1209         drm_modeset_lock_all(&i915->drm);
1210         acomp->base.ops = NULL;
1211         acomp->base.dev = NULL;
1212         i915->display.audio.component = NULL;
1213         drm_modeset_unlock_all(&i915->drm);
1214
1215         device_link_remove(hda_kdev, i915_kdev);
1216
1217         if (i915->display.audio.power_refcount)
1218                 drm_err(&i915->drm, "audio power refcount %d after unbind\n",
1219                         i915->display.audio.power_refcount);
1220 }
1221
1222 static const struct component_ops i915_audio_component_bind_ops = {
1223         .bind   = i915_audio_component_bind,
1224         .unbind = i915_audio_component_unbind,
1225 };
1226
1227 #define AUD_FREQ_TMODE_SHIFT    14
1228 #define AUD_FREQ_4T             0
1229 #define AUD_FREQ_8T             (2 << AUD_FREQ_TMODE_SHIFT)
1230 #define AUD_FREQ_PULLCLKS(x)    (((x) & 0x3) << 11)
1231 #define AUD_FREQ_BCLK_96M       BIT(4)
1232
1233 #define AUD_FREQ_GEN12          (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(0) | AUD_FREQ_BCLK_96M)
1234 #define AUD_FREQ_TGL_BROKEN     (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(2) | AUD_FREQ_BCLK_96M)
1235
1236 /**
1237  * i915_audio_component_init - initialize and register the audio component
1238  * @i915: i915 device instance
1239  *
1240  * This will register with the component framework a child component which
1241  * will bind dynamically to the snd_hda_intel driver's corresponding master
1242  * component when the latter is registered. During binding the child
1243  * initializes an instance of struct i915_audio_component which it receives
1244  * from the master. The master can then start to use the interface defined by
1245  * this struct. Each side can break the binding at any point by deregistering
1246  * its own component after which each side's component unbind callback is
1247  * called.
1248  *
1249  * We ignore any error during registration and continue with reduced
1250  * functionality (i.e. without HDMI audio).
1251  */
1252 static void i915_audio_component_init(struct drm_i915_private *i915)
1253 {
1254         u32 aud_freq, aud_freq_init;
1255         int ret;
1256
1257         ret = component_add_typed(i915->drm.dev,
1258                                   &i915_audio_component_bind_ops,
1259                                   I915_COMPONENT_AUDIO);
1260         if (ret < 0) {
1261                 drm_err(&i915->drm,
1262                         "failed to add audio component (%d)\n", ret);
1263                 /* continue with reduced functionality */
1264                 return;
1265         }
1266
1267         if (DISPLAY_VER(i915) >= 9) {
1268                 aud_freq_init = intel_de_read(i915, AUD_FREQ_CNTRL);
1269
1270                 if (DISPLAY_VER(i915) >= 12)
1271                         aud_freq = AUD_FREQ_GEN12;
1272                 else
1273                         aud_freq = aud_freq_init;
1274
1275                 /* use BIOS provided value for TGL and RKL unless it is a known bad value */
1276                 if ((IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) &&
1277                     aud_freq_init != AUD_FREQ_TGL_BROKEN)
1278                         aud_freq = aud_freq_init;
1279
1280                 drm_dbg_kms(&i915->drm, "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n",
1281                             aud_freq, aud_freq_init);
1282
1283                 i915->display.audio.freq_cntrl = aud_freq;
1284         }
1285
1286         /* init with current cdclk */
1287         intel_audio_cdclk_change_post(i915);
1288
1289         i915->display.audio.component_registered = true;
1290 }
1291
1292 /**
1293  * i915_audio_component_cleanup - deregister the audio component
1294  * @i915: i915 device instance
1295  *
1296  * Deregisters the audio component, breaking any existing binding to the
1297  * corresponding snd_hda_intel driver's master component.
1298  */
1299 static void i915_audio_component_cleanup(struct drm_i915_private *i915)
1300 {
1301         if (!i915->display.audio.component_registered)
1302                 return;
1303
1304         component_del(i915->drm.dev, &i915_audio_component_bind_ops);
1305         i915->display.audio.component_registered = false;
1306 }
1307
1308 /**
1309  * intel_audio_init() - Initialize the audio driver either using
1310  * component framework or using lpe audio bridge
1311  * @i915: the i915 drm device private data
1312  *
1313  */
1314 void intel_audio_init(struct drm_i915_private *i915)
1315 {
1316         if (intel_lpe_audio_init(i915) < 0)
1317                 i915_audio_component_init(i915);
1318 }
1319
1320 /**
1321  * intel_audio_deinit() - deinitialize the audio driver
1322  * @i915: the i915 drm device private data
1323  *
1324  */
1325 void intel_audio_deinit(struct drm_i915_private *i915)
1326 {
1327         if (i915->display.audio.lpe.platdev != NULL)
1328                 intel_lpe_audio_teardown(i915);
1329         else
1330                 i915_audio_component_cleanup(i915);
1331 }