1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2019 NVIDIA CORPORATION. All rights reserved.
7 #include <linux/debugfs.h>
8 #include <linux/module.h>
9 #include <linux/mod_devicetable.h>
10 #include <linux/of_platform.h>
11 #include <linux/platform_device.h>
13 #include <soc/tegra/bpmp.h>
16 struct tegra186_emc_dvfs {
17 unsigned long latency;
22 struct tegra_bpmp *bpmp;
26 struct tegra186_emc_dvfs *dvfs;
27 unsigned int num_dvfs;
31 unsigned long min_rate;
32 unsigned long max_rate;
35 struct icc_provider provider;
38 static inline struct tegra186_emc *to_tegra186_emc(struct icc_provider *provider)
40 return container_of(provider, struct tegra186_emc, provider);
46 * The memory controller driver exposes some files in debugfs that can be used
47 * to control the EMC frequency. The top-level directory can be found here:
49 * /sys/kernel/debug/emc
51 * It contains the following files:
53 * - available_rates: This file contains a list of valid, space-separated
56 * - min_rate: Writing a value to this file sets the given frequency as the
57 * floor of the permitted range. If this is higher than the currently
58 * configured EMC frequency, this will cause the frequency to be
59 * increased so that it stays within the valid range.
61 * - max_rate: Similarily to the min_rate file, writing a value to this file
62 * sets the given frequency as the ceiling of the permitted range. If
63 * the value is lower than the currently configured EMC frequency, this
64 * will cause the frequency to be decreased so that it stays within the
68 static bool tegra186_emc_validate_rate(struct tegra186_emc *emc,
73 for (i = 0; i < emc->num_dvfs; i++)
74 if (rate == emc->dvfs[i].rate)
80 static int tegra186_emc_debug_available_rates_show(struct seq_file *s,
83 struct tegra186_emc *emc = s->private;
84 const char *prefix = "";
87 for (i = 0; i < emc->num_dvfs; i++) {
88 seq_printf(s, "%s%lu", prefix, emc->dvfs[i].rate);
96 DEFINE_SHOW_ATTRIBUTE(tegra186_emc_debug_available_rates);
98 static int tegra186_emc_debug_min_rate_get(void *data, u64 *rate)
100 struct tegra186_emc *emc = data;
102 *rate = emc->debugfs.min_rate;
107 static int tegra186_emc_debug_min_rate_set(void *data, u64 rate)
109 struct tegra186_emc *emc = data;
112 if (!tegra186_emc_validate_rate(emc, rate))
115 err = clk_set_min_rate(emc->clk, rate);
119 emc->debugfs.min_rate = rate;
124 DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_min_rate_fops,
125 tegra186_emc_debug_min_rate_get,
126 tegra186_emc_debug_min_rate_set, "%llu\n");
128 static int tegra186_emc_debug_max_rate_get(void *data, u64 *rate)
130 struct tegra186_emc *emc = data;
132 *rate = emc->debugfs.max_rate;
137 static int tegra186_emc_debug_max_rate_set(void *data, u64 rate)
139 struct tegra186_emc *emc = data;
142 if (!tegra186_emc_validate_rate(emc, rate))
145 err = clk_set_max_rate(emc->clk, rate);
149 emc->debugfs.max_rate = rate;
154 DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_max_rate_fops,
155 tegra186_emc_debug_max_rate_get,
156 tegra186_emc_debug_max_rate_set, "%llu\n");
158 static int tegra186_emc_get_emc_dvfs_latency(struct tegra186_emc *emc)
160 struct mrq_emc_dvfs_latency_response response;
161 struct tegra_bpmp_message msg;
165 memset(&msg, 0, sizeof(msg));
166 msg.mrq = MRQ_EMC_DVFS_LATENCY;
169 msg.rx.data = &response;
170 msg.rx.size = sizeof(response);
172 err = tegra_bpmp_transfer(emc->bpmp, &msg);
174 dev_err(emc->dev, "failed to EMC DVFS pairs: %d\n", err);
177 if (msg.rx.ret < 0) {
178 dev_err(emc->dev, "EMC DVFS MRQ failed: %d (BPMP error code)\n", msg.rx.ret);
182 emc->debugfs.min_rate = ULONG_MAX;
183 emc->debugfs.max_rate = 0;
185 emc->num_dvfs = response.num_pairs;
187 emc->dvfs = devm_kmalloc_array(emc->dev, emc->num_dvfs, sizeof(*emc->dvfs), GFP_KERNEL);
191 dev_dbg(emc->dev, "%u DVFS pairs:\n", emc->num_dvfs);
193 for (i = 0; i < emc->num_dvfs; i++) {
194 emc->dvfs[i].rate = response.pairs[i].freq * 1000;
195 emc->dvfs[i].latency = response.pairs[i].latency;
197 if (emc->dvfs[i].rate < emc->debugfs.min_rate)
198 emc->debugfs.min_rate = emc->dvfs[i].rate;
200 if (emc->dvfs[i].rate > emc->debugfs.max_rate)
201 emc->debugfs.max_rate = emc->dvfs[i].rate;
203 dev_dbg(emc->dev, " %2u: %lu Hz -> %lu us\n", i,
204 emc->dvfs[i].rate, emc->dvfs[i].latency);
207 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, emc->debugfs.max_rate);
209 dev_err(emc->dev, "failed to set rate range [%lu-%lu] for %pC\n",
210 emc->debugfs.min_rate, emc->debugfs.max_rate, emc->clk);
214 emc->debugfs.root = debugfs_create_dir("emc", NULL);
215 debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc,
216 &tegra186_emc_debug_available_rates_fops);
217 debugfs_create_file("min_rate", 0644, emc->debugfs.root, emc,
218 &tegra186_emc_debug_min_rate_fops);
219 debugfs_create_file("max_rate", 0644, emc->debugfs.root, emc,
220 &tegra186_emc_debug_max_rate_fops);
226 * tegra_emc_icc_set_bw() - Set BW api for EMC provider
227 * @src: ICC node for External Memory Controller (EMC)
228 * @dst: ICC node for External Memory (DRAM)
230 * Do nothing here as info to BPMP-FW is now passed in the BW set function
231 * of the MC driver. BPMP-FW sets the final Freq based on the passed values.
233 static int tegra_emc_icc_set_bw(struct icc_node *src, struct icc_node *dst)
238 static struct icc_node *
239 tegra_emc_of_icc_xlate(struct of_phandle_args *spec, void *data)
241 struct icc_provider *provider = data;
242 struct icc_node *node;
244 /* External Memory is the only possible ICC route */
245 list_for_each_entry(node, &provider->nodes, node_list) {
246 if (node->id != TEGRA_ICC_EMEM)
252 return ERR_PTR(-EPROBE_DEFER);
255 static int tegra_emc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *peak)
263 static int tegra_emc_interconnect_init(struct tegra186_emc *emc)
265 struct tegra_mc *mc = dev_get_drvdata(emc->dev->parent);
266 const struct tegra_mc_soc *soc = mc->soc;
267 struct icc_node *node;
270 emc->provider.dev = emc->dev;
271 emc->provider.set = tegra_emc_icc_set_bw;
272 emc->provider.data = &emc->provider;
273 emc->provider.aggregate = soc->icc_ops->aggregate;
274 emc->provider.xlate = tegra_emc_of_icc_xlate;
275 emc->provider.get_bw = tegra_emc_icc_get_init_bw;
277 icc_provider_init(&emc->provider);
279 /* create External Memory Controller node */
280 node = icc_node_create(TEGRA_ICC_EMC);
286 node->name = "External Memory Controller";
287 icc_node_add(node, &emc->provider);
289 /* link External Memory Controller to External Memory (DRAM) */
290 err = icc_link_create(node, TEGRA_ICC_EMEM);
294 /* create External Memory node */
295 node = icc_node_create(TEGRA_ICC_EMEM);
301 node->name = "External Memory (DRAM)";
302 icc_node_add(node, &emc->provider);
304 err = icc_provider_register(&emc->provider);
311 icc_nodes_remove(&emc->provider);
313 dev_err(emc->dev, "failed to initialize ICC: %d\n", err);
318 static int tegra186_emc_probe(struct platform_device *pdev)
320 struct tegra_mc *mc = dev_get_drvdata(pdev->dev.parent);
321 struct tegra186_emc *emc;
324 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
328 emc->bpmp = tegra_bpmp_get(&pdev->dev);
329 if (IS_ERR(emc->bpmp))
330 return dev_err_probe(&pdev->dev, PTR_ERR(emc->bpmp), "failed to get BPMP\n");
332 emc->clk = devm_clk_get(&pdev->dev, "emc");
333 if (IS_ERR(emc->clk)) {
334 err = PTR_ERR(emc->clk);
335 dev_err(&pdev->dev, "failed to get EMC clock: %d\n", err);
339 platform_set_drvdata(pdev, emc);
340 emc->dev = &pdev->dev;
342 if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_EMC_DVFS_LATENCY)) {
343 err = tegra186_emc_get_emc_dvfs_latency(emc);
348 if (mc && mc->soc->icc_ops) {
349 if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_BWMGR_INT)) {
350 mc->bwmgr_mrq_supported = true;
353 * MC driver probe can't get BPMP reference as it gets probed
354 * earlier than BPMP. So, save the BPMP ref got from the EMC
355 * DT node in the mc->bpmp and use it in MC's icc_set hook.
357 mc->bpmp = emc->bpmp;
362 * Initialize the ICC even if BPMP-FW doesn't support 'MRQ_BWMGR_INT'.
363 * Use the flag 'mc->bwmgr_mrq_supported' within MC driver and return
364 * EINVAL instead of passing the request to BPMP-FW later when the BW
365 * request is made by client with 'icc_set_bw()' call.
367 err = tegra_emc_interconnect_init(emc);
377 tegra_bpmp_put(emc->bpmp);
381 static void tegra186_emc_remove(struct platform_device *pdev)
383 struct tegra_mc *mc = dev_get_drvdata(pdev->dev.parent);
384 struct tegra186_emc *emc = platform_get_drvdata(pdev);
386 debugfs_remove_recursive(emc->debugfs.root);
389 tegra_bpmp_put(emc->bpmp);
392 static const struct of_device_id tegra186_emc_of_match[] = {
393 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
394 { .compatible = "nvidia,tegra186-emc" },
396 #if defined(CONFIG_ARCH_TEGRA_194_SOC)
397 { .compatible = "nvidia,tegra194-emc" },
399 #if defined(CONFIG_ARCH_TEGRA_234_SOC)
400 { .compatible = "nvidia,tegra234-emc" },
404 MODULE_DEVICE_TABLE(of, tegra186_emc_of_match);
406 static struct platform_driver tegra186_emc_driver = {
408 .name = "tegra186-emc",
409 .of_match_table = tegra186_emc_of_match,
410 .suppress_bind_attrs = true,
411 .sync_state = icc_sync_state,
413 .probe = tegra186_emc_probe,
414 .remove_new = tegra186_emc_remove,
416 module_platform_driver(tegra186_emc_driver);
418 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
419 MODULE_DESCRIPTION("NVIDIA Tegra186 External Memory Controller driver");