1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
9 #define MT7530_NUM_PORTS 7
10 #define MT7530_NUM_PHYS 5
11 #define MT7530_NUM_FDB_RECORDS 2048
12 #define MT7530_ALL_MEMBERS 0xff
15 #define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN)
24 #define NUM_TRGMII_CTRL 5
26 #define TRGMII_BASE(x) (0x10000 + (x))
28 /* Registers to ethsys access */
29 #define ETHSYS_CLKCFG0 0x2c
30 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
32 #define SYSC_REG_RSTCTRL 0x34
33 #define RESET_MCM BIT(2)
35 /* Registers to mac forward control for unknown frames */
36 #define MT7530_MFC 0x10
37 #define BC_FFP(x) (((x) & 0xff) << 24)
38 #define BC_FFP_MASK BC_FFP(~0)
39 #define UNM_FFP(x) (((x) & 0xff) << 16)
40 #define UNM_FFP_MASK UNM_FFP(~0)
41 #define UNU_FFP(x) (((x) & 0xff) << 8)
42 #define UNU_FFP_MASK UNU_FFP(~0)
44 #define CPU_PORT_MASK GENMASK(6, 4)
45 #define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x)
46 #define MIRROR_EN BIT(3)
47 #define MIRROR_PORT(x) ((x) & 0x7)
48 #define MIRROR_MASK 0x7
50 /* Registers for CPU forward control */
51 #define MT7531_CFC 0x4
52 #define MT7531_MIRROR_EN BIT(19)
53 #define MT7531_MIRROR_MASK (MIRROR_MASK << 16)
54 #define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK)
55 #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16)
56 #define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
57 #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x)
59 #define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
60 MT7531_CFC : MT7530_MFC)
61 #define MT753X_MIRROR_EN(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
62 MT7531_MIRROR_EN : MIRROR_EN)
63 #define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
64 MT7531_MIRROR_MASK : MIRROR_MASK)
66 /* Registers for BPDU and PAE frame control*/
67 #define MT753X_BPC 0x24
68 #define MT753X_PAE_EG_TAG_MASK GENMASK(24, 22)
69 #define MT753X_PAE_EG_TAG(x) FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x)
70 #define MT753X_PAE_PORT_FW_MASK GENMASK(18, 16)
71 #define MT753X_PAE_PORT_FW(x) FIELD_PREP(MT753X_PAE_PORT_FW_MASK, x)
72 #define MT753X_BPDU_EG_TAG_MASK GENMASK(8, 6)
73 #define MT753X_BPDU_EG_TAG(x) FIELD_PREP(MT753X_BPDU_EG_TAG_MASK, x)
74 #define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
76 /* Register for :01 and :02 MAC DA frame control */
77 #define MT753X_RGAC1 0x28
78 #define MT753X_R02_EG_TAG_MASK GENMASK(24, 22)
79 #define MT753X_R02_EG_TAG(x) FIELD_PREP(MT753X_R02_EG_TAG_MASK, x)
80 #define MT753X_R02_PORT_FW_MASK GENMASK(18, 16)
81 #define MT753X_R02_PORT_FW(x) FIELD_PREP(MT753X_R02_PORT_FW_MASK, x)
82 #define MT753X_R01_EG_TAG_MASK GENMASK(8, 6)
83 #define MT753X_R01_EG_TAG(x) FIELD_PREP(MT753X_R01_EG_TAG_MASK, x)
84 #define MT753X_R01_PORT_FW_MASK GENMASK(2, 0)
86 /* Register for :03 and :0E MAC DA frame control */
87 #define MT753X_RGAC2 0x2c
88 #define MT753X_R0E_EG_TAG_MASK GENMASK(24, 22)
89 #define MT753X_R0E_EG_TAG(x) FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x)
90 #define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16)
91 #define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x)
92 #define MT753X_R03_EG_TAG_MASK GENMASK(8, 6)
93 #define MT753X_R03_EG_TAG(x) FIELD_PREP(MT753X_R03_EG_TAG_MASK, x)
94 #define MT753X_R03_PORT_FW_MASK GENMASK(2, 0)
96 enum mt753x_bpdu_port_fw {
97 MT753X_BPDU_FOLLOW_MFC,
98 MT753X_BPDU_CPU_EXCLUDE = 4,
99 MT753X_BPDU_CPU_INCLUDE = 5,
100 MT753X_BPDU_CPU_ONLY = 6,
101 MT753X_BPDU_DROP = 7,
104 /* Registers for address table access */
105 #define MT7530_ATA1 0x74
108 #define MT7530_ATA2 0x78
109 #define ATA2_IVL BIT(15)
110 #define ATA2_FID(x) (((x) & 0x7) << 12)
112 /* Register for address table write data */
113 #define MT7530_ATWD 0x7c
115 /* Register for address table control */
116 #define MT7530_ATC 0x80
117 #define ATC_HASH (((x) & 0xfff) << 16)
118 #define ATC_BUSY BIT(15)
119 #define ATC_SRCH_END BIT(14)
120 #define ATC_SRCH_HIT BIT(13)
121 #define ATC_INVALID BIT(12)
122 #define ATC_MAT(x) (((x) & 0xf) << 8)
123 #define ATC_MAT_MACTAB ATC_MAT(0)
125 enum mt7530_fdb_cmd {
127 MT7530_FDB_WRITE = 1,
128 MT7530_FDB_FLUSH = 2,
129 MT7530_FDB_START = 4,
133 /* Registers for table search read address */
134 #define MT7530_TSRA1 0x84
135 #define MAC_BYTE_0 24
136 #define MAC_BYTE_1 16
139 #define MAC_BYTE_MASK 0xff
141 #define MT7530_TSRA2 0x88
142 #define MAC_BYTE_4 24
143 #define MAC_BYTE_5 16
145 #define CVID_MASK 0xfff
147 #define MT7530_ATRD 0x8C
149 #define AGE_TIMER_MASK 0xff
151 #define PORT_MAP_MASK 0xff
153 #define ENT_STATUS_MASK 0x3
155 /* Register for vlan table control */
156 #define MT7530_VTCR 0x90
157 #define VTCR_BUSY BIT(31)
158 #define VTCR_INVALID BIT(16)
159 #define VTCR_FUNC(x) (((x) & 0xf) << 12)
160 #define VTCR_VID ((x) & 0xfff)
162 enum mt7530_vlan_cmd {
163 /* Read/Write the specified VID entry from VAWD register based
166 MT7530_VTCR_RD_VID = 0,
167 MT7530_VTCR_WR_VID = 1,
170 /* Register for setup vlan and acl write data */
171 #define MT7530_VAWD1 0x94
172 #define PORT_STAG BIT(31)
173 /* Independent VLAN Learning */
174 #define IVL_MAC BIT(30)
175 /* Egress Tag Consistent */
176 #define EG_CON BIT(29)
177 /* Per VLAN Egress Tag Control */
178 #define VTAG_EN BIT(28)
179 /* VLAN Member Control */
180 #define PORT_MEM(x) (((x) & 0xff) << 16)
182 #define FID(x) (((x) & 0x7) << 1)
183 /* VLAN Entry Valid */
184 #define VLAN_VALID BIT(0)
185 #define PORT_MEM_SHFT 16
186 #define PORT_MEM_MASK 0xff
193 #define MT7530_VAWD2 0x98
194 /* Egress Tag Control */
195 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
196 #define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3)
198 enum mt7530_vlan_egress_attr {
199 MT7530_VLAN_EGRESS_UNTAG = 0,
200 MT7530_VLAN_EGRESS_TAG = 2,
201 MT7530_VLAN_EGRESS_STACK = 3,
204 /* Register for address age control */
205 #define MT7530_AAC 0xa0
207 #define AGE_DIS BIT(20)
209 #define AGE_CNT_MASK GENMASK(19, 12)
210 #define AGE_CNT_MAX 0xff
211 #define AGE_CNT(x) (AGE_CNT_MASK & ((x) << 12))
213 #define AGE_UNIT_MASK GENMASK(11, 0)
214 #define AGE_UNIT_MAX 0xfff
215 #define AGE_UNIT(x) (AGE_UNIT_MASK & (x))
217 /* Register for port STP state control */
218 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100))
219 #define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2))
220 #define FID_PST_MASK(fid) FID_PST(fid, 0x3)
222 enum mt7530_stp_state {
223 MT7530_STP_DISABLED = 0,
224 MT7530_STP_BLOCKING = 1,
225 MT7530_STP_LISTENING = 1,
226 MT7530_STP_LEARNING = 2,
227 MT7530_STP_FORWARDING = 3
230 /* Register for port control */
231 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
232 #define PORT_TX_MIR BIT(9)
233 #define PORT_RX_MIR BIT(8)
234 #define PORT_VLAN(x) ((x) & 0x3)
236 enum mt7530_port_mode {
237 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
238 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0),
240 /* Fallback Mode: Forward received frames with ingress ports that do
241 * not belong to the VLAN member. Frames whose VID is not listed on
242 * the VLAN table are forwarded by the PCR_MATRIX members.
244 MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1),
246 /* Security Mode: Discard any frame due to ingress membership
247 * violation or VID missed on the VLAN table.
249 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3),
252 #define PCR_MATRIX(x) (((x) & 0xff) << 16)
253 #define PORT_PRI(x) (((x) & 0x7) << 24)
254 #define EG_TAG(x) (((x) & 0x3) << 28)
255 #define PCR_MATRIX_MASK PCR_MATRIX(0xff)
256 #define PCR_MATRIX_CLR PCR_MATRIX(0)
257 #define PCR_PORT_VLAN_MASK PORT_VLAN(3)
259 /* Register for port security control */
260 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100))
261 #define SA_DIS BIT(4)
263 /* Register for port vlan control */
264 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100))
265 #define PORT_SPEC_TAG BIT(5)
266 #define PVC_EG_TAG(x) (((x) & 0x7) << 8)
267 #define PVC_EG_TAG_MASK PVC_EG_TAG(7)
268 #define VLAN_ATTR(x) (((x) & 0x3) << 6)
269 #define VLAN_ATTR_MASK VLAN_ATTR(3)
270 #define ACC_FRM_MASK GENMASK(1, 0)
272 enum mt7530_vlan_port_eg_tag {
273 MT7530_VLAN_EG_DISABLED = 0,
274 MT7530_VLAN_EG_CONSISTENT = 1,
275 MT7530_VLAN_EG_UNTAGGED = 4,
278 enum mt7530_vlan_port_attr {
279 MT7530_VLAN_USER = 0,
280 MT7530_VLAN_TRANSPARENT = 3,
283 enum mt7530_vlan_port_acc_frm {
284 MT7530_VLAN_ACC_ALL = 0,
285 MT7530_VLAN_ACC_TAGGED = 1,
286 MT7530_VLAN_ACC_UNTAGGED = 2,
289 #define STAG_VPID (((x) & 0xffff) << 16)
291 /* Register for port port-and-protocol based vlan 1 control */
292 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
293 #define G0_PORT_VID(x) (((x) & 0xfff) << 0)
294 #define G0_PORT_VID_MASK G0_PORT_VID(0xfff)
295 #define G0_PORT_VID_DEF G0_PORT_VID(0)
297 /* Register for port MAC control register */
298 #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
299 #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
300 #define PMCR_EXT_PHY BIT(17)
301 #define PMCR_MAC_MODE BIT(16)
302 #define PMCR_FORCE_MODE BIT(15)
303 #define PMCR_TX_EN BIT(14)
304 #define PMCR_RX_EN BIT(13)
305 #define PMCR_BACKOFF_EN BIT(9)
306 #define PMCR_BACKPR_EN BIT(8)
307 #define PMCR_FORCE_EEE1G BIT(7)
308 #define PMCR_FORCE_EEE100 BIT(6)
309 #define PMCR_TX_FC_EN BIT(5)
310 #define PMCR_RX_FC_EN BIT(4)
311 #define PMCR_FORCE_SPEED_1000 BIT(3)
312 #define PMCR_FORCE_SPEED_100 BIT(2)
313 #define PMCR_FORCE_FDX BIT(1)
314 #define PMCR_FORCE_LNK BIT(0)
315 #define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
316 PMCR_FORCE_SPEED_1000)
317 #define MT7531_FORCE_LNK BIT(31)
318 #define MT7531_FORCE_SPD BIT(30)
319 #define MT7531_FORCE_DPX BIT(29)
320 #define MT7531_FORCE_RX_FC BIT(28)
321 #define MT7531_FORCE_TX_FC BIT(27)
322 #define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
325 MT7531_FORCE_RX_FC | \
327 #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
328 PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
329 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
330 PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
331 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
333 #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
334 #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
335 #define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16)
336 #define LPI_THRESH_MASK GENMASK(15, 4)
337 #define LPI_THRESH_SHT 4
338 #define SET_LPI_THRESH(x) (((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK)
339 #define GET_LPI_THRESH(x) (((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT)
340 #define LPI_MODE_EN BIT(0)
342 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
343 #define PMSR_EEE1G BIT(7)
344 #define PMSR_EEE100M BIT(6)
345 #define PMSR_RX_FC BIT(5)
346 #define PMSR_TX_FC BIT(4)
347 #define PMSR_SPEED_1000 BIT(3)
348 #define PMSR_SPEED_100 BIT(2)
349 #define PMSR_SPEED_10 0x00
350 #define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000)
351 #define PMSR_DPX BIT(1)
352 #define PMSR_LINK BIT(0)
354 /* Register for port debug count */
355 #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100)
356 #define MT7531_DIS_CLR BIT(31)
358 #define MT7530_GMACCR 0x30e0
359 #define MAX_RX_JUMBO(x) ((x) << 2)
360 #define MAX_RX_JUMBO_MASK GENMASK(5, 2)
361 #define MAX_RX_PKT_LEN_MASK GENMASK(1, 0)
362 #define MAX_RX_PKT_LEN_1522 0x0
363 #define MAX_RX_PKT_LEN_1536 0x1
364 #define MAX_RX_PKT_LEN_1552 0x2
365 #define MAX_RX_PKT_LEN_JUMBO 0x3
367 /* Register for MIB */
368 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
369 #define MT7530_MIB_CCR 0x4fe0
370 #define CCR_MIB_ENABLE BIT(31)
371 #define CCR_RX_OCT_CNT_GOOD BIT(7)
372 #define CCR_RX_OCT_CNT_BAD BIT(6)
373 #define CCR_TX_OCT_CNT_GOOD BIT(5)
374 #define CCR_TX_OCT_CNT_BAD BIT(4)
375 #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \
376 CCR_RX_OCT_CNT_BAD | \
377 CCR_TX_OCT_CNT_GOOD | \
379 #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \
380 CCR_RX_OCT_CNT_GOOD | \
381 CCR_RX_OCT_CNT_BAD | \
382 CCR_TX_OCT_CNT_GOOD | \
385 /* MT7531 SGMII register group */
386 #define MT7531_SGMII_REG_BASE(p) (0x5000 + ((p) - 5) * 0x1000)
387 #define MT7531_PHYA_CTRL_SIGNAL3 0x128
389 /* Register for system reset */
390 #define MT7530_SYS_CTRL 0x7000
391 #define SYS_CTRL_PHY_RST BIT(2)
392 #define SYS_CTRL_SW_RST BIT(1)
393 #define SYS_CTRL_REG_RST BIT(0)
395 /* Register for system interrupt */
396 #define MT7530_SYS_INT_EN 0x7008
398 /* Register for system interrupt status */
399 #define MT7530_SYS_INT_STS 0x700c
401 /* Register for PHY Indirect Access Control */
402 #define MT7531_PHY_IAC 0x701C
403 #define MT7531_PHY_ACS_ST BIT(31)
404 #define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25)
405 #define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20)
406 #define MT7531_MDIO_CMD_MASK (0x3 << 18)
407 #define MT7531_MDIO_ST_MASK (0x3 << 16)
408 #define MT7531_MDIO_RW_DATA_MASK (0xffff)
409 #define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25)
410 #define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25)
411 #define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20)
412 #define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18)
413 #define MT7531_MDIO_ST(x) (((x) & 0x3) << 16)
415 enum mt7531_phy_iac_cmd {
416 MT7531_MDIO_ADDR = 0,
417 MT7531_MDIO_WRITE = 1,
418 MT7531_MDIO_READ = 2,
419 MT7531_MDIO_READ_CL45 = 3,
422 /* MDIO_ST: MDIO start field */
423 enum mt7531_mdio_st {
424 MT7531_MDIO_ST_CL45 = 0,
425 MT7531_MDIO_ST_CL22 = 1,
428 #define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
429 MT7531_MDIO_CMD(MT7531_MDIO_READ))
430 #define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
431 MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
432 #define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
433 MT7531_MDIO_CMD(MT7531_MDIO_ADDR))
434 #define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
435 MT7531_MDIO_CMD(MT7531_MDIO_READ))
436 #define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
437 MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
439 /* Register for RGMII clock phase */
440 #define MT7531_CLKGEN_CTRL 0x7500
441 #define CLK_SKEW_OUT(x) (((x) & 0x3) << 8)
442 #define CLK_SKEW_OUT_MASK GENMASK(9, 8)
443 #define CLK_SKEW_IN(x) (((x) & 0x3) << 6)
444 #define CLK_SKEW_IN_MASK GENMASK(7, 6)
445 #define RXCLK_NO_DELAY BIT(5)
446 #define TXCLK_NO_REVERSE BIT(4)
447 #define GP_MODE(x) (((x) & 0x3) << 1)
448 #define GP_MODE_MASK GENMASK(2, 1)
449 #define GP_CLK_EN BIT(0)
451 enum mt7531_gp_mode {
452 MT7531_GP_MODE_RGMII = 0,
453 MT7531_GP_MODE_MII = 1,
454 MT7531_GP_MODE_REV_MII = 2
457 enum mt7531_clk_skew {
458 MT7531_CLK_SKEW_NO_CHG = 0,
459 MT7531_CLK_SKEW_DLY_100PPS = 1,
460 MT7531_CLK_SKEW_DLY_200PPS = 2,
461 MT7531_CLK_SKEW_REVERSE = 3,
464 /* Register for hw trap status */
465 #define MT7530_HWTRAP 0x7800
466 #define HWTRAP_XTAL_MASK (BIT(10) | BIT(9))
467 #define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9))
468 #define HWTRAP_XTAL_40MHZ (BIT(10))
469 #define HWTRAP_XTAL_20MHZ (BIT(9))
471 #define MT7531_HWTRAP 0x7800
472 #define HWTRAP_XTAL_FSEL_MASK BIT(7)
473 #define HWTRAP_XTAL_FSEL_25MHZ BIT(7)
474 #define HWTRAP_XTAL_FSEL_40MHZ 0
475 /* Unique fields of (M)HWSTRAP for MT7531 */
476 #define XTAL_FSEL_S 7
477 #define XTAL_FSEL_M BIT(7)
478 #define PHY_EN BIT(6)
479 #define CHG_STRAP BIT(8)
481 /* Register for hw trap modification */
482 #define MT7530_MHWTRAP 0x7804
483 #define MHWTRAP_PHY0_SEL BIT(20)
484 #define MHWTRAP_MANUAL BIT(16)
485 #define MHWTRAP_P5_MAC_SEL BIT(13)
486 #define MHWTRAP_P6_DIS BIT(8)
487 #define MHWTRAP_P5_RGMII_MODE BIT(7)
488 #define MHWTRAP_P5_DIS BIT(6)
489 #define MHWTRAP_PHY_ACCESS BIT(5)
491 /* Register for TOP signal control */
492 #define MT7530_TOP_SIG_CTRL 0x7808
493 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16))
495 #define MT7531_TOP_SIG_SR 0x780c
496 #define PAD_DUAL_SGMII_EN BIT(1)
497 #define PAD_MCM_SMI_EN BIT(0)
499 #define MT7530_IO_DRV_CR 0x7810
500 #define P5_IO_CLK_DRV(x) ((x) & 0x3)
501 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
503 #define MT7531_CHIP_REV 0x781C
505 #define MT7531_PLLGP_EN 0x7820
506 #define EN_COREPLL BIT(2)
507 #define SW_CLKSW BIT(1)
508 #define SW_PLLGP BIT(0)
510 #define MT7530_P6ECR 0x7830
511 #define P6_INTF_MODE_MASK 0x3
512 #define P6_INTF_MODE(x) ((x) & 0x3)
514 #define MT7531_PLLGP_CR0 0x78a8
515 #define RG_COREPLL_EN BIT(22)
516 #define RG_COREPLL_POSDIV_S 23
517 #define RG_COREPLL_POSDIV_M 0x3800000
518 #define RG_COREPLL_SDM_PCW_S 1
519 #define RG_COREPLL_SDM_PCW_M 0x3ffffe
520 #define RG_COREPLL_SDM_PCW_CHG BIT(0)
522 /* Registers for RGMII and SGMII PLL clock */
523 #define MT7531_ANA_PLLGP_CR2 0x78b0
524 #define MT7531_ANA_PLLGP_CR5 0x78bc
526 /* Registers for TRGMII on the both side */
527 #define MT7530_TRGMII_RCK_CTRL 0x7a00
528 #define RX_RST BIT(31)
529 #define RXC_DQSISEL BIT(30)
530 #define DQSI1_TAP_MASK (0x7f << 8)
531 #define DQSI0_TAP_MASK 0x7f
532 #define DQSI1_TAP(x) (((x) & 0x7f) << 8)
533 #define DQSI0_TAP(x) ((x) & 0x7f)
535 #define MT7530_TRGMII_RCK_RTT 0x7a04
536 #define DQS1_GATE BIT(31)
537 #define DQS0_GATE BIT(30)
539 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8)
540 #define BSLIP_EN BIT(31)
541 #define EDGE_CHK BIT(30)
542 #define RD_TAP_MASK 0x7f
543 #define RD_TAP(x) ((x) & 0x7f)
545 #define MT7530_TRGMII_TXCTRL 0x7a40
546 #define TRAIN_TXEN BIT(31)
547 #define TXC_INV BIT(30)
548 #define TX_RST BIT(28)
550 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i))
551 #define TD_DM_DRVP(x) ((x) & 0xf)
552 #define TD_DM_DRVN(x) (((x) & 0xf) << 4)
554 #define MT7530_TRGMII_TCK_CTRL 0x7a78
555 #define TCK_TAP(x) (((x) & 0xf) << 8)
557 #define MT7530_P5RGMIIRXCR 0x7b00
558 #define CSR_RGMII_EDGE_ALIGN BIT(8)
559 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf)
561 #define MT7530_P5RGMIITXCR 0x7b04
562 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
564 /* Registers for GPIO mode */
565 #define MT7531_GPIO_MODE0 0x7c0c
566 #define MT7531_GPIO0_MASK GENMASK(3, 0)
567 #define MT7531_GPIO0_INTERRUPT 1
569 #define MT7531_GPIO_MODE1 0x7c10
570 #define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12)
571 #define MT7531_EXT_P_MDC_11 (2 << 12)
572 #define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16)
573 #define MT7531_EXT_P_MDIO_12 (2 << 16)
575 /* Registers for LED GPIO control (MT7530 only)
576 * All registers follow this pattern:
584 /* LED enable, 0: Disable, 1: Enable (Default) */
585 #define MT7530_LED_EN 0x7d00
586 /* LED mode, 0: GPIO mode, 1: PHY mode (Default) */
587 #define MT7530_LED_IO_MODE 0x7d04
588 /* GPIO direction, 0: Input, 1: Output */
589 #define MT7530_LED_GPIO_DIR 0x7d10
590 /* GPIO output enable, 0: Disable, 1: Enable */
591 #define MT7530_LED_GPIO_OE 0x7d14
592 /* GPIO value, 0: Low, 1: High */
593 #define MT7530_LED_GPIO_DATA 0x7d18
595 #define MT7530_CREV 0x7ffc
596 #define CHIP_NAME_SHIFT 16
597 #define MT7530_ID 0x7530
599 #define MT7531_CREV 0x781C
600 #define CHIP_REV_M 0x0f
601 #define MT7531_ID 0x7531
603 /* Registers for core PLL access through mmd indirect */
604 #define CORE_PLL_GROUP2 0x401
605 #define RG_SYSPLL_EN_NORMAL BIT(15)
606 #define RG_SYSPLL_VODEN BIT(14)
607 #define RG_SYSPLL_LF BIT(13)
608 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12)
609 #define RG_SYSPLL_LVROD_EN BIT(10)
610 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8)
611 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5)
612 #define RG_SYSPLL_FBKSEL BIT(4)
613 #define RT_SYSPLL_EN_AFE_OLT BIT(0)
615 #define CORE_PLL_GROUP4 0x403
616 #define RG_SYSPLL_DDSFBK_EN BIT(12)
617 #define RG_SYSPLL_BIAS_EN BIT(11)
618 #define RG_SYSPLL_BIAS_LPF_EN BIT(10)
619 #define MT7531_PHY_PLL_OFF BIT(5)
620 #define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
622 #define MT753X_CTRL_PHY_ADDR 0
624 #define CORE_PLL_GROUP5 0x404
625 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
627 #define CORE_PLL_GROUP6 0x405
628 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff)
630 #define CORE_PLL_GROUP7 0x406
631 #define RG_LCDDS_PWDB BIT(15)
632 #define RG_LCDDS_ISO_EN BIT(13)
633 #define RG_LCCDS_C(x) (((x) & 0x7) << 4)
634 #define RG_LCDDS_PCW_NCPO_CHG BIT(3)
636 #define CORE_PLL_GROUP10 0x409
637 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff)
639 #define CORE_PLL_GROUP11 0x40a
640 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff)
642 #define CORE_GSWPLL_GRP1 0x40d
643 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14)
644 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12)
645 #define RG_GSWPLL_EN_PRE BIT(11)
646 #define RG_GSWPLL_FBKSEL BIT(10)
647 #define RG_GSWPLL_BP BIT(9)
648 #define RG_GSWPLL_BR BIT(8)
649 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff)
651 #define CORE_GSWPLL_GRP2 0x40e
652 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8)
653 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff)
655 #define CORE_TRGMII_GSW_CLK_CG 0x410
656 #define REG_GSWCK_EN BIT(0)
657 #define REG_TRGMIICK_EN BIT(1)
659 #define MIB_DESC(_s, _o, _n) \
666 struct mt7530_mib_desc {
680 /* struct mt7530_port - This is the main data structure for holding the state
682 * @enable: The status used for show port is enabled or not.
683 * @pm: The matrix used to show all connections with the port.
684 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any
685 * untagged frames will be assigned to the related VLAN.
686 * @sgmii_pcs: Pointer to PCS instance for SerDes ports
692 struct phylink_pcs *sgmii_pcs;
695 /* Port 5 interface select definitions */
696 enum p5_interface_select {
706 struct phylink_pcs pcs;
707 struct mt7530_priv *priv;
711 /* struct mt753x_info - This is the main data structure for holding the specific
712 * part for each supported device
713 * @sw_setup: Holding the handler to a device initialization
714 * @phy_read_c22: Holding the way reading PHY port using C22
715 * @phy_write_c22: Holding the way writing PHY port using C22
716 * @phy_read_c45: Holding the way reading PHY port using C45
717 * @phy_write_c45: Holding the way writing PHY port using C45
718 * @phy_mode_supported: Check if the PHY type is being supported on a certain
720 * @mac_port_validate: Holding the way to set addition validate type for a
722 * @mac_port_config: Holding the way setting up the PHY attribute to a
728 const struct phylink_pcs_ops *pcs_ops;
730 int (*sw_setup)(struct dsa_switch *ds);
731 int (*phy_read_c22)(struct mt7530_priv *priv, int port, int regnum);
732 int (*phy_write_c22)(struct mt7530_priv *priv, int port, int regnum,
734 int (*phy_read_c45)(struct mt7530_priv *priv, int port, int devad,
736 int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad,
737 int regnum, u16 val);
738 void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
739 struct phylink_config *config);
740 void (*mac_port_validate)(struct dsa_switch *ds, int port,
741 phy_interface_t interface,
742 unsigned long *supported);
743 void (*mac_port_config)(struct dsa_switch *ds, int port,
745 phy_interface_t interface);
748 /* struct mt7530_priv - This is the main data structure for holding the state
750 * @dev: The device pointer
751 * @ds: The pointer to the dsa core structure
752 * @bus: The bus used for the device and built-in PHY
753 * @regmap: The regmap instance representing all switch registers
754 * @rstc: The pointer to reset control used by MCM
755 * @core_pwr: The power supplied into the core
756 * @io_pwr: The power supplied into the I/O
757 * @reset: The descriptor for GPIO line tied to its reset pin
758 * @mcm: Flag for distinguishing if standalone IC or module
760 * @ports: Holding the state among ports
761 * @reg_mutex: The lock for protecting among process accessing
763 * @p5_intf_sel: Holding the current port 5 interface select
764 * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
766 * @irq: IRQ number of the switch
767 * @irq_domain: IRQ domain of the switch irq_chip
768 * @irq_enable: IRQ enable bits, synced to SYS_INT_EN
769 * @create_sgmii: Pointer to function creating SGMII PCS instance(s)
770 * @active_cpu_ports: Holding the active CPU ports
774 struct dsa_switch *ds;
776 struct regmap *regmap;
777 struct reset_control *rstc;
778 struct regulator *core_pwr;
779 struct regulator *io_pwr;
780 struct gpio_desc *reset;
781 const struct mt753x_info *info;
784 enum p5_interface_select p5_intf_sel;
788 struct mt7530_port ports[MT7530_NUM_PORTS];
789 struct mt753x_pcs pcs[MT7530_NUM_PORTS];
790 /* protect among processes for registers access*/
791 struct mutex reg_mutex;
793 struct irq_domain *irq_domain;
795 int (*create_sgmii)(struct mt7530_priv *priv);
799 struct mt7530_hw_vlan_entry {
805 static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e,
806 int port, bool untagged)
809 e->untagged = untagged;
812 typedef void (*mt7530_vlan_op)(struct mt7530_priv *,
813 struct mt7530_hw_vlan_entry *);
815 struct mt7530_hw_stats {
821 struct mt7530_dummy_poll {
822 struct mt7530_priv *priv;
826 static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p,
827 struct mt7530_priv *priv, u32 reg)
833 int mt7530_probe_common(struct mt7530_priv *priv);
834 void mt7530_remove_common(struct mt7530_priv *priv);
836 extern const struct dsa_switch_ops mt7530_switch_ops;
837 extern const struct mt753x_info mt753x_table[];
839 #endif /* __MT7530_H */