drivers/net/dsa/mv88e6xxx/chip.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Marvell 88e6xxx Ethernet switch single-chip support
   4  *
   5  * Copyright (c) 2008 Marvell Semiconductor
   6  *
   7  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
   8  *
   9  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
  10  *      Vivien Didelot <vivien.didelot@savoirfairelinux.com>
  11  */
  12
  13 #include <linux/bitfield.h>
  14 #include <linux/delay.h>
  15 #include <linux/dsa/mv88e6xxx.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/if_bridge.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irq.h>
  21 #include <linux/irqdomain.h>
  22 #include <linux/jiffies.h>
  23 #include <linux/list.h>
  24 #include <linux/mdio.h>
  25 #include <linux/module.h>
  26 #include <linux/of.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/of_mdio.h>
  29 #include <linux/platform_data/mv88e6xxx.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/gpio/consumer.h>
  32 #include <linux/phylink.h>
  33 #include <net/dsa.h>
  34
  35 #include "chip.h"
  36 #include "devlink.h"
  37 #include "global1.h"
  38 #include "global2.h"
  39 #include "hwtstamp.h"
  40 #include "phy.h"
  41 #include "port.h"
  42 #include "ptp.h"
  43 #include "serdes.h"
  44 #include "smi.h"
  45
  46 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  47 {
  48         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  49                 dev_err(chip->dev, "Switch registers lock not held!\n");
  50                 dump_stack();
  51         }
  52 }
  53
  54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
  55 {
  56         int err;
  57
  58         assert_reg_lock(chip);
  59
  60         err = mv88e6xxx_smi_read(chip, addr, reg, val);
  61         if (err)
  62                 return err;
  63
  64         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  65                 addr, reg, *val);
  66
  67         return 0;
  68 }
  69
  70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
  71 {
  72         int err;
  73
  74         assert_reg_lock(chip);
  75
  76         err = mv88e6xxx_smi_write(chip, addr, reg, val);
  77         if (err)
  78                 return err;
  79
  80         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  81                 addr, reg, val);
  82
  83         return 0;
  84 }
  85
  86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
  87                         u16 mask, u16 val)
  88 {
  89         const unsigned long timeout = jiffies + msecs_to_jiffies(50);
  90         u16 data;
  91         int err;
  92         int i;
  93
  94         /* There's no bus specific operation to wait for a mask. Even
  95          * if the initial poll takes longer than 50ms, always do at
  96          * least one more attempt.
  97          */
  98         for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) {
  99                 err = mv88e6xxx_read(chip, addr, reg, &data);
 100                 if (err)
 101                         return err;
 102
 103                 if ((data & mask) == val)
 104                         return 0;
 105
 106                 if (i < 2)
 107                         cpu_relax();
 108                 else
 109                         usleep_range(1000, 2000);
 110         }
 111
 112         err = mv88e6xxx_read(chip, addr, reg, &data);
 113         if (err)
 114                 return err;
 115
 116         if ((data & mask) == val)
 117                 return 0;
 118
 119         dev_err(chip->dev, "Timeout while waiting for switch\n");
 120         return -ETIMEDOUT;
 121 }
 122
 123 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
 124                        int bit, int val)
 125 {
 126         return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
 127                                    val ? BIT(bit) : 0x0000);
 128 }
 129
 130 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
 131 {
 132         struct mv88e6xxx_mdio_bus *mdio_bus;
 133
 134         mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
 135                                     list);
 136         if (!mdio_bus)
 137                 return NULL;
 138
 139         return mdio_bus->bus;
 140 }
 141
 142 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
 143 {
 144         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 145         unsigned int n = d->hwirq;
 146
 147         chip->g1_irq.masked |= (1 << n);
 148 }
 149
 150 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
 151 {
 152         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 153         unsigned int n = d->hwirq;
 154
 155         chip->g1_irq.masked &= ~(1 << n);
 156 }
 157
 158 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
 159 {
 160         unsigned int nhandled = 0;
 161         unsigned int sub_irq;
 162         unsigned int n;
 163         u16 reg;
 164         u16 ctl1;
 165         int err;
 166
 167         mv88e6xxx_reg_lock(chip);
 168         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 169         mv88e6xxx_reg_unlock(chip);
 170
 171         if (err)
 172                 goto out;
 173
 174         do {
 175                 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
 176                         if (reg & (1 << n)) {
 177                                 sub_irq = irq_find_mapping(chip->g1_irq.domain,
 178                                                            n);
 179                                 handle_nested_irq(sub_irq);
 180                                 ++nhandled;
 181                         }
 182                 }
 183
 184                 mv88e6xxx_reg_lock(chip);
 185                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
 186                 if (err)
 187                         goto unlock;
 188                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 189 unlock:
 190                 mv88e6xxx_reg_unlock(chip);
 191                 if (err)
 192                         goto out;
 193                 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
 194         } while (reg & ctl1);
 195
 196 out:
 197         return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
 198 }
 199
 200 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
 201 {
 202         struct mv88e6xxx_chip *chip = dev_id;
 203
 204         return mv88e6xxx_g1_irq_thread_work(chip);
 205 }
 206
 207 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
 208 {
 209         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 210
 211         mv88e6xxx_reg_lock(chip);
 212 }
 213
 214 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
 215 {
 216         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 217         u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
 218         u16 reg;
 219         int err;
 220
 221         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
 222         if (err)
 223                 goto out;
 224
 225         reg &= ~mask;
 226         reg |= (~chip->g1_irq.masked & mask);
 227
 228         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
 229         if (err)
 230                 goto out;
 231
 232 out:
 233         mv88e6xxx_reg_unlock(chip);
 234 }
 235
 236 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
 237         .name                   = "mv88e6xxx-g1",
 238         .irq_mask               = mv88e6xxx_g1_irq_mask,
 239         .irq_unmask             = mv88e6xxx_g1_irq_unmask,
 240         .irq_bus_lock           = mv88e6xxx_g1_irq_bus_lock,
 241         .irq_bus_sync_unlock    = mv88e6xxx_g1_irq_bus_sync_unlock,
 242 };
 243
 244 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
 245                                        unsigned int irq,
 246                                        irq_hw_number_t hwirq)
 247 {
 248         struct mv88e6xxx_chip *chip = d->host_data;
 249
 250         irq_set_chip_data(irq, d->host_data);
 251         irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
 252         irq_set_noprobe(irq);
 253
 254         return 0;
 255 }
 256
 257 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
 258         .map    = mv88e6xxx_g1_irq_domain_map,
 259         .xlate  = irq_domain_xlate_twocell,
 260 };
 261
 262 /* To be called with reg_lock held */
 263 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
 264 {
 265         int irq, virq;
 266         u16 mask;
 267
 268         mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 269         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 270         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 271
 272         for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
 273                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 274                 irq_dispose_mapping(virq);
 275         }
 276
 277         irq_domain_remove(chip->g1_irq.domain);
 278 }
 279
 280 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
 281 {
 282         /*
 283          * free_irq must be called without reg_lock taken because the irq
 284          * handler takes this lock, too.
 285          */
 286         free_irq(chip->irq, chip);
 287
 288         mv88e6xxx_reg_lock(chip);
 289         mv88e6xxx_g1_irq_free_common(chip);
 290         mv88e6xxx_reg_unlock(chip);
 291 }
 292
 293 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
 294 {
 295         int err, irq, virq;
 296         u16 reg, mask;
 297
 298         chip->g1_irq.nirqs = chip->info->g1_irqs;
 299         chip->g1_irq.domain = irq_domain_add_simple(
 300                 NULL, chip->g1_irq.nirqs, 0,
 301                 &mv88e6xxx_g1_irq_domain_ops, chip);
 302         if (!chip->g1_irq.domain)
 303                 return -ENOMEM;
 304
 305         for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
 306                 irq_create_mapping(chip->g1_irq.domain, irq);
 307
 308         chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
 309         chip->g1_irq.masked = ~0;
 310
 311         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 312         if (err)
 313                 goto out_mapping;
 314
 315         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 316
 317         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 318         if (err)
 319                 goto out_disable;
 320
 321         /* Reading the interrupt status clears (most of) them */
 322         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 323         if (err)
 324                 goto out_disable;
 325
 326         return 0;
 327
 328 out_disable:
 329         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 330         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 331
 332 out_mapping:
 333         for (irq = 0; irq < 16; irq++) {
 334                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 335                 irq_dispose_mapping(virq);
 336         }
 337
 338         irq_domain_remove(chip->g1_irq.domain);
 339
 340         return err;
 341 }
 342
 343 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
 344 {
 345         static struct lock_class_key lock_key;
 346         static struct lock_class_key request_key;
 347         int err;
 348
 349         err = mv88e6xxx_g1_irq_setup_common(chip);
 350         if (err)
 351                 return err;
 352
 353         /* These lock classes tells lockdep that global 1 irqs are in
 354          * a different category than their parent GPIO, so it won't
 355          * report false recursion.
 356          */
 357         irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
 358
 359         snprintf(chip->irq_name, sizeof(chip->irq_name),
 360                  "mv88e6xxx-%s", dev_name(chip->dev));
 361
 362         mv88e6xxx_reg_unlock(chip);
 363         err = request_threaded_irq(chip->irq, NULL,
 364                                    mv88e6xxx_g1_irq_thread_fn,
 365                                    IRQF_ONESHOT | IRQF_SHARED,
 366                                    chip->irq_name, chip);
 367         mv88e6xxx_reg_lock(chip);
 368         if (err)
 369                 mv88e6xxx_g1_irq_free_common(chip);
 370
 371         return err;
 372 }
 373
 374 static void mv88e6xxx_irq_poll(struct kthread_work *work)
 375 {
 376         struct mv88e6xxx_chip *chip = container_of(work,
 377                                                    struct mv88e6xxx_chip,
 378                                                    irq_poll_work.work);
 379         mv88e6xxx_g1_irq_thread_work(chip);
 380
 381         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 382                                    msecs_to_jiffies(100));
 383 }
 384
 385 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
 386 {
 387         int err;
 388
 389         err = mv88e6xxx_g1_irq_setup_common(chip);
 390         if (err)
 391                 return err;
 392
 393         kthread_init_delayed_work(&chip->irq_poll_work,
 394                                   mv88e6xxx_irq_poll);
 395
 396         chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
 397         if (IS_ERR(chip->kworker))
 398                 return PTR_ERR(chip->kworker);
 399
 400         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 401                                    msecs_to_jiffies(100));
 402
 403         return 0;
 404 }
 405
 406 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
 407 {
 408         kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
 409         kthread_destroy_worker(chip->kworker);
 410
 411         mv88e6xxx_reg_lock(chip);
 412         mv88e6xxx_g1_irq_free_common(chip);
 413         mv88e6xxx_reg_unlock(chip);
 414 }
 415
 416 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
 417                                            int port, phy_interface_t interface)
 418 {
 419         int err;
 420
 421         if (chip->info->ops->port_set_rgmii_delay) {
 422                 err = chip->info->ops->port_set_rgmii_delay(chip, port,
 423                                                             interface);
 424                 if (err && err != -EOPNOTSUPP)
 425                         return err;
 426         }
 427
 428         if (chip->info->ops->port_set_cmode) {
 429                 err = chip->info->ops->port_set_cmode(chip, port,
 430                                                       interface);
 431                 if (err && err != -EOPNOTSUPP)
 432                         return err;
 433         }
 434
 435         return 0;
 436 }
 437
 438 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
 439                                     int link, int speed, int duplex, int pause,
 440                                     phy_interface_t mode)
 441 {
 442         int err;
 443
 444         if (!chip->info->ops->port_set_link)
 445                 return 0;
 446
 447         /* Port's MAC control must not be changed unless the link is down */
 448         err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
 449         if (err)
 450                 return err;
 451
 452         if (chip->info->ops->port_set_speed_duplex) {
 453                 err = chip->info->ops->port_set_speed_duplex(chip, port,
 454                                                              speed, duplex);
 455                 if (err && err != -EOPNOTSUPP)
 456                         goto restore_link;
 457         }
 458
 459         if (chip->info->ops->port_set_pause) {
 460                 err = chip->info->ops->port_set_pause(chip, port, pause);
 461                 if (err)
 462                         goto restore_link;
 463         }
 464
 465         err = mv88e6xxx_port_config_interface(chip, port, mode);
 466 restore_link:
 467         if (chip->info->ops->port_set_link(chip, port, link))
 468                 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
 469
 470         return err;
 471 }
 472
 473 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
 474 {
 475         return port >= chip->info->internal_phys_offset &&
 476                 port < chip->info->num_internal_phys +
 477                         chip->info->internal_phys_offset;
 478 }
 479
 480 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
 481 {
 482         u16 reg;
 483         int err;
 484
 485         /* The 88e6250 family does not have the PHY detect bit. Instead,
 486          * report whether the port is internal.
 487          */
 488         if (chip->info->family == MV88E6XXX_FAMILY_6250)
 489                 return mv88e6xxx_phy_is_internal(chip, port);
 490
 491         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
 492         if (err) {
 493                 dev_err(chip->dev,
 494                         "p%d: %s: failed to read port status\n",
 495                         port, __func__);
 496                 return err;
 497         }
 498
 499         return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
 500 }
 501
 502 static const u8 mv88e6185_phy_interface_modes[] = {
 503         [MV88E6185_PORT_STS_CMODE_GMII_FD]       = PHY_INTERFACE_MODE_GMII,
 504         [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII,
 505         [MV88E6185_PORT_STS_CMODE_MII_100]       = PHY_INTERFACE_MODE_MII,
 506         [MV88E6185_PORT_STS_CMODE_MII_10]        = PHY_INTERFACE_MODE_MII,
 507         [MV88E6185_PORT_STS_CMODE_SERDES]        = PHY_INTERFACE_MODE_1000BASEX,
 508         [MV88E6185_PORT_STS_CMODE_1000BASE_X]    = PHY_INTERFACE_MODE_1000BASEX,
 509         [MV88E6185_PORT_STS_CMODE_PHY]           = PHY_INTERFACE_MODE_SGMII,
 510 };
 511
 512 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 513                                        struct phylink_config *config)
 514 {
 515         u8 cmode = chip->ports[port].cmode;
 516
 517         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
 518
 519         if (mv88e6xxx_phy_is_internal(chip, port)) {
 520                 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
 521         } else {
 522                 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
 523                     mv88e6185_phy_interface_modes[cmode])
 524                         __set_bit(mv88e6185_phy_interface_modes[cmode],
 525                                   config->supported_interfaces);
 526
 527                 config->mac_capabilities |= MAC_1000FD;
 528         }
 529 }
 530
 531 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 532                                        struct phylink_config *config)
 533 {
 534         u8 cmode = chip->ports[port].cmode;
 535
 536         if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
 537             mv88e6185_phy_interface_modes[cmode])
 538                 __set_bit(mv88e6185_phy_interface_modes[cmode],
 539                           config->supported_interfaces);
 540
 541         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 542                                    MAC_1000FD;
 543 }
 544
 545 static const u8 mv88e6xxx_phy_interface_modes[] = {
 546         [MV88E6XXX_PORT_STS_CMODE_MII_PHY]      = PHY_INTERFACE_MODE_REVMII,
 547         [MV88E6XXX_PORT_STS_CMODE_MII]          = PHY_INTERFACE_MODE_MII,
 548         [MV88E6XXX_PORT_STS_CMODE_GMII]         = PHY_INTERFACE_MODE_GMII,
 549         [MV88E6XXX_PORT_STS_CMODE_RMII_PHY]     = PHY_INTERFACE_MODE_REVRMII,
 550         [MV88E6XXX_PORT_STS_CMODE_RMII]         = PHY_INTERFACE_MODE_RMII,
 551         [MV88E6XXX_PORT_STS_CMODE_100BASEX]     = PHY_INTERFACE_MODE_100BASEX,
 552         [MV88E6XXX_PORT_STS_CMODE_1000BASEX]    = PHY_INTERFACE_MODE_1000BASEX,
 553         [MV88E6XXX_PORT_STS_CMODE_SGMII]        = PHY_INTERFACE_MODE_SGMII,
 554         /* higher interface modes are not needed here, since ports supporting
 555          * them are writable, and so the supported interfaces are filled in the
 556          * corresponding .phylink_set_interfaces() implementation below
 557          */
 558 };
 559
 560 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported)
 561 {
 562         if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) &&
 563             mv88e6xxx_phy_interface_modes[cmode])
 564                 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported);
 565         else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII)
 566                 phy_interface_set_rgmii(supported);
 567 }
 568
 569 static void
 570 mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port,
 571                                      struct phylink_config *config)
 572 {
 573         unsigned long *supported = config->supported_interfaces;
 574         int err;
 575         u16 reg;
 576
 577         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
 578         if (err) {
 579                 dev_err(chip->dev, "p%d: failed to read port status\n", port);
 580                 return;
 581         }
 582
 583         switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) {
 584         case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY:
 585         case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY:
 586         case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY:
 587         case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY:
 588                 __set_bit(PHY_INTERFACE_MODE_REVMII, supported);
 589                 break;
 590
 591         case MV88E6250_PORT_STS_PORTMODE_MII_HALF:
 592         case MV88E6250_PORT_STS_PORTMODE_MII_FULL:
 593                 __set_bit(PHY_INTERFACE_MODE_MII, supported);
 594                 break;
 595
 596         case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY:
 597         case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY:
 598         case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY:
 599         case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY:
 600                 __set_bit(PHY_INTERFACE_MODE_REVRMII, supported);
 601                 break;
 602
 603         case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL:
 604         case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL:
 605                 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
 606                 break;
 607
 608         case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII:
 609                 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
 610                 break;
 611
 612         default:
 613                 dev_err(chip->dev,
 614                         "p%d: invalid port mode in status register: %04x\n",
 615                         port, reg);
 616         }
 617 }
 618
 619 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 620                                        struct phylink_config *config)
 621 {
 622         if (!mv88e6xxx_phy_is_internal(chip, port))
 623                 mv88e6250_setup_supported_interfaces(chip, port, config);
 624
 625         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
 626 }
 627
 628 static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 629                                        struct phylink_config *config)
 630 {
 631         unsigned long *supported = config->supported_interfaces;
 632
 633         /* Translate the default cmode */
 634         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 635
 636         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 637                                    MAC_1000FD;
 638 }
 639
 640 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)
 641 {
 642         u16 reg, val;
 643         int err;
 644
 645         err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &reg);
 646         if (err)
 647                 return err;
 648
 649         /* If PHY_DETECT is zero, then we are not in auto-media mode */
 650         if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT))
 651                 return 0xf;
 652
 653         val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT;
 654         err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val);
 655         if (err)
 656                 return err;
 657
 658         err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val);
 659         if (err)
 660                 return err;
 661
 662         /* Restore PHY_DETECT value */
 663         err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg);
 664         if (err)
 665                 return err;
 666
 667         return val & MV88E6XXX_PORT_STS_CMODE_MASK;
 668 }
 669
 670 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 671                                        struct phylink_config *config)
 672 {
 673         unsigned long *supported = config->supported_interfaces;
 674         int err, cmode;
 675
 676         /* Translate the default cmode */
 677         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 678
 679         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 680                                    MAC_1000FD;
 681
 682         /* Port 4 supports automedia if the serdes is associated with it. */
 683         if (port == 4) {
 684                 err = mv88e6352_g2_scratch_port_has_serdes(chip, port);
 685                 if (err < 0)
 686                         dev_err(chip->dev, "p%d: failed to read scratch\n",
 687                                 port);
 688                 if (err <= 0)
 689                         return;
 690
 691                 cmode = mv88e6352_get_port4_serdes_cmode(chip);
 692                 if (cmode < 0)
 693                         dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
 694                                 port);
 695                 else
 696                         mv88e6xxx_translate_cmode(cmode, supported);
 697         }
 698 }
 699
 700 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 701                                        struct phylink_config *config)
 702 {
 703         unsigned long *supported = config->supported_interfaces;
 704
 705         /* Translate the default cmode */
 706         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 707
 708         /* No ethtool bits for 200Mbps */
 709         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 710                                    MAC_1000FD;
 711
 712         /* The C_Mode field is programmable on port 5 */
 713         if (port == 5) {
 714                 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
 715                 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
 716                 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
 717
 718                 config->mac_capabilities |= MAC_2500FD;
 719         }
 720 }
 721
 722 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 723                                        struct phylink_config *config)
 724 {
 725         unsigned long *supported = config->supported_interfaces;
 726
 727         /* Translate the default cmode */
 728         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 729
 730         /* No ethtool bits for 200Mbps */
 731         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 732                                    MAC_1000FD;
 733
 734         /* The C_Mode field is programmable on ports 9 and 10 */
 735         if (port == 9 || port == 10) {
 736                 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
 737                 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
 738                 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
 739
 740                 config->mac_capabilities |= MAC_2500FD;
 741         }
 742 }
 743
 744 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 745                                         struct phylink_config *config)
 746 {
 747         unsigned long *supported = config->supported_interfaces;
 748
 749         mv88e6390_phylink_get_caps(chip, port, config);
 750
 751         /* For the 6x90X, ports 2-7 can be in automedia mode.
 752          * (Note that 6x90 doesn't support RXAUI nor XAUI).
 753          *
 754          * Port 2 can also support 1000BASE-X in automedia mode if port 9 is
 755          * configured for 1000BASE-X, SGMII or 2500BASE-X.
 756          * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is
 757          * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
 758          *
 759          * Port 5 can also support 1000BASE-X in automedia mode if port 10 is
 760          * configured for 1000BASE-X, SGMII or 2500BASE-X.
 761          * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is
 762          * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
 763          *
 764          * For now, be permissive (as the old code was) and allow 1000BASE-X
 765          * on ports 2..7.
 766          */
 767         if (port >= 2 && port <= 7)
 768                 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
 769
 770         /* The C_Mode field can also be programmed for 10G speeds */
 771         if (port == 9 || port == 10) {
 772                 __set_bit(PHY_INTERFACE_MODE_XAUI, supported);
 773                 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported);
 774
 775                 config->mac_capabilities |= MAC_10000FD;
 776         }
 777 }
 778
 779 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 780                                         struct phylink_config *config)
 781 {
 782         unsigned long *supported = config->supported_interfaces;
 783         bool is_6191x =
 784                 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
 785         bool is_6361 =
 786                 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361;
 787
 788         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 789
 790         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 791                                    MAC_1000FD;
 792
 793         /* The C_Mode field can be programmed for ports 0, 9 and 10 */
 794         if (port == 0 || port == 9 || port == 10) {
 795                 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
 796                 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
 797
 798                 /* 6191X supports >1G modes only on port 10 */
 799                 if (!is_6191x || port == 10) {
 800                         __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
 801                         config->mac_capabilities |= MAC_2500FD;
 802
 803                         /* 6361 only supports up to 2500BaseX */
 804                         if (!is_6361) {
 805                                 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
 806                                 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
 807                                 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported);
 808                                 config->mac_capabilities |= MAC_5000FD |
 809                                         MAC_10000FD;
 810                         }
 811                 }
 812         }
 813
 814         if (port == 0) {
 815                 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
 816                 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
 817                 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported);
 818                 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported);
 819                 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported);
 820         }
 821 }
 822
 823 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,
 824                                struct phylink_config *config)
 825 {
 826         struct mv88e6xxx_chip *chip = ds->priv;
 827
 828         mv88e6xxx_reg_lock(chip);
 829         chip->info->ops->phylink_get_caps(chip, port, config);
 830         mv88e6xxx_reg_unlock(chip);
 831
 832         if (mv88e6xxx_phy_is_internal(chip, port)) {
 833                 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
 834                           config->supported_interfaces);
 835                 /* Internal ports with no phy-mode need GMII for PHYLIB */
 836                 __set_bit(PHY_INTERFACE_MODE_GMII,
 837                           config->supported_interfaces);
 838         }
 839 }
 840
 841 static struct phylink_pcs *mv88e6xxx_mac_select_pcs(struct dsa_switch *ds,
 842                                                     int port,
 843                                                     phy_interface_t interface)
 844 {
 845         struct mv88e6xxx_chip *chip = ds->priv;
 846         struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP);
 847
 848         if (chip->info->ops->pcs_ops)
 849                 pcs = chip->info->ops->pcs_ops->pcs_select(chip, port,
 850                                                            interface);
 851
 852         return pcs;
 853 }
 854
 855 static int mv88e6xxx_mac_prepare(struct dsa_switch *ds, int port,
 856                                  unsigned int mode, phy_interface_t interface)
 857 {
 858         struct mv88e6xxx_chip *chip = ds->priv;
 859         int err = 0;
 860
 861         /* In inband mode, the link may come up at any time while the link
 862          * is not forced down. Force the link down while we reconfigure the
 863          * interface mode.
 864          */
 865         if (mode == MLO_AN_INBAND &&
 866             chip->ports[port].interface != interface &&
 867             chip->info->ops->port_set_link) {
 868                 mv88e6xxx_reg_lock(chip);
 869                 err = chip->info->ops->port_set_link(chip, port,
 870                                                      LINK_FORCED_DOWN);
 871                 mv88e6xxx_reg_unlock(chip);
 872         }
 873
 874         return err;
 875 }
 876
 877 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
 878                                  unsigned int mode,
 879                                  const struct phylink_link_state *state)
 880 {
 881         struct mv88e6xxx_chip *chip = ds->priv;
 882         int err = 0;
 883
 884         mv88e6xxx_reg_lock(chip);
 885
 886         if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) {
 887                 err = mv88e6xxx_port_config_interface(chip, port,
 888                                                       state->interface);
 889                 if (err && err != -EOPNOTSUPP)
 890                         goto err_unlock;
 891         }
 892
 893 err_unlock:
 894         mv88e6xxx_reg_unlock(chip);
 895
 896         if (err && err != -EOPNOTSUPP)
 897                 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
 898 }
 899
 900 static int mv88e6xxx_mac_finish(struct dsa_switch *ds, int port,
 901                                 unsigned int mode, phy_interface_t interface)
 902 {
 903         struct mv88e6xxx_chip *chip = ds->priv;
 904         int err = 0;
 905
 906         /* Undo the forced down state above after completing configuration
 907          * irrespective of its state on entry, which allows the link to come
 908          * up in the in-band case where there is no separate SERDES. Also
 909          * ensure that the link can come up if the PPU is in use and we are
 910          * in PHY mode (we treat the PPU as an effective in-band mechanism.)
 911          */
 912         mv88e6xxx_reg_lock(chip);
 913
 914         if (chip->info->ops->port_set_link &&
 915             ((mode == MLO_AN_INBAND &&
 916               chip->ports[port].interface != interface) ||
 917              (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
 918                 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
 919
 920         mv88e6xxx_reg_unlock(chip);
 921
 922         chip->ports[port].interface = interface;
 923
 924         return err;
 925 }
 926
 927 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
 928                                     unsigned int mode,
 929                                     phy_interface_t interface)
 930 {
 931         struct mv88e6xxx_chip *chip = ds->priv;
 932         const struct mv88e6xxx_ops *ops;
 933         int err = 0;
 934
 935         ops = chip->info->ops;
 936
 937         mv88e6xxx_reg_lock(chip);
 938         /* Force the link down if we know the port may not be automatically
 939          * updated by the switch or if we are using fixed-link mode.
 940          */
 941         if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
 942              mode == MLO_AN_FIXED) && ops->port_sync_link)
 943                 err = ops->port_sync_link(chip, port, mode, false);
 944
 945         if (!err && ops->port_set_speed_duplex)
 946                 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
 947                                                  DUPLEX_UNFORCED);
 948         mv88e6xxx_reg_unlock(chip);
 949
 950         if (err)
 951                 dev_err(chip->dev,
 952                         "p%d: failed to force MAC link down\n", port);
 953 }
 954
 955 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
 956                                   unsigned int mode, phy_interface_t interface,
 957                                   struct phy_device *phydev,
 958                                   int speed, int duplex,
 959                                   bool tx_pause, bool rx_pause)
 960 {
 961         struct mv88e6xxx_chip *chip = ds->priv;
 962         const struct mv88e6xxx_ops *ops;
 963         int err = 0;
 964
 965         ops = chip->info->ops;
 966
 967         mv88e6xxx_reg_lock(chip);
 968         /* Configure and force the link up if we know that the port may not
 969          * automatically updated by the switch or if we are using fixed-link
 970          * mode.
 971          */
 972         if (!mv88e6xxx_port_ppu_updates(chip, port) ||
 973             mode == MLO_AN_FIXED) {
 974                 if (ops->port_set_speed_duplex) {
 975                         err = ops->port_set_speed_duplex(chip, port,
 976                                                          speed, duplex);
 977                         if (err && err != -EOPNOTSUPP)
 978                                 goto error;
 979                 }
 980
 981                 if (ops->port_sync_link)
 982                         err = ops->port_sync_link(chip, port, mode, true);
 983         }
 984 error:
 985         mv88e6xxx_reg_unlock(chip);
 986
 987         if (err && err != -EOPNOTSUPP)
 988                 dev_err(ds->dev,
 989                         "p%d: failed to configure MAC link up\n", port);
 990 }
 991
 992 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 993 {
 994         int err;
 995
 996         if (!chip->info->ops->stats_snapshot)
 997                 return -EOPNOTSUPP;
 998
 999         mv88e6xxx_reg_lock(chip);
1000         err = chip->info->ops->stats_snapshot(chip, port);
1001         mv88e6xxx_reg_unlock(chip);
1002
1003         return err;
1004 }
1005
1006 #define MV88E6XXX_HW_STAT_MAPPER(_fn)                               \
1007         _fn(in_good_octets,             8, 0x00, STATS_TYPE_BANK0), \
1008         _fn(in_bad_octets,              4, 0x02, STATS_TYPE_BANK0), \
1009         _fn(in_unicast,                 4, 0x04, STATS_TYPE_BANK0), \
1010         _fn(in_broadcasts,              4, 0x06, STATS_TYPE_BANK0), \
1011         _fn(in_multicasts,              4, 0x07, STATS_TYPE_BANK0), \
1012         _fn(in_pause,                   4, 0x16, STATS_TYPE_BANK0), \
1013         _fn(in_undersize,               4, 0x18, STATS_TYPE_BANK0), \
1014         _fn(in_fragments,               4, 0x19, STATS_TYPE_BANK0), \
1015         _fn(in_oversize,                4, 0x1a, STATS_TYPE_BANK0), \
1016         _fn(in_jabber,                  4, 0x1b, STATS_TYPE_BANK0), \
1017         _fn(in_rx_error,                4, 0x1c, STATS_TYPE_BANK0), \
1018         _fn(in_fcs_error,               4, 0x1d, STATS_TYPE_BANK0), \
1019         _fn(out_octets,                 8, 0x0e, STATS_TYPE_BANK0), \
1020         _fn(out_unicast,                4, 0x10, STATS_TYPE_BANK0), \
1021         _fn(out_broadcasts,             4, 0x13, STATS_TYPE_BANK0), \
1022         _fn(out_multicasts,             4, 0x12, STATS_TYPE_BANK0), \
1023         _fn(out_pause,                  4, 0x15, STATS_TYPE_BANK0), \
1024         _fn(excessive,                  4, 0x11, STATS_TYPE_BANK0), \
1025         _fn(collisions,                 4, 0x1e, STATS_TYPE_BANK0), \
1026         _fn(deferred,                   4, 0x05, STATS_TYPE_BANK0), \
1027         _fn(single,                     4, 0x14, STATS_TYPE_BANK0), \
1028         _fn(multiple,                   4, 0x17, STATS_TYPE_BANK0), \
1029         _fn(out_fcs_error,              4, 0x03, STATS_TYPE_BANK0), \
1030         _fn(late,                       4, 0x1f, STATS_TYPE_BANK0), \
1031         _fn(hist_64bytes,               4, 0x08, STATS_TYPE_BANK0), \
1032         _fn(hist_65_127bytes,           4, 0x09, STATS_TYPE_BANK0), \
1033         _fn(hist_128_255bytes,          4, 0x0a, STATS_TYPE_BANK0), \
1034         _fn(hist_256_511bytes,          4, 0x0b, STATS_TYPE_BANK0), \
1035         _fn(hist_512_1023bytes,         4, 0x0c, STATS_TYPE_BANK0), \
1036         _fn(hist_1024_max_bytes,        4, 0x0d, STATS_TYPE_BANK0), \
1037         _fn(sw_in_discards,             4, 0x10, STATS_TYPE_PORT), \
1038         _fn(sw_in_filtered,             2, 0x12, STATS_TYPE_PORT), \
1039         _fn(sw_out_filtered,            2, 0x13, STATS_TYPE_PORT), \
1040         _fn(in_discards,                4, 0x00, STATS_TYPE_BANK1), \
1041         _fn(in_filtered,                4, 0x01, STATS_TYPE_BANK1), \
1042         _fn(in_accepted,                4, 0x02, STATS_TYPE_BANK1), \
1043         _fn(in_bad_accepted,            4, 0x03, STATS_TYPE_BANK1), \
1044         _fn(in_good_avb_class_a,        4, 0x04, STATS_TYPE_BANK1), \
1045         _fn(in_good_avb_class_b,        4, 0x05, STATS_TYPE_BANK1), \
1046         _fn(in_bad_avb_class_a,         4, 0x06, STATS_TYPE_BANK1), \
1047         _fn(in_bad_avb_class_b,         4, 0x07, STATS_TYPE_BANK1), \
1048         _fn(tcam_counter_0,             4, 0x08, STATS_TYPE_BANK1), \
1049         _fn(tcam_counter_1,             4, 0x09, STATS_TYPE_BANK1), \
1050         _fn(tcam_counter_2,             4, 0x0a, STATS_TYPE_BANK1), \
1051         _fn(tcam_counter_3,             4, 0x0b, STATS_TYPE_BANK1), \
1052         _fn(in_da_unknown,              4, 0x0e, STATS_TYPE_BANK1), \
1053         _fn(in_management,              4, 0x0f, STATS_TYPE_BANK1), \
1054         _fn(out_queue_0,                4, 0x10, STATS_TYPE_BANK1), \
1055         _fn(out_queue_1,                4, 0x11, STATS_TYPE_BANK1), \
1056         _fn(out_queue_2,                4, 0x12, STATS_TYPE_BANK1), \
1057         _fn(out_queue_3,                4, 0x13, STATS_TYPE_BANK1), \
1058         _fn(out_queue_4,                4, 0x14, STATS_TYPE_BANK1), \
1059         _fn(out_queue_5,                4, 0x15, STATS_TYPE_BANK1), \
1060         _fn(out_queue_6,                4, 0x16, STATS_TYPE_BANK1), \
1061         _fn(out_queue_7,                4, 0x17, STATS_TYPE_BANK1), \
1062         _fn(out_cut_through,            4, 0x18, STATS_TYPE_BANK1), \
1063         _fn(out_octets_a,               4, 0x1a, STATS_TYPE_BANK1), \
1064         _fn(out_octets_b,               4, 0x1b, STATS_TYPE_BANK1), \
1065         _fn(out_management,             4, 0x1f, STATS_TYPE_BANK1), \
1066         /*  */
1067
1068 #define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \
1069         { #_string, _size, _reg, _type }
1070 static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
1071         MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY)
1072 };
1073
1074 #define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \
1075         MV88E6XXX_HW_STAT_ID_ ## _string
1076 enum mv88e6xxx_hw_stat_id {
1077         MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM)
1078 };
1079
1080 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
1081                                             const struct mv88e6xxx_hw_stat *s,
1082                                             int port, u16 bank1_select,
1083                                             u16 histogram)
1084 {
1085         u32 low;
1086         u32 high = 0;
1087         u16 reg = 0;
1088         int err;
1089         u64 value;
1090
1091         switch (s->type) {
1092         case STATS_TYPE_PORT:
1093                 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
1094                 if (err)
1095                         return U64_MAX;
1096
1097                 low = reg;
1098                 if (s->size == 4) {
1099                         err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
1100                         if (err)
1101                                 return U64_MAX;
1102                         low |= ((u32)reg) << 16;
1103                 }
1104                 break;
1105         case STATS_TYPE_BANK1:
1106                 reg = bank1_select;
1107                 fallthrough;
1108         case STATS_TYPE_BANK0:
1109                 reg |= s->reg | histogram;
1110                 mv88e6xxx_g1_stats_read(chip, reg, &low);
1111                 if (s->size == 8)
1112                         mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
1113                 break;
1114         default:
1115                 return U64_MAX;
1116         }
1117         value = (((u64)high) << 32) | low;
1118         return value;
1119 }
1120
1121 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
1122                                        uint8_t *data, int types)
1123 {
1124         const struct mv88e6xxx_hw_stat *stat;
1125         int i, j;
1126
1127         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1128                 stat = &mv88e6xxx_hw_stats[i];
1129                 if (stat->type & types) {
1130                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
1131                                ETH_GSTRING_LEN);
1132                         j++;
1133                 }
1134         }
1135
1136         return j;
1137 }
1138
1139 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
1140                                        uint8_t *data)
1141 {
1142         return mv88e6xxx_stats_get_strings(chip, data,
1143                                            STATS_TYPE_BANK0 | STATS_TYPE_PORT);
1144 }
1145
1146 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
1147                                        uint8_t *data)
1148 {
1149         return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
1150 }
1151
1152 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
1153                                        uint8_t *data)
1154 {
1155         return mv88e6xxx_stats_get_strings(chip, data,
1156                                            STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
1157 }
1158
1159 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
1160         "atu_member_violation",
1161         "atu_miss_violation",
1162         "atu_full_violation",
1163         "vtu_member_violation",
1164         "vtu_miss_violation",
1165 };
1166
1167 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
1168 {
1169         unsigned int i;
1170
1171         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
1172                 strscpy(data + i * ETH_GSTRING_LEN,
1173                         mv88e6xxx_atu_vtu_stats_strings[i],
1174                         ETH_GSTRING_LEN);
1175 }
1176
1177 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
1178                                   u32 stringset, uint8_t *data)
1179 {
1180         struct mv88e6xxx_chip *chip = ds->priv;
1181         int count = 0;
1182
1183         if (stringset != ETH_SS_STATS)
1184                 return;
1185
1186         mv88e6xxx_reg_lock(chip);
1187
1188         if (chip->info->ops->stats_get_strings)
1189                 count = chip->info->ops->stats_get_strings(chip, data);
1190
1191         if (chip->info->ops->serdes_get_strings) {
1192                 data += count * ETH_GSTRING_LEN;
1193                 count = chip->info->ops->serdes_get_strings(chip, port, data);
1194         }
1195
1196         data += count * ETH_GSTRING_LEN;
1197         mv88e6xxx_atu_vtu_get_strings(data);
1198
1199         mv88e6xxx_reg_unlock(chip);
1200 }
1201
1202 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1203                                           int types)
1204 {
1205         const struct mv88e6xxx_hw_stat *stat;
1206         int i, j;
1207
1208         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1209                 stat = &mv88e6xxx_hw_stats[i];
1210                 if (stat->type & types)
1211                         j++;
1212         }
1213         return j;
1214 }
1215
1216 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1217 {
1218         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1219                                               STATS_TYPE_PORT);
1220 }
1221
1222 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1223 {
1224         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1225 }
1226
1227 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1228 {
1229         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1230                                               STATS_TYPE_BANK1);
1231 }
1232
1233 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1234 {
1235         struct mv88e6xxx_chip *chip = ds->priv;
1236         int serdes_count = 0;
1237         int count = 0;
1238
1239         if (sset != ETH_SS_STATS)
1240                 return 0;
1241
1242         mv88e6xxx_reg_lock(chip);
1243         if (chip->info->ops->stats_get_sset_count)
1244                 count = chip->info->ops->stats_get_sset_count(chip);
1245         if (count < 0)
1246                 goto out;
1247
1248         if (chip->info->ops->serdes_get_sset_count)
1249                 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1250                                                                       port);
1251         if (serdes_count < 0) {
1252                 count = serdes_count;
1253                 goto out;
1254         }
1255         count += serdes_count;
1256         count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1257
1258 out:
1259         mv88e6xxx_reg_unlock(chip);
1260
1261         return count;
1262 }
1263
1264 static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1265                                        const struct mv88e6xxx_hw_stat *stat,
1266                                        uint64_t *data)
1267 {
1268         if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_PORT)))
1269                 return 0;
1270
1271         *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,
1272                                             MV88E6XXX_G1_STATS_OP_HIST_RX);
1273         return 1;
1274 }
1275
1276 static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1277                                        const struct mv88e6xxx_hw_stat *stat,
1278                                        uint64_t *data)
1279 {
1280         if (!(stat->type & STATS_TYPE_BANK0))
1281                 return 0;
1282
1283         *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,
1284                                             MV88E6XXX_G1_STATS_OP_HIST_RX);
1285         return 1;
1286 }
1287
1288 static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1289                                        const struct mv88e6xxx_hw_stat *stat,
1290                                        uint64_t *data)
1291 {
1292         if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1)))
1293                 return 0;
1294
1295         *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1296                                             MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1297                                             MV88E6XXX_G1_STATS_OP_HIST_RX);
1298         return 1;
1299 }
1300
1301 static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1302                                        const struct mv88e6xxx_hw_stat *stat,
1303                                        uint64_t *data)
1304 {
1305         if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1)))
1306                 return 0;
1307
1308         *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1309                                             MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1310                                             0);
1311         return 1;
1312 }
1313
1314 static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1315                                        const struct mv88e6xxx_hw_stat *stat,
1316                                        uint64_t *data)
1317 {
1318         int ret = 0;
1319
1320         if (chip->info->ops->stats_get_stat) {
1321                 mv88e6xxx_reg_lock(chip);
1322                 ret = chip->info->ops->stats_get_stat(chip, port, stat, data);
1323                 mv88e6xxx_reg_unlock(chip);
1324         }
1325
1326         return ret;
1327 }
1328
1329 static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1330                                         uint64_t *data)
1331 {
1332         const struct mv88e6xxx_hw_stat *stat;
1333         size_t i, j;
1334
1335         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1336                 stat = &mv88e6xxx_hw_stats[i];
1337                 j += mv88e6xxx_stats_get_stat(chip, port, stat, &data[j]);
1338         }
1339         return j;
1340 }
1341
1342 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1343                                         uint64_t *data)
1344 {
1345         *data++ = chip->ports[port].atu_member_violation;
1346         *data++ = chip->ports[port].atu_miss_violation;
1347         *data++ = chip->ports[port].atu_full_violation;
1348         *data++ = chip->ports[port].vtu_member_violation;
1349         *data++ = chip->ports[port].vtu_miss_violation;
1350 }
1351
1352 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1353                                 uint64_t *data)
1354 {
1355         size_t count;
1356
1357         count = mv88e6xxx_stats_get_stats(chip, port, data);
1358
1359         mv88e6xxx_reg_lock(chip);
1360         if (chip->info->ops->serdes_get_stats) {
1361                 data += count;
1362                 count = chip->info->ops->serdes_get_stats(chip, port, data);
1363         }
1364         data += count;
1365         mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1366         mv88e6xxx_reg_unlock(chip);
1367 }
1368
1369 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1370                                         uint64_t *data)
1371 {
1372         struct mv88e6xxx_chip *chip = ds->priv;
1373         int ret;
1374
1375         ret = mv88e6xxx_stats_snapshot(chip, port);
1376         if (ret < 0)
1377                 return;
1378
1379         mv88e6xxx_get_stats(chip, port, data);
1380 }
1381
1382 static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port,
1383                                         struct ethtool_eth_mac_stats *mac_stats)
1384 {
1385         struct mv88e6xxx_chip *chip = ds->priv;
1386         int ret;
1387
1388         ret = mv88e6xxx_stats_snapshot(chip, port);
1389         if (ret < 0)
1390                 return;
1391
1392 #define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member)                        \
1393         mv88e6xxx_stats_get_stat(chip, port,                            \
1394                                  &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \
1395                                  &mac_stats->stats._member)
1396
1397         MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK);
1398         MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames);
1399         MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames);
1400         MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK);
1401         MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors);
1402         MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK);
1403         MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions);
1404         MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions);
1405         MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK);
1406         MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK);
1407         MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK);
1408         MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral);
1409         MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK);
1410         MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK);
1411
1412 #undef MV88E6XXX_ETH_MAC_STAT_MAP
1413
1414         mac_stats->stats.FramesTransmittedOK += mac_stats->stats.MulticastFramesXmittedOK;
1415         mac_stats->stats.FramesTransmittedOK += mac_stats->stats.BroadcastFramesXmittedOK;
1416         mac_stats->stats.FramesReceivedOK += mac_stats->stats.MulticastFramesReceivedOK;
1417         mac_stats->stats.FramesReceivedOK += mac_stats->stats.BroadcastFramesReceivedOK;
1418 }
1419
1420 static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port,
1421                                      struct ethtool_rmon_stats *rmon_stats,
1422                                      const struct ethtool_rmon_hist_range **ranges)
1423 {
1424         static const struct ethtool_rmon_hist_range rmon_ranges[] = {
1425                 {   64,    64 },
1426                 {   65,   127 },
1427                 {  128,   255 },
1428                 {  256,   511 },
1429                 {  512,  1023 },
1430                 { 1024, 65535 },
1431                 {}
1432         };
1433         struct mv88e6xxx_chip *chip = ds->priv;
1434         int ret;
1435
1436         ret = mv88e6xxx_stats_snapshot(chip, port);
1437         if (ret < 0)
1438                 return;
1439
1440 #define MV88E6XXX_RMON_STAT_MAP(_id, _member)                           \
1441         mv88e6xxx_stats_get_stat(chip, port,                            \
1442                                  &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \
1443                                  &rmon_stats->stats._member)
1444
1445         MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts);
1446         MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts);
1447         MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments);
1448         MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers);
1449         MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]);
1450         MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]);
1451         MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]);
1452         MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]);
1453         MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]);
1454         MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]);
1455
1456 #undef MV88E6XXX_RMON_STAT_MAP
1457
1458         *ranges = rmon_ranges;
1459 }
1460
1461 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1462 {
1463         struct mv88e6xxx_chip *chip = ds->priv;
1464         int len;
1465
1466         len = 32 * sizeof(u16);
1467         if (chip->info->ops->serdes_get_regs_len)
1468                 len += chip->info->ops->serdes_get_regs_len(chip, port);
1469
1470         return len;
1471 }
1472
1473 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1474                                struct ethtool_regs *regs, void *_p)
1475 {
1476         struct mv88e6xxx_chip *chip = ds->priv;
1477         int err;
1478         u16 reg;
1479         u16 *p = _p;
1480         int i;
1481
1482         regs->version = chip->info->prod_num;
1483
1484         memset(p, 0xff, 32 * sizeof(u16));
1485
1486         mv88e6xxx_reg_lock(chip);
1487
1488         for (i = 0; i < 32; i++) {
1489
1490                 err = mv88e6xxx_port_read(chip, port, i, &reg);
1491                 if (!err)
1492                         p[i] = reg;
1493         }
1494
1495         if (chip->info->ops->serdes_get_regs)
1496                 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1497
1498         mv88e6xxx_reg_unlock(chip);
1499 }
1500
1501 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1502                                  struct ethtool_keee *e)
1503 {
1504         /* Nothing to do on the port's MAC */
1505         return 0;
1506 }
1507
1508 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1509                                  struct ethtool_keee *e)
1510 {
1511         /* Nothing to do on the port's MAC */
1512         return 0;
1513 }
1514
1515 /* Mask of the local ports allowed to receive frames from a given fabric port */
1516 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1517 {
1518         struct dsa_switch *ds = chip->ds;
1519         struct dsa_switch_tree *dst = ds->dst;
1520         struct dsa_port *dp, *other_dp;
1521         bool found = false;
1522         u16 pvlan;
1523
1524         /* dev is a physical switch */
1525         if (dev <= dst->last_switch) {
1526                 list_for_each_entry(dp, &dst->ports, list) {
1527                         if (dp->ds->index == dev && dp->index == port) {
1528                                 /* dp might be a DSA link or a user port, so it
1529                                  * might or might not have a bridge.
1530                                  * Use the "found" variable for both cases.
1531                                  */
1532                                 found = true;
1533                                 break;
1534                         }
1535                 }
1536         /* dev is a virtual bridge */
1537         } else {
1538                 list_for_each_entry(dp, &dst->ports, list) {
1539                         unsigned int bridge_num = dsa_port_bridge_num_get(dp);
1540
1541                         if (!bridge_num)
1542                                 continue;
1543
1544                         if (bridge_num + dst->last_switch != dev)
1545                                 continue;
1546
1547                         found = true;
1548                         break;
1549                 }
1550         }
1551
1552         /* Prevent frames from unknown switch or virtual bridge */
1553         if (!found)
1554                 return 0;
1555
1556         /* Frames from DSA links and CPU ports can egress any local port */
1557         if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1558                 return mv88e6xxx_port_mask(chip);
1559
1560         pvlan = 0;
1561
1562         /* Frames from standalone user ports can only egress on the
1563          * upstream port.
1564          */
1565         if (!dsa_port_bridge_dev_get(dp))
1566                 return BIT(dsa_switch_upstream_port(ds));
1567
1568         /* Frames from bridged user ports can egress any local DSA
1569          * links and CPU ports, as well as any local member of their
1570          * bridge group.
1571          */
1572         dsa_switch_for_each_port(other_dp, ds)
1573                 if (other_dp->type == DSA_PORT_TYPE_CPU ||
1574                     other_dp->type == DSA_PORT_TYPE_DSA ||
1575                     dsa_port_bridge_same(dp, other_dp))
1576                         pvlan |= BIT(other_dp->index);
1577
1578         return pvlan;
1579 }
1580
1581 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1582 {
1583         u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1584
1585         /* prevent frames from going back out of the port they came in on */
1586         output_ports &= ~BIT(port);
1587
1588         return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1589 }
1590
1591 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1592                                          u8 state)
1593 {
1594         struct mv88e6xxx_chip *chip = ds->priv;
1595         int err;
1596
1597         mv88e6xxx_reg_lock(chip);
1598         err = mv88e6xxx_port_set_state(chip, port, state);
1599         mv88e6xxx_reg_unlock(chip);
1600
1601         if (err)
1602                 dev_err(ds->dev, "p%d: failed to update state\n", port);
1603 }
1604
1605 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1606 {
1607         int err;
1608
1609         if (chip->info->ops->ieee_pri_map) {
1610                 err = chip->info->ops->ieee_pri_map(chip);
1611                 if (err)
1612                         return err;
1613         }
1614
1615         if (chip->info->ops->ip_pri_map) {
1616                 err = chip->info->ops->ip_pri_map(chip);
1617                 if (err)
1618                         return err;
1619         }
1620
1621         return 0;
1622 }
1623
1624 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1625 {
1626         struct dsa_switch *ds = chip->ds;
1627         int target, port;
1628         int err;
1629
1630         if (!chip->info->global2_addr)
1631                 return 0;
1632
1633         /* Initialize the routing port to the 32 possible target devices */
1634         for (target = 0; target < 32; target++) {
1635                 port = dsa_routing_port(ds, target);
1636                 if (port == ds->num_ports)
1637                         port = 0x1f;
1638
1639                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1640                 if (err)
1641                         return err;
1642         }
1643
1644         if (chip->info->ops->set_cascade_port) {
1645                 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1646                 err = chip->info->ops->set_cascade_port(chip, port);
1647                 if (err)
1648                         return err;
1649         }
1650
1651         err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1652         if (err)
1653                 return err;
1654
1655         return 0;
1656 }
1657
1658 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1659 {
1660         /* Clear all trunk masks and mapping */
1661         if (chip->info->global2_addr)
1662                 return mv88e6xxx_g2_trunk_clear(chip);
1663
1664         return 0;
1665 }
1666
1667 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1668 {
1669         if (chip->info->ops->rmu_disable)
1670                 return chip->info->ops->rmu_disable(chip);
1671
1672         return 0;
1673 }
1674
1675 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1676 {
1677         if (chip->info->ops->pot_clear)
1678                 return chip->info->ops->pot_clear(chip);
1679
1680         return 0;
1681 }
1682
1683 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1684 {
1685         if (chip->info->ops->mgmt_rsvd2cpu)
1686                 return chip->info->ops->mgmt_rsvd2cpu(chip);
1687
1688         return 0;
1689 }
1690
1691 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1692 {
1693         int err;
1694
1695         err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1696         if (err)
1697                 return err;
1698
1699         /* The chips that have a "learn2all" bit in Global1, ATU
1700          * Control are precisely those whose port registers have a
1701          * Message Port bit in Port Control 1 and hence implement
1702          * ->port_setup_message_port.
1703          */
1704         if (chip->info->ops->port_setup_message_port) {
1705                 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1706                 if (err)
1707                         return err;
1708         }
1709
1710         return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1711 }
1712
1713 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1714 {
1715         int port;
1716         int err;
1717
1718         if (!chip->info->ops->irl_init_all)
1719                 return 0;
1720
1721         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1722                 /* Disable ingress rate limiting by resetting all per port
1723                  * ingress rate limit resources to their initial state.
1724                  */
1725                 err = chip->info->ops->irl_init_all(chip, port);
1726                 if (err)
1727                         return err;
1728         }
1729
1730         return 0;
1731 }
1732
1733 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1734 {
1735         if (chip->info->ops->set_switch_mac) {
1736                 u8 addr[ETH_ALEN];
1737
1738                 eth_random_addr(addr);
1739
1740                 return chip->info->ops->set_switch_mac(chip, addr);
1741         }
1742
1743         return 0;
1744 }
1745
1746 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1747 {
1748         struct dsa_switch_tree *dst = chip->ds->dst;
1749         struct dsa_switch *ds;
1750         struct dsa_port *dp;
1751         u16 pvlan = 0;
1752
1753         if (!mv88e6xxx_has_pvt(chip))
1754                 return 0;
1755
1756         /* Skip the local source device, which uses in-chip port VLAN */
1757         if (dev != chip->ds->index) {
1758                 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1759
1760                 ds = dsa_switch_find(dst->index, dev);
1761                 dp = ds ? dsa_to_port(ds, port) : NULL;
1762                 if (dp && dp->lag) {
1763                         /* As the PVT is used to limit flooding of
1764                          * FORWARD frames, which use the LAG ID as the
1765                          * source port, we must translate dev/port to
1766                          * the special "LAG device" in the PVT, using
1767                          * the LAG ID (one-based) as the port number
1768                          * (zero-based).
1769                          */
1770                         dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1771                         port = dsa_port_lag_id_get(dp) - 1;
1772                 }
1773         }
1774
1775         return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1776 }
1777
1778 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1779 {
1780         int dev, port;
1781         int err;
1782
1783         if (!mv88e6xxx_has_pvt(chip))
1784                 return 0;
1785
1786         /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1787          * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1788          */
1789         err = mv88e6xxx_g2_misc_4_bit_port(chip);
1790         if (err)
1791                 return err;
1792
1793         for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1794                 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1795                         err = mv88e6xxx_pvt_map(chip, dev, port);
1796                         if (err)
1797                                 return err;
1798                 }
1799         }
1800
1801         return 0;
1802 }
1803
1804 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port,
1805                                        u16 fid)
1806 {
1807         if (dsa_to_port(chip->ds, port)->lag)
1808                 /* Hardware is incapable of fast-aging a LAG through a
1809                  * regular ATU move operation. Until we have something
1810                  * more fancy in place this is a no-op.
1811                  */
1812                 return -EOPNOTSUPP;
1813
1814         return mv88e6xxx_g1_atu_remove(chip, fid, port, false);
1815 }
1816
1817 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1818 {
1819         struct mv88e6xxx_chip *chip = ds->priv;
1820         int err;
1821
1822         mv88e6xxx_reg_lock(chip);
1823         err = mv88e6xxx_port_fast_age_fid(chip, port, 0);
1824         mv88e6xxx_reg_unlock(chip);
1825
1826         if (err)
1827                 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n",
1828                         port, err);
1829 }
1830
1831 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1832 {
1833         if (!mv88e6xxx_max_vid(chip))
1834                 return 0;
1835
1836         return mv88e6xxx_g1_vtu_flush(chip);
1837 }
1838
1839 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1840                              struct mv88e6xxx_vtu_entry *entry)
1841 {
1842         int err;
1843
1844         if (!chip->info->ops->vtu_getnext)
1845                 return -EOPNOTSUPP;
1846
1847         entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1848         entry->valid = false;
1849
1850         err = chip->info->ops->vtu_getnext(chip, entry);
1851
1852         if (entry->vid != vid)
1853                 entry->valid = false;
1854
1855         return err;
1856 }
1857
1858 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1859                        int (*cb)(struct mv88e6xxx_chip *chip,
1860                                  const struct mv88e6xxx_vtu_entry *entry,
1861                                  void *priv),
1862                        void *priv)
1863 {
1864         struct mv88e6xxx_vtu_entry entry = {
1865                 .vid = mv88e6xxx_max_vid(chip),
1866                 .valid = false,
1867         };
1868         int err;
1869
1870         if (!chip->info->ops->vtu_getnext)
1871                 return -EOPNOTSUPP;
1872
1873         do {
1874                 err = chip->info->ops->vtu_getnext(chip, &entry);
1875                 if (err)
1876                         return err;
1877
1878                 if (!entry.valid)
1879                         break;
1880
1881                 err = cb(chip, &entry, priv);
1882                 if (err)
1883                         return err;
1884         } while (entry.vid < mv88e6xxx_max_vid(chip));
1885
1886         return 0;
1887 }
1888
1889 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1890                                    struct mv88e6xxx_vtu_entry *entry)
1891 {
1892         if (!chip->info->ops->vtu_loadpurge)
1893                 return -EOPNOTSUPP;
1894
1895         return chip->info->ops->vtu_loadpurge(chip, entry);
1896 }
1897
1898 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1899                                   const struct mv88e6xxx_vtu_entry *entry,
1900                                   void *_fid_bitmap)
1901 {
1902         unsigned long *fid_bitmap = _fid_bitmap;
1903
1904         set_bit(entry->fid, fid_bitmap);
1905         return 0;
1906 }
1907
1908 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1909 {
1910         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1911
1912         /* Every FID has an associated VID, so walking the VTU
1913          * will discover the full set of FIDs in use.
1914          */
1915         return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
1916 }
1917
1918 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1919 {
1920         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1921         int err;
1922
1923         err = mv88e6xxx_fid_map(chip, fid_bitmap);
1924         if (err)
1925                 return err;
1926
1927         *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID);
1928         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1929                 return -ENOSPC;
1930
1931         /* Clear the database */
1932         return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1933 }
1934
1935 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1936                                    struct mv88e6xxx_stu_entry *entry)
1937 {
1938         if (!chip->info->ops->stu_loadpurge)
1939                 return -EOPNOTSUPP;
1940
1941         return chip->info->ops->stu_loadpurge(chip, entry);
1942 }
1943
1944 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip)
1945 {
1946         struct mv88e6xxx_stu_entry stu = {
1947                 .valid = true,
1948                 .sid = 0
1949         };
1950
1951         if (!mv88e6xxx_has_stu(chip))
1952                 return 0;
1953
1954         /* Make sure that SID 0 is always valid. This is used by VTU
1955          * entries that do not make use of the STU, e.g. when creating
1956          * a VLAN upper on a port that is also part of a VLAN
1957          * filtering bridge.
1958          */
1959         return mv88e6xxx_stu_loadpurge(chip, &stu);
1960 }
1961
1962 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid)
1963 {
1964         DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 };
1965         struct mv88e6xxx_mst *mst;
1966
1967         __set_bit(0, busy);
1968
1969         list_for_each_entry(mst, &chip->msts, node)
1970                 __set_bit(mst->stu.sid, busy);
1971
1972         *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID);
1973
1974         return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0;
1975 }
1976
1977 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid)
1978 {
1979         struct mv88e6xxx_mst *mst, *tmp;
1980         int err;
1981
1982         if (!sid)
1983                 return 0;
1984
1985         list_for_each_entry_safe(mst, tmp, &chip->msts, node) {
1986                 if (mst->stu.sid != sid)
1987                         continue;
1988
1989                 if (!refcount_dec_and_test(&mst->refcnt))
1990                         return 0;
1991
1992                 mst->stu.valid = false;
1993                 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1994                 if (err) {
1995                         refcount_set(&mst->refcnt, 1);
1996                         return err;
1997                 }
1998
1999                 list_del(&mst->node);
2000                 kfree(mst);
2001                 return 0;
2002         }
2003
2004         return -ENOENT;
2005 }
2006
2007 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br,
2008                              u16 msti, u8 *sid)
2009 {
2010         struct mv88e6xxx_mst *mst;
2011         int err, i;
2012
2013         if (!mv88e6xxx_has_stu(chip)) {
2014                 err = -EOPNOTSUPP;
2015                 goto err;
2016         }
2017
2018         if (!msti) {
2019                 *sid = 0;
2020                 return 0;
2021         }
2022
2023         list_for_each_entry(mst, &chip->msts, node) {
2024                 if (mst->br == br && mst->msti == msti) {
2025                         refcount_inc(&mst->refcnt);
2026                         *sid = mst->stu.sid;
2027                         return 0;
2028                 }
2029         }
2030
2031         err = mv88e6xxx_sid_get(chip, sid);
2032         if (err)
2033                 goto err;
2034
2035         mst = kzalloc(sizeof(*mst), GFP_KERNEL);
2036         if (!mst) {
2037                 err = -ENOMEM;
2038                 goto err;
2039         }
2040
2041         INIT_LIST_HEAD(&mst->node);
2042         refcount_set(&mst->refcnt, 1);
2043         mst->br = br;
2044         mst->msti = msti;
2045         mst->stu.valid = true;
2046         mst->stu.sid = *sid;
2047
2048         /* The bridge starts out all ports in the disabled state. But
2049          * a STU state of disabled means to go by the port-global
2050          * state. So we set all user port's initial state to blocking,
2051          * to match the bridge's behavior.
2052          */
2053         for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
2054                 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ?
2055                         MV88E6XXX_PORT_CTL0_STATE_BLOCKING :
2056                         MV88E6XXX_PORT_CTL0_STATE_DISABLED;
2057
2058         err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2059         if (err)
2060                 goto err_free;
2061
2062         list_add_tail(&mst->node, &chip->msts);
2063         return 0;
2064
2065 err_free:
2066         kfree(mst);
2067 err:
2068         return err;
2069 }
2070
2071 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port,
2072                                         const struct switchdev_mst_state *st)
2073 {
2074         struct dsa_port *dp = dsa_to_port(ds, port);
2075         struct mv88e6xxx_chip *chip = ds->priv;
2076         struct mv88e6xxx_mst *mst;
2077         u8 state;
2078         int err;
2079
2080         if (!mv88e6xxx_has_stu(chip))
2081                 return -EOPNOTSUPP;
2082
2083         switch (st->state) {
2084         case BR_STATE_DISABLED:
2085         case BR_STATE_BLOCKING:
2086         case BR_STATE_LISTENING:
2087                 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
2088                 break;
2089         case BR_STATE_LEARNING:
2090                 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
2091                 break;
2092         case BR_STATE_FORWARDING:
2093                 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2094                 break;
2095         default:
2096                 return -EINVAL;
2097         }
2098
2099         list_for_each_entry(mst, &chip->msts, node) {
2100                 if (mst->br == dsa_port_bridge_dev_get(dp) &&
2101                     mst->msti == st->msti) {
2102                         if (mst->stu.state[port] == state)
2103                                 return 0;
2104
2105                         mst->stu.state[port] = state;
2106                         mv88e6xxx_reg_lock(chip);
2107                         err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2108                         mv88e6xxx_reg_unlock(chip);
2109                         return err;
2110                 }
2111         }
2112
2113         return -ENOENT;
2114 }
2115
2116 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
2117                                         u16 vid)
2118 {
2119         struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
2120         struct mv88e6xxx_chip *chip = ds->priv;
2121         struct mv88e6xxx_vtu_entry vlan;
2122         int err;
2123
2124         /* DSA and CPU ports have to be members of multiple vlans */
2125         if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
2126                 return 0;
2127
2128         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2129         if (err)
2130                 return err;
2131
2132         if (!vlan.valid)
2133                 return 0;
2134
2135         dsa_switch_for_each_user_port(other_dp, ds) {
2136                 struct net_device *other_br;
2137
2138                 if (vlan.member[other_dp->index] ==
2139                     MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2140                         continue;
2141
2142                 if (dsa_port_bridge_same(dp, other_dp))
2143                         break; /* same bridge, check next VLAN */
2144
2145                 other_br = dsa_port_bridge_dev_get(other_dp);
2146                 if (!other_br)
2147                         continue;
2148
2149                 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
2150                         port, vlan.vid, other_dp->index, netdev_name(other_br));
2151                 return -EOPNOTSUPP;
2152         }
2153
2154         return 0;
2155 }
2156
2157 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
2158 {
2159         struct dsa_port *dp = dsa_to_port(chip->ds, port);
2160         struct net_device *br = dsa_port_bridge_dev_get(dp);
2161         struct mv88e6xxx_port *p = &chip->ports[port];
2162         u16 pvid = MV88E6XXX_VID_STANDALONE;
2163         bool drop_untagged = false;
2164         int err;
2165
2166         if (br) {
2167                 if (br_vlan_enabled(br)) {
2168                         pvid = p->bridge_pvid.vid;
2169                         drop_untagged = !p->bridge_pvid.valid;
2170                 } else {
2171                         pvid = MV88E6XXX_VID_BRIDGED;
2172                 }
2173         }
2174
2175         err = mv88e6xxx_port_set_pvid(chip, port, pvid);
2176         if (err)
2177                 return err;
2178
2179         return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
2180 }
2181
2182 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2183                                          bool vlan_filtering,
2184                                          struct netlink_ext_ack *extack)
2185 {
2186         struct mv88e6xxx_chip *chip = ds->priv;
2187         u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
2188                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
2189         int err;
2190
2191         if (!mv88e6xxx_max_vid(chip))
2192                 return -EOPNOTSUPP;
2193
2194         mv88e6xxx_reg_lock(chip);
2195
2196         err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
2197         if (err)
2198                 goto unlock;
2199
2200         err = mv88e6xxx_port_commit_pvid(chip, port);
2201         if (err)
2202                 goto unlock;
2203
2204 unlock:
2205         mv88e6xxx_reg_unlock(chip);
2206
2207         return err;
2208 }
2209
2210 static int
2211 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2212                             const struct switchdev_obj_port_vlan *vlan)
2213 {
2214         struct mv88e6xxx_chip *chip = ds->priv;
2215         int err;
2216
2217         if (!mv88e6xxx_max_vid(chip))
2218                 return -EOPNOTSUPP;
2219
2220         /* If the requested port doesn't belong to the same bridge as the VLAN
2221          * members, do not support it (yet) and fallback to software VLAN.
2222          */
2223         mv88e6xxx_reg_lock(chip);
2224         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
2225         mv88e6xxx_reg_unlock(chip);
2226
2227         return err;
2228 }
2229
2230 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2231                                         const unsigned char *addr, u16 vid,
2232                                         u8 state)
2233 {
2234         struct mv88e6xxx_atu_entry entry;
2235         struct mv88e6xxx_vtu_entry vlan;
2236         u16 fid;
2237         int err;
2238
2239         /* Ports have two private address databases: one for when the port is
2240          * standalone and one for when the port is under a bridge and the
2241          * 802.1Q mode is disabled. When the port is standalone, DSA wants its
2242          * address database to remain 100% empty, so we never load an ATU entry
2243          * into a standalone port's database. Therefore, translate the null
2244          * VLAN ID into the port's database used for VLAN-unaware bridging.
2245          */
2246         if (vid == 0) {
2247                 fid = MV88E6XXX_FID_BRIDGED;
2248         } else {
2249                 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2250                 if (err)
2251                         return err;
2252
2253                 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
2254                 if (!vlan.valid)
2255                         return -EOPNOTSUPP;
2256
2257                 fid = vlan.fid;
2258         }
2259
2260         entry.state = 0;
2261         ether_addr_copy(entry.mac, addr);
2262         eth_addr_dec(entry.mac);
2263
2264         err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
2265         if (err)
2266                 return err;
2267
2268         /* Initialize a fresh ATU entry if it isn't found */
2269         if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
2270                 memset(&entry, 0, sizeof(entry));
2271                 ether_addr_copy(entry.mac, addr);
2272         }
2273
2274         /* Purge the ATU entry only if no port is using it anymore */
2275         if (!state) {
2276                 entry.portvec &= ~BIT(port);
2277                 if (!entry.portvec)
2278                         entry.state = 0;
2279         } else {
2280                 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
2281                         entry.portvec = BIT(port);
2282                 else
2283                         entry.portvec |= BIT(port);
2284
2285                 entry.state = state;
2286         }
2287
2288         return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
2289 }
2290
2291 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
2292                                   const struct mv88e6xxx_policy *policy)
2293 {
2294         enum mv88e6xxx_policy_mapping mapping = policy->mapping;
2295         enum mv88e6xxx_policy_action action = policy->action;
2296         const u8 *addr = policy->addr;
2297         u16 vid = policy->vid;
2298         u8 state;
2299         int err;
2300         int id;
2301
2302         if (!chip->info->ops->port_set_policy)
2303                 return -EOPNOTSUPP;
2304
2305         switch (mapping) {
2306         case MV88E6XXX_POLICY_MAPPING_DA:
2307         case MV88E6XXX_POLICY_MAPPING_SA:
2308                 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2309                         state = 0; /* Dissociate the port and address */
2310                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2311                          is_multicast_ether_addr(addr))
2312                         state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
2313                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2314                          is_unicast_ether_addr(addr))
2315                         state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
2316                 else
2317                         return -EOPNOTSUPP;
2318
2319                 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2320                                                    state);
2321                 if (err)
2322                         return err;
2323                 break;
2324         default:
2325                 return -EOPNOTSUPP;
2326         }
2327
2328         /* Skip the port's policy clearing if the mapping is still in use */
2329         if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2330                 idr_for_each_entry(&chip->policies, policy, id)
2331                         if (policy->port == port &&
2332                             policy->mapping == mapping &&
2333                             policy->action != action)
2334                                 return 0;
2335
2336         return chip->info->ops->port_set_policy(chip, port, mapping, action);
2337 }
2338
2339 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
2340                                    struct ethtool_rx_flow_spec *fs)
2341 {
2342         struct ethhdr *mac_entry = &fs->h_u.ether_spec;
2343         struct ethhdr *mac_mask = &fs->m_u.ether_spec;
2344         enum mv88e6xxx_policy_mapping mapping;
2345         enum mv88e6xxx_policy_action action;
2346         struct mv88e6xxx_policy *policy;
2347         u16 vid = 0;
2348         u8 *addr;
2349         int err;
2350         int id;
2351
2352         if (fs->location != RX_CLS_LOC_ANY)
2353                 return -EINVAL;
2354
2355         if (fs->ring_cookie == RX_CLS_FLOW_DISC)
2356                 action = MV88E6XXX_POLICY_ACTION_DISCARD;
2357         else
2358                 return -EOPNOTSUPP;
2359
2360         switch (fs->flow_type & ~FLOW_EXT) {
2361         case ETHER_FLOW:
2362                 if (!is_zero_ether_addr(mac_mask->h_dest) &&
2363                     is_zero_ether_addr(mac_mask->h_source)) {
2364                         mapping = MV88E6XXX_POLICY_MAPPING_DA;
2365                         addr = mac_entry->h_dest;
2366                 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
2367                     !is_zero_ether_addr(mac_mask->h_source)) {
2368                         mapping = MV88E6XXX_POLICY_MAPPING_SA;
2369                         addr = mac_entry->h_source;
2370                 } else {
2371                         /* Cannot support DA and SA mapping in the same rule */
2372                         return -EOPNOTSUPP;
2373                 }
2374                 break;
2375         default:
2376                 return -EOPNOTSUPP;
2377         }
2378
2379         if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
2380                 if (fs->m_ext.vlan_tci != htons(0xffff))
2381                         return -EOPNOTSUPP;
2382                 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
2383         }
2384
2385         idr_for_each_entry(&chip->policies, policy, id) {
2386                 if (policy->port == port && policy->mapping == mapping &&
2387                     policy->action == action && policy->vid == vid &&
2388                     ether_addr_equal(policy->addr, addr))
2389                         return -EEXIST;
2390         }
2391
2392         policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
2393         if (!policy)
2394                 return -ENOMEM;
2395
2396         fs->location = 0;
2397         err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
2398                             GFP_KERNEL);
2399         if (err) {
2400                 devm_kfree(chip->dev, policy);
2401                 return err;
2402         }
2403
2404         memcpy(&policy->fs, fs, sizeof(*fs));
2405         ether_addr_copy(policy->addr, addr);
2406         policy->mapping = mapping;
2407         policy->action = action;
2408         policy->port = port;
2409         policy->vid = vid;
2410
2411         err = mv88e6xxx_policy_apply(chip, port, policy);
2412         if (err) {
2413                 idr_remove(&chip->policies, fs->location);
2414                 devm_kfree(chip->dev, policy);
2415                 return err;
2416         }
2417
2418         return 0;
2419 }
2420
2421 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
2422                                struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
2423 {
2424         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2425         struct mv88e6xxx_chip *chip = ds->priv;
2426         struct mv88e6xxx_policy *policy;
2427         int err;
2428         int id;
2429
2430         mv88e6xxx_reg_lock(chip);
2431
2432         switch (rxnfc->cmd) {
2433         case ETHTOOL_GRXCLSRLCNT:
2434                 rxnfc->data = 0;
2435                 rxnfc->data |= RX_CLS_LOC_SPECIAL;
2436                 rxnfc->rule_cnt = 0;
2437                 idr_for_each_entry(&chip->policies, policy, id)
2438                         if (policy->port == port)
2439                                 rxnfc->rule_cnt++;
2440                 err = 0;
2441                 break;
2442         case ETHTOOL_GRXCLSRULE:
2443                 err = -ENOENT;
2444                 policy = idr_find(&chip->policies, fs->location);
2445                 if (policy) {
2446                         memcpy(fs, &policy->fs, sizeof(*fs));
2447                         err = 0;
2448                 }
2449                 break;
2450         case ETHTOOL_GRXCLSRLALL:
2451                 rxnfc->data = 0;
2452                 rxnfc->rule_cnt = 0;
2453                 idr_for_each_entry(&chip->policies, policy, id)
2454                         if (policy->port == port)
2455                                 rule_locs[rxnfc->rule_cnt++] = id;
2456                 err = 0;
2457                 break;
2458         default:
2459                 err = -EOPNOTSUPP;
2460                 break;
2461         }
2462
2463         mv88e6xxx_reg_unlock(chip);
2464
2465         return err;
2466 }
2467
2468 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
2469                                struct ethtool_rxnfc *rxnfc)
2470 {
2471         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2472         struct mv88e6xxx_chip *chip = ds->priv;
2473         struct mv88e6xxx_policy *policy;
2474         int err;
2475
2476         mv88e6xxx_reg_lock(chip);
2477
2478         switch (rxnfc->cmd) {
2479         case ETHTOOL_SRXCLSRLINS:
2480                 err = mv88e6xxx_policy_insert(chip, port, fs);
2481                 break;
2482         case ETHTOOL_SRXCLSRLDEL:
2483                 err = -ENOENT;
2484                 policy = idr_remove(&chip->policies, fs->location);
2485                 if (policy) {
2486                         policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2487                         err = mv88e6xxx_policy_apply(chip, port, policy);
2488                         devm_kfree(chip->dev, policy);
2489                 }
2490                 break;
2491         default:
2492                 err = -EOPNOTSUPP;
2493                 break;
2494         }
2495
2496         mv88e6xxx_reg_unlock(chip);
2497
2498         return err;
2499 }
2500
2501 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2502                                         u16 vid)
2503 {
2504         u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2505         u8 broadcast[ETH_ALEN];
2506
2507         eth_broadcast_addr(broadcast);
2508
2509         return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2510 }
2511
2512 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2513 {
2514         int port;
2515         int err;
2516
2517         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2518                 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2519                 struct net_device *brport;
2520
2521                 if (dsa_is_unused_port(chip->ds, port))
2522                         continue;
2523
2524                 brport = dsa_port_to_bridge_port(dp);
2525                 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2526                         /* Skip bridged user ports where broadcast
2527                          * flooding is disabled.
2528                          */
2529                         continue;
2530
2531                 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2532                 if (err)
2533                         return err;
2534         }
2535
2536         return 0;
2537 }
2538
2539 struct mv88e6xxx_port_broadcast_sync_ctx {
2540         int port;
2541         bool flood;
2542 };
2543
2544 static int
2545 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2546                                    const struct mv88e6xxx_vtu_entry *vlan,
2547                                    void *_ctx)
2548 {
2549         struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2550         u8 broadcast[ETH_ALEN];
2551         u8 state;
2552
2553         if (ctx->flood)
2554                 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2555         else
2556                 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2557
2558         eth_broadcast_addr(broadcast);
2559
2560         return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2561                                             vlan->vid, state);
2562 }
2563
2564 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2565                                          bool flood)
2566 {
2567         struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2568                 .port = port,
2569                 .flood = flood,
2570         };
2571         struct mv88e6xxx_vtu_entry vid0 = {
2572                 .vid = 0,
2573         };
2574         int err;
2575
2576         /* Update the port's private database... */
2577         err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2578         if (err)
2579                 return err;
2580
2581         /* ...and the database for all VLANs. */
2582         return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2583                                   &ctx);
2584 }
2585
2586 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2587                                     u16 vid, u8 member, bool warn)
2588 {
2589         const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2590         struct mv88e6xxx_vtu_entry vlan;
2591         int i, err;
2592
2593         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2594         if (err)
2595                 return err;
2596
2597         if (!vlan.valid) {
2598                 memset(&vlan, 0, sizeof(vlan));
2599
2600                 if (vid == MV88E6XXX_VID_STANDALONE)
2601                         vlan.policy = true;
2602
2603                 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2604                 if (err)
2605                         return err;
2606
2607                 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2608                         if (i == port)
2609                                 vlan.member[i] = member;
2610                         else
2611                                 vlan.member[i] = non_member;
2612
2613                 vlan.vid = vid;
2614                 vlan.valid = true;
2615
2616                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2617                 if (err)
2618                         return err;
2619
2620                 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2621                 if (err)
2622                         return err;
2623         } else if (vlan.member[port] != member) {
2624                 vlan.member[port] = member;
2625
2626                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2627                 if (err)
2628                         return err;
2629         } else if (warn) {
2630                 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2631                          port, vid);
2632         }
2633
2634         return 0;
2635 }
2636
2637 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2638                                    const struct switchdev_obj_port_vlan *vlan,
2639                                    struct netlink_ext_ack *extack)
2640 {
2641         struct mv88e6xxx_chip *chip = ds->priv;
2642         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2643         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2644         struct mv88e6xxx_port *p = &chip->ports[port];
2645         bool warn;
2646         u8 member;
2647         int err;
2648
2649         if (!vlan->vid)
2650                 return 0;
2651
2652         err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2653         if (err)
2654                 return err;
2655
2656         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2657                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2658         else if (untagged)
2659                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2660         else
2661                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2662
2663         /* net/dsa/user.c will call dsa_port_vlan_add() for the affected port
2664          * and then the CPU port. Do not warn for duplicates for the CPU port.
2665          */
2666         warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2667
2668         mv88e6xxx_reg_lock(chip);
2669
2670         err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2671         if (err) {
2672                 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2673                         vlan->vid, untagged ? 'u' : 't');
2674                 goto out;
2675         }
2676
2677         if (pvid) {
2678                 p->bridge_pvid.vid = vlan->vid;
2679                 p->bridge_pvid.valid = true;
2680
2681                 err = mv88e6xxx_port_commit_pvid(chip, port);
2682                 if (err)
2683                         goto out;
2684         } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
2685                 /* The old pvid was reinstalled as a non-pvid VLAN */
2686                 p->bridge_pvid.valid = false;
2687
2688                 err = mv88e6xxx_port_commit_pvid(chip, port);
2689                 if (err)
2690                         goto out;
2691         }
2692
2693 out:
2694         mv88e6xxx_reg_unlock(chip);
2695
2696         return err;
2697 }
2698
2699 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2700                                      int port, u16 vid)
2701 {
2702         struct mv88e6xxx_vtu_entry vlan;
2703         int i, err;
2704
2705         if (!vid)
2706                 return 0;
2707
2708         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2709         if (err)
2710                 return err;
2711
2712         /* If the VLAN doesn't exist in hardware or the port isn't a member,
2713          * tell switchdev that this VLAN is likely handled in software.
2714          */
2715         if (!vlan.valid ||
2716             vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2717                 return -EOPNOTSUPP;
2718
2719         vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2720
2721         /* keep the VLAN unless all ports are excluded */
2722         vlan.valid = false;
2723         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2724                 if (vlan.member[i] !=
2725                     MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2726                         vlan.valid = true;
2727                         break;
2728                 }
2729         }
2730
2731         err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2732         if (err)
2733                 return err;
2734
2735         if (!vlan.valid) {
2736                 err = mv88e6xxx_mst_put(chip, vlan.sid);
2737                 if (err)
2738                         return err;
2739         }
2740
2741         return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2742 }
2743
2744 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2745                                    const struct switchdev_obj_port_vlan *vlan)
2746 {
2747         struct mv88e6xxx_chip *chip = ds->priv;
2748         struct mv88e6xxx_port *p = &chip->ports[port];
2749         int err = 0;
2750         u16 pvid;
2751
2752         if (!mv88e6xxx_max_vid(chip))
2753                 return -EOPNOTSUPP;
2754
2755         /* The ATU removal procedure needs the FID to be mapped in the VTU,
2756          * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA
2757          * switchdev workqueue to ensure that all FDB entries are deleted
2758          * before we remove the VLAN.
2759          */
2760         dsa_flush_workqueue();
2761
2762         mv88e6xxx_reg_lock(chip);
2763
2764         err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2765         if (err)
2766                 goto unlock;
2767
2768         err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2769         if (err)
2770                 goto unlock;
2771
2772         if (vlan->vid == pvid) {
2773                 p->bridge_pvid.valid = false;
2774
2775                 err = mv88e6xxx_port_commit_pvid(chip, port);
2776                 if (err)
2777                         goto unlock;
2778         }
2779
2780 unlock:
2781         mv88e6xxx_reg_unlock(chip);
2782
2783         return err;
2784 }
2785
2786 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid)
2787 {
2788         struct mv88e6xxx_chip *chip = ds->priv;
2789         struct mv88e6xxx_vtu_entry vlan;
2790         int err;
2791
2792         mv88e6xxx_reg_lock(chip);
2793
2794         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2795         if (err)
2796                 goto unlock;
2797
2798         err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid);
2799
2800 unlock:
2801         mv88e6xxx_reg_unlock(chip);
2802
2803         return err;
2804 }
2805
2806 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds,
2807                                    struct dsa_bridge bridge,
2808                                    const struct switchdev_vlan_msti *msti)
2809 {
2810         struct mv88e6xxx_chip *chip = ds->priv;
2811         struct mv88e6xxx_vtu_entry vlan;
2812         u8 old_sid, new_sid;
2813         int err;
2814
2815         if (!mv88e6xxx_has_stu(chip))
2816                 return -EOPNOTSUPP;
2817
2818         mv88e6xxx_reg_lock(chip);
2819
2820         err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan);
2821         if (err)
2822                 goto unlock;
2823
2824         if (!vlan.valid) {
2825                 err = -EINVAL;
2826                 goto unlock;
2827         }
2828
2829         old_sid = vlan.sid;
2830
2831         err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid);
2832         if (err)
2833                 goto unlock;
2834
2835         if (new_sid != old_sid) {
2836                 vlan.sid = new_sid;
2837
2838                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2839                 if (err) {
2840                         mv88e6xxx_mst_put(chip, new_sid);
2841                         goto unlock;
2842                 }
2843         }
2844
2845         err = mv88e6xxx_mst_put(chip, old_sid);
2846
2847 unlock:
2848         mv88e6xxx_reg_unlock(chip);
2849         return err;
2850 }
2851
2852 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2853                                   const unsigned char *addr, u16 vid,
2854                                   struct dsa_db db)
2855 {
2856         struct mv88e6xxx_chip *chip = ds->priv;
2857         int err;
2858
2859         mv88e6xxx_reg_lock(chip);
2860         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2861                                            MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2862         mv88e6xxx_reg_unlock(chip);
2863
2864         return err;
2865 }
2866
2867 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2868                                   const unsigned char *addr, u16 vid,
2869                                   struct dsa_db db)
2870 {
2871         struct mv88e6xxx_chip *chip = ds->priv;
2872         int err;
2873
2874         mv88e6xxx_reg_lock(chip);
2875         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2876         mv88e6xxx_reg_unlock(chip);
2877
2878         return err;
2879 }
2880
2881 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2882                                       u16 fid, u16 vid, int port,
2883                                       dsa_fdb_dump_cb_t *cb, void *data)
2884 {
2885         struct mv88e6xxx_atu_entry addr;
2886         bool is_static;
2887         int err;
2888
2889         addr.state = 0;
2890         eth_broadcast_addr(addr.mac);
2891
2892         do {
2893                 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2894                 if (err)
2895                         return err;
2896
2897                 if (!addr.state)
2898                         break;
2899
2900                 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2901                         continue;
2902
2903                 if (!is_unicast_ether_addr(addr.mac))
2904                         continue;
2905
2906                 is_static = (addr.state ==
2907                              MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2908                 err = cb(addr.mac, vid, is_static, data);
2909                 if (err)
2910                         return err;
2911         } while (!is_broadcast_ether_addr(addr.mac));
2912
2913         return err;
2914 }
2915
2916 struct mv88e6xxx_port_db_dump_vlan_ctx {
2917         int port;
2918         dsa_fdb_dump_cb_t *cb;
2919         void *data;
2920 };
2921
2922 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2923                                        const struct mv88e6xxx_vtu_entry *entry,
2924                                        void *_data)
2925 {
2926         struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2927
2928         return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2929                                           ctx->port, ctx->cb, ctx->data);
2930 }
2931
2932 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2933                                   dsa_fdb_dump_cb_t *cb, void *data)
2934 {
2935         struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2936                 .port = port,
2937                 .cb = cb,
2938                 .data = data,
2939         };
2940         u16 fid;
2941         int err;
2942
2943         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2944         err = mv88e6xxx_port_get_fid(chip, port, &fid);
2945         if (err)
2946                 return err;
2947
2948         err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2949         if (err)
2950                 return err;
2951
2952         return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2953 }
2954
2955 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2956                                    dsa_fdb_dump_cb_t *cb, void *data)
2957 {
2958         struct mv88e6xxx_chip *chip = ds->priv;
2959         int err;
2960
2961         mv88e6xxx_reg_lock(chip);
2962         err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2963         mv88e6xxx_reg_unlock(chip);
2964
2965         return err;
2966 }
2967
2968 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2969                                 struct dsa_bridge bridge)
2970 {
2971         struct dsa_switch *ds = chip->ds;
2972         struct dsa_switch_tree *dst = ds->dst;
2973         struct dsa_port *dp;
2974         int err;
2975
2976         list_for_each_entry(dp, &dst->ports, list) {
2977                 if (dsa_port_offloads_bridge(dp, &bridge)) {
2978                         if (dp->ds == ds) {
2979                                 /* This is a local bridge group member,
2980                                  * remap its Port VLAN Map.
2981                                  */
2982                                 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2983                                 if (err)
2984                                         return err;
2985                         } else {
2986                                 /* This is an external bridge group member,
2987                                  * remap its cross-chip Port VLAN Table entry.
2988                                  */
2989                                 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2990                                                         dp->index);
2991                                 if (err)
2992                                         return err;
2993                         }
2994                 }
2995         }
2996
2997         return 0;
2998 }
2999
3000 /* Treat the software bridge as a virtual single-port switch behind the
3001  * CPU and map in the PVT. First dst->last_switch elements are taken by
3002  * physical switches, so start from beyond that range.
3003  */
3004 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
3005                                                unsigned int bridge_num)
3006 {
3007         u8 dev = bridge_num + ds->dst->last_switch;
3008         struct mv88e6xxx_chip *chip = ds->priv;
3009
3010         return mv88e6xxx_pvt_map(chip, dev, 0);
3011 }
3012
3013 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
3014                                       struct dsa_bridge bridge,
3015                                       bool *tx_fwd_offload,
3016                                       struct netlink_ext_ack *extack)
3017 {
3018         struct mv88e6xxx_chip *chip = ds->priv;
3019         int err;
3020
3021         mv88e6xxx_reg_lock(chip);
3022
3023         err = mv88e6xxx_bridge_map(chip, bridge);
3024         if (err)
3025                 goto unlock;
3026
3027         err = mv88e6xxx_port_set_map_da(chip, port, true);
3028         if (err)
3029                 goto unlock;
3030
3031         err = mv88e6xxx_port_commit_pvid(chip, port);
3032         if (err)
3033                 goto unlock;
3034
3035         if (mv88e6xxx_has_pvt(chip)) {
3036                 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
3037                 if (err)
3038                         goto unlock;
3039
3040                 *tx_fwd_offload = true;
3041         }
3042
3043 unlock:
3044         mv88e6xxx_reg_unlock(chip);
3045
3046         return err;
3047 }
3048
3049 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
3050                                         struct dsa_bridge bridge)
3051 {
3052         struct mv88e6xxx_chip *chip = ds->priv;
3053         int err;
3054
3055         mv88e6xxx_reg_lock(chip);
3056
3057         if (bridge.tx_fwd_offload &&
3058             mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
3059                 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3060
3061         if (mv88e6xxx_bridge_map(chip, bridge) ||
3062             mv88e6xxx_port_vlan_map(chip, port))
3063                 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
3064
3065         err = mv88e6xxx_port_set_map_da(chip, port, false);
3066         if (err)
3067                 dev_err(ds->dev,
3068                         "port %d failed to restore map-DA: %pe\n",
3069                         port, ERR_PTR(err));
3070
3071         err = mv88e6xxx_port_commit_pvid(chip, port);
3072         if (err)
3073                 dev_err(ds->dev,
3074                         "port %d failed to restore standalone pvid: %pe\n",
3075                         port, ERR_PTR(err));
3076
3077         mv88e6xxx_reg_unlock(chip);
3078 }
3079
3080 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
3081                                            int tree_index, int sw_index,
3082                                            int port, struct dsa_bridge bridge,
3083                                            struct netlink_ext_ack *extack)
3084 {
3085         struct mv88e6xxx_chip *chip = ds->priv;
3086         int err;
3087
3088         if (tree_index != ds->dst->index)
3089                 return 0;
3090
3091         mv88e6xxx_reg_lock(chip);
3092         err = mv88e6xxx_pvt_map(chip, sw_index, port);
3093         err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
3094         mv88e6xxx_reg_unlock(chip);
3095
3096         return err;
3097 }
3098
3099 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
3100                                              int tree_index, int sw_index,
3101                                              int port, struct dsa_bridge bridge)
3102 {
3103         struct mv88e6xxx_chip *chip = ds->priv;
3104
3105         if (tree_index != ds->dst->index)
3106                 return;
3107
3108         mv88e6xxx_reg_lock(chip);
3109         if (mv88e6xxx_pvt_map(chip, sw_index, port) ||
3110             mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
3111                 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3112         mv88e6xxx_reg_unlock(chip);
3113 }
3114
3115 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
3116 {
3117         if (chip->info->ops->reset)
3118                 return chip->info->ops->reset(chip);
3119
3120         return 0;
3121 }
3122
3123 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
3124 {
3125         struct gpio_desc *gpiod = chip->reset;
3126
3127         /* If there is a GPIO connected to the reset pin, toggle it */
3128         if (gpiod) {
3129                 /* If the switch has just been reset and not yet completed
3130                  * loading EEPROM, the reset may interrupt the I2C transaction
3131                  * mid-byte, causing the first EEPROM read after the reset
3132                  * from the wrong location resulting in the switch booting
3133                  * to wrong mode and inoperable.
3134                  */
3135                 if (chip->info->ops->get_eeprom)
3136                         mv88e6xxx_g2_eeprom_wait(chip);
3137
3138                 gpiod_set_value_cansleep(gpiod, 1);
3139                 usleep_range(10000, 20000);
3140                 gpiod_set_value_cansleep(gpiod, 0);
3141                 usleep_range(10000, 20000);
3142
3143                 if (chip->info->ops->get_eeprom)
3144                         mv88e6xxx_g2_eeprom_wait(chip);
3145         }
3146 }
3147
3148 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
3149 {
3150         int i, err;
3151
3152         /* Set all ports to the Disabled state */
3153         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3154                 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
3155                 if (err)
3156                         return err;
3157         }
3158
3159         /* Wait for transmit queues to drain,
3160          * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
3161          */
3162         usleep_range(2000, 4000);
3163
3164         return 0;
3165 }
3166
3167 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
3168 {
3169         int err;
3170
3171         err = mv88e6xxx_disable_ports(chip);
3172         if (err)
3173                 return err;
3174
3175         mv88e6xxx_hardware_reset(chip);
3176
3177         return mv88e6xxx_software_reset(chip);
3178 }
3179
3180 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
3181                                    enum mv88e6xxx_frame_mode frame,
3182                                    enum mv88e6xxx_egress_mode egress, u16 etype)
3183 {
3184         int err;
3185
3186         if (!chip->info->ops->port_set_frame_mode)
3187                 return -EOPNOTSUPP;
3188
3189         err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
3190         if (err)
3191                 return err;
3192
3193         err = chip->info->ops->port_set_frame_mode(chip, port, frame);
3194         if (err)
3195                 return err;
3196
3197         if (chip->info->ops->port_set_ether_type)
3198                 return chip->info->ops->port_set_ether_type(chip, port, etype);
3199
3200         return 0;
3201 }
3202
3203 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
3204 {
3205         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
3206                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3207                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3208 }
3209
3210 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
3211 {
3212         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
3213                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3214                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3215 }
3216
3217 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
3218 {
3219         return mv88e6xxx_set_port_mode(chip, port,
3220                                        MV88E6XXX_FRAME_MODE_ETHERTYPE,
3221                                        MV88E6XXX_EGRESS_MODE_ETHERTYPE,
3222                                        ETH_P_EDSA);
3223 }
3224
3225 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
3226 {
3227         if (dsa_is_dsa_port(chip->ds, port))
3228                 return mv88e6xxx_set_port_mode_dsa(chip, port);
3229
3230         if (dsa_is_user_port(chip->ds, port))
3231                 return mv88e6xxx_set_port_mode_normal(chip, port);
3232
3233         /* Setup CPU port mode depending on its supported tag format */
3234         if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
3235                 return mv88e6xxx_set_port_mode_dsa(chip, port);
3236
3237         if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
3238                 return mv88e6xxx_set_port_mode_edsa(chip, port);
3239
3240         return -EINVAL;
3241 }
3242
3243 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
3244 {
3245         bool message = dsa_is_dsa_port(chip->ds, port);
3246
3247         return mv88e6xxx_port_set_message_port(chip, port, message);
3248 }
3249
3250 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
3251 {
3252         int err;
3253
3254         if (chip->info->ops->port_set_ucast_flood) {
3255                 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
3256                 if (err)
3257                         return err;
3258         }
3259         if (chip->info->ops->port_set_mcast_flood) {
3260                 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
3261                 if (err)
3262                         return err;
3263         }
3264
3265         return 0;
3266 }
3267
3268 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
3269                                      enum mv88e6xxx_egress_direction direction,
3270                                      int port)
3271 {
3272         int err;
3273
3274         if (!chip->info->ops->set_egress_port)
3275                 return -EOPNOTSUPP;
3276
3277         err = chip->info->ops->set_egress_port(chip, direction, port);
3278         if (err)
3279                 return err;
3280
3281         if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
3282                 chip->ingress_dest_port = port;
3283         else
3284                 chip->egress_dest_port = port;
3285
3286         return 0;
3287 }
3288
3289 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
3290 {
3291         struct dsa_switch *ds = chip->ds;
3292         int upstream_port;
3293         int err;
3294
3295         upstream_port = dsa_upstream_port(ds, port);
3296         if (chip->info->ops->port_set_upstream_port) {
3297                 err = chip->info->ops->port_set_upstream_port(chip, port,
3298                                                               upstream_port);
3299                 if (err)
3300                         return err;
3301         }
3302
3303         if (port == upstream_port) {
3304                 if (chip->info->ops->set_cpu_port) {
3305                         err = chip->info->ops->set_cpu_port(chip,
3306                                                             upstream_port);
3307                         if (err)
3308                                 return err;
3309                 }
3310
3311                 err = mv88e6xxx_set_egress_port(chip,
3312                                                 MV88E6XXX_EGRESS_DIR_INGRESS,
3313                                                 upstream_port);
3314                 if (err && err != -EOPNOTSUPP)
3315                         return err;
3316
3317                 err = mv88e6xxx_set_egress_port(chip,
3318                                                 MV88E6XXX_EGRESS_DIR_EGRESS,
3319                                                 upstream_port);
3320                 if (err && err != -EOPNOTSUPP)
3321                         return err;
3322         }
3323
3324         return 0;
3325 }
3326
3327 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
3328 {
3329         struct device_node *phy_handle = NULL;
3330         struct dsa_switch *ds = chip->ds;
3331         struct dsa_port *dp;
3332         int tx_amp;
3333         int err;
3334         u16 reg;
3335
3336         chip->ports[port].chip = chip;
3337         chip->ports[port].port = port;
3338
3339         err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
3340                                        SPEED_UNFORCED, DUPLEX_UNFORCED,
3341                                        PAUSE_ON, PHY_INTERFACE_MODE_NA);
3342         if (err)
3343                 return err;
3344
3345         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
3346          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
3347          * tunneling, determine priority by looking at 802.1p and IP
3348          * priority fields (IP prio has precedence), and set STP state
3349          * to Forwarding.
3350          *
3351          * If this is the CPU link, use DSA or EDSA tagging depending
3352          * on which tagging mode was configured.
3353          *
3354          * If this is a link to another switch, use DSA tagging mode.
3355          *
3356          * If this is the upstream port for this switch, enable
3357          * forwarding of unknown unicasts and multicasts.
3358          */
3359         reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
3360                 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
3361         /* Forward any IPv4 IGMP or IPv6 MLD frames received
3362          * by a USER port to the CPU port to allow snooping.
3363          */
3364         if (dsa_is_user_port(ds, port))
3365                 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP;
3366
3367         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
3368         if (err)
3369                 return err;
3370
3371         err = mv88e6xxx_setup_port_mode(chip, port);
3372         if (err)
3373                 return err;
3374
3375         err = mv88e6xxx_setup_egress_floods(chip, port);
3376         if (err)
3377                 return err;
3378
3379         /* Port Control 2: don't force a good FCS, set the MTU size to
3380          * 10222 bytes, disable 802.1q tags checking, don't discard
3381          * tagged or untagged frames on this port, skip destination
3382          * address lookup on user ports, disable ARP mirroring and don't
3383          * send a copy of all transmitted/received frames on this port
3384          * to the CPU.
3385          */
3386         err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port));
3387         if (err)
3388                 return err;
3389
3390         err = mv88e6xxx_setup_upstream_port(chip, port);
3391         if (err)
3392                 return err;
3393
3394         /* On chips that support it, set all downstream DSA ports'
3395          * VLAN policy to TRAP. In combination with loading
3396          * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this
3397          * provides a better isolation barrier between standalone
3398          * ports, as the ATU is bypassed on any intermediate switches
3399          * between the incoming port and the CPU.
3400          */
3401         if (dsa_is_downstream_port(ds, port) &&
3402             chip->info->ops->port_set_policy) {
3403                 err = chip->info->ops->port_set_policy(chip, port,
3404                                                 MV88E6XXX_POLICY_MAPPING_VTU,
3405                                                 MV88E6XXX_POLICY_ACTION_TRAP);
3406                 if (err)
3407                         return err;
3408         }
3409
3410         /* User ports start out in standalone mode and 802.1Q is
3411          * therefore disabled. On DSA ports, all valid VIDs are always
3412          * loaded in the VTU - therefore, enable 802.1Q in order to take
3413          * advantage of VLAN policy on chips that supports it.
3414          */
3415         err = mv88e6xxx_port_set_8021q_mode(chip, port,
3416                                 dsa_is_user_port(ds, port) ?
3417                                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED :
3418                                 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE);
3419         if (err)
3420                 return err;
3421
3422         /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by
3423          * virtue of the fact that mv88e6xxx_atu_new() will pick it as
3424          * the first free FID. This will be used as the private PVID for
3425          * unbridged ports. Shared (DSA and CPU) ports must also be
3426          * members of this VID, in order to trap all frames assigned to
3427          * it to the CPU.
3428          */
3429         err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE,
3430                                        MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3431                                        false);
3432         if (err)
3433                 return err;
3434
3435         /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
3436          * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
3437          * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
3438          * as the private PVID on ports under a VLAN-unaware bridge.
3439          * Shared (DSA and CPU) ports must also be members of it, to translate
3440          * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
3441          * relying on their port default FID.
3442          */
3443         err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
3444                                        MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3445                                        false);
3446         if (err)
3447                 return err;
3448
3449         if (chip->info->ops->port_set_jumbo_size) {
3450                 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
3451                 if (err)
3452                         return err;
3453         }
3454
3455         /* Port Association Vector: disable automatic address learning
3456          * on all user ports since they start out in standalone
3457          * mode. When joining a bridge, learning will be configured to
3458          * match the bridge port settings. Enable learning on all
3459          * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
3460          * learning process.
3461          *
3462          * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
3463          * and RefreshLocked. I.e. setup standard automatic learning.
3464          */
3465         if (dsa_is_user_port(ds, port))
3466                 reg = 0;
3467         else
3468                 reg = 1 << port;
3469
3470         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
3471                                    reg);
3472         if (err)
3473                 return err;
3474
3475         /* Egress rate control 2: disable egress rate control. */
3476         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
3477                                    0x0000);
3478         if (err)
3479                 return err;
3480
3481         if (chip->info->ops->port_pause_limit) {
3482                 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
3483                 if (err)
3484                         return err;
3485         }
3486
3487         if (chip->info->ops->port_disable_learn_limit) {
3488                 err = chip->info->ops->port_disable_learn_limit(chip, port);
3489                 if (err)
3490                         return err;
3491         }
3492
3493         if (chip->info->ops->port_disable_pri_override) {
3494                 err = chip->info->ops->port_disable_pri_override(chip, port);
3495                 if (err)
3496                         return err;
3497         }
3498
3499         if (chip->info->ops->port_tag_remap) {
3500                 err = chip->info->ops->port_tag_remap(chip, port);
3501                 if (err)
3502                         return err;
3503         }
3504
3505         if (chip->info->ops->port_egress_rate_limiting) {
3506                 err = chip->info->ops->port_egress_rate_limiting(chip, port);
3507                 if (err)
3508                         return err;
3509         }
3510
3511         if (chip->info->ops->port_setup_message_port) {
3512                 err = chip->info->ops->port_setup_message_port(chip, port);
3513                 if (err)
3514                         return err;
3515         }
3516
3517         if (chip->info->ops->serdes_set_tx_amplitude) {
3518                 dp = dsa_to_port(ds, port);
3519                 if (dp)
3520                         phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0);
3521
3522                 if (phy_handle && !of_property_read_u32(phy_handle,
3523                                                         "tx-p2p-microvolt",
3524                                                         &tx_amp))
3525                         err = chip->info->ops->serdes_set_tx_amplitude(chip,
3526                                                                 port, tx_amp);
3527                 if (phy_handle) {
3528                         of_node_put(phy_handle);
3529                         if (err)
3530                                 return err;
3531                 }
3532         }
3533
3534         /* Port based VLAN map: give each port the same default address
3535          * database, and allow bidirectional communication between the
3536          * CPU and DSA port(s), and the other ports.
3537          */
3538         err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
3539         if (err)
3540                 return err;
3541
3542         err = mv88e6xxx_port_vlan_map(chip, port);
3543         if (err)
3544                 return err;
3545
3546         /* Default VLAN ID and priority: don't set a default VLAN
3547          * ID, and set the default packet priority to zero.
3548          */
3549         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
3550 }
3551
3552 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
3553 {
3554         struct mv88e6xxx_chip *chip = ds->priv;
3555
3556         if (chip->info->ops->port_set_jumbo_size)
3557                 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3558         else if (chip->info->ops->set_max_frame_size)
3559                 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3560         return ETH_DATA_LEN;
3561 }
3562
3563 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3564 {
3565         struct mv88e6xxx_chip *chip = ds->priv;
3566         int ret = 0;
3567
3568         /* For families where we don't know how to alter the MTU,
3569          * just accept any value up to ETH_DATA_LEN
3570          */
3571         if (!chip->info->ops->port_set_jumbo_size &&
3572             !chip->info->ops->set_max_frame_size) {
3573                 if (new_mtu > ETH_DATA_LEN)
3574                         return -EINVAL;
3575
3576                 return 0;
3577         }
3578
3579         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3580                 new_mtu += EDSA_HLEN;
3581
3582         mv88e6xxx_reg_lock(chip);
3583         if (chip->info->ops->port_set_jumbo_size)
3584                 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
3585         else if (chip->info->ops->set_max_frame_size)
3586                 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
3587         mv88e6xxx_reg_unlock(chip);
3588
3589         return ret;
3590 }
3591
3592 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3593                                      unsigned int ageing_time)
3594 {
3595         struct mv88e6xxx_chip *chip = ds->priv;
3596         int err;
3597
3598         mv88e6xxx_reg_lock(chip);
3599         err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
3600         mv88e6xxx_reg_unlock(chip);
3601
3602         return err;
3603 }
3604
3605 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
3606 {
3607         int err;
3608
3609         /* Initialize the statistics unit */
3610         if (chip->info->ops->stats_set_histogram) {
3611                 err = chip->info->ops->stats_set_histogram(chip);
3612                 if (err)
3613                         return err;
3614         }
3615
3616         return mv88e6xxx_g1_stats_clear(chip);
3617 }
3618
3619 /* Check if the errata has already been applied. */
3620 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3621 {
3622         int port;
3623         int err;
3624         u16 val;
3625
3626         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3627                 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
3628                 if (err) {
3629                         dev_err(chip->dev,
3630                                 "Error reading hidden register: %d\n", err);
3631                         return false;
3632                 }
3633                 if (val != 0x01c0)
3634                         return false;
3635         }
3636
3637         return true;
3638 }
3639
3640 /* The 6390 copper ports have an errata which require poking magic
3641  * values into undocumented hidden registers and then performing a
3642  * software reset.
3643  */
3644 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3645 {
3646         int port;
3647         int err;
3648
3649         if (mv88e6390_setup_errata_applied(chip))
3650                 return 0;
3651
3652         /* Set the ports into blocking mode */
3653         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3654                 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3655                 if (err)
3656                         return err;
3657         }
3658
3659         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3660                 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3661                 if (err)
3662                         return err;
3663         }
3664
3665         return mv88e6xxx_software_reset(chip);
3666 }
3667
3668 /* prod_id for switch families which do not have a PHY model number */
3669 static const u16 family_prod_id_table[] = {
3670         [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3671         [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3672         [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3673 };
3674
3675 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3676 {
3677         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3678         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3679         u16 prod_id;
3680         u16 val;
3681         int err;
3682
3683         if (!chip->info->ops->phy_read)
3684                 return -EOPNOTSUPP;
3685
3686         mv88e6xxx_reg_lock(chip);
3687         err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3688         mv88e6xxx_reg_unlock(chip);
3689
3690         /* Some internal PHYs don't have a model number. */
3691         if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3692             chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3693                 prod_id = family_prod_id_table[chip->info->family];
3694                 if (prod_id)
3695                         val |= prod_id >> 4;
3696         }
3697
3698         return err ? err : val;
3699 }
3700
3701 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad,
3702                                    int reg)
3703 {
3704         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3705         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3706         u16 val;
3707         int err;
3708
3709         if (!chip->info->ops->phy_read_c45)
3710                 return -ENODEV;
3711
3712         mv88e6xxx_reg_lock(chip);
3713         err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val);
3714         mv88e6xxx_reg_unlock(chip);
3715
3716         return err ? err : val;
3717 }
3718
3719 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3720 {
3721         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3722         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3723         int err;
3724
3725         if (!chip->info->ops->phy_write)
3726                 return -EOPNOTSUPP;
3727
3728         mv88e6xxx_reg_lock(chip);
3729         err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3730         mv88e6xxx_reg_unlock(chip);
3731
3732         return err;
3733 }
3734
3735 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad,
3736                                     int reg, u16 val)
3737 {
3738         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3739         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3740         int err;
3741
3742         if (!chip->info->ops->phy_write_c45)
3743                 return -EOPNOTSUPP;
3744
3745         mv88e6xxx_reg_lock(chip);
3746         err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val);
3747         mv88e6xxx_reg_unlock(chip);
3748
3749         return err;
3750 }
3751
3752 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3753                                    struct device_node *np,
3754                                    bool external)
3755 {
3756         static int index;
3757         struct mv88e6xxx_mdio_bus *mdio_bus;
3758         struct mii_bus *bus;
3759         int err;
3760
3761         if (external) {
3762                 mv88e6xxx_reg_lock(chip);
3763                 if (chip->info->family == MV88E6XXX_FAMILY_6393)
3764                         err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true);
3765                 else
3766                         err = mv88e6390_g2_scratch_gpio_set_smi(chip, true);
3767                 mv88e6xxx_reg_unlock(chip);
3768
3769                 if (err)
3770                         return err;
3771         }
3772
3773         bus = mdiobus_alloc_size(sizeof(*mdio_bus));
3774         if (!bus)
3775                 return -ENOMEM;
3776
3777         mdio_bus = bus->priv;
3778         mdio_bus->bus = bus;
3779         mdio_bus->chip = chip;
3780         INIT_LIST_HEAD(&mdio_bus->list);
3781         mdio_bus->external = external;
3782
3783         if (np) {
3784                 bus->name = np->full_name;
3785                 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3786         } else {
3787                 bus->name = "mv88e6xxx SMI";
3788                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3789         }
3790
3791         bus->read = mv88e6xxx_mdio_read;
3792         bus->write = mv88e6xxx_mdio_write;
3793         bus->read_c45 = mv88e6xxx_mdio_read_c45;
3794         bus->write_c45 = mv88e6xxx_mdio_write_c45;
3795         bus->parent = chip->dev;
3796         bus->phy_mask = ~GENMASK(chip->info->phy_base_addr +
3797                                  mv88e6xxx_num_ports(chip) - 1,
3798                                  chip->info->phy_base_addr);
3799
3800         if (!external) {
3801                 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3802                 if (err)
3803                         goto out;
3804         }
3805
3806         err = of_mdiobus_register(bus, np);
3807         if (err) {
3808                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3809                 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3810                 goto out;
3811         }
3812
3813         if (external)
3814                 list_add_tail(&mdio_bus->list, &chip->mdios);
3815         else
3816                 list_add(&mdio_bus->list, &chip->mdios);
3817
3818         return 0;
3819
3820 out:
3821         mdiobus_free(bus);
3822         return err;
3823 }
3824
3825 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3826
3827 {
3828         struct mv88e6xxx_mdio_bus *mdio_bus, *p;
3829         struct mii_bus *bus;
3830
3831         list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
3832                 bus = mdio_bus->bus;
3833
3834                 if (!mdio_bus->external)
3835                         mv88e6xxx_g2_irq_mdio_free(chip, bus);
3836
3837                 mdiobus_unregister(bus);
3838                 mdiobus_free(bus);
3839         }
3840 }
3841
3842 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip)
3843 {
3844         struct device_node *np = chip->dev->of_node;
3845         struct device_node *child;
3846         int err;
3847
3848         /* Always register one mdio bus for the internal/default mdio
3849          * bus. This maybe represented in the device tree, but is
3850          * optional.
3851          */
3852         child = of_get_child_by_name(np, "mdio");
3853         err = mv88e6xxx_mdio_register(chip, child, false);
3854         of_node_put(child);
3855         if (err)
3856                 return err;
3857
3858         /* Walk the device tree, and see if there are any other nodes
3859          * which say they are compatible with the external mdio
3860          * bus.
3861          */
3862         for_each_available_child_of_node(np, child) {
3863                 if (of_device_is_compatible(
3864                             child, "marvell,mv88e6xxx-mdio-external")) {
3865                         err = mv88e6xxx_mdio_register(chip, child, true);
3866                         if (err) {
3867                                 mv88e6xxx_mdios_unregister(chip);
3868                                 of_node_put(child);
3869                                 return err;
3870                         }
3871                 }
3872         }
3873
3874         return 0;
3875 }
3876
3877 static void mv88e6xxx_teardown(struct dsa_switch *ds)
3878 {
3879         struct mv88e6xxx_chip *chip = ds->priv;
3880
3881         mv88e6xxx_teardown_devlink_params(ds);
3882         dsa_devlink_resources_unregister(ds);
3883         mv88e6xxx_teardown_devlink_regions_global(ds);
3884         mv88e6xxx_mdios_unregister(chip);
3885 }
3886
3887 static int mv88e6xxx_setup(struct dsa_switch *ds)
3888 {
3889         struct mv88e6xxx_chip *chip = ds->priv;
3890         u8 cmode;
3891         int err;
3892         int i;
3893
3894         err = mv88e6xxx_mdios_register(chip);
3895         if (err)
3896                 return err;
3897
3898         chip->ds = ds;
3899         ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3900
3901         /* Since virtual bridges are mapped in the PVT, the number we support
3902          * depends on the physical switch topology. We need to let DSA figure
3903          * that out and therefore we cannot set this at dsa_register_switch()
3904          * time.
3905          */
3906         if (mv88e6xxx_has_pvt(chip))
3907                 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3908                                       ds->dst->last_switch - 1;
3909
3910         mv88e6xxx_reg_lock(chip);
3911
3912         if (chip->info->ops->setup_errata) {
3913                 err = chip->info->ops->setup_errata(chip);
3914                 if (err)
3915                         goto unlock;
3916         }
3917
3918         /* Cache the cmode of each port. */
3919         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3920                 if (chip->info->ops->port_get_cmode) {
3921                         err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3922                         if (err)
3923                                 goto unlock;
3924
3925                         chip->ports[i].cmode = cmode;
3926                 }
3927         }
3928
3929         err = mv88e6xxx_vtu_setup(chip);
3930         if (err)
3931                 goto unlock;
3932
3933         /* Must be called after mv88e6xxx_vtu_setup (which flushes the
3934          * VTU, thereby also flushing the STU).
3935          */
3936         err = mv88e6xxx_stu_setup(chip);
3937         if (err)
3938                 goto unlock;
3939
3940         /* Setup Switch Port Registers */
3941         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3942                 if (dsa_is_unused_port(ds, i))
3943                         continue;
3944
3945                 /* Prevent the use of an invalid port. */
3946                 if (mv88e6xxx_is_invalid_port(chip, i)) {
3947                         dev_err(chip->dev, "port %d is invalid\n", i);
3948                         err = -EINVAL;
3949                         goto unlock;
3950                 }
3951
3952                 err = mv88e6xxx_setup_port(chip, i);
3953                 if (err)
3954                         goto unlock;
3955         }
3956
3957         err = mv88e6xxx_irl_setup(chip);
3958         if (err)
3959                 goto unlock;
3960
3961         err = mv88e6xxx_mac_setup(chip);
3962         if (err)
3963                 goto unlock;
3964
3965         err = mv88e6xxx_phy_setup(chip);
3966         if (err)
3967                 goto unlock;
3968
3969         err = mv88e6xxx_pvt_setup(chip);
3970         if (err)
3971                 goto unlock;
3972
3973         err = mv88e6xxx_atu_setup(chip);
3974         if (err)
3975                 goto unlock;
3976
3977         err = mv88e6xxx_broadcast_setup(chip, 0);
3978         if (err)
3979                 goto unlock;
3980
3981         err = mv88e6xxx_pot_setup(chip);
3982         if (err)
3983                 goto unlock;
3984
3985         err = mv88e6xxx_rmu_setup(chip);
3986         if (err)
3987                 goto unlock;
3988
3989         err = mv88e6xxx_rsvd2cpu_setup(chip);
3990         if (err)
3991                 goto unlock;
3992
3993         err = mv88e6xxx_trunk_setup(chip);
3994         if (err)
3995                 goto unlock;
3996
3997         err = mv88e6xxx_devmap_setup(chip);
3998         if (err)
3999                 goto unlock;
4000
4001         err = mv88e6xxx_pri_setup(chip);
4002         if (err)
4003                 goto unlock;
4004
4005         /* Setup PTP Hardware Clock and timestamping */
4006         if (chip->info->ptp_support) {
4007                 err = mv88e6xxx_ptp_setup(chip);
4008                 if (err)
4009                         goto unlock;
4010
4011                 err = mv88e6xxx_hwtstamp_setup(chip);
4012                 if (err)
4013                         goto unlock;
4014         }
4015
4016         err = mv88e6xxx_stats_setup(chip);
4017         if (err)
4018                 goto unlock;
4019
4020 unlock:
4021         mv88e6xxx_reg_unlock(chip);
4022
4023         if (err)
4024                 goto out_mdios;
4025
4026         /* Have to be called without holding the register lock, since
4027          * they take the devlink lock, and we later take the locks in
4028          * the reverse order when getting/setting parameters or
4029          * resource occupancy.
4030          */
4031         err = mv88e6xxx_setup_devlink_resources(ds);
4032         if (err)
4033                 goto out_mdios;
4034
4035         err = mv88e6xxx_setup_devlink_params(ds);
4036         if (err)
4037                 goto out_resources;
4038
4039         err = mv88e6xxx_setup_devlink_regions_global(ds);
4040         if (err)
4041                 goto out_params;
4042
4043         return 0;
4044
4045 out_params:
4046         mv88e6xxx_teardown_devlink_params(ds);
4047 out_resources:
4048         dsa_devlink_resources_unregister(ds);
4049 out_mdios:
4050         mv88e6xxx_mdios_unregister(chip);
4051
4052         return err;
4053 }
4054
4055 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
4056 {
4057         struct mv88e6xxx_chip *chip = ds->priv;
4058         int err;
4059
4060         if (chip->info->ops->pcs_ops &&
4061             chip->info->ops->pcs_ops->pcs_init) {
4062                 err = chip->info->ops->pcs_ops->pcs_init(chip, port);
4063                 if (err)
4064                         return err;
4065         }
4066
4067         return mv88e6xxx_setup_devlink_regions_port(ds, port);
4068 }
4069
4070 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
4071 {
4072         struct mv88e6xxx_chip *chip = ds->priv;
4073
4074         mv88e6xxx_teardown_devlink_regions_port(ds, port);
4075
4076         if (chip->info->ops->pcs_ops &&
4077             chip->info->ops->pcs_ops->pcs_teardown)
4078                 chip->info->ops->pcs_ops->pcs_teardown(chip, port);
4079 }
4080
4081 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
4082 {
4083         struct mv88e6xxx_chip *chip = ds->priv;
4084
4085         return chip->eeprom_len;
4086 }
4087
4088 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
4089                                 struct ethtool_eeprom *eeprom, u8 *data)
4090 {
4091         struct mv88e6xxx_chip *chip = ds->priv;
4092         int err;
4093
4094         if (!chip->info->ops->get_eeprom)
4095                 return -EOPNOTSUPP;
4096
4097         mv88e6xxx_reg_lock(chip);
4098         err = chip->info->ops->get_eeprom(chip, eeprom, data);
4099         mv88e6xxx_reg_unlock(chip);
4100
4101         if (err)
4102                 return err;
4103
4104         eeprom->magic = 0xc3ec4951;
4105
4106         return 0;
4107 }
4108
4109 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
4110                                 struct ethtool_eeprom *eeprom, u8 *data)
4111 {
4112         struct mv88e6xxx_chip *chip = ds->priv;
4113         int err;
4114
4115         if (!chip->info->ops->set_eeprom)
4116                 return -EOPNOTSUPP;
4117
4118         if (eeprom->magic != 0xc3ec4951)
4119                 return -EINVAL;
4120
4121         mv88e6xxx_reg_lock(chip);
4122         err = chip->info->ops->set_eeprom(chip, eeprom, data);
4123         mv88e6xxx_reg_unlock(chip);
4124
4125         return err;
4126 }
4127
4128 static const struct mv88e6xxx_ops mv88e6085_ops = {
4129         /* MV88E6XXX_FAMILY_6097 */
4130         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4131         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4132         .irl_init_all = mv88e6352_g2_irl_init_all,
4133         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4134         .phy_read = mv88e6185_phy_ppu_read,
4135         .phy_write = mv88e6185_phy_ppu_write,
4136         .port_set_link = mv88e6xxx_port_set_link,
4137         .port_sync_link = mv88e6xxx_port_sync_link,
4138         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4139         .port_tag_remap = mv88e6095_port_tag_remap,
4140         .port_set_policy = mv88e6352_port_set_policy,
4141         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4142         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4143         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4144         .port_set_ether_type = mv88e6351_port_set_ether_type,
4145         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4146         .port_pause_limit = mv88e6097_port_pause_limit,
4147         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4148         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4149         .port_get_cmode = mv88e6185_port_get_cmode,
4150         .port_setup_message_port = mv88e6xxx_setup_message_port,
4151         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4152         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4153         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4154         .stats_get_strings = mv88e6095_stats_get_strings,
4155         .stats_get_stat = mv88e6095_stats_get_stat,
4156         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4157         .set_egress_port = mv88e6095_g1_set_egress_port,
4158         .watchdog_ops = &mv88e6097_watchdog_ops,
4159         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4160         .pot_clear = mv88e6xxx_g2_pot_clear,
4161         .ppu_enable = mv88e6185_g1_ppu_enable,
4162         .ppu_disable = mv88e6185_g1_ppu_disable,
4163         .reset = mv88e6185_g1_reset,
4164         .rmu_disable = mv88e6085_g1_rmu_disable,
4165         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4166         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4167         .stu_getnext = mv88e6352_g1_stu_getnext,
4168         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4169         .phylink_get_caps = mv88e6185_phylink_get_caps,
4170         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4171 };
4172
4173 static const struct mv88e6xxx_ops mv88e6095_ops = {
4174         /* MV88E6XXX_FAMILY_6095 */
4175         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4176         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4177         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4178         .phy_read = mv88e6185_phy_ppu_read,
4179         .phy_write = mv88e6185_phy_ppu_write,
4180         .port_set_link = mv88e6xxx_port_set_link,
4181         .port_sync_link = mv88e6185_port_sync_link,
4182         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4183         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4184         .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4185         .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4186         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4187         .port_get_cmode = mv88e6185_port_get_cmode,
4188         .port_setup_message_port = mv88e6xxx_setup_message_port,
4189         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4190         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4191         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4192         .stats_get_strings = mv88e6095_stats_get_strings,
4193         .stats_get_stat = mv88e6095_stats_get_stat,
4194         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4195         .ppu_enable = mv88e6185_g1_ppu_enable,
4196         .ppu_disable = mv88e6185_g1_ppu_disable,
4197         .reset = mv88e6185_g1_reset,
4198         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4199         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4200         .phylink_get_caps = mv88e6095_phylink_get_caps,
4201         .pcs_ops = &mv88e6185_pcs_ops,
4202         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4203 };
4204
4205 static const struct mv88e6xxx_ops mv88e6097_ops = {
4206         /* MV88E6XXX_FAMILY_6097 */
4207         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4208         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4209         .irl_init_all = mv88e6352_g2_irl_init_all,
4210         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4211         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4212         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4213         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4214         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4215         .port_set_link = mv88e6xxx_port_set_link,
4216         .port_sync_link = mv88e6185_port_sync_link,
4217         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4218         .port_tag_remap = mv88e6095_port_tag_remap,
4219         .port_set_policy = mv88e6352_port_set_policy,
4220         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4221         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4222         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4223         .port_set_ether_type = mv88e6351_port_set_ether_type,
4224         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4225         .port_pause_limit = mv88e6097_port_pause_limit,
4226         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4227         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4228         .port_get_cmode = mv88e6185_port_get_cmode,
4229         .port_setup_message_port = mv88e6xxx_setup_message_port,
4230         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4231         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4232         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4233         .stats_get_strings = mv88e6095_stats_get_strings,
4234         .stats_get_stat = mv88e6095_stats_get_stat,
4235         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4236         .set_egress_port = mv88e6095_g1_set_egress_port,
4237         .watchdog_ops = &mv88e6097_watchdog_ops,
4238         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4239         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4240         .pot_clear = mv88e6xxx_g2_pot_clear,
4241         .reset = mv88e6352_g1_reset,
4242         .rmu_disable = mv88e6085_g1_rmu_disable,
4243         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4244         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4245         .phylink_get_caps = mv88e6095_phylink_get_caps,
4246         .pcs_ops = &mv88e6185_pcs_ops,
4247         .stu_getnext = mv88e6352_g1_stu_getnext,
4248         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4249         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4250 };
4251
4252 static const struct mv88e6xxx_ops mv88e6123_ops = {
4253         /* MV88E6XXX_FAMILY_6165 */
4254         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4255         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4256         .irl_init_all = mv88e6352_g2_irl_init_all,
4257         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4258         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4259         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4260         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4261         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4262         .port_set_link = mv88e6xxx_port_set_link,
4263         .port_sync_link = mv88e6xxx_port_sync_link,
4264         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4265         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4266         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4267         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4268         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4269         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4270         .port_get_cmode = mv88e6185_port_get_cmode,
4271         .port_setup_message_port = mv88e6xxx_setup_message_port,
4272         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4273         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4274         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4275         .stats_get_strings = mv88e6095_stats_get_strings,
4276         .stats_get_stat = mv88e6095_stats_get_stat,
4277         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4278         .set_egress_port = mv88e6095_g1_set_egress_port,
4279         .watchdog_ops = &mv88e6097_watchdog_ops,
4280         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4281         .pot_clear = mv88e6xxx_g2_pot_clear,
4282         .reset = mv88e6352_g1_reset,
4283         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4284         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4285         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4286         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4287         .stu_getnext = mv88e6352_g1_stu_getnext,
4288         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4289         .phylink_get_caps = mv88e6185_phylink_get_caps,
4290         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4291 };
4292
4293 static const struct mv88e6xxx_ops mv88e6131_ops = {
4294         /* MV88E6XXX_FAMILY_6185 */
4295         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4296         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4297         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4298         .phy_read = mv88e6185_phy_ppu_read,
4299         .phy_write = mv88e6185_phy_ppu_write,
4300         .port_set_link = mv88e6xxx_port_set_link,
4301         .port_sync_link = mv88e6xxx_port_sync_link,
4302         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4303         .port_tag_remap = mv88e6095_port_tag_remap,
4304         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4305         .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4306         .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4307         .port_set_ether_type = mv88e6351_port_set_ether_type,
4308         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4309         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4310         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4311         .port_pause_limit = mv88e6097_port_pause_limit,
4312         .port_set_pause = mv88e6185_port_set_pause,
4313         .port_get_cmode = mv88e6185_port_get_cmode,
4314         .port_setup_message_port = mv88e6xxx_setup_message_port,
4315         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4316         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4317         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4318         .stats_get_strings = mv88e6095_stats_get_strings,
4319         .stats_get_stat = mv88e6095_stats_get_stat,
4320         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4321         .set_egress_port = mv88e6095_g1_set_egress_port,
4322         .watchdog_ops = &mv88e6097_watchdog_ops,
4323         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4324         .ppu_enable = mv88e6185_g1_ppu_enable,
4325         .set_cascade_port = mv88e6185_g1_set_cascade_port,
4326         .ppu_disable = mv88e6185_g1_ppu_disable,
4327         .reset = mv88e6185_g1_reset,
4328         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4329         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4330         .phylink_get_caps = mv88e6185_phylink_get_caps,
4331 };
4332
4333 static const struct mv88e6xxx_ops mv88e6141_ops = {
4334         /* MV88E6XXX_FAMILY_6341 */
4335         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4336         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4337         .irl_init_all = mv88e6352_g2_irl_init_all,
4338         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4339         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4340         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4341         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4342         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4343         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4344         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4345         .port_set_link = mv88e6xxx_port_set_link,
4346         .port_sync_link = mv88e6xxx_port_sync_link,
4347         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4348         .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4349         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4350         .port_tag_remap = mv88e6095_port_tag_remap,
4351         .port_set_policy = mv88e6352_port_set_policy,
4352         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4353         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4354         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4355         .port_set_ether_type = mv88e6351_port_set_ether_type,
4356         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4357         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4358         .port_pause_limit = mv88e6097_port_pause_limit,
4359         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4360         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4361         .port_get_cmode = mv88e6352_port_get_cmode,
4362         .port_set_cmode = mv88e6341_port_set_cmode,
4363         .port_setup_message_port = mv88e6xxx_setup_message_port,
4364         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4365         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4366         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4367         .stats_get_strings = mv88e6320_stats_get_strings,
4368         .stats_get_stat = mv88e6390_stats_get_stat,
4369         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4370         .set_egress_port = mv88e6390_g1_set_egress_port,
4371         .watchdog_ops = &mv88e6390_watchdog_ops,
4372         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
4373         .pot_clear = mv88e6xxx_g2_pot_clear,
4374         .reset = mv88e6352_g1_reset,
4375         .rmu_disable = mv88e6390_g1_rmu_disable,
4376         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4377         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4378         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4379         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4380         .stu_getnext = mv88e6352_g1_stu_getnext,
4381         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4382         .serdes_get_lane = mv88e6341_serdes_get_lane,
4383         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4384         .gpio_ops = &mv88e6352_gpio_ops,
4385         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4386         .serdes_get_strings = mv88e6390_serdes_get_strings,
4387         .serdes_get_stats = mv88e6390_serdes_get_stats,
4388         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4389         .serdes_get_regs = mv88e6390_serdes_get_regs,
4390         .phylink_get_caps = mv88e6341_phylink_get_caps,
4391         .pcs_ops = &mv88e6390_pcs_ops,
4392 };
4393
4394 static const struct mv88e6xxx_ops mv88e6161_ops = {
4395         /* MV88E6XXX_FAMILY_6165 */
4396         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4397         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4398         .irl_init_all = mv88e6352_g2_irl_init_all,
4399         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4400         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4401         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4402         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4403         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4404         .port_set_link = mv88e6xxx_port_set_link,
4405         .port_sync_link = mv88e6xxx_port_sync_link,
4406         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4407         .port_tag_remap = mv88e6095_port_tag_remap,
4408         .port_set_policy = mv88e6352_port_set_policy,
4409         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4410         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4411         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4412         .port_set_ether_type = mv88e6351_port_set_ether_type,
4413         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4414         .port_pause_limit = mv88e6097_port_pause_limit,
4415         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4416         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4417         .port_get_cmode = mv88e6185_port_get_cmode,
4418         .port_setup_message_port = mv88e6xxx_setup_message_port,
4419         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4420         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4421         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4422         .stats_get_strings = mv88e6095_stats_get_strings,
4423         .stats_get_stat = mv88e6095_stats_get_stat,
4424         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4425         .set_egress_port = mv88e6095_g1_set_egress_port,
4426         .watchdog_ops = &mv88e6097_watchdog_ops,
4427         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4428         .pot_clear = mv88e6xxx_g2_pot_clear,
4429         .reset = mv88e6352_g1_reset,
4430         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4431         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4432         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4433         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4434         .stu_getnext = mv88e6352_g1_stu_getnext,
4435         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4436         .avb_ops = &mv88e6165_avb_ops,
4437         .ptp_ops = &mv88e6165_ptp_ops,
4438         .phylink_get_caps = mv88e6185_phylink_get_caps,
4439         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4440 };
4441
4442 static const struct mv88e6xxx_ops mv88e6165_ops = {
4443         /* MV88E6XXX_FAMILY_6165 */
4444         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4445         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4446         .irl_init_all = mv88e6352_g2_irl_init_all,
4447         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4448         .phy_read = mv88e6165_phy_read,
4449         .phy_write = mv88e6165_phy_write,
4450         .port_set_link = mv88e6xxx_port_set_link,
4451         .port_sync_link = mv88e6xxx_port_sync_link,
4452         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4453         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4454         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4455         .port_get_cmode = mv88e6185_port_get_cmode,
4456         .port_setup_message_port = mv88e6xxx_setup_message_port,
4457         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4458         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4459         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4460         .stats_get_strings = mv88e6095_stats_get_strings,
4461         .stats_get_stat = mv88e6095_stats_get_stat,
4462         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4463         .set_egress_port = mv88e6095_g1_set_egress_port,
4464         .watchdog_ops = &mv88e6097_watchdog_ops,
4465         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4466         .pot_clear = mv88e6xxx_g2_pot_clear,
4467         .reset = mv88e6352_g1_reset,
4468         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4469         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4470         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4471         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4472         .stu_getnext = mv88e6352_g1_stu_getnext,
4473         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4474         .avb_ops = &mv88e6165_avb_ops,
4475         .ptp_ops = &mv88e6165_ptp_ops,
4476         .phylink_get_caps = mv88e6185_phylink_get_caps,
4477 };
4478
4479 static const struct mv88e6xxx_ops mv88e6171_ops = {
4480         /* MV88E6XXX_FAMILY_6351 */
4481         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4482         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4483         .irl_init_all = mv88e6352_g2_irl_init_all,
4484         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4485         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4486         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4487         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4488         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4489         .port_set_link = mv88e6xxx_port_set_link,
4490         .port_sync_link = mv88e6xxx_port_sync_link,
4491         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4492         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4493         .port_tag_remap = mv88e6095_port_tag_remap,
4494         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4495         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4496         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4497         .port_set_ether_type = mv88e6351_port_set_ether_type,
4498         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4499         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4500         .port_pause_limit = mv88e6097_port_pause_limit,
4501         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4502         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4503         .port_get_cmode = mv88e6352_port_get_cmode,
4504         .port_setup_message_port = mv88e6xxx_setup_message_port,
4505         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4506         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4507         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4508         .stats_get_strings = mv88e6095_stats_get_strings,
4509         .stats_get_stat = mv88e6095_stats_get_stat,
4510         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4511         .set_egress_port = mv88e6095_g1_set_egress_port,
4512         .watchdog_ops = &mv88e6097_watchdog_ops,
4513         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4514         .pot_clear = mv88e6xxx_g2_pot_clear,
4515         .reset = mv88e6352_g1_reset,
4516         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4517         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4518         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4519         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4520         .stu_getnext = mv88e6352_g1_stu_getnext,
4521         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4522         .phylink_get_caps = mv88e6351_phylink_get_caps,
4523 };
4524
4525 static const struct mv88e6xxx_ops mv88e6172_ops = {
4526         /* MV88E6XXX_FAMILY_6352 */
4527         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4528         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4529         .irl_init_all = mv88e6352_g2_irl_init_all,
4530         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4531         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4532         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4533         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4534         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4535         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4536         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4537         .port_set_link = mv88e6xxx_port_set_link,
4538         .port_sync_link = mv88e6xxx_port_sync_link,
4539         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4540         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4541         .port_tag_remap = mv88e6095_port_tag_remap,
4542         .port_set_policy = mv88e6352_port_set_policy,
4543         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4544         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4545         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4546         .port_set_ether_type = mv88e6351_port_set_ether_type,
4547         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4548         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4549         .port_pause_limit = mv88e6097_port_pause_limit,
4550         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4551         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4552         .port_get_cmode = mv88e6352_port_get_cmode,
4553         .port_setup_message_port = mv88e6xxx_setup_message_port,
4554         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4555         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4556         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4557         .stats_get_strings = mv88e6095_stats_get_strings,
4558         .stats_get_stat = mv88e6095_stats_get_stat,
4559         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4560         .set_egress_port = mv88e6095_g1_set_egress_port,
4561         .watchdog_ops = &mv88e6097_watchdog_ops,
4562         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4563         .pot_clear = mv88e6xxx_g2_pot_clear,
4564         .reset = mv88e6352_g1_reset,
4565         .rmu_disable = mv88e6352_g1_rmu_disable,
4566         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4567         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4568         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4569         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4570         .stu_getnext = mv88e6352_g1_stu_getnext,
4571         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4572         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4573         .serdes_get_regs = mv88e6352_serdes_get_regs,
4574         .gpio_ops = &mv88e6352_gpio_ops,
4575         .phylink_get_caps = mv88e6352_phylink_get_caps,
4576         .pcs_ops = &mv88e6352_pcs_ops,
4577 };
4578
4579 static const struct mv88e6xxx_ops mv88e6175_ops = {
4580         /* MV88E6XXX_FAMILY_6351 */
4581         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4582         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4583         .irl_init_all = mv88e6352_g2_irl_init_all,
4584         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4585         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4586         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4587         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4588         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4589         .port_set_link = mv88e6xxx_port_set_link,
4590         .port_sync_link = mv88e6xxx_port_sync_link,
4591         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4592         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4593         .port_tag_remap = mv88e6095_port_tag_remap,
4594         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4595         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4596         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4597         .port_set_ether_type = mv88e6351_port_set_ether_type,
4598         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4599         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4600         .port_pause_limit = mv88e6097_port_pause_limit,
4601         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4602         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4603         .port_get_cmode = mv88e6352_port_get_cmode,
4604         .port_setup_message_port = mv88e6xxx_setup_message_port,
4605         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4606         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4607         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4608         .stats_get_strings = mv88e6095_stats_get_strings,
4609         .stats_get_stat = mv88e6095_stats_get_stat,
4610         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4611         .set_egress_port = mv88e6095_g1_set_egress_port,
4612         .watchdog_ops = &mv88e6097_watchdog_ops,
4613         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4614         .pot_clear = mv88e6xxx_g2_pot_clear,
4615         .reset = mv88e6352_g1_reset,
4616         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4617         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4618         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4619         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4620         .stu_getnext = mv88e6352_g1_stu_getnext,
4621         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4622         .phylink_get_caps = mv88e6351_phylink_get_caps,
4623 };
4624
4625 static const struct mv88e6xxx_ops mv88e6176_ops = {
4626         /* MV88E6XXX_FAMILY_6352 */
4627         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4628         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4629         .irl_init_all = mv88e6352_g2_irl_init_all,
4630         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4631         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4632         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4633         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4634         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4635         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4636         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4637         .port_set_link = mv88e6xxx_port_set_link,
4638         .port_sync_link = mv88e6xxx_port_sync_link,
4639         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4640         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4641         .port_tag_remap = mv88e6095_port_tag_remap,
4642         .port_set_policy = mv88e6352_port_set_policy,
4643         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4644         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4645         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4646         .port_set_ether_type = mv88e6351_port_set_ether_type,
4647         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4648         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4649         .port_pause_limit = mv88e6097_port_pause_limit,
4650         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4651         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4652         .port_get_cmode = mv88e6352_port_get_cmode,
4653         .port_setup_message_port = mv88e6xxx_setup_message_port,
4654         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4655         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4656         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4657         .stats_get_strings = mv88e6095_stats_get_strings,
4658         .stats_get_stat = mv88e6095_stats_get_stat,
4659         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4660         .set_egress_port = mv88e6095_g1_set_egress_port,
4661         .watchdog_ops = &mv88e6097_watchdog_ops,
4662         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4663         .pot_clear = mv88e6xxx_g2_pot_clear,
4664         .reset = mv88e6352_g1_reset,
4665         .rmu_disable = mv88e6352_g1_rmu_disable,
4666         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4667         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4668         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4669         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4670         .stu_getnext = mv88e6352_g1_stu_getnext,
4671         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4672         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4673         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4674         .serdes_get_regs = mv88e6352_serdes_get_regs,
4675         .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4676         .gpio_ops = &mv88e6352_gpio_ops,
4677         .phylink_get_caps = mv88e6352_phylink_get_caps,
4678         .pcs_ops = &mv88e6352_pcs_ops,
4679 };
4680
4681 static const struct mv88e6xxx_ops mv88e6185_ops = {
4682         /* MV88E6XXX_FAMILY_6185 */
4683         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4684         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4685         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4686         .phy_read = mv88e6185_phy_ppu_read,
4687         .phy_write = mv88e6185_phy_ppu_write,
4688         .port_set_link = mv88e6xxx_port_set_link,
4689         .port_sync_link = mv88e6185_port_sync_link,
4690         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4691         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4692         .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4693         .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4694         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4695         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4696         .port_set_pause = mv88e6185_port_set_pause,
4697         .port_get_cmode = mv88e6185_port_get_cmode,
4698         .port_setup_message_port = mv88e6xxx_setup_message_port,
4699         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4700         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4701         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4702         .stats_get_strings = mv88e6095_stats_get_strings,
4703         .stats_get_stat = mv88e6095_stats_get_stat,
4704         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4705         .set_egress_port = mv88e6095_g1_set_egress_port,
4706         .watchdog_ops = &mv88e6097_watchdog_ops,
4707         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4708         .set_cascade_port = mv88e6185_g1_set_cascade_port,
4709         .ppu_enable = mv88e6185_g1_ppu_enable,
4710         .ppu_disable = mv88e6185_g1_ppu_disable,
4711         .reset = mv88e6185_g1_reset,
4712         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4713         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4714         .phylink_get_caps = mv88e6185_phylink_get_caps,
4715         .pcs_ops = &mv88e6185_pcs_ops,
4716         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4717 };
4718
4719 static const struct mv88e6xxx_ops mv88e6190_ops = {
4720         /* MV88E6XXX_FAMILY_6390 */
4721         .setup_errata = mv88e6390_setup_errata,
4722         .irl_init_all = mv88e6390_g2_irl_init_all,
4723         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4724         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4725         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4726         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4727         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4728         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4729         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4730         .port_set_link = mv88e6xxx_port_set_link,
4731         .port_sync_link = mv88e6xxx_port_sync_link,
4732         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4733         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4734         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4735         .port_tag_remap = mv88e6390_port_tag_remap,
4736         .port_set_policy = mv88e6352_port_set_policy,
4737         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4738         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4739         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4740         .port_set_ether_type = mv88e6351_port_set_ether_type,
4741         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4742         .port_pause_limit = mv88e6390_port_pause_limit,
4743         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4744         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4745         .port_get_cmode = mv88e6352_port_get_cmode,
4746         .port_set_cmode = mv88e6390_port_set_cmode,
4747         .port_setup_message_port = mv88e6xxx_setup_message_port,
4748         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4749         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4750         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4751         .stats_get_strings = mv88e6320_stats_get_strings,
4752         .stats_get_stat = mv88e6390_stats_get_stat,
4753         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4754         .set_egress_port = mv88e6390_g1_set_egress_port,
4755         .watchdog_ops = &mv88e6390_watchdog_ops,
4756         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4757         .pot_clear = mv88e6xxx_g2_pot_clear,
4758         .reset = mv88e6352_g1_reset,
4759         .rmu_disable = mv88e6390_g1_rmu_disable,
4760         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4761         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4762         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4763         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4764         .stu_getnext = mv88e6390_g1_stu_getnext,
4765         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4766         .serdes_get_lane = mv88e6390_serdes_get_lane,
4767         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4768         .serdes_get_strings = mv88e6390_serdes_get_strings,
4769         .serdes_get_stats = mv88e6390_serdes_get_stats,
4770         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4771         .serdes_get_regs = mv88e6390_serdes_get_regs,
4772         .gpio_ops = &mv88e6352_gpio_ops,
4773         .phylink_get_caps = mv88e6390_phylink_get_caps,
4774         .pcs_ops = &mv88e6390_pcs_ops,
4775 };
4776
4777 static const struct mv88e6xxx_ops mv88e6190x_ops = {
4778         /* MV88E6XXX_FAMILY_6390 */
4779         .setup_errata = mv88e6390_setup_errata,
4780         .irl_init_all = mv88e6390_g2_irl_init_all,
4781         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4782         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4783         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4784         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4785         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4786         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4787         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4788         .port_set_link = mv88e6xxx_port_set_link,
4789         .port_sync_link = mv88e6xxx_port_sync_link,
4790         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4791         .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4792         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4793         .port_tag_remap = mv88e6390_port_tag_remap,
4794         .port_set_policy = mv88e6352_port_set_policy,
4795         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4796         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4797         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4798         .port_set_ether_type = mv88e6351_port_set_ether_type,
4799         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4800         .port_pause_limit = mv88e6390_port_pause_limit,
4801         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4802         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4803         .port_get_cmode = mv88e6352_port_get_cmode,
4804         .port_set_cmode = mv88e6390x_port_set_cmode,
4805         .port_setup_message_port = mv88e6xxx_setup_message_port,
4806         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4807         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4808         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4809         .stats_get_strings = mv88e6320_stats_get_strings,
4810         .stats_get_stat = mv88e6390_stats_get_stat,
4811         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4812         .set_egress_port = mv88e6390_g1_set_egress_port,
4813         .watchdog_ops = &mv88e6390_watchdog_ops,
4814         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4815         .pot_clear = mv88e6xxx_g2_pot_clear,
4816         .reset = mv88e6352_g1_reset,
4817         .rmu_disable = mv88e6390_g1_rmu_disable,
4818         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4819         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4820         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4821         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4822         .stu_getnext = mv88e6390_g1_stu_getnext,
4823         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4824         .serdes_get_lane = mv88e6390x_serdes_get_lane,
4825         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4826         .serdes_get_strings = mv88e6390_serdes_get_strings,
4827         .serdes_get_stats = mv88e6390_serdes_get_stats,
4828         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4829         .serdes_get_regs = mv88e6390_serdes_get_regs,
4830         .gpio_ops = &mv88e6352_gpio_ops,
4831         .phylink_get_caps = mv88e6390x_phylink_get_caps,
4832         .pcs_ops = &mv88e6390_pcs_ops,
4833 };
4834
4835 static const struct mv88e6xxx_ops mv88e6191_ops = {
4836         /* MV88E6XXX_FAMILY_6390 */
4837         .setup_errata = mv88e6390_setup_errata,
4838         .irl_init_all = mv88e6390_g2_irl_init_all,
4839         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4840         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4841         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4842         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4843         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4844         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4845         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4846         .port_set_link = mv88e6xxx_port_set_link,
4847         .port_sync_link = mv88e6xxx_port_sync_link,
4848         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4849         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4850         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4851         .port_tag_remap = mv88e6390_port_tag_remap,
4852         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4853         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4854         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4855         .port_set_ether_type = mv88e6351_port_set_ether_type,
4856         .port_pause_limit = mv88e6390_port_pause_limit,
4857         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4858         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4859         .port_get_cmode = mv88e6352_port_get_cmode,
4860         .port_set_cmode = mv88e6390_port_set_cmode,
4861         .port_setup_message_port = mv88e6xxx_setup_message_port,
4862         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4863         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4864         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4865         .stats_get_strings = mv88e6320_stats_get_strings,
4866         .stats_get_stat = mv88e6390_stats_get_stat,
4867         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4868         .set_egress_port = mv88e6390_g1_set_egress_port,
4869         .watchdog_ops = &mv88e6390_watchdog_ops,
4870         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4871         .pot_clear = mv88e6xxx_g2_pot_clear,
4872         .reset = mv88e6352_g1_reset,
4873         .rmu_disable = mv88e6390_g1_rmu_disable,
4874         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4875         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4876         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4877         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4878         .stu_getnext = mv88e6390_g1_stu_getnext,
4879         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4880         .serdes_get_lane = mv88e6390_serdes_get_lane,
4881         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4882         .serdes_get_strings = mv88e6390_serdes_get_strings,
4883         .serdes_get_stats = mv88e6390_serdes_get_stats,
4884         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4885         .serdes_get_regs = mv88e6390_serdes_get_regs,
4886         .avb_ops = &mv88e6390_avb_ops,
4887         .ptp_ops = &mv88e6352_ptp_ops,
4888         .phylink_get_caps = mv88e6390_phylink_get_caps,
4889         .pcs_ops = &mv88e6390_pcs_ops,
4890 };
4891
4892 static const struct mv88e6xxx_ops mv88e6240_ops = {
4893         /* MV88E6XXX_FAMILY_6352 */
4894         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4895         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4896         .irl_init_all = mv88e6352_g2_irl_init_all,
4897         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4898         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4899         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4900         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4901         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4902         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4903         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4904         .port_set_link = mv88e6xxx_port_set_link,
4905         .port_sync_link = mv88e6xxx_port_sync_link,
4906         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4907         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4908         .port_tag_remap = mv88e6095_port_tag_remap,
4909         .port_set_policy = mv88e6352_port_set_policy,
4910         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4911         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4912         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4913         .port_set_ether_type = mv88e6351_port_set_ether_type,
4914         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4915         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4916         .port_pause_limit = mv88e6097_port_pause_limit,
4917         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4918         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4919         .port_get_cmode = mv88e6352_port_get_cmode,
4920         .port_setup_message_port = mv88e6xxx_setup_message_port,
4921         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4922         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4923         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4924         .stats_get_strings = mv88e6095_stats_get_strings,
4925         .stats_get_stat = mv88e6095_stats_get_stat,
4926         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4927         .set_egress_port = mv88e6095_g1_set_egress_port,
4928         .watchdog_ops = &mv88e6097_watchdog_ops,
4929         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4930         .pot_clear = mv88e6xxx_g2_pot_clear,
4931         .reset = mv88e6352_g1_reset,
4932         .rmu_disable = mv88e6352_g1_rmu_disable,
4933         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4934         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4935         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4936         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4937         .stu_getnext = mv88e6352_g1_stu_getnext,
4938         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4939         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4940         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4941         .serdes_get_regs = mv88e6352_serdes_get_regs,
4942         .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4943         .gpio_ops = &mv88e6352_gpio_ops,
4944         .avb_ops = &mv88e6352_avb_ops,
4945         .ptp_ops = &mv88e6352_ptp_ops,
4946         .phylink_get_caps = mv88e6352_phylink_get_caps,
4947         .pcs_ops = &mv88e6352_pcs_ops,
4948 };
4949
4950 static const struct mv88e6xxx_ops mv88e6250_ops = {
4951         /* MV88E6XXX_FAMILY_6250 */
4952         .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4953         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4954         .irl_init_all = mv88e6352_g2_irl_init_all,
4955         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4956         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4957         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4958         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4959         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4960         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4961         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4962         .port_set_link = mv88e6xxx_port_set_link,
4963         .port_sync_link = mv88e6xxx_port_sync_link,
4964         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4965         .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
4966         .port_tag_remap = mv88e6095_port_tag_remap,
4967         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4968         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4969         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4970         .port_set_ether_type = mv88e6351_port_set_ether_type,
4971         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4972         .port_pause_limit = mv88e6097_port_pause_limit,
4973         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4974         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4975         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4976         .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4977         .stats_get_strings = mv88e6250_stats_get_strings,
4978         .stats_get_stat = mv88e6250_stats_get_stat,
4979         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4980         .set_egress_port = mv88e6095_g1_set_egress_port,
4981         .watchdog_ops = &mv88e6250_watchdog_ops,
4982         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4983         .pot_clear = mv88e6xxx_g2_pot_clear,
4984         .reset = mv88e6250_g1_reset,
4985         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4986         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4987         .avb_ops = &mv88e6352_avb_ops,
4988         .ptp_ops = &mv88e6250_ptp_ops,
4989         .phylink_get_caps = mv88e6250_phylink_get_caps,
4990         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4991 };
4992
4993 static const struct mv88e6xxx_ops mv88e6290_ops = {
4994         /* MV88E6XXX_FAMILY_6390 */
4995         .setup_errata = mv88e6390_setup_errata,
4996         .irl_init_all = mv88e6390_g2_irl_init_all,
4997         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4998         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4999         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5000         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5001         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5002         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5003         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5004         .port_set_link = mv88e6xxx_port_set_link,
5005         .port_sync_link = mv88e6xxx_port_sync_link,
5006         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5007         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5008         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5009         .port_tag_remap = mv88e6390_port_tag_remap,
5010         .port_set_policy = mv88e6352_port_set_policy,
5011         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5012         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5013         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5014         .port_set_ether_type = mv88e6351_port_set_ether_type,
5015         .port_pause_limit = mv88e6390_port_pause_limit,
5016         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5017         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5018         .port_get_cmode = mv88e6352_port_get_cmode,
5019         .port_set_cmode = mv88e6390_port_set_cmode,
5020         .port_setup_message_port = mv88e6xxx_setup_message_port,
5021         .stats_snapshot = mv88e6390_g1_stats_snapshot,
5022         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5023         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5024         .stats_get_strings = mv88e6320_stats_get_strings,
5025         .stats_get_stat = mv88e6390_stats_get_stat,
5026         .set_cpu_port = mv88e6390_g1_set_cpu_port,
5027         .set_egress_port = mv88e6390_g1_set_egress_port,
5028         .watchdog_ops = &mv88e6390_watchdog_ops,
5029         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5030         .pot_clear = mv88e6xxx_g2_pot_clear,
5031         .reset = mv88e6352_g1_reset,
5032         .rmu_disable = mv88e6390_g1_rmu_disable,
5033         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5034         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5035         .vtu_getnext = mv88e6390_g1_vtu_getnext,
5036         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5037         .stu_getnext = mv88e6390_g1_stu_getnext,
5038         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5039         .serdes_get_lane = mv88e6390_serdes_get_lane,
5040         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5041         .serdes_get_strings = mv88e6390_serdes_get_strings,
5042         .serdes_get_stats = mv88e6390_serdes_get_stats,
5043         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5044         .serdes_get_regs = mv88e6390_serdes_get_regs,
5045         .gpio_ops = &mv88e6352_gpio_ops,
5046         .avb_ops = &mv88e6390_avb_ops,
5047         .ptp_ops = &mv88e6390_ptp_ops,
5048         .phylink_get_caps = mv88e6390_phylink_get_caps,
5049         .pcs_ops = &mv88e6390_pcs_ops,
5050 };
5051
5052 static const struct mv88e6xxx_ops mv88e6320_ops = {
5053         /* MV88E6XXX_FAMILY_6320 */
5054         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5055         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5056         .irl_init_all = mv88e6352_g2_irl_init_all,
5057         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5058         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5059         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5060         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5061         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5062         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5063         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5064         .port_set_link = mv88e6xxx_port_set_link,
5065         .port_sync_link = mv88e6xxx_port_sync_link,
5066         .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5067         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5068         .port_tag_remap = mv88e6095_port_tag_remap,
5069         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5070         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5071         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5072         .port_set_ether_type = mv88e6351_port_set_ether_type,
5073         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5074         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5075         .port_pause_limit = mv88e6097_port_pause_limit,
5076         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5077         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5078         .port_get_cmode = mv88e6352_port_get_cmode,
5079         .port_setup_message_port = mv88e6xxx_setup_message_port,
5080         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5081         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5082         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5083         .stats_get_strings = mv88e6320_stats_get_strings,
5084         .stats_get_stat = mv88e6320_stats_get_stat,
5085         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5086         .set_egress_port = mv88e6095_g1_set_egress_port,
5087         .watchdog_ops = &mv88e6390_watchdog_ops,
5088         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5089         .pot_clear = mv88e6xxx_g2_pot_clear,
5090         .reset = mv88e6352_g1_reset,
5091         .vtu_getnext = mv88e6185_g1_vtu_getnext,
5092         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5093         .gpio_ops = &mv88e6352_gpio_ops,
5094         .avb_ops = &mv88e6352_avb_ops,
5095         .ptp_ops = &mv88e6352_ptp_ops,
5096         .phylink_get_caps = mv88e6185_phylink_get_caps,
5097 };
5098
5099 static const struct mv88e6xxx_ops mv88e6321_ops = {
5100         /* MV88E6XXX_FAMILY_6320 */
5101         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5102         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5103         .irl_init_all = mv88e6352_g2_irl_init_all,
5104         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5105         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5106         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5107         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5108         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5109         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5110         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5111         .port_set_link = mv88e6xxx_port_set_link,
5112         .port_sync_link = mv88e6xxx_port_sync_link,
5113         .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5114         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5115         .port_tag_remap = mv88e6095_port_tag_remap,
5116         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5117         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5118         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5119         .port_set_ether_type = mv88e6351_port_set_ether_type,
5120         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5121         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5122         .port_pause_limit = mv88e6097_port_pause_limit,
5123         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5124         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5125         .port_get_cmode = mv88e6352_port_get_cmode,
5126         .port_setup_message_port = mv88e6xxx_setup_message_port,
5127         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5128         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5129         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5130         .stats_get_strings = mv88e6320_stats_get_strings,
5131         .stats_get_stat = mv88e6320_stats_get_stat,
5132         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5133         .set_egress_port = mv88e6095_g1_set_egress_port,
5134         .watchdog_ops = &mv88e6390_watchdog_ops,
5135         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5136         .reset = mv88e6352_g1_reset,
5137         .vtu_getnext = mv88e6185_g1_vtu_getnext,
5138         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5139         .gpio_ops = &mv88e6352_gpio_ops,
5140         .avb_ops = &mv88e6352_avb_ops,
5141         .ptp_ops = &mv88e6352_ptp_ops,
5142         .phylink_get_caps = mv88e6185_phylink_get_caps,
5143 };
5144
5145 static const struct mv88e6xxx_ops mv88e6341_ops = {
5146         /* MV88E6XXX_FAMILY_6341 */
5147         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5148         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5149         .irl_init_all = mv88e6352_g2_irl_init_all,
5150         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5151         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5152         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5153         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5154         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5155         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5156         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5157         .port_set_link = mv88e6xxx_port_set_link,
5158         .port_sync_link = mv88e6xxx_port_sync_link,
5159         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5160         .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
5161         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
5162         .port_tag_remap = mv88e6095_port_tag_remap,
5163         .port_set_policy = mv88e6352_port_set_policy,
5164         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5165         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5166         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5167         .port_set_ether_type = mv88e6351_port_set_ether_type,
5168         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5169         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5170         .port_pause_limit = mv88e6097_port_pause_limit,
5171         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5172         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5173         .port_get_cmode = mv88e6352_port_get_cmode,
5174         .port_set_cmode = mv88e6341_port_set_cmode,
5175         .port_setup_message_port = mv88e6xxx_setup_message_port,
5176         .stats_snapshot = mv88e6390_g1_stats_snapshot,
5177         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5178         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5179         .stats_get_strings = mv88e6320_stats_get_strings,
5180         .stats_get_stat = mv88e6390_stats_get_stat,
5181         .set_cpu_port = mv88e6390_g1_set_cpu_port,
5182         .set_egress_port = mv88e6390_g1_set_egress_port,
5183         .watchdog_ops = &mv88e6390_watchdog_ops,
5184         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
5185         .pot_clear = mv88e6xxx_g2_pot_clear,
5186         .reset = mv88e6352_g1_reset,
5187         .rmu_disable = mv88e6390_g1_rmu_disable,
5188         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5189         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5190         .vtu_getnext = mv88e6352_g1_vtu_getnext,
5191         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5192         .stu_getnext = mv88e6352_g1_stu_getnext,
5193         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5194         .serdes_get_lane = mv88e6341_serdes_get_lane,
5195         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5196         .gpio_ops = &mv88e6352_gpio_ops,
5197         .avb_ops = &mv88e6390_avb_ops,
5198         .ptp_ops = &mv88e6352_ptp_ops,
5199         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5200         .serdes_get_strings = mv88e6390_serdes_get_strings,
5201         .serdes_get_stats = mv88e6390_serdes_get_stats,
5202         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5203         .serdes_get_regs = mv88e6390_serdes_get_regs,
5204         .phylink_get_caps = mv88e6341_phylink_get_caps,
5205         .pcs_ops = &mv88e6390_pcs_ops,
5206 };
5207
5208 static const struct mv88e6xxx_ops mv88e6350_ops = {
5209         /* MV88E6XXX_FAMILY_6351 */
5210         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5211         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5212         .irl_init_all = mv88e6352_g2_irl_init_all,
5213         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5214         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5215         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5216         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5217         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5218         .port_set_link = mv88e6xxx_port_set_link,
5219         .port_sync_link = mv88e6xxx_port_sync_link,
5220         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5221         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5222         .port_tag_remap = mv88e6095_port_tag_remap,
5223         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5224         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5225         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5226         .port_set_ether_type = mv88e6351_port_set_ether_type,
5227         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5228         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5229         .port_pause_limit = mv88e6097_port_pause_limit,
5230         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5231         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5232         .port_get_cmode = mv88e6352_port_get_cmode,
5233         .port_setup_message_port = mv88e6xxx_setup_message_port,
5234         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5235         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5236         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5237         .stats_get_strings = mv88e6095_stats_get_strings,
5238         .stats_get_stat = mv88e6095_stats_get_stat,
5239         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5240         .set_egress_port = mv88e6095_g1_set_egress_port,
5241         .watchdog_ops = &mv88e6097_watchdog_ops,
5242         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5243         .pot_clear = mv88e6xxx_g2_pot_clear,
5244         .reset = mv88e6352_g1_reset,
5245         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5246         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5247         .vtu_getnext = mv88e6352_g1_vtu_getnext,
5248         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5249         .stu_getnext = mv88e6352_g1_stu_getnext,
5250         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5251         .phylink_get_caps = mv88e6351_phylink_get_caps,
5252 };
5253
5254 static const struct mv88e6xxx_ops mv88e6351_ops = {
5255         /* MV88E6XXX_FAMILY_6351 */
5256         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5257         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5258         .irl_init_all = mv88e6352_g2_irl_init_all,
5259         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5260         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5261         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5262         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5263         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5264         .port_set_link = mv88e6xxx_port_set_link,
5265         .port_sync_link = mv88e6xxx_port_sync_link,
5266         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5267         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5268         .port_tag_remap = mv88e6095_port_tag_remap,
5269         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5270         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5271         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5272         .port_set_ether_type = mv88e6351_port_set_ether_type,
5273         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5274         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5275         .port_pause_limit = mv88e6097_port_pause_limit,
5276         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5277         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5278         .port_get_cmode = mv88e6352_port_get_cmode,
5279         .port_setup_message_port = mv88e6xxx_setup_message_port,
5280         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5281         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5282         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5283         .stats_get_strings = mv88e6095_stats_get_strings,
5284         .stats_get_stat = mv88e6095_stats_get_stat,
5285         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5286         .set_egress_port = mv88e6095_g1_set_egress_port,
5287         .watchdog_ops = &mv88e6097_watchdog_ops,
5288         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5289         .pot_clear = mv88e6xxx_g2_pot_clear,
5290         .reset = mv88e6352_g1_reset,
5291         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5292         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5293         .vtu_getnext = mv88e6352_g1_vtu_getnext,
5294         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5295         .stu_getnext = mv88e6352_g1_stu_getnext,
5296         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5297         .avb_ops = &mv88e6352_avb_ops,
5298         .ptp_ops = &mv88e6352_ptp_ops,
5299         .phylink_get_caps = mv88e6351_phylink_get_caps,
5300 };
5301
5302 static const struct mv88e6xxx_ops mv88e6352_ops = {
5303         /* MV88E6XXX_FAMILY_6352 */
5304         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5305         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5306         .irl_init_all = mv88e6352_g2_irl_init_all,
5307         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5308         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5309         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5310         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5311         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5312         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5313         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5314         .port_set_link = mv88e6xxx_port_set_link,
5315         .port_sync_link = mv88e6xxx_port_sync_link,
5316         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5317         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
5318         .port_tag_remap = mv88e6095_port_tag_remap,
5319         .port_set_policy = mv88e6352_port_set_policy,
5320         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5321         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5322         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5323         .port_set_ether_type = mv88e6351_port_set_ether_type,
5324         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5325         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5326         .port_pause_limit = mv88e6097_port_pause_limit,
5327         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5328         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5329         .port_get_cmode = mv88e6352_port_get_cmode,
5330         .port_setup_message_port = mv88e6xxx_setup_message_port,
5331         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5332         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5333         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5334         .stats_get_strings = mv88e6095_stats_get_strings,
5335         .stats_get_stat = mv88e6095_stats_get_stat,
5336         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5337         .set_egress_port = mv88e6095_g1_set_egress_port,
5338         .watchdog_ops = &mv88e6097_watchdog_ops,
5339         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5340         .pot_clear = mv88e6xxx_g2_pot_clear,
5341         .reset = mv88e6352_g1_reset,
5342         .rmu_disable = mv88e6352_g1_rmu_disable,
5343         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5344         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5345         .vtu_getnext = mv88e6352_g1_vtu_getnext,
5346         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5347         .stu_getnext = mv88e6352_g1_stu_getnext,
5348         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5349         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5350         .gpio_ops = &mv88e6352_gpio_ops,
5351         .avb_ops = &mv88e6352_avb_ops,
5352         .ptp_ops = &mv88e6352_ptp_ops,
5353         .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
5354         .serdes_get_strings = mv88e6352_serdes_get_strings,
5355         .serdes_get_stats = mv88e6352_serdes_get_stats,
5356         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5357         .serdes_get_regs = mv88e6352_serdes_get_regs,
5358         .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5359         .phylink_get_caps = mv88e6352_phylink_get_caps,
5360         .pcs_ops = &mv88e6352_pcs_ops,
5361 };
5362
5363 static const struct mv88e6xxx_ops mv88e6390_ops = {
5364         /* MV88E6XXX_FAMILY_6390 */
5365         .setup_errata = mv88e6390_setup_errata,
5366         .irl_init_all = mv88e6390_g2_irl_init_all,
5367         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5368         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5369         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5370         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5371         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5372         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5373         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5374         .port_set_link = mv88e6xxx_port_set_link,
5375         .port_sync_link = mv88e6xxx_port_sync_link,
5376         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5377         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5378         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5379         .port_tag_remap = mv88e6390_port_tag_remap,
5380         .port_set_policy = mv88e6352_port_set_policy,
5381         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5382         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5383         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5384         .port_set_ether_type = mv88e6351_port_set_ether_type,
5385         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5386         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5387         .port_pause_limit = mv88e6390_port_pause_limit,
5388         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5389         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5390         .port_get_cmode = mv88e6352_port_get_cmode,
5391         .port_set_cmode = mv88e6390_port_set_cmode,
5392         .port_setup_message_port = mv88e6xxx_setup_message_port,
5393         .stats_snapshot = mv88e6390_g1_stats_snapshot,
5394         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5395         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5396         .stats_get_strings = mv88e6320_stats_get_strings,
5397         .stats_get_stat = mv88e6390_stats_get_stat,
5398         .set_cpu_port = mv88e6390_g1_set_cpu_port,
5399         .set_egress_port = mv88e6390_g1_set_egress_port,
5400         .watchdog_ops = &mv88e6390_watchdog_ops,
5401         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5402         .pot_clear = mv88e6xxx_g2_pot_clear,
5403         .reset = mv88e6352_g1_reset,
5404         .rmu_disable = mv88e6390_g1_rmu_disable,
5405         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5406         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5407         .vtu_getnext = mv88e6390_g1_vtu_getnext,
5408         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5409         .stu_getnext = mv88e6390_g1_stu_getnext,
5410         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5411         .serdes_get_lane = mv88e6390_serdes_get_lane,
5412         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5413         .gpio_ops = &mv88e6352_gpio_ops,
5414         .avb_ops = &mv88e6390_avb_ops,
5415         .ptp_ops = &mv88e6390_ptp_ops,
5416         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5417         .serdes_get_strings = mv88e6390_serdes_get_strings,
5418         .serdes_get_stats = mv88e6390_serdes_get_stats,
5419         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5420         .serdes_get_regs = mv88e6390_serdes_get_regs,
5421         .phylink_get_caps = mv88e6390_phylink_get_caps,
5422         .pcs_ops = &mv88e6390_pcs_ops,
5423 };
5424
5425 static const struct mv88e6xxx_ops mv88e6390x_ops = {
5426         /* MV88E6XXX_FAMILY_6390 */
5427         .setup_errata = mv88e6390_setup_errata,
5428         .irl_init_all = mv88e6390_g2_irl_init_all,
5429         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5430         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5431         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5432         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5433         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5434         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5435         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5436         .port_set_link = mv88e6xxx_port_set_link,
5437         .port_sync_link = mv88e6xxx_port_sync_link,
5438         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5439         .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
5440         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
5441         .port_tag_remap = mv88e6390_port_tag_remap,
5442         .port_set_policy = mv88e6352_port_set_policy,
5443         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5444         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5445         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5446         .port_set_ether_type = mv88e6351_port_set_ether_type,
5447         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5448         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5449         .port_pause_limit = mv88e6390_port_pause_limit,
5450         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5451         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5452         .port_get_cmode = mv88e6352_port_get_cmode,
5453         .port_set_cmode = mv88e6390x_port_set_cmode,
5454         .port_setup_message_port = mv88e6xxx_setup_message_port,
5455         .stats_snapshot = mv88e6390_g1_stats_snapshot,
5456         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5457         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5458         .stats_get_strings = mv88e6320_stats_get_strings,
5459         .stats_get_stat = mv88e6390_stats_get_stat,
5460         .set_cpu_port = mv88e6390_g1_set_cpu_port,
5461         .set_egress_port = mv88e6390_g1_set_egress_port,
5462         .watchdog_ops = &mv88e6390_watchdog_ops,
5463         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5464         .pot_clear = mv88e6xxx_g2_pot_clear,
5465         .reset = mv88e6352_g1_reset,
5466         .rmu_disable = mv88e6390_g1_rmu_disable,
5467         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5468         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5469         .vtu_getnext = mv88e6390_g1_vtu_getnext,
5470         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5471         .stu_getnext = mv88e6390_g1_stu_getnext,
5472         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5473         .serdes_get_lane = mv88e6390x_serdes_get_lane,
5474         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5475         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5476         .serdes_get_strings = mv88e6390_serdes_get_strings,
5477         .serdes_get_stats = mv88e6390_serdes_get_stats,
5478         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5479         .serdes_get_regs = mv88e6390_serdes_get_regs,
5480         .gpio_ops = &mv88e6352_gpio_ops,
5481         .avb_ops = &mv88e6390_avb_ops,
5482         .ptp_ops = &mv88e6390_ptp_ops,
5483         .phylink_get_caps = mv88e6390x_phylink_get_caps,
5484         .pcs_ops = &mv88e6390_pcs_ops,
5485 };
5486
5487 static const struct mv88e6xxx_ops mv88e6393x_ops = {
5488         /* MV88E6XXX_FAMILY_6393 */
5489         .irl_init_all = mv88e6390_g2_irl_init_all,
5490         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5491         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5492         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5493         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5494         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5495         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5496         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5497         .port_set_link = mv88e6xxx_port_set_link,
5498         .port_sync_link = mv88e6xxx_port_sync_link,
5499         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5500         .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
5501         .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
5502         .port_tag_remap = mv88e6390_port_tag_remap,
5503         .port_set_policy = mv88e6393x_port_set_policy,
5504         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5505         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5506         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5507         .port_set_ether_type = mv88e6393x_port_set_ether_type,
5508         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5509         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5510         .port_pause_limit = mv88e6390_port_pause_limit,
5511         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5512         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5513         .port_get_cmode = mv88e6352_port_get_cmode,
5514         .port_set_cmode = mv88e6393x_port_set_cmode,
5515         .port_setup_message_port = mv88e6xxx_setup_message_port,
5516         .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
5517         .stats_snapshot = mv88e6390_g1_stats_snapshot,
5518         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5519         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5520         .stats_get_strings = mv88e6320_stats_get_strings,
5521         .stats_get_stat = mv88e6390_stats_get_stat,
5522         /* .set_cpu_port is missing because this family does not support a global
5523          * CPU port, only per port CPU port which is set via
5524          * .port_set_upstream_port method.
5525          */
5526         .set_egress_port = mv88e6393x_set_egress_port,
5527         .watchdog_ops = &mv88e6393x_watchdog_ops,
5528         .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
5529         .pot_clear = mv88e6xxx_g2_pot_clear,
5530         .reset = mv88e6352_g1_reset,
5531         .rmu_disable = mv88e6390_g1_rmu_disable,
5532         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5533         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5534         .vtu_getnext = mv88e6390_g1_vtu_getnext,
5535         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5536         .stu_getnext = mv88e6390_g1_stu_getnext,
5537         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5538         .serdes_get_lane = mv88e6393x_serdes_get_lane,
5539         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5540         /* TODO: serdes stats */
5541         .gpio_ops = &mv88e6352_gpio_ops,
5542         .avb_ops = &mv88e6390_avb_ops,
5543         .ptp_ops = &mv88e6352_ptp_ops,
5544         .phylink_get_caps = mv88e6393x_phylink_get_caps,
5545         .pcs_ops = &mv88e6393x_pcs_ops,
5546 };
5547
5548 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
5549         [MV88E6020] = {
5550                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020,
5551                 .family = MV88E6XXX_FAMILY_6250,
5552                 .name = "Marvell 88E6020",
5553                 .num_databases = 64,
5554                 /* Ports 2-4 are not routed to pins
5555                  * => usable ports 0, 1, 5, 6
5556                  */
5557                 .num_ports = 7,
5558                 .num_internal_phys = 2,
5559                 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5560                 .max_vid = 4095,
5561                 .port_base_addr = 0x8,
5562                 .phy_base_addr = 0x0,
5563                 .global1_addr = 0xf,
5564                 .global2_addr = 0x7,
5565                 .age_time_coeff = 15000,
5566                 .g1_irqs = 9,
5567                 .g2_irqs = 5,
5568                 .atu_move_port_mask = 0xf,
5569                 .dual_chip = true,
5570                 .ops = &mv88e6250_ops,
5571         },
5572
5573         [MV88E6071] = {
5574                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071,
5575                 .family = MV88E6XXX_FAMILY_6250,
5576                 .name = "Marvell 88E6071",
5577                 .num_databases = 64,
5578                 .num_ports = 7,
5579                 .num_internal_phys = 5,
5580                 .max_vid = 4095,
5581                 .port_base_addr = 0x08,
5582                 .phy_base_addr = 0x00,
5583                 .global1_addr = 0x0f,
5584                 .global2_addr = 0x07,
5585                 .age_time_coeff = 15000,
5586                 .g1_irqs = 9,
5587                 .g2_irqs = 5,
5588                 .atu_move_port_mask = 0xf,
5589                 .dual_chip = true,
5590                 .ops = &mv88e6250_ops,
5591         },
5592
5593         [MV88E6085] = {
5594                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
5595                 .family = MV88E6XXX_FAMILY_6097,
5596                 .name = "Marvell 88E6085",
5597                 .num_databases = 4096,
5598                 .num_macs = 8192,
5599                 .num_ports = 10,
5600                 .num_internal_phys = 5,
5601                 .max_vid = 4095,
5602                 .max_sid = 63,
5603                 .port_base_addr = 0x10,
5604                 .phy_base_addr = 0x0,
5605                 .global1_addr = 0x1b,
5606                 .global2_addr = 0x1c,
5607                 .age_time_coeff = 15000,
5608                 .g1_irqs = 8,
5609                 .g2_irqs = 10,
5610                 .atu_move_port_mask = 0xf,
5611                 .pvt = true,
5612                 .multi_chip = true,
5613                 .ops = &mv88e6085_ops,
5614         },
5615
5616         [MV88E6095] = {
5617                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
5618                 .family = MV88E6XXX_FAMILY_6095,
5619                 .name = "Marvell 88E6095/88E6095F",
5620                 .num_databases = 256,
5621                 .num_macs = 8192,
5622                 .num_ports = 11,
5623                 .num_internal_phys = 0,
5624                 .max_vid = 4095,
5625                 .port_base_addr = 0x10,
5626                 .phy_base_addr = 0x0,
5627                 .global1_addr = 0x1b,
5628                 .global2_addr = 0x1c,
5629                 .age_time_coeff = 15000,
5630                 .g1_irqs = 8,
5631                 .atu_move_port_mask = 0xf,
5632                 .multi_chip = true,
5633                 .ops = &mv88e6095_ops,
5634         },
5635
5636         [MV88E6097] = {
5637                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
5638                 .family = MV88E6XXX_FAMILY_6097,
5639                 .name = "Marvell 88E6097/88E6097F",
5640                 .num_databases = 4096,
5641                 .num_macs = 8192,
5642                 .num_ports = 11,
5643                 .num_internal_phys = 8,
5644                 .max_vid = 4095,
5645                 .max_sid = 63,
5646                 .port_base_addr = 0x10,
5647                 .phy_base_addr = 0x0,
5648                 .global1_addr = 0x1b,
5649                 .global2_addr = 0x1c,
5650                 .age_time_coeff = 15000,
5651                 .g1_irqs = 8,
5652                 .g2_irqs = 10,
5653                 .atu_move_port_mask = 0xf,
5654                 .pvt = true,
5655                 .multi_chip = true,
5656                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5657                 .ops = &mv88e6097_ops,
5658         },
5659
5660         [MV88E6123] = {
5661                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
5662                 .family = MV88E6XXX_FAMILY_6165,
5663                 .name = "Marvell 88E6123",
5664                 .num_databases = 4096,
5665                 .num_macs = 1024,
5666                 .num_ports = 3,
5667                 .num_internal_phys = 5,
5668                 .max_vid = 4095,
5669                 .max_sid = 63,
5670                 .port_base_addr = 0x10,
5671                 .phy_base_addr = 0x0,
5672                 .global1_addr = 0x1b,
5673                 .global2_addr = 0x1c,
5674                 .age_time_coeff = 15000,
5675                 .g1_irqs = 9,
5676                 .g2_irqs = 10,
5677                 .atu_move_port_mask = 0xf,
5678                 .pvt = true,
5679                 .multi_chip = true,
5680                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5681                 .ops = &mv88e6123_ops,
5682         },
5683
5684         [MV88E6131] = {
5685                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
5686                 .family = MV88E6XXX_FAMILY_6185,
5687                 .name = "Marvell 88E6131",
5688                 .num_databases = 256,
5689                 .num_macs = 8192,
5690                 .num_ports = 8,
5691                 .num_internal_phys = 0,
5692                 .max_vid = 4095,
5693                 .port_base_addr = 0x10,
5694                 .phy_base_addr = 0x0,
5695                 .global1_addr = 0x1b,
5696                 .global2_addr = 0x1c,
5697                 .age_time_coeff = 15000,
5698                 .g1_irqs = 9,
5699                 .atu_move_port_mask = 0xf,
5700                 .multi_chip = true,
5701                 .ops = &mv88e6131_ops,
5702         },
5703
5704         [MV88E6141] = {
5705                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
5706                 .family = MV88E6XXX_FAMILY_6341,
5707                 .name = "Marvell 88E6141",
5708                 .num_databases = 4096,
5709                 .num_macs = 2048,
5710                 .num_ports = 6,
5711                 .num_internal_phys = 5,
5712                 .num_gpio = 11,
5713                 .max_vid = 4095,
5714                 .max_sid = 63,
5715                 .port_base_addr = 0x10,
5716                 .phy_base_addr = 0x10,
5717                 .global1_addr = 0x1b,
5718                 .global2_addr = 0x1c,
5719                 .age_time_coeff = 3750,
5720                 .atu_move_port_mask = 0x1f,
5721                 .g1_irqs = 9,
5722                 .g2_irqs = 10,
5723                 .pvt = true,
5724                 .multi_chip = true,
5725                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5726                 .ops = &mv88e6141_ops,
5727         },
5728
5729         [MV88E6161] = {
5730                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
5731                 .family = MV88E6XXX_FAMILY_6165,
5732                 .name = "Marvell 88E6161",
5733                 .num_databases = 4096,
5734                 .num_macs = 1024,
5735                 .num_ports = 6,
5736                 .num_internal_phys = 5,
5737                 .max_vid = 4095,
5738                 .max_sid = 63,
5739                 .port_base_addr = 0x10,
5740                 .phy_base_addr = 0x0,
5741                 .global1_addr = 0x1b,
5742                 .global2_addr = 0x1c,
5743                 .age_time_coeff = 15000,
5744                 .g1_irqs = 9,
5745                 .g2_irqs = 10,
5746                 .atu_move_port_mask = 0xf,
5747                 .pvt = true,
5748                 .multi_chip = true,
5749                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5750                 .ptp_support = true,
5751                 .ops = &mv88e6161_ops,
5752         },
5753
5754         [MV88E6165] = {
5755                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
5756                 .family = MV88E6XXX_FAMILY_6165,
5757                 .name = "Marvell 88E6165",
5758                 .num_databases = 4096,
5759                 .num_macs = 8192,
5760                 .num_ports = 6,
5761                 .num_internal_phys = 0,
5762                 .max_vid = 4095,
5763                 .max_sid = 63,
5764                 .port_base_addr = 0x10,
5765                 .phy_base_addr = 0x0,
5766                 .global1_addr = 0x1b,
5767                 .global2_addr = 0x1c,
5768                 .age_time_coeff = 15000,
5769                 .g1_irqs = 9,
5770                 .g2_irqs = 10,
5771                 .atu_move_port_mask = 0xf,
5772                 .pvt = true,
5773                 .multi_chip = true,
5774                 .ptp_support = true,
5775                 .ops = &mv88e6165_ops,
5776         },
5777
5778         [MV88E6171] = {
5779                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
5780                 .family = MV88E6XXX_FAMILY_6351,
5781                 .name = "Marvell 88E6171",
5782                 .num_databases = 4096,
5783                 .num_macs = 8192,
5784                 .num_ports = 7,
5785                 .num_internal_phys = 5,
5786                 .max_vid = 4095,
5787                 .max_sid = 63,
5788                 .port_base_addr = 0x10,
5789                 .phy_base_addr = 0x0,
5790                 .global1_addr = 0x1b,
5791                 .global2_addr = 0x1c,
5792                 .age_time_coeff = 15000,
5793                 .g1_irqs = 9,
5794                 .g2_irqs = 10,
5795                 .atu_move_port_mask = 0xf,
5796                 .pvt = true,
5797                 .multi_chip = true,
5798                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5799                 .ops = &mv88e6171_ops,
5800         },
5801
5802         [MV88E6172] = {
5803                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
5804                 .family = MV88E6XXX_FAMILY_6352,
5805                 .name = "Marvell 88E6172",
5806                 .num_databases = 4096,
5807                 .num_macs = 8192,
5808                 .num_ports = 7,
5809                 .num_internal_phys = 5,
5810                 .num_gpio = 15,
5811                 .max_vid = 4095,
5812                 .max_sid = 63,
5813                 .port_base_addr = 0x10,
5814                 .phy_base_addr = 0x0,
5815                 .global1_addr = 0x1b,
5816                 .global2_addr = 0x1c,
5817                 .age_time_coeff = 15000,
5818                 .g1_irqs = 9,
5819                 .g2_irqs = 10,
5820                 .atu_move_port_mask = 0xf,
5821                 .pvt = true,
5822                 .multi_chip = true,
5823                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5824                 .ops = &mv88e6172_ops,
5825         },
5826
5827         [MV88E6175] = {
5828                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5829                 .family = MV88E6XXX_FAMILY_6351,
5830                 .name = "Marvell 88E6175",
5831                 .num_databases = 4096,
5832                 .num_macs = 8192,
5833                 .num_ports = 7,
5834                 .num_internal_phys = 5,
5835                 .max_vid = 4095,
5836                 .max_sid = 63,
5837                 .port_base_addr = 0x10,
5838                 .phy_base_addr = 0x0,
5839                 .global1_addr = 0x1b,
5840                 .global2_addr = 0x1c,
5841                 .age_time_coeff = 15000,
5842                 .g1_irqs = 9,
5843                 .g2_irqs = 10,
5844                 .atu_move_port_mask = 0xf,
5845                 .pvt = true,
5846                 .multi_chip = true,
5847                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5848                 .ops = &mv88e6175_ops,
5849         },
5850
5851         [MV88E6176] = {
5852                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5853                 .family = MV88E6XXX_FAMILY_6352,
5854                 .name = "Marvell 88E6176",
5855                 .num_databases = 4096,
5856                 .num_macs = 8192,
5857                 .num_ports = 7,
5858                 .num_internal_phys = 5,
5859                 .num_gpio = 15,
5860                 .max_vid = 4095,
5861                 .max_sid = 63,
5862                 .port_base_addr = 0x10,
5863                 .phy_base_addr = 0x0,
5864                 .global1_addr = 0x1b,
5865                 .global2_addr = 0x1c,
5866                 .age_time_coeff = 15000,
5867                 .g1_irqs = 9,
5868                 .g2_irqs = 10,
5869                 .atu_move_port_mask = 0xf,
5870                 .pvt = true,
5871                 .multi_chip = true,
5872                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5873                 .ops = &mv88e6176_ops,
5874         },
5875
5876         [MV88E6185] = {
5877                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
5878                 .family = MV88E6XXX_FAMILY_6185,
5879                 .name = "Marvell 88E6185",
5880                 .num_databases = 256,
5881                 .num_macs = 8192,
5882                 .num_ports = 10,
5883                 .num_internal_phys = 0,
5884                 .max_vid = 4095,
5885                 .port_base_addr = 0x10,
5886                 .phy_base_addr = 0x0,
5887                 .global1_addr = 0x1b,
5888                 .global2_addr = 0x1c,
5889                 .age_time_coeff = 15000,
5890                 .g1_irqs = 8,
5891                 .atu_move_port_mask = 0xf,
5892                 .multi_chip = true,
5893                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5894                 .ops = &mv88e6185_ops,
5895         },
5896
5897         [MV88E6190] = {
5898                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
5899                 .family = MV88E6XXX_FAMILY_6390,
5900                 .name = "Marvell 88E6190",
5901                 .num_databases = 4096,
5902                 .num_macs = 16384,
5903                 .num_ports = 11,        /* 10 + Z80 */
5904                 .num_internal_phys = 9,
5905                 .num_gpio = 16,
5906                 .max_vid = 8191,
5907                 .max_sid = 63,
5908                 .port_base_addr = 0x0,
5909                 .phy_base_addr = 0x0,
5910                 .global1_addr = 0x1b,
5911                 .global2_addr = 0x1c,
5912                 .age_time_coeff = 3750,
5913                 .g1_irqs = 9,
5914                 .g2_irqs = 14,
5915                 .pvt = true,
5916                 .multi_chip = true,
5917                 .atu_move_port_mask = 0x1f,
5918                 .ops = &mv88e6190_ops,
5919         },
5920
5921         [MV88E6190X] = {
5922                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
5923                 .family = MV88E6XXX_FAMILY_6390,
5924                 .name = "Marvell 88E6190X",
5925                 .num_databases = 4096,
5926                 .num_macs = 16384,
5927                 .num_ports = 11,        /* 10 + Z80 */
5928                 .num_internal_phys = 9,
5929                 .num_gpio = 16,
5930                 .max_vid = 8191,
5931                 .max_sid = 63,
5932                 .port_base_addr = 0x0,
5933                 .phy_base_addr = 0x0,
5934                 .global1_addr = 0x1b,
5935                 .global2_addr = 0x1c,
5936                 .age_time_coeff = 3750,
5937                 .g1_irqs = 9,
5938                 .g2_irqs = 14,
5939                 .atu_move_port_mask = 0x1f,
5940                 .pvt = true,
5941                 .multi_chip = true,
5942                 .ops = &mv88e6190x_ops,
5943         },
5944
5945         [MV88E6191] = {
5946                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
5947                 .family = MV88E6XXX_FAMILY_6390,
5948                 .name = "Marvell 88E6191",
5949                 .num_databases = 4096,
5950                 .num_macs = 16384,
5951                 .num_ports = 11,        /* 10 + Z80 */
5952                 .num_internal_phys = 9,
5953                 .max_vid = 8191,
5954                 .max_sid = 63,
5955                 .port_base_addr = 0x0,
5956                 .phy_base_addr = 0x0,
5957                 .global1_addr = 0x1b,
5958                 .global2_addr = 0x1c,
5959                 .age_time_coeff = 3750,
5960                 .g1_irqs = 9,
5961                 .g2_irqs = 14,
5962                 .atu_move_port_mask = 0x1f,
5963                 .pvt = true,
5964                 .multi_chip = true,
5965                 .ptp_support = true,
5966                 .ops = &mv88e6191_ops,
5967         },
5968
5969         [MV88E6191X] = {
5970                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5971                 .family = MV88E6XXX_FAMILY_6393,
5972                 .name = "Marvell 88E6191X",
5973                 .num_databases = 4096,
5974                 .num_ports = 11,        /* 10 + Z80 */
5975                 .num_internal_phys = 8,
5976                 .internal_phys_offset = 1,
5977                 .max_vid = 8191,
5978                 .max_sid = 63,
5979                 .port_base_addr = 0x0,
5980                 .phy_base_addr = 0x0,
5981                 .global1_addr = 0x1b,
5982                 .global2_addr = 0x1c,
5983                 .age_time_coeff = 3750,
5984                 .g1_irqs = 10,
5985                 .g2_irqs = 14,
5986                 .atu_move_port_mask = 0x1f,
5987                 .pvt = true,
5988                 .multi_chip = true,
5989                 .ptp_support = true,
5990                 .ops = &mv88e6393x_ops,
5991         },
5992
5993         [MV88E6193X] = {
5994                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5995                 .family = MV88E6XXX_FAMILY_6393,
5996                 .name = "Marvell 88E6193X",
5997                 .num_databases = 4096,
5998                 .num_ports = 11,        /* 10 + Z80 */
5999                 .num_internal_phys = 8,
6000                 .internal_phys_offset = 1,
6001                 .max_vid = 8191,
6002                 .max_sid = 63,
6003                 .port_base_addr = 0x0,
6004                 .phy_base_addr = 0x0,
6005                 .global1_addr = 0x1b,
6006                 .global2_addr = 0x1c,
6007                 .age_time_coeff = 3750,
6008                 .g1_irqs = 10,
6009                 .g2_irqs = 14,
6010                 .atu_move_port_mask = 0x1f,
6011                 .pvt = true,
6012                 .multi_chip = true,
6013                 .ptp_support = true,
6014                 .ops = &mv88e6393x_ops,
6015         },
6016
6017         [MV88E6220] = {
6018                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
6019                 .family = MV88E6XXX_FAMILY_6250,
6020                 .name = "Marvell 88E6220",
6021                 .num_databases = 64,
6022
6023                 /* Ports 2-4 are not routed to pins
6024                  * => usable ports 0, 1, 5, 6
6025                  */
6026                 .num_ports = 7,
6027                 .num_internal_phys = 2,
6028                 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
6029                 .max_vid = 4095,
6030                 .port_base_addr = 0x08,
6031                 .phy_base_addr = 0x00,
6032                 .global1_addr = 0x0f,
6033                 .global2_addr = 0x07,
6034                 .age_time_coeff = 15000,
6035                 .g1_irqs = 9,
6036                 .g2_irqs = 10,
6037                 .atu_move_port_mask = 0xf,
6038                 .dual_chip = true,
6039                 .ptp_support = true,
6040                 .ops = &mv88e6250_ops,
6041         },
6042
6043         [MV88E6240] = {
6044                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
6045                 .family = MV88E6XXX_FAMILY_6352,
6046                 .name = "Marvell 88E6240",
6047                 .num_databases = 4096,
6048                 .num_macs = 8192,
6049                 .num_ports = 7,
6050                 .num_internal_phys = 5,
6051                 .num_gpio = 15,
6052                 .max_vid = 4095,
6053                 .max_sid = 63,
6054                 .port_base_addr = 0x10,
6055                 .phy_base_addr = 0x0,
6056                 .global1_addr = 0x1b,
6057                 .global2_addr = 0x1c,
6058                 .age_time_coeff = 15000,
6059                 .g1_irqs = 9,
6060                 .g2_irqs = 10,
6061                 .atu_move_port_mask = 0xf,
6062                 .pvt = true,
6063                 .multi_chip = true,
6064                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6065                 .ptp_support = true,
6066                 .ops = &mv88e6240_ops,
6067         },
6068
6069         [MV88E6250] = {
6070                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
6071                 .family = MV88E6XXX_FAMILY_6250,
6072                 .name = "Marvell 88E6250",
6073                 .num_databases = 64,
6074                 .num_ports = 7,
6075                 .num_internal_phys = 5,
6076                 .max_vid = 4095,
6077                 .port_base_addr = 0x08,
6078                 .phy_base_addr = 0x00,
6079                 .global1_addr = 0x0f,
6080                 .global2_addr = 0x07,
6081                 .age_time_coeff = 15000,
6082                 .g1_irqs = 9,
6083                 .g2_irqs = 10,
6084                 .atu_move_port_mask = 0xf,
6085                 .dual_chip = true,
6086                 .ptp_support = true,
6087                 .ops = &mv88e6250_ops,
6088         },
6089
6090         [MV88E6290] = {
6091                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
6092                 .family = MV88E6XXX_FAMILY_6390,
6093                 .name = "Marvell 88E6290",
6094                 .num_databases = 4096,
6095                 .num_ports = 11,        /* 10 + Z80 */
6096                 .num_internal_phys = 9,
6097                 .num_gpio = 16,
6098                 .max_vid = 8191,
6099                 .max_sid = 63,
6100                 .port_base_addr = 0x0,
6101                 .phy_base_addr = 0x0,
6102                 .global1_addr = 0x1b,
6103                 .global2_addr = 0x1c,
6104                 .age_time_coeff = 3750,
6105                 .g1_irqs = 9,
6106                 .g2_irqs = 14,
6107                 .atu_move_port_mask = 0x1f,
6108                 .pvt = true,
6109                 .multi_chip = true,
6110                 .ptp_support = true,
6111                 .ops = &mv88e6290_ops,
6112         },
6113
6114         [MV88E6320] = {
6115                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
6116                 .family = MV88E6XXX_FAMILY_6320,
6117                 .name = "Marvell 88E6320",
6118                 .num_databases = 4096,
6119                 .num_macs = 8192,
6120                 .num_ports = 7,
6121                 .num_internal_phys = 5,
6122                 .num_gpio = 15,
6123                 .max_vid = 4095,
6124                 .port_base_addr = 0x10,
6125                 .phy_base_addr = 0x0,
6126                 .global1_addr = 0x1b,
6127                 .global2_addr = 0x1c,
6128                 .age_time_coeff = 15000,
6129                 .g1_irqs = 8,
6130                 .g2_irqs = 10,
6131                 .atu_move_port_mask = 0xf,
6132                 .pvt = true,
6133                 .multi_chip = true,
6134                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6135                 .ptp_support = true,
6136                 .ops = &mv88e6320_ops,
6137         },
6138
6139         [MV88E6321] = {
6140                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
6141                 .family = MV88E6XXX_FAMILY_6320,
6142                 .name = "Marvell 88E6321",
6143                 .num_databases = 4096,
6144                 .num_macs = 8192,
6145                 .num_ports = 7,
6146                 .num_internal_phys = 5,
6147                 .num_gpio = 15,
6148                 .max_vid = 4095,
6149                 .port_base_addr = 0x10,
6150                 .phy_base_addr = 0x0,
6151                 .global1_addr = 0x1b,
6152                 .global2_addr = 0x1c,
6153                 .age_time_coeff = 15000,
6154                 .g1_irqs = 8,
6155                 .g2_irqs = 10,
6156                 .atu_move_port_mask = 0xf,
6157                 .multi_chip = true,
6158                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6159                 .ptp_support = true,
6160                 .ops = &mv88e6321_ops,
6161         },
6162
6163         [MV88E6341] = {
6164                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
6165                 .family = MV88E6XXX_FAMILY_6341,
6166                 .name = "Marvell 88E6341",
6167                 .num_databases = 4096,
6168                 .num_macs = 2048,
6169                 .num_internal_phys = 5,
6170                 .num_ports = 6,
6171                 .num_gpio = 11,
6172                 .max_vid = 4095,
6173                 .max_sid = 63,
6174                 .port_base_addr = 0x10,
6175                 .phy_base_addr = 0x10,
6176                 .global1_addr = 0x1b,
6177                 .global2_addr = 0x1c,
6178                 .age_time_coeff = 3750,
6179                 .atu_move_port_mask = 0x1f,
6180                 .g1_irqs = 9,
6181                 .g2_irqs = 10,
6182                 .pvt = true,
6183                 .multi_chip = true,
6184                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6185                 .ptp_support = true,
6186                 .ops = &mv88e6341_ops,
6187         },
6188
6189         [MV88E6350] = {
6190                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
6191                 .family = MV88E6XXX_FAMILY_6351,
6192                 .name = "Marvell 88E6350",
6193                 .num_databases = 4096,
6194                 .num_macs = 8192,
6195                 .num_ports = 7,
6196                 .num_internal_phys = 5,
6197                 .max_vid = 4095,
6198                 .max_sid = 63,
6199                 .port_base_addr = 0x10,
6200                 .phy_base_addr = 0x0,
6201                 .global1_addr = 0x1b,
6202                 .global2_addr = 0x1c,
6203                 .age_time_coeff = 15000,
6204                 .g1_irqs = 9,
6205                 .g2_irqs = 10,
6206                 .atu_move_port_mask = 0xf,
6207                 .pvt = true,
6208                 .multi_chip = true,
6209                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6210                 .ops = &mv88e6350_ops,
6211         },
6212
6213         [MV88E6351] = {
6214                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
6215                 .family = MV88E6XXX_FAMILY_6351,
6216                 .name = "Marvell 88E6351",
6217                 .num_databases = 4096,
6218                 .num_macs = 8192,
6219                 .num_ports = 7,
6220                 .num_internal_phys = 5,
6221                 .max_vid = 4095,
6222                 .max_sid = 63,
6223                 .port_base_addr = 0x10,
6224                 .phy_base_addr = 0x0,
6225                 .global1_addr = 0x1b,
6226                 .global2_addr = 0x1c,
6227                 .age_time_coeff = 15000,
6228                 .g1_irqs = 9,
6229                 .g2_irqs = 10,
6230                 .atu_move_port_mask = 0xf,
6231                 .pvt = true,
6232                 .multi_chip = true,
6233                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6234                 .ops = &mv88e6351_ops,
6235         },
6236
6237         [MV88E6352] = {
6238                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
6239                 .family = MV88E6XXX_FAMILY_6352,
6240                 .name = "Marvell 88E6352",
6241                 .num_databases = 4096,
6242                 .num_macs = 8192,
6243                 .num_ports = 7,
6244                 .num_internal_phys = 5,
6245                 .num_gpio = 15,
6246                 .max_vid = 4095,
6247                 .max_sid = 63,
6248                 .port_base_addr = 0x10,
6249                 .phy_base_addr = 0x0,
6250                 .global1_addr = 0x1b,
6251                 .global2_addr = 0x1c,
6252                 .age_time_coeff = 15000,
6253                 .g1_irqs = 9,
6254                 .g2_irqs = 10,
6255                 .atu_move_port_mask = 0xf,
6256                 .pvt = true,
6257                 .multi_chip = true,
6258                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6259                 .ptp_support = true,
6260                 .ops = &mv88e6352_ops,
6261         },
6262         [MV88E6361] = {
6263                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361,
6264                 .family = MV88E6XXX_FAMILY_6393,
6265                 .name = "Marvell 88E6361",
6266                 .num_databases = 4096,
6267                 .num_macs = 16384,
6268                 .num_ports = 11,
6269                 /* Ports 1, 2 and 8 are not routed */
6270                 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8),
6271                 .num_internal_phys = 5,
6272                 .internal_phys_offset = 3,
6273                 .max_vid = 4095,
6274                 .max_sid = 63,
6275                 .port_base_addr = 0x0,
6276                 .phy_base_addr = 0x0,
6277                 .global1_addr = 0x1b,
6278                 .global2_addr = 0x1c,
6279                 .age_time_coeff = 3750,
6280                 .g1_irqs = 10,
6281                 .g2_irqs = 14,
6282                 .atu_move_port_mask = 0x1f,
6283                 .pvt = true,
6284                 .multi_chip = true,
6285                 .ptp_support = true,
6286                 .ops = &mv88e6393x_ops,
6287         },
6288         [MV88E6390] = {
6289                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
6290                 .family = MV88E6XXX_FAMILY_6390,
6291                 .name = "Marvell 88E6390",
6292                 .num_databases = 4096,
6293                 .num_macs = 16384,
6294                 .num_ports = 11,        /* 10 + Z80 */
6295                 .num_internal_phys = 9,
6296                 .num_gpio = 16,
6297                 .max_vid = 8191,
6298                 .max_sid = 63,
6299                 .port_base_addr = 0x0,
6300                 .phy_base_addr = 0x0,
6301                 .global1_addr = 0x1b,
6302                 .global2_addr = 0x1c,
6303                 .age_time_coeff = 3750,
6304                 .g1_irqs = 9,
6305                 .g2_irqs = 14,
6306                 .atu_move_port_mask = 0x1f,
6307                 .pvt = true,
6308                 .multi_chip = true,
6309                 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6310                 .ptp_support = true,
6311                 .ops = &mv88e6390_ops,
6312         },
6313         [MV88E6390X] = {
6314                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
6315                 .family = MV88E6XXX_FAMILY_6390,
6316                 .name = "Marvell 88E6390X",
6317                 .num_databases = 4096,
6318                 .num_macs = 16384,
6319                 .num_ports = 11,        /* 10 + Z80 */
6320                 .num_internal_phys = 9,
6321                 .num_gpio = 16,
6322                 .max_vid = 8191,
6323                 .max_sid = 63,
6324                 .port_base_addr = 0x0,
6325                 .phy_base_addr = 0x0,
6326                 .global1_addr = 0x1b,
6327                 .global2_addr = 0x1c,
6328                 .age_time_coeff = 3750,
6329                 .g1_irqs = 9,
6330                 .g2_irqs = 14,
6331                 .atu_move_port_mask = 0x1f,
6332                 .pvt = true,
6333                 .multi_chip = true,
6334                 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6335                 .ptp_support = true,
6336                 .ops = &mv88e6390x_ops,
6337         },
6338
6339         [MV88E6393X] = {
6340                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
6341                 .family = MV88E6XXX_FAMILY_6393,
6342                 .name = "Marvell 88E6393X",
6343                 .num_databases = 4096,
6344                 .num_ports = 11,        /* 10 + Z80 */
6345                 .num_internal_phys = 8,
6346                 .internal_phys_offset = 1,
6347                 .max_vid = 8191,
6348                 .max_sid = 63,
6349                 .port_base_addr = 0x0,
6350                 .phy_base_addr = 0x0,
6351                 .global1_addr = 0x1b,
6352                 .global2_addr = 0x1c,
6353                 .age_time_coeff = 3750,
6354                 .g1_irqs = 10,
6355                 .g2_irqs = 14,
6356                 .atu_move_port_mask = 0x1f,
6357                 .pvt = true,
6358                 .multi_chip = true,
6359                 .ptp_support = true,
6360                 .ops = &mv88e6393x_ops,
6361         },
6362 };
6363
6364 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
6365 {
6366         int i;
6367
6368         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
6369                 if (mv88e6xxx_table[i].prod_num == prod_num)
6370                         return &mv88e6xxx_table[i];
6371
6372         return NULL;
6373 }
6374
6375 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
6376 {
6377         const struct mv88e6xxx_info *info;
6378         unsigned int prod_num, rev;
6379         u16 id;
6380         int err;
6381
6382         mv88e6xxx_reg_lock(chip);
6383         err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
6384         mv88e6xxx_reg_unlock(chip);
6385         if (err)
6386                 return err;
6387
6388         prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
6389         rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
6390
6391         info = mv88e6xxx_lookup_info(prod_num);
6392         if (!info)
6393                 return -ENODEV;
6394
6395         /* Update the compatible info with the probed one */
6396         chip->info = info;
6397
6398         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
6399                  chip->info->prod_num, chip->info->name, rev);
6400
6401         return 0;
6402 }
6403
6404 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip,
6405                                         struct mdio_device *mdiodev)
6406 {
6407         int err;
6408
6409         /* dual_chip takes precedence over single/multi-chip modes */
6410         if (chip->info->dual_chip)
6411                 return -EINVAL;
6412
6413         /* If the mdio addr is 16 indicating the first port address of a switch
6414          * (e.g. mv88e6*41) in single chip addressing mode the device may be
6415          * configured in single chip addressing mode. Setup the smi access as
6416          * single chip addressing mode and attempt to detect the model of the
6417          * switch, if this fails the device is not configured in single chip
6418          * addressing mode.
6419          */
6420         if (mdiodev->addr != 16)
6421                 return -EINVAL;
6422
6423         err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0);
6424         if (err)
6425                 return err;
6426
6427         return mv88e6xxx_detect(chip);
6428 }
6429
6430 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
6431 {
6432         struct mv88e6xxx_chip *chip;
6433
6434         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
6435         if (!chip)
6436                 return NULL;
6437
6438         chip->dev = dev;
6439
6440         mutex_init(&chip->reg_lock);
6441         INIT_LIST_HEAD(&chip->mdios);
6442         idr_init(&chip->policies);
6443         INIT_LIST_HEAD(&chip->msts);
6444
6445         return chip;
6446 }
6447
6448 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
6449                                                         int port,
6450                                                         enum dsa_tag_protocol m)
6451 {
6452         struct mv88e6xxx_chip *chip = ds->priv;
6453
6454         return chip->tag_protocol;
6455 }
6456
6457 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds,
6458                                          enum dsa_tag_protocol proto)
6459 {
6460         struct mv88e6xxx_chip *chip = ds->priv;
6461         enum dsa_tag_protocol old_protocol;
6462         struct dsa_port *cpu_dp;
6463         int err;
6464
6465         switch (proto) {
6466         case DSA_TAG_PROTO_EDSA:
6467                 switch (chip->info->edsa_support) {
6468                 case MV88E6XXX_EDSA_UNSUPPORTED:
6469                         return -EPROTONOSUPPORT;
6470                 case MV88E6XXX_EDSA_UNDOCUMENTED:
6471                         dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
6472                         fallthrough;
6473                 case MV88E6XXX_EDSA_SUPPORTED:
6474                         break;
6475                 }
6476                 break;
6477         case DSA_TAG_PROTO_DSA:
6478                 break;
6479         default:
6480                 return -EPROTONOSUPPORT;
6481         }
6482
6483         old_protocol = chip->tag_protocol;
6484         chip->tag_protocol = proto;
6485
6486         mv88e6xxx_reg_lock(chip);
6487         dsa_switch_for_each_cpu_port(cpu_dp, ds) {
6488                 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6489                 if (err) {
6490                         mv88e6xxx_reg_unlock(chip);
6491                         goto unwind;
6492                 }
6493         }
6494         mv88e6xxx_reg_unlock(chip);
6495
6496         return 0;
6497
6498 unwind:
6499         chip->tag_protocol = old_protocol;
6500
6501         mv88e6xxx_reg_lock(chip);
6502         dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds)
6503                 mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6504         mv88e6xxx_reg_unlock(chip);
6505
6506         return err;
6507 }
6508
6509 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
6510                                   const struct switchdev_obj_port_mdb *mdb,
6511                                   struct dsa_db db)
6512 {
6513         struct mv88e6xxx_chip *chip = ds->priv;
6514         int err;
6515
6516         mv88e6xxx_reg_lock(chip);
6517         err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
6518                                            MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
6519         mv88e6xxx_reg_unlock(chip);
6520
6521         return err;
6522 }
6523
6524 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
6525                                   const struct switchdev_obj_port_mdb *mdb,
6526                                   struct dsa_db db)
6527 {
6528         struct mv88e6xxx_chip *chip = ds->priv;
6529         int err;
6530
6531         mv88e6xxx_reg_lock(chip);
6532         err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
6533         mv88e6xxx_reg_unlock(chip);
6534
6535         return err;
6536 }
6537
6538 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
6539                                      struct dsa_mall_mirror_tc_entry *mirror,
6540                                      bool ingress,
6541                                      struct netlink_ext_ack *extack)
6542 {
6543         enum mv88e6xxx_egress_direction direction = ingress ?
6544                                                 MV88E6XXX_EGRESS_DIR_INGRESS :
6545                                                 MV88E6XXX_EGRESS_DIR_EGRESS;
6546         struct mv88e6xxx_chip *chip = ds->priv;
6547         bool other_mirrors = false;
6548         int i;
6549         int err;
6550
6551         mutex_lock(&chip->reg_lock);
6552         if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
6553             mirror->to_local_port) {
6554                 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6555                         other_mirrors |= ingress ?
6556                                          chip->ports[i].mirror_ingress :
6557                                          chip->ports[i].mirror_egress;
6558
6559                 /* Can't change egress port when other mirror is active */
6560                 if (other_mirrors) {
6561                         err = -EBUSY;
6562                         goto out;
6563                 }
6564
6565                 err = mv88e6xxx_set_egress_port(chip, direction,
6566                                                 mirror->to_local_port);
6567                 if (err)
6568                         goto out;
6569         }
6570
6571         err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
6572 out:
6573         mutex_unlock(&chip->reg_lock);
6574
6575         return err;
6576 }
6577
6578 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
6579                                       struct dsa_mall_mirror_tc_entry *mirror)
6580 {
6581         enum mv88e6xxx_egress_direction direction = mirror->ingress ?
6582                                                 MV88E6XXX_EGRESS_DIR_INGRESS :
6583                                                 MV88E6XXX_EGRESS_DIR_EGRESS;
6584         struct mv88e6xxx_chip *chip = ds->priv;
6585         bool other_mirrors = false;
6586         int i;
6587
6588         mutex_lock(&chip->reg_lock);
6589         if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
6590                 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
6591
6592         for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6593                 other_mirrors |= mirror->ingress ?
6594                                  chip->ports[i].mirror_ingress :
6595                                  chip->ports[i].mirror_egress;
6596
6597         /* Reset egress port when no other mirror is active */
6598         if (!other_mirrors) {
6599                 if (mv88e6xxx_set_egress_port(chip, direction,
6600                                               dsa_upstream_port(ds, port)))
6601                         dev_err(ds->dev, "failed to set egress port\n");
6602         }
6603
6604         mutex_unlock(&chip->reg_lock);
6605 }
6606
6607 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
6608                                            struct switchdev_brport_flags flags,
6609                                            struct netlink_ext_ack *extack)
6610 {
6611         struct mv88e6xxx_chip *chip = ds->priv;
6612         const struct mv88e6xxx_ops *ops;
6613
6614         if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
6615                            BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB))
6616                 return -EINVAL;
6617
6618         ops = chip->info->ops;
6619
6620         if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
6621                 return -EINVAL;
6622
6623         if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
6624                 return -EINVAL;
6625
6626         return 0;
6627 }
6628
6629 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
6630                                        struct switchdev_brport_flags flags,
6631                                        struct netlink_ext_ack *extack)
6632 {
6633         struct mv88e6xxx_chip *chip = ds->priv;
6634         int err = 0;
6635
6636         mv88e6xxx_reg_lock(chip);
6637
6638         if (flags.mask & BR_LEARNING) {
6639                 bool learning = !!(flags.val & BR_LEARNING);
6640                 u16 pav = learning ? (1 << port) : 0;
6641
6642                 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
6643                 if (err)
6644                         goto out;
6645         }
6646
6647         if (flags.mask & BR_FLOOD) {
6648                 bool unicast = !!(flags.val & BR_FLOOD);
6649
6650                 err = chip->info->ops->port_set_ucast_flood(chip, port,
6651                                                             unicast);
6652                 if (err)
6653                         goto out;
6654         }
6655
6656         if (flags.mask & BR_MCAST_FLOOD) {
6657                 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
6658
6659                 err = chip->info->ops->port_set_mcast_flood(chip, port,
6660                                                             multicast);
6661                 if (err)
6662                         goto out;
6663         }
6664
6665         if (flags.mask & BR_BCAST_FLOOD) {
6666                 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
6667
6668                 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
6669                 if (err)
6670                         goto out;
6671         }
6672
6673         if (flags.mask & BR_PORT_MAB) {
6674                 bool mab = !!(flags.val & BR_PORT_MAB);
6675
6676                 mv88e6xxx_port_set_mab(chip, port, mab);
6677         }
6678
6679         if (flags.mask & BR_PORT_LOCKED) {
6680                 bool locked = !!(flags.val & BR_PORT_LOCKED);
6681
6682                 err = mv88e6xxx_port_set_lock(chip, port, locked);
6683                 if (err)
6684                         goto out;
6685         }
6686 out:
6687         mv88e6xxx_reg_unlock(chip);
6688
6689         return err;
6690 }
6691
6692 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
6693                                       struct dsa_lag lag,
6694                                       struct netdev_lag_upper_info *info,
6695                                       struct netlink_ext_ack *extack)
6696 {
6697         struct mv88e6xxx_chip *chip = ds->priv;
6698         struct dsa_port *dp;
6699         int members = 0;
6700
6701         if (!mv88e6xxx_has_lag(chip)) {
6702                 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload");
6703                 return false;
6704         }
6705
6706         if (!lag.id)
6707                 return false;
6708
6709         dsa_lag_foreach_port(dp, ds->dst, &lag)
6710                 /* Includes the port joining the LAG */
6711                 members++;
6712
6713         if (members > 8) {
6714                 NL_SET_ERR_MSG_MOD(extack,
6715                                    "Cannot offload more than 8 LAG ports");
6716                 return false;
6717         }
6718
6719         /* We could potentially relax this to include active
6720          * backup in the future.
6721          */
6722         if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
6723                 NL_SET_ERR_MSG_MOD(extack,
6724                                    "Can only offload LAG using hash TX type");
6725                 return false;
6726         }
6727
6728         /* Ideally we would also validate that the hash type matches
6729          * the hardware. Alas, this is always set to unknown on team
6730          * interfaces.
6731          */
6732         return true;
6733 }
6734
6735 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag)
6736 {
6737         struct mv88e6xxx_chip *chip = ds->priv;
6738         struct dsa_port *dp;
6739         u16 map = 0;
6740         int id;
6741
6742         /* DSA LAG IDs are one-based, hardware is zero-based */
6743         id = lag.id - 1;
6744
6745         /* Build the map of all ports to distribute flows destined for
6746          * this LAG. This can be either a local user port, or a DSA
6747          * port if the LAG port is on a remote chip.
6748          */
6749         dsa_lag_foreach_port(dp, ds->dst, &lag)
6750                 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
6751
6752         return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
6753 }
6754
6755 static const u8 mv88e6xxx_lag_mask_table[8][8] = {
6756         /* Row number corresponds to the number of active members in a
6757          * LAG. Each column states which of the eight hash buckets are
6758          * mapped to the column:th port in the LAG.
6759          *
6760          * Example: In a LAG with three active ports, the second port
6761          * ([2][1]) would be selected for traffic mapped to buckets
6762          * 3,4,5 (0x38).
6763          */
6764         { 0xff,    0,    0,    0,    0,    0,    0,    0 },
6765         { 0x0f, 0xf0,    0,    0,    0,    0,    0,    0 },
6766         { 0x07, 0x38, 0xc0,    0,    0,    0,    0,    0 },
6767         { 0x03, 0x0c, 0x30, 0xc0,    0,    0,    0,    0 },
6768         { 0x03, 0x0c, 0x30, 0x40, 0x80,    0,    0,    0 },
6769         { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80,    0,    0 },
6770         { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80,    0 },
6771         { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
6772 };
6773
6774 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
6775                                         int num_tx, int nth)
6776 {
6777         u8 active = 0;
6778         int i;
6779
6780         num_tx = num_tx <= 8 ? num_tx : 8;
6781         if (nth < num_tx)
6782                 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
6783
6784         for (i = 0; i < 8; i++) {
6785                 if (BIT(i) & active)
6786                         mask[i] |= BIT(port);
6787         }
6788 }
6789
6790 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
6791 {
6792         struct mv88e6xxx_chip *chip = ds->priv;
6793         unsigned int id, num_tx;
6794         struct dsa_port *dp;
6795         struct dsa_lag *lag;
6796         int i, err, nth;
6797         u16 mask[8];
6798         u16 ivec;
6799
6800         /* Assume no port is a member of any LAG. */
6801         ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
6802
6803         /* Disable all masks for ports that _are_ members of a LAG. */
6804         dsa_switch_for_each_port(dp, ds) {
6805                 if (!dp->lag)
6806                         continue;
6807
6808                 ivec &= ~BIT(dp->index);
6809         }
6810
6811         for (i = 0; i < 8; i++)
6812                 mask[i] = ivec;
6813
6814         /* Enable the correct subset of masks for all LAG ports that
6815          * are in the Tx set.
6816          */
6817         dsa_lags_foreach_id(id, ds->dst) {
6818                 lag = dsa_lag_by_id(ds->dst, id);
6819                 if (!lag)
6820                         continue;
6821
6822                 num_tx = 0;
6823                 dsa_lag_foreach_port(dp, ds->dst, lag) {
6824                         if (dp->lag_tx_enabled)
6825                                 num_tx++;
6826                 }
6827
6828                 if (!num_tx)
6829                         continue;
6830
6831                 nth = 0;
6832                 dsa_lag_foreach_port(dp, ds->dst, lag) {
6833                         if (!dp->lag_tx_enabled)
6834                                 continue;
6835
6836                         if (dp->ds == ds)
6837                                 mv88e6xxx_lag_set_port_mask(mask, dp->index,
6838                                                             num_tx, nth);
6839
6840                         nth++;
6841                 }
6842         }
6843
6844         for (i = 0; i < 8; i++) {
6845                 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
6846                 if (err)
6847                         return err;
6848         }
6849
6850         return 0;
6851 }
6852
6853 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
6854                                         struct dsa_lag lag)
6855 {
6856         int err;
6857
6858         err = mv88e6xxx_lag_sync_masks(ds);
6859
6860         if (!err)
6861                 err = mv88e6xxx_lag_sync_map(ds, lag);
6862
6863         return err;
6864 }
6865
6866 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
6867 {
6868         struct mv88e6xxx_chip *chip = ds->priv;
6869         int err;
6870
6871         mv88e6xxx_reg_lock(chip);
6872         err = mv88e6xxx_lag_sync_masks(ds);
6873         mv88e6xxx_reg_unlock(chip);
6874         return err;
6875 }
6876
6877 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
6878                                    struct dsa_lag lag,
6879                                    struct netdev_lag_upper_info *info,
6880                                    struct netlink_ext_ack *extack)
6881 {
6882         struct mv88e6xxx_chip *chip = ds->priv;
6883         int err, id;
6884
6885         if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6886                 return -EOPNOTSUPP;
6887
6888         /* DSA LAG IDs are one-based */
6889         id = lag.id - 1;
6890
6891         mv88e6xxx_reg_lock(chip);
6892
6893         err = mv88e6xxx_port_set_trunk(chip, port, true, id);
6894         if (err)
6895                 goto err_unlock;
6896
6897         err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6898         if (err)
6899                 goto err_clear_trunk;
6900
6901         mv88e6xxx_reg_unlock(chip);
6902         return 0;
6903
6904 err_clear_trunk:
6905         mv88e6xxx_port_set_trunk(chip, port, false, 0);
6906 err_unlock:
6907         mv88e6xxx_reg_unlock(chip);
6908         return err;
6909 }
6910
6911 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6912                                     struct dsa_lag lag)
6913 {
6914         struct mv88e6xxx_chip *chip = ds->priv;
6915         int err_sync, err_trunk;
6916
6917         mv88e6xxx_reg_lock(chip);
6918         err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6919         err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6920         mv88e6xxx_reg_unlock(chip);
6921         return err_sync ? : err_trunk;
6922 }
6923
6924 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6925                                           int port)
6926 {
6927         struct mv88e6xxx_chip *chip = ds->priv;
6928         int err;
6929
6930         mv88e6xxx_reg_lock(chip);
6931         err = mv88e6xxx_lag_sync_masks(ds);
6932         mv88e6xxx_reg_unlock(chip);
6933         return err;
6934 }
6935
6936 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6937                                         int port, struct dsa_lag lag,
6938                                         struct netdev_lag_upper_info *info,
6939                                         struct netlink_ext_ack *extack)
6940 {
6941         struct mv88e6xxx_chip *chip = ds->priv;
6942         int err;
6943
6944         if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6945                 return -EOPNOTSUPP;
6946
6947         mv88e6xxx_reg_lock(chip);
6948
6949         err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6950         if (err)
6951                 goto unlock;
6952
6953         err = mv88e6xxx_pvt_map(chip, sw_index, port);
6954
6955 unlock:
6956         mv88e6xxx_reg_unlock(chip);
6957         return err;
6958 }
6959
6960 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6961                                          int port, struct dsa_lag lag)
6962 {
6963         struct mv88e6xxx_chip *chip = ds->priv;
6964         int err_sync, err_pvt;
6965
6966         mv88e6xxx_reg_lock(chip);
6967         err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6968         err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6969         mv88e6xxx_reg_unlock(chip);
6970         return err_sync ? : err_pvt;
6971 }
6972
6973 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
6974         .get_tag_protocol       = mv88e6xxx_get_tag_protocol,
6975         .change_tag_protocol    = mv88e6xxx_change_tag_protocol,
6976         .setup                  = mv88e6xxx_setup,
6977         .teardown               = mv88e6xxx_teardown,
6978         .port_setup             = mv88e6xxx_port_setup,
6979         .port_teardown          = mv88e6xxx_port_teardown,
6980         .phylink_get_caps       = mv88e6xxx_get_caps,
6981         .phylink_mac_select_pcs = mv88e6xxx_mac_select_pcs,
6982         .phylink_mac_prepare    = mv88e6xxx_mac_prepare,
6983         .phylink_mac_config     = mv88e6xxx_mac_config,
6984         .phylink_mac_finish     = mv88e6xxx_mac_finish,
6985         .phylink_mac_link_down  = mv88e6xxx_mac_link_down,
6986         .phylink_mac_link_up    = mv88e6xxx_mac_link_up,
6987         .get_strings            = mv88e6xxx_get_strings,
6988         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
6989         .get_eth_mac_stats      = mv88e6xxx_get_eth_mac_stats,
6990         .get_rmon_stats         = mv88e6xxx_get_rmon_stats,
6991         .get_sset_count         = mv88e6xxx_get_sset_count,
6992         .port_max_mtu           = mv88e6xxx_get_max_mtu,
6993         .port_change_mtu        = mv88e6xxx_change_mtu,
6994         .get_mac_eee            = mv88e6xxx_get_mac_eee,
6995         .set_mac_eee            = mv88e6xxx_set_mac_eee,
6996         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
6997         .get_eeprom             = mv88e6xxx_get_eeprom,
6998         .set_eeprom             = mv88e6xxx_set_eeprom,
6999         .get_regs_len           = mv88e6xxx_get_regs_len,
7000         .get_regs               = mv88e6xxx_get_regs,
7001         .get_rxnfc              = mv88e6xxx_get_rxnfc,
7002         .set_rxnfc              = mv88e6xxx_set_rxnfc,
7003         .set_ageing_time        = mv88e6xxx_set_ageing_time,
7004         .port_bridge_join       = mv88e6xxx_port_bridge_join,
7005         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
7006         .port_pre_bridge_flags  = mv88e6xxx_port_pre_bridge_flags,
7007         .port_bridge_flags      = mv88e6xxx_port_bridge_flags,
7008         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
7009         .port_mst_state_set     = mv88e6xxx_port_mst_state_set,
7010         .port_fast_age          = mv88e6xxx_port_fast_age,
7011         .port_vlan_fast_age     = mv88e6xxx_port_vlan_fast_age,
7012         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
7013         .port_vlan_add          = mv88e6xxx_port_vlan_add,
7014         .port_vlan_del          = mv88e6xxx_port_vlan_del,
7015         .vlan_msti_set          = mv88e6xxx_vlan_msti_set,
7016         .port_fdb_add           = mv88e6xxx_port_fdb_add,
7017         .port_fdb_del           = mv88e6xxx_port_fdb_del,
7018         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
7019         .port_mdb_add           = mv88e6xxx_port_mdb_add,
7020         .port_mdb_del           = mv88e6xxx_port_mdb_del,
7021         .port_mirror_add        = mv88e6xxx_port_mirror_add,
7022         .port_mirror_del        = mv88e6xxx_port_mirror_del,
7023         .crosschip_bridge_join  = mv88e6xxx_crosschip_bridge_join,
7024         .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
7025         .port_hwtstamp_set      = mv88e6xxx_port_hwtstamp_set,
7026         .port_hwtstamp_get      = mv88e6xxx_port_hwtstamp_get,
7027         .port_txtstamp          = mv88e6xxx_port_txtstamp,
7028         .port_rxtstamp          = mv88e6xxx_port_rxtstamp,
7029         .get_ts_info            = mv88e6xxx_get_ts_info,
7030         .devlink_param_get      = mv88e6xxx_devlink_param_get,
7031         .devlink_param_set      = mv88e6xxx_devlink_param_set,
7032         .devlink_info_get       = mv88e6xxx_devlink_info_get,
7033         .port_lag_change        = mv88e6xxx_port_lag_change,
7034         .port_lag_join          = mv88e6xxx_port_lag_join,
7035         .port_lag_leave         = mv88e6xxx_port_lag_leave,
7036         .crosschip_lag_change   = mv88e6xxx_crosschip_lag_change,
7037         .crosschip_lag_join     = mv88e6xxx_crosschip_lag_join,
7038         .crosschip_lag_leave    = mv88e6xxx_crosschip_lag_leave,
7039 };
7040
7041 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
7042 {
7043         struct device *dev = chip->dev;
7044         struct dsa_switch *ds;
7045
7046         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
7047         if (!ds)
7048                 return -ENOMEM;
7049
7050         ds->dev = dev;
7051         ds->num_ports = mv88e6xxx_num_ports(chip);
7052         ds->priv = chip;
7053         ds->dev = dev;
7054         ds->ops = &mv88e6xxx_switch_ops;
7055         ds->ageing_time_min = chip->info->age_time_coeff;
7056         ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
7057
7058         /* Some chips support up to 32, but that requires enabling the
7059          * 5-bit port mode, which we do not support. 640k^W16 ought to
7060          * be enough for anyone.
7061          */
7062         ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
7063
7064         dev_set_drvdata(dev, ds);
7065
7066         return dsa_register_switch(ds);
7067 }
7068
7069 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
7070 {
7071         dsa_unregister_switch(chip->ds);
7072 }
7073
7074 static const void *pdata_device_get_match_data(struct device *dev)
7075 {
7076         const struct of_device_id *matches = dev->driver->of_match_table;
7077         const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
7078
7079         for (; matches->name[0] || matches->type[0] || matches->compatible[0];
7080              matches++) {
7081                 if (!strcmp(pdata->compatible, matches->compatible))
7082                         return matches->data;
7083         }
7084         return NULL;
7085 }
7086
7087 /* There is no suspend to RAM support at DSA level yet, the switch configuration
7088  * would be lost after a power cycle so prevent it to be suspended.
7089  */
7090 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
7091 {
7092         return -EOPNOTSUPP;
7093 }
7094
7095 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
7096 {
7097         return 0;
7098 }
7099
7100 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
7101
7102 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
7103 {
7104         struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
7105         const struct mv88e6xxx_info *compat_info = NULL;
7106         struct device *dev = &mdiodev->dev;
7107         struct device_node *np = dev->of_node;
7108         struct mv88e6xxx_chip *chip;
7109         int port;
7110         int err;
7111
7112         if (!np && !pdata)
7113                 return -EINVAL;
7114
7115         if (np)
7116                 compat_info = of_device_get_match_data(dev);
7117
7118         if (pdata) {
7119                 compat_info = pdata_device_get_match_data(dev);
7120
7121                 if (!pdata->netdev)
7122                         return -EINVAL;
7123
7124                 for (port = 0; port < DSA_MAX_PORTS; port++) {
7125                         if (!(pdata->enabled_ports & (1 << port)))
7126                                 continue;
7127                         if (strcmp(pdata->cd.port_names[port], "cpu"))
7128                                 continue;
7129                         pdata->cd.netdev[port] = &pdata->netdev->dev;
7130                         break;
7131                 }
7132         }
7133
7134         if (!compat_info)
7135                 return -EINVAL;
7136
7137         chip = mv88e6xxx_alloc_chip(dev);
7138         if (!chip) {
7139                 err = -ENOMEM;
7140                 goto out;
7141         }
7142
7143         chip->info = compat_info;
7144
7145         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
7146         if (IS_ERR(chip->reset)) {
7147                 err = PTR_ERR(chip->reset);
7148                 goto out;
7149         }
7150         if (chip->reset)
7151                 usleep_range(10000, 20000);
7152
7153         /* Detect if the device is configured in single chip addressing mode,
7154          * otherwise continue with address specific smi init/detection.
7155          */
7156         err = mv88e6xxx_single_chip_detect(chip, mdiodev);
7157         if (err) {
7158                 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
7159                 if (err)
7160                         goto out;
7161
7162                 err = mv88e6xxx_detect(chip);
7163                 if (err)
7164                         goto out;
7165         }
7166
7167         if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
7168                 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
7169         else
7170                 chip->tag_protocol = DSA_TAG_PROTO_DSA;
7171
7172         mv88e6xxx_phy_init(chip);
7173
7174         if (chip->info->ops->get_eeprom) {
7175                 if (np)
7176                         of_property_read_u32(np, "eeprom-length",
7177                                              &chip->eeprom_len);
7178                 else
7179                         chip->eeprom_len = pdata->eeprom_len;
7180         }
7181
7182         mv88e6xxx_reg_lock(chip);
7183         err = mv88e6xxx_switch_reset(chip);
7184         mv88e6xxx_reg_unlock(chip);
7185         if (err)
7186                 goto out;
7187
7188         if (np) {
7189                 chip->irq = of_irq_get(np, 0);
7190                 if (chip->irq == -EPROBE_DEFER) {
7191                         err = chip->irq;
7192                         goto out;
7193                 }
7194         }
7195
7196         if (pdata)
7197                 chip->irq = pdata->irq;
7198
7199         /* Has to be performed before the MDIO bus is created, because
7200          * the PHYs will link their interrupts to these interrupt
7201          * controllers
7202          */
7203         mv88e6xxx_reg_lock(chip);
7204         if (chip->irq > 0)
7205                 err = mv88e6xxx_g1_irq_setup(chip);
7206         else
7207                 err = mv88e6xxx_irq_poll_setup(chip);
7208         mv88e6xxx_reg_unlock(chip);
7209
7210         if (err)
7211                 goto out;
7212
7213         if (chip->info->g2_irqs > 0) {
7214                 err = mv88e6xxx_g2_irq_setup(chip);
7215                 if (err)
7216                         goto out_g1_irq;
7217         }
7218
7219         err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
7220         if (err)
7221                 goto out_g2_irq;
7222
7223         err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
7224         if (err)
7225                 goto out_g1_atu_prob_irq;
7226
7227         err = mv88e6xxx_register_switch(chip);
7228         if (err)
7229                 goto out_g1_vtu_prob_irq;
7230
7231         return 0;
7232
7233 out_g1_vtu_prob_irq:
7234         mv88e6xxx_g1_vtu_prob_irq_free(chip);
7235 out_g1_atu_prob_irq:
7236         mv88e6xxx_g1_atu_prob_irq_free(chip);
7237 out_g2_irq:
7238         if (chip->info->g2_irqs > 0)
7239                 mv88e6xxx_g2_irq_free(chip);
7240 out_g1_irq:
7241         if (chip->irq > 0)
7242                 mv88e6xxx_g1_irq_free(chip);
7243         else
7244                 mv88e6xxx_irq_poll_free(chip);
7245 out:
7246         if (pdata)
7247                 dev_put(pdata->netdev);
7248
7249         return err;
7250 }
7251
7252 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
7253 {
7254         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7255         struct mv88e6xxx_chip *chip;
7256
7257         if (!ds)
7258                 return;
7259
7260         chip = ds->priv;
7261
7262         if (chip->info->ptp_support) {
7263                 mv88e6xxx_hwtstamp_free(chip);
7264                 mv88e6xxx_ptp_free(chip);
7265         }
7266
7267         mv88e6xxx_phy_destroy(chip);
7268         mv88e6xxx_unregister_switch(chip);
7269
7270         mv88e6xxx_g1_vtu_prob_irq_free(chip);
7271         mv88e6xxx_g1_atu_prob_irq_free(chip);
7272
7273         if (chip->info->g2_irqs > 0)
7274                 mv88e6xxx_g2_irq_free(chip);
7275
7276         if (chip->irq > 0)
7277                 mv88e6xxx_g1_irq_free(chip);
7278         else
7279                 mv88e6xxx_irq_poll_free(chip);
7280 }
7281
7282 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
7283 {
7284         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7285
7286         if (!ds)
7287                 return;
7288
7289         dsa_switch_shutdown(ds);
7290
7291         dev_set_drvdata(&mdiodev->dev, NULL);
7292 }
7293
7294 static const struct of_device_id mv88e6xxx_of_match[] = {
7295         {
7296                 .compatible = "marvell,mv88e6085",
7297                 .data = &mv88e6xxx_table[MV88E6085],
7298         },
7299         {
7300                 .compatible = "marvell,mv88e6190",
7301                 .data = &mv88e6xxx_table[MV88E6190],
7302         },
7303         {
7304                 .compatible = "marvell,mv88e6250",
7305                 .data = &mv88e6xxx_table[MV88E6250],
7306         },
7307         { /* sentinel */ },
7308 };
7309
7310 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
7311
7312 static struct mdio_driver mv88e6xxx_driver = {
7313         .probe  = mv88e6xxx_probe,
7314         .remove = mv88e6xxx_remove,
7315         .shutdown = mv88e6xxx_shutdown,
7316         .mdiodrv.driver = {
7317                 .name = "mv88e6085",
7318                 .of_match_table = mv88e6xxx_of_match,
7319                 .pm = &mv88e6xxx_pm_ops,
7320         },
7321 };
7322
7323 mdio_module_driver(mv88e6xxx_driver);
7324
7325 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
7326 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
7327 MODULE_LICENSE("GPL");