1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2023 Advanced Micro Devices, Inc */
7 #include <linux/debugfs.h>
8 #include <net/devlink.h>
10 #include <linux/pds/pds_common.h>
11 #include <linux/pds/pds_core_if.h>
12 #include <linux/pds/pds_adminq.h>
13 #include <linux/pds/pds_intr.h>
15 #define PDSC_DRV_DESCRIPTION "AMD/Pensando Core Driver"
17 #define PDSC_WATCHDOG_SECS 5
18 #define PDSC_QUEUE_NAME_MAX_SZ 16
19 #define PDSC_ADMINQ_MIN_LENGTH 16 /* must be a power of two */
20 #define PDSC_NOTIFYQ_LENGTH 64 /* must be a power of two */
21 #define PDSC_TEARDOWN_RECOVERY false
22 #define PDSC_TEARDOWN_REMOVING true
23 #define PDSC_SETUP_RECOVERY false
24 #define PDSC_SETUP_INIT true
36 struct pds_auxiliary_dev *padev;
39 __le16 vif_types[PDS_DEV_TYPE_MAX];
45 char fw_version[PDS_CORE_DEVINFO_FWVERS_BUFLEN + 1];
46 char serial_num[PDS_CORE_DEVINFO_SERIAL_BUFLEN + 1];
50 struct pdsc_q_info *info;
56 unsigned int num_descs;
60 unsigned int hw_index;
63 struct pds_core_admin_cmd *adminq;
65 dma_addr_t base_pa; /* must be page aligned */
66 unsigned int desc_size;
68 char name[PDSC_QUEUE_NAME_MAX_SZ];
71 #define PDSC_INTR_NAME_MAX_SZ 32
73 struct pdsc_intr_info {
74 char name[PDSC_INTR_NAME_MAX_SZ];
84 struct pdsc_buf_info {
94 struct pdsc_admin_cmd *adminq_desc;
98 struct pdsc_buf_info bufs[PDS_CORE_MAX_FRAGS];
99 struct pdsc_wait_context *wc;
104 struct pdsc_cq_info *info;
105 struct pdsc_queue *bound_q;
106 struct pdsc_intr_info *bound_intr;
109 unsigned int num_descs;
110 unsigned int desc_size;
112 dma_addr_t base_pa; /* must be page aligned */
113 } ____cacheline_aligned_in_smp;
118 dma_addr_t q_base_pa; /* might not be page aligned */
120 dma_addr_t cq_base_pa; /* might not be page aligned */
126 struct work_struct work;
132 struct dentry *dentry;
135 struct pdsc_viftype {
141 struct pds_auxiliary_dev *padev;
144 /* No state flags set means we are in a steady running state */
145 enum pdsc_state_flags {
146 PDSC_S_FW_DEAD, /* stopped, wait on startup or recovery */
147 PDSC_S_INITING_DRIVER, /* initial startup from probe */
148 PDSC_S_STOPPING_DRIVER, /* driver remove */
150 /* leave this as last */
155 struct pci_dev *pdev;
156 struct dentry *dentry;
158 struct pdsc_dev_bar bars[PDS_CORE_BARS_MAX];
168 unsigned long last_fw_time;
170 struct timer_list wdtimer;
171 unsigned int wdtimer_period;
172 struct work_struct health_work;
173 struct devlink_health_reporter *fw_reporter;
176 struct pdsc_devinfo dev_info;
177 struct pds_core_dev_identity dev_ident;
179 struct pdsc_intr_info *intr_info; /* array of nintrs elements */
181 struct workqueue_struct *wq;
183 unsigned int devcmd_timeout;
184 struct mutex devcmd_lock; /* lock for dev_cmd operations */
185 struct mutex config_lock; /* lock for configuration operations */
186 spinlock_t adminq_lock; /* lock for adminq operations */
187 struct pds_core_dev_info_regs __iomem *info_regs;
188 struct pds_core_dev_cmd_regs __iomem *cmd_regs;
189 struct pds_core_intr __iomem *intr_ctrl;
190 u64 __iomem *intr_status;
191 u64 __iomem *db_pages;
192 dma_addr_t phy_db_pages;
193 u64 __iomem *kern_dbpage;
195 struct pdsc_qcq adminqcq;
196 struct pdsc_qcq notifyqcq;
198 struct pdsc_viftype *viftype_status;
201 /** enum pds_core_dbell_bits - bitwise composition of dbell values.
203 * @PDS_CORE_DBELL_QID_MASK: unshifted mask of valid queue id bits.
204 * @PDS_CORE_DBELL_QID_SHIFT: queue id shift amount in dbell value.
205 * @PDS_CORE_DBELL_QID: macro to build QID component of dbell value.
207 * @PDS_CORE_DBELL_RING_MASK: unshifted mask of valid ring bits.
208 * @PDS_CORE_DBELL_RING_SHIFT: ring shift amount in dbell value.
209 * @PDS_CORE_DBELL_RING: macro to build ring component of dbell value.
211 * @PDS_CORE_DBELL_RING_0: ring zero dbell component value.
212 * @PDS_CORE_DBELL_RING_1: ring one dbell component value.
213 * @PDS_CORE_DBELL_RING_2: ring two dbell component value.
214 * @PDS_CORE_DBELL_RING_3: ring three dbell component value.
216 * @PDS_CORE_DBELL_INDEX_MASK: bit mask of valid index bits, no shift needed.
218 enum pds_core_dbell_bits {
219 PDS_CORE_DBELL_QID_MASK = 0xffffff,
220 PDS_CORE_DBELL_QID_SHIFT = 24,
222 #define PDS_CORE_DBELL_QID(n) \
223 (((u64)(n) & PDS_CORE_DBELL_QID_MASK) << PDS_CORE_DBELL_QID_SHIFT)
225 PDS_CORE_DBELL_RING_MASK = 0x7,
226 PDS_CORE_DBELL_RING_SHIFT = 16,
228 #define PDS_CORE_DBELL_RING(n) \
229 (((u64)(n) & PDS_CORE_DBELL_RING_MASK) << PDS_CORE_DBELL_RING_SHIFT)
231 PDS_CORE_DBELL_RING_0 = 0,
232 PDS_CORE_DBELL_RING_1 = PDS_CORE_DBELL_RING(1),
233 PDS_CORE_DBELL_RING_2 = PDS_CORE_DBELL_RING(2),
234 PDS_CORE_DBELL_RING_3 = PDS_CORE_DBELL_RING(3),
236 PDS_CORE_DBELL_INDEX_MASK = 0xffff,
239 static inline void pds_core_dbell_ring(u64 __iomem *db_page,
240 enum pds_core_logical_qtype qtype,
243 writeq(val, &db_page[qtype]);
246 int pdsc_fw_reporter_diagnose(struct devlink_health_reporter *reporter,
247 struct devlink_fmsg *fmsg,
248 struct netlink_ext_ack *extack);
249 int pdsc_dl_info_get(struct devlink *dl, struct devlink_info_req *req,
250 struct netlink_ext_ack *extack);
251 int pdsc_dl_flash_update(struct devlink *dl,
252 struct devlink_flash_update_params *params,
253 struct netlink_ext_ack *extack);
254 int pdsc_dl_enable_get(struct devlink *dl, u32 id,
255 struct devlink_param_gset_ctx *ctx);
256 int pdsc_dl_enable_set(struct devlink *dl, u32 id,
257 struct devlink_param_gset_ctx *ctx);
258 int pdsc_dl_enable_validate(struct devlink *dl, u32 id,
259 union devlink_param_value val,
260 struct netlink_ext_ack *extack);
262 void __iomem *pdsc_map_dbpage(struct pdsc *pdsc, int page_num);
264 void pdsc_debugfs_create(void);
265 void pdsc_debugfs_destroy(void);
266 void pdsc_debugfs_add_dev(struct pdsc *pdsc);
267 void pdsc_debugfs_del_dev(struct pdsc *pdsc);
268 void pdsc_debugfs_add_ident(struct pdsc *pdsc);
269 void pdsc_debugfs_add_viftype(struct pdsc *pdsc);
270 void pdsc_debugfs_add_irqs(struct pdsc *pdsc);
271 void pdsc_debugfs_add_qcq(struct pdsc *pdsc, struct pdsc_qcq *qcq);
272 void pdsc_debugfs_del_qcq(struct pdsc_qcq *qcq);
274 int pdsc_err_to_errno(enum pds_core_status_code code);
275 bool pdsc_is_fw_running(struct pdsc *pdsc);
276 bool pdsc_is_fw_good(struct pdsc *pdsc);
277 int pdsc_devcmd(struct pdsc *pdsc, union pds_core_dev_cmd *cmd,
278 union pds_core_dev_comp *comp, int max_seconds);
279 int pdsc_devcmd_locked(struct pdsc *pdsc, union pds_core_dev_cmd *cmd,
280 union pds_core_dev_comp *comp, int max_seconds);
281 int pdsc_devcmd_init(struct pdsc *pdsc);
282 int pdsc_devcmd_reset(struct pdsc *pdsc);
283 int pdsc_dev_reinit(struct pdsc *pdsc);
284 int pdsc_dev_init(struct pdsc *pdsc);
286 void pdsc_reset_prepare(struct pci_dev *pdev);
287 void pdsc_reset_done(struct pci_dev *pdev);
289 int pdsc_intr_alloc(struct pdsc *pdsc, char *name,
290 irq_handler_t handler, void *data);
291 void pdsc_intr_free(struct pdsc *pdsc, int index);
292 void pdsc_qcq_free(struct pdsc *pdsc, struct pdsc_qcq *qcq);
293 int pdsc_qcq_alloc(struct pdsc *pdsc, unsigned int type, unsigned int index,
294 const char *name, unsigned int flags, unsigned int num_descs,
295 unsigned int desc_size, unsigned int cq_desc_size,
296 unsigned int pid, struct pdsc_qcq *qcq);
297 int pdsc_setup(struct pdsc *pdsc, bool init);
298 void pdsc_teardown(struct pdsc *pdsc, bool removing);
299 int pdsc_start(struct pdsc *pdsc);
300 void pdsc_stop(struct pdsc *pdsc);
301 void pdsc_health_thread(struct work_struct *work);
303 int pdsc_register_notify(struct notifier_block *nb);
304 void pdsc_unregister_notify(struct notifier_block *nb);
305 void pdsc_notify(unsigned long event, void *data);
306 int pdsc_auxbus_dev_add(struct pdsc *cf, struct pdsc *pf);
307 int pdsc_auxbus_dev_del(struct pdsc *cf, struct pdsc *pf);
309 void pdsc_process_adminq(struct pdsc_qcq *qcq);
310 void pdsc_work_thread(struct work_struct *work);
311 irqreturn_t pdsc_adminq_isr(int irq, void *data);
313 int pdsc_firmware_update(struct pdsc *pdsc, const struct firmware *fw,
314 struct netlink_ext_ack *extack);
316 void pdsc_fw_down(struct pdsc *pdsc);
317 void pdsc_fw_up(struct pdsc *pdsc);
319 #endif /* _PDSC_H_ */