drivers/phy/qualcomm/phy-qcom-qmp-ufs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/phy/phy.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regulator/consumer.h>
  19 #include <linux/reset.h>
  20 #include <linux/slab.h>
  21
  22 #include <ufs/unipro.h>
  23 #include "phy-qcom-qmp.h"
  24 #include "phy-qcom-qmp-pcs-ufs-v2.h"
  25 #include "phy-qcom-qmp-pcs-ufs-v3.h"
  26 #include "phy-qcom-qmp-pcs-ufs-v4.h"
  27 #include "phy-qcom-qmp-pcs-ufs-v5.h"
  28 #include "phy-qcom-qmp-pcs-ufs-v6.h"
  29
  30 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
  31
  32 /* QPHY_SW_RESET bit */
  33 #define SW_RESET                                BIT(0)
  34 /* QPHY_POWER_DOWN_CONTROL */
  35 #define SW_PWRDN                                BIT(0)
  36 /* QPHY_START_CONTROL bits */
  37 #define SERDES_START                            BIT(0)
  38 #define PCS_START                               BIT(1)
  39 /* QPHY_PCS_READY_STATUS bit */
  40 #define PCS_READY                               BIT(0)
  41
  42 #define PHY_INIT_COMPLETE_TIMEOUT               10000
  43
  44 struct qmp_phy_init_tbl {
  45         unsigned int offset;
  46         unsigned int val;
  47         /*
  48          * mask of lanes for which this register is written
  49          * for cases when second lane needs different values
  50          */
  51         u8 lane_mask;
  52 };
  53
  54 #define QMP_PHY_INIT_CFG(o, v)          \
  55         {                               \
  56                 .offset = o,            \
  57                 .val = v,               \
  58                 .lane_mask = 0xff,      \
  59         }
  60
  61 #define QMP_PHY_INIT_CFG_LANE(o, v, l)  \
  62         {                               \
  63                 .offset = o,            \
  64                 .val = v,               \
  65                 .lane_mask = l,         \
  66         }
  67
  68 /* set of registers with offsets different per-PHY */
  69 enum qphy_reg_layout {
  70         /* PCS registers */
  71         QPHY_SW_RESET,
  72         QPHY_START_CTRL,
  73         QPHY_PCS_READY_STATUS,
  74         QPHY_PCS_POWER_DOWN_CONTROL,
  75         /* Keep last to ensure regs_layout arrays are properly initialized */
  76         QPHY_LAYOUT_SIZE
  77 };
  78
  79 static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
  80         [QPHY_START_CTRL]               = QPHY_V2_PCS_UFS_PHY_START,
  81         [QPHY_PCS_READY_STATUS]         = QPHY_V2_PCS_UFS_READY_STATUS,
  82         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL,
  83 };
  84
  85 static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
  86         [QPHY_START_CTRL]               = QPHY_V3_PCS_UFS_PHY_START,
  87         [QPHY_PCS_READY_STATUS]         = QPHY_V3_PCS_UFS_READY_STATUS,
  88         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL,
  89 };
  90
  91 static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
  92         [QPHY_START_CTRL]               = QPHY_V4_PCS_UFS_PHY_START,
  93         [QPHY_PCS_READY_STATUS]         = QPHY_V4_PCS_UFS_READY_STATUS,
  94         [QPHY_SW_RESET]                 = QPHY_V4_PCS_UFS_SW_RESET,
  95         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL,
  96 };
  97
  98 static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
  99         [QPHY_START_CTRL]               = QPHY_V5_PCS_UFS_PHY_START,
 100         [QPHY_PCS_READY_STATUS]         = QPHY_V5_PCS_UFS_READY_STATUS,
 101         [QPHY_SW_RESET]                 = QPHY_V5_PCS_UFS_SW_RESET,
 102         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL,
 103 };
 104
 105 static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
 106         [QPHY_START_CTRL]               = QPHY_V6_PCS_UFS_PHY_START,
 107         [QPHY_PCS_READY_STATUS]         = QPHY_V6_PCS_UFS_READY_STATUS,
 108         [QPHY_SW_RESET]                 = QPHY_V6_PCS_UFS_SW_RESET,
 109         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL,
 110 };
 111
 112 static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = {
 113         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
 114         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
 115         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 116         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 117         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 118         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 119         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
 120         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 121         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
 122         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
 123         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
 124         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 125         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 126         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 127         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 128         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
 129         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
 130         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
 131         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 132         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
 133         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
 134         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
 135         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 136         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 137         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 138         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 139         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 140         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
 141         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
 142         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
 143         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
 144         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 145         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
 146         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
 147         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
 148         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
 149         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
 150         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
 151         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
 152         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
 153         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 154         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
 155         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
 156         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
 157         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
 158         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
 159 };
 160
 161 static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] = {
 162         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 163         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
 164 };
 165
 166 static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = {
 167         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
 168         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
 169         QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
 170         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
 171         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
 172         QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
 173         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
 174         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
 175         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
 176         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
 177         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
 178 };
 179
 180 static const struct qmp_phy_init_tbl sc7280_ufsphy_tx[] = {
 181         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
 182         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
 183         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
 184         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
 185         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
 186         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
 187 };
 188
 189 static const struct qmp_phy_init_tbl sc7280_ufsphy_rx[] = {
 190         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
 191         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
 192         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
 193         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
 194         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
 195         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
 196         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
 197         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 198         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
 199         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
 200         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
 201         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
 202         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
 203         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 204         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
 205         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
 206         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
 207         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 208         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 209         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x6d),
 210         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x6d),
 211         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xed),
 212         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
 213         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3c),
 214         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
 215         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
 216         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
 217         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
 218         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
 219         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
 220         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
 221         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
 222         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
 223         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
 224         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 225 };
 226
 227 static const struct qmp_phy_init_tbl sc7280_ufsphy_pcs[] = {
 228         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
 229         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
 230         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
 231         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
 232         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
 233         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
 234         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 235         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x03),
 236         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
 237         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
 238         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
 239         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
 240         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
 241         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
 242 };
 243
 244 static const struct qmp_phy_init_tbl sc7280_ufsphy_hs_g4_rx[] = {
 245         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
 246         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
 247         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
 248         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
 249         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
 250         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
 251         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
 252         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 253         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
 254         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
 255         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
 256         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
 257         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
 258         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
 259         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
 260         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
 261         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
 262         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
 263         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
 264         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
 265         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
 266         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
 267         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
 268         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
 269         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 270         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
 271         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
 272         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
 273         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
 274         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
 275         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
 276         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
 277         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
 278         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
 279         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
 280         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
 281         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 282         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f),
 283 };
 284
 285 static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = {
 286         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
 287         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
 288         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 289         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
 290         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 291         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 292         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 293         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 294         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
 295         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
 296         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
 297         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 298         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 299         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 300         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 301         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
 302         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
 303         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
 304         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 305         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
 306         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
 307         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
 308         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 309         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 310         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 311         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 312         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 313         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
 314         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
 315         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
 316         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
 317         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 318         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
 319         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
 320         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
 321         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
 322         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
 323         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
 324         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
 325         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
 326         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 327         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
 328         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
 329         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
 330         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
 331         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
 332         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 333         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 334         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
 335         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
 336 };
 337
 338 static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] = {
 339         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
 340 };
 341
 342 static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] = {
 343         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 344         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 345 };
 346
 347 static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] = {
 348         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
 349         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
 350         QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
 351         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
 352         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
 353         QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
 354         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
 355         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
 356         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
 357         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
 358         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
 359         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
 360         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
 361         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
 362         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
 363 };
 364
 365 static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] = {
 366         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND, 0x15),
 367         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
 368         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
 369         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
 370         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
 371         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
 372         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
 373         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
 374         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
 375 };
 376
 377 static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = {
 378         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 379         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 380         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
 381         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 382         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 383         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
 384         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 385         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 386         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 387         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 388         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
 389         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 390         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
 391         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
 392         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
 393         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
 394         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 395         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 396         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 397         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 398         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 399         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 400         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
 401         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 402         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
 403         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
 404         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
 405         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
 406         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
 407         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
 408         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
 409         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 410         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
 411         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
 412         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
 413         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
 414 };
 415
 416 static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] = {
 417         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
 418 };
 419
 420 static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] = {
 421         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 422         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
 423         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
 424 };
 425
 426 static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] = {
 427         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
 428         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
 429         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
 430         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 431         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 432         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
 433         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
 434         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 435         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
 436         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
 437         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
 438         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
 439         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 440         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
 441         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 442         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
 443 };
 444
 445 static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] = {
 446         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e),
 447         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
 448         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
 449         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
 450         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
 451         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f),
 452         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a),
 453         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 454 };
 455
 456 static const struct qmp_phy_init_tbl sm7150_ufsphy_rx[] = {
 457         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
 458         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
 459         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
 460         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 461         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 462         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
 463         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
 464         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 465         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
 466         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
 467         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
 468         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
 469         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5b),
 470         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
 471         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 472         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
 473 };
 474
 475 static const struct qmp_phy_init_tbl sm7150_ufsphy_pcs[] = {
 476         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6f),
 477         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
 478         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
 479         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
 480         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
 481         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f),
 482         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
 483         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 484 };
 485
 486 static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = {
 487         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
 488         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
 489         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
 490         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
 491         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
 492         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
 493         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
 494         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
 495         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
 496         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 497         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 498         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 499         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
 500         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
 501         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
 502         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
 503         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
 504         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
 505         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
 506         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
 507         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
 508         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
 509         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
 510         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
 511 };
 512
 513 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] = {
 514         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
 515 };
 516
 517 static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = {
 518         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
 519         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
 520         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
 521         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
 522         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
 523         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
 524 };
 525
 526 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] = {
 527         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75),
 528 };
 529
 530 static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {
 531         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
 532         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
 533         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
 534         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
 535         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
 536         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 537         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
 538         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 539         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
 540         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
 541         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
 542         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
 543         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
 544         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 545         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
 546         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
 547         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
 548         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 549         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 550         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
 551         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
 552         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
 553         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
 554         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
 555         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
 556         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
 557         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
 558         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
 559         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
 560         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
 561         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
 562         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
 563         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
 564         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
 565 };
 566
 567 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] = {
 568         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
 569         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
 570         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
 571         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
 572         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
 573         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
 574         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
 575         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
 576         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
 577         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
 578         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 579         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c),
 580         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
 581         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
 582         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
 583         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
 584 };
 585
 586 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {
 587         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
 588         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
 589         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
 590         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
 591         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
 592         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
 593         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 594 };
 595
 596 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = {
 597         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10),
 598         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
 599 };
 600
 601 static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = {
 602         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5),
 603 };
 604
 605 static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = {
 606         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
 607         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
 608         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
 609         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
 610         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
 611         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
 612         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
 613         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
 614         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
 615         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
 616         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
 617         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
 618         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
 619         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
 620         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
 621         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 622         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
 623         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
 624         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
 625         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
 626         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
 627 };
 628
 629 static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {
 630         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
 631         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
 632         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
 633         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
 634         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
 635         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
 636         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
 637         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
 638         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
 639         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
 640         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
 641         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
 642         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
 643         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
 644         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
 645         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
 646         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
 647         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
 648         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
 649         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
 650         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
 651         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
 652         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
 653         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
 654 };
 655
 656 static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] = {
 657         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
 658 };
 659
 660 static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] = {
 661         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
 662         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
 663         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
 664         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
 665         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
 666         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
 667         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
 668         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
 669         QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
 670 };
 671
 672 static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] = {
 673         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
 674         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
 675         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
 676         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
 677         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
 678         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
 679         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
 680         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 681         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
 682         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
 683         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
 684         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
 685         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
 686         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
 687         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 688         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
 689         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
 690         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
 691         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
 692         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 693         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 694         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
 695         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
 696         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
 697         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
 698         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
 699         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
 700         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
 701         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
 702         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
 703         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
 704         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
 705         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
 706         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
 707         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
 708         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
 709         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
 710 };
 711
 712 static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = {
 713         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
 714         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
 715         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
 716         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
 717         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
 718         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
 719         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
 720         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 721 };
 722
 723 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] = {
 724         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5),
 725 };
 726
 727 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] = {
 728         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81),
 729         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f),
 730         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
 731         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 732         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 733         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20),
 734         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80),
 735         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
 736         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf),
 737         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf),
 738         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
 739         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f),
 740         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d),
 741         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d),
 742         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d),
 743         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed),
 744         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c),
 745 };
 746
 747 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = {
 748         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
 749 };
 750
 751 static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
 752         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
 753         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
 754         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
 755         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
 756         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
 757         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
 758         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
 759         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
 760         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
 761         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
 762         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
 763         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
 764         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
 765         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
 766         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
 767         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
 768         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
 769         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
 770         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
 771         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
 772 };
 773
 774 static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
 775         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
 776 };
 777
 778 static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
 779         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
 780         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
 781         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
 782 };
 783
 784 static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
 785         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
 786         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
 787
 788         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
 789         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
 790         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),
 791         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),
 792
 793         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),
 794         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
 795
 796         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),
 797         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),
 798         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),
 799         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
 800 };
 801
 802 static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
 803         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
 804         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
 805         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
 806         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
 807         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 808         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
 809         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
 810 };
 811
 812 static const struct qmp_phy_init_tbl sm8650_ufsphy_serdes[] = {
 813         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
 814         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
 815         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
 816         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
 817         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
 818         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
 819         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
 820         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
 821         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
 822         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
 823         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
 824         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
 825         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
 826         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
 827         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
 828         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
 829         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
 830         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
 831         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
 832         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
 833 };
 834
 835 static const struct qmp_phy_init_tbl sm8650_ufsphy_tx[] = {
 836         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
 837         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
 838 };
 839
 840 static const struct qmp_phy_init_tbl sm8650_ufsphy_rx[] = {
 841         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
 842         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0f),
 843         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
 844         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
 845         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
 846         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),
 847         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),
 848         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),
 849         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
 850         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),
 851         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),
 852         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),
 853         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
 854         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
 855         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
 856         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_SATURATION, 0x1f),
 857         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CTRL1, 0x94),
 858         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0, 0xfa),
 859 };
 860
 861 static const struct qmp_phy_init_tbl sm8650_ufsphy_pcs[] = {
 862         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x00),
 863         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
 864         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0xc1),
 865         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
 866         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
 867         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
 868         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
 869         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
 870         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 871 };
 872
 873 struct qmp_ufs_offsets {
 874         u16 serdes;
 875         u16 pcs;
 876         u16 tx;
 877         u16 rx;
 878         u16 tx2;
 879         u16 rx2;
 880 };
 881
 882 struct qmp_phy_cfg_tbls {
 883         /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
 884         const struct qmp_phy_init_tbl *serdes;
 885         int serdes_num;
 886         const struct qmp_phy_init_tbl *tx;
 887         int tx_num;
 888         const struct qmp_phy_init_tbl *rx;
 889         int rx_num;
 890         const struct qmp_phy_init_tbl *pcs;
 891         int pcs_num;
 892 };
 893
 894 /* struct qmp_phy_cfg - per-PHY initialization config */
 895 struct qmp_phy_cfg {
 896         int lanes;
 897
 898         const struct qmp_ufs_offsets *offsets;
 899
 900         /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
 901         const struct qmp_phy_cfg_tbls tbls;
 902         /* Additional sequence for HS Series B */
 903         const struct qmp_phy_cfg_tbls tbls_hs_b;
 904         /* Additional sequence for HS G4 */
 905         const struct qmp_phy_cfg_tbls tbls_hs_g4;
 906
 907         /* clock ids to be requested */
 908         const char * const *clk_list;
 909         int num_clks;
 910         /* regulators to be requested */
 911         const char * const *vreg_list;
 912         int num_vregs;
 913
 914         /* array of registers with different offsets */
 915         const unsigned int *regs;
 916
 917         /* true, if PCS block has no separate SW_RESET register */
 918         bool no_pcs_sw_reset;
 919 };
 920
 921 struct qmp_ufs {
 922         struct device *dev;
 923
 924         const struct qmp_phy_cfg *cfg;
 925
 926         void __iomem *serdes;
 927         void __iomem *pcs;
 928         void __iomem *pcs_misc;
 929         void __iomem *tx;
 930         void __iomem *rx;
 931         void __iomem *tx2;
 932         void __iomem *rx2;
 933
 934         struct clk_bulk_data *clks;
 935         struct regulator_bulk_data *vregs;
 936         struct reset_control *ufs_reset;
 937
 938         struct phy *phy;
 939         u32 mode;
 940         u32 submode;
 941 };
 942
 943 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
 944 {
 945         u32 reg;
 946
 947         reg = readl(base + offset);
 948         reg |= val;
 949         writel(reg, base + offset);
 950
 951         /* ensure that above write is through */
 952         readl(base + offset);
 953 }
 954
 955 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
 956 {
 957         u32 reg;
 958
 959         reg = readl(base + offset);
 960         reg &= ~val;
 961         writel(reg, base + offset);
 962
 963         /* ensure that above write is through */
 964         readl(base + offset);
 965 }
 966
 967 /* list of clocks required by phy */
 968 static const char * const msm8996_ufs_phy_clk_l[] = {
 969         "ref",
 970 };
 971
 972 /* the primary usb3 phy on sm8250 doesn't have a ref clock */
 973 static const char * const sm8450_ufs_phy_clk_l[] = {
 974         "qref", "ref", "ref_aux",
 975 };
 976
 977 static const char * const sdm845_ufs_phy_clk_l[] = {
 978         "ref", "ref_aux",
 979 };
 980
 981 /* list of regulators */
 982 static const char * const qmp_phy_vreg_l[] = {
 983         "vdda-phy", "vdda-pll",
 984 };
 985
 986 static const struct qmp_ufs_offsets qmp_ufs_offsets = {
 987         .serdes         = 0,
 988         .pcs            = 0xc00,
 989         .tx             = 0x400,
 990         .rx             = 0x600,
 991         .tx2            = 0x800,
 992         .rx2            = 0xa00,
 993 };
 994
 995 static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = {
 996         .serdes         = 0,
 997         .pcs            = 0x0400,
 998         .tx             = 0x1000,
 999         .rx             = 0x1200,
1000         .tx2            = 0x1800,
1001         .rx2            = 0x1a00,
1002 };
1003
1004 static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
1005         .lanes                  = 1,
1006
1007         .offsets                = &qmp_ufs_offsets,
1008
1009         .tbls = {
1010                 .serdes         = msm8996_ufsphy_serdes,
1011                 .serdes_num     = ARRAY_SIZE(msm8996_ufsphy_serdes),
1012                 .tx             = msm8996_ufsphy_tx,
1013                 .tx_num         = ARRAY_SIZE(msm8996_ufsphy_tx),
1014                 .rx             = msm8996_ufsphy_rx,
1015                 .rx_num         = ARRAY_SIZE(msm8996_ufsphy_rx),
1016         },
1017
1018         .clk_list               = msm8996_ufs_phy_clk_l,
1019         .num_clks               = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
1020
1021         .vreg_list              = qmp_phy_vreg_l,
1022         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1023
1024         .regs                   = ufsphy_v2_regs_layout,
1025
1026         .no_pcs_sw_reset        = true,
1027 };
1028
1029 static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
1030         .lanes                  = 2,
1031
1032         .offsets                = &qmp_ufs_offsets,
1033
1034         .tbls = {
1035                 .serdes         = sm8350_ufsphy_serdes,
1036                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_serdes),
1037                 .tx             = sm8350_ufsphy_tx,
1038                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_tx),
1039                 .rx             = sm8350_ufsphy_rx,
1040                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_rx),
1041                 .pcs            = sm8350_ufsphy_pcs,
1042                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_pcs),
1043         },
1044         .tbls_hs_b = {
1045                 .serdes         = sm8350_ufsphy_hs_b_serdes,
1046                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1047         },
1048         .tbls_hs_g4 = {
1049                 .tx             = sm8350_ufsphy_g4_tx,
1050                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1051                 .rx             = sm8350_ufsphy_g4_rx,
1052                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1053                 .pcs            = sm8350_ufsphy_g4_pcs,
1054                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1055         },
1056         .clk_list               = sm8450_ufs_phy_clk_l,
1057         .num_clks               = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
1058         .vreg_list              = qmp_phy_vreg_l,
1059         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1060         .regs                   = ufsphy_v5_regs_layout,
1061 };
1062
1063 static const struct qmp_phy_cfg sc7280_ufsphy_cfg = {
1064         .lanes                  = 2,
1065
1066         .offsets                = &qmp_ufs_offsets,
1067
1068         .tbls = {
1069                 .serdes         = sm8150_ufsphy_serdes,
1070                 .serdes_num     = ARRAY_SIZE(sm8150_ufsphy_serdes),
1071                 .tx             = sc7280_ufsphy_tx,
1072                 .tx_num         = ARRAY_SIZE(sc7280_ufsphy_tx),
1073                 .rx             = sc7280_ufsphy_rx,
1074                 .rx_num         = ARRAY_SIZE(sc7280_ufsphy_rx),
1075                 .pcs            = sc7280_ufsphy_pcs,
1076                 .pcs_num        = ARRAY_SIZE(sc7280_ufsphy_pcs),
1077         },
1078         .tbls_hs_b = {
1079                 .serdes         = sm8150_ufsphy_hs_b_serdes,
1080                 .serdes_num     = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
1081         },
1082         .tbls_hs_g4 = {
1083                 .tx             = sm8250_ufsphy_hs_g4_tx,
1084                 .tx_num         = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
1085                 .rx             = sc7280_ufsphy_hs_g4_rx,
1086                 .rx_num         = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx),
1087                 .pcs            = sm8150_ufsphy_hs_g4_pcs,
1088                 .pcs_num        = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
1089         },
1090         .clk_list               = sm8450_ufs_phy_clk_l,
1091         .num_clks               = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
1092         .vreg_list              = qmp_phy_vreg_l,
1093         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1094         .regs                   = ufsphy_v4_regs_layout,
1095 };
1096
1097 static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
1098         .lanes                  = 2,
1099
1100         .offsets                = &qmp_ufs_offsets,
1101
1102         .tbls = {
1103                 .serdes         = sm8350_ufsphy_serdes,
1104                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_serdes),
1105                 .tx             = sm8350_ufsphy_tx,
1106                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_tx),
1107                 .rx             = sm8350_ufsphy_rx,
1108                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_rx),
1109                 .pcs            = sm8350_ufsphy_pcs,
1110                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_pcs),
1111         },
1112         .tbls_hs_b = {
1113                 .serdes         = sm8350_ufsphy_hs_b_serdes,
1114                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1115         },
1116         .tbls_hs_g4 = {
1117                 .tx             = sm8350_ufsphy_g4_tx,
1118                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1119                 .rx             = sm8350_ufsphy_g4_rx,
1120                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1121                 .pcs            = sm8350_ufsphy_g4_pcs,
1122                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1123         },
1124         .clk_list               = sdm845_ufs_phy_clk_l,
1125         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1126         .vreg_list              = qmp_phy_vreg_l,
1127         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1128         .regs                   = ufsphy_v5_regs_layout,
1129 };
1130
1131 static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
1132         .lanes                  = 2,
1133
1134         .offsets                = &qmp_ufs_offsets,
1135
1136         .tbls = {
1137                 .serdes         = sdm845_ufsphy_serdes,
1138                 .serdes_num     = ARRAY_SIZE(sdm845_ufsphy_serdes),
1139                 .tx             = sdm845_ufsphy_tx,
1140                 .tx_num         = ARRAY_SIZE(sdm845_ufsphy_tx),
1141                 .rx             = sdm845_ufsphy_rx,
1142                 .rx_num         = ARRAY_SIZE(sdm845_ufsphy_rx),
1143                 .pcs            = sdm845_ufsphy_pcs,
1144                 .pcs_num        = ARRAY_SIZE(sdm845_ufsphy_pcs),
1145         },
1146         .tbls_hs_b = {
1147                 .serdes         = sdm845_ufsphy_hs_b_serdes,
1148                 .serdes_num     = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
1149         },
1150         .clk_list               = sdm845_ufs_phy_clk_l,
1151         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1152         .vreg_list              = qmp_phy_vreg_l,
1153         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1154         .regs                   = ufsphy_v3_regs_layout,
1155
1156         .no_pcs_sw_reset        = true,
1157 };
1158
1159 static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
1160         .lanes                  = 1,
1161
1162         .offsets                = &qmp_ufs_offsets,
1163
1164         .tbls = {
1165                 .serdes         = sm6115_ufsphy_serdes,
1166                 .serdes_num     = ARRAY_SIZE(sm6115_ufsphy_serdes),
1167                 .tx             = sm6115_ufsphy_tx,
1168                 .tx_num         = ARRAY_SIZE(sm6115_ufsphy_tx),
1169                 .rx             = sm6115_ufsphy_rx,
1170                 .rx_num         = ARRAY_SIZE(sm6115_ufsphy_rx),
1171                 .pcs            = sm6115_ufsphy_pcs,
1172                 .pcs_num        = ARRAY_SIZE(sm6115_ufsphy_pcs),
1173         },
1174         .tbls_hs_b = {
1175                 .serdes         = sm6115_ufsphy_hs_b_serdes,
1176                 .serdes_num     = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes),
1177         },
1178         .clk_list               = sdm845_ufs_phy_clk_l,
1179         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1180         .vreg_list              = qmp_phy_vreg_l,
1181         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1182         .regs                   = ufsphy_v2_regs_layout,
1183
1184         .no_pcs_sw_reset        = true,
1185 };
1186
1187 static const struct qmp_phy_cfg sm7150_ufsphy_cfg = {
1188         .lanes                  = 1,
1189
1190         .offsets                = &qmp_ufs_offsets,
1191
1192         .tbls = {
1193                 .serdes         = sdm845_ufsphy_serdes,
1194                 .serdes_num     = ARRAY_SIZE(sdm845_ufsphy_serdes),
1195                 .tx             = sdm845_ufsphy_tx,
1196                 .tx_num         = ARRAY_SIZE(sdm845_ufsphy_tx),
1197                 .rx             = sm7150_ufsphy_rx,
1198                 .rx_num         = ARRAY_SIZE(sm7150_ufsphy_rx),
1199                 .pcs            = sm7150_ufsphy_pcs,
1200                 .pcs_num        = ARRAY_SIZE(sm7150_ufsphy_pcs),
1201         },
1202         .tbls_hs_b = {
1203                 .serdes         = sdm845_ufsphy_hs_b_serdes,
1204                 .serdes_num     = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
1205         },
1206         .clk_list               = sdm845_ufs_phy_clk_l,
1207         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1208         .vreg_list              = qmp_phy_vreg_l,
1209         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1210         .regs                   = ufsphy_v3_regs_layout,
1211
1212         .no_pcs_sw_reset        = true,
1213 };
1214
1215 static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
1216         .lanes                  = 2,
1217
1218         .offsets                = &qmp_ufs_offsets,
1219
1220         .tbls = {
1221                 .serdes         = sm8150_ufsphy_serdes,
1222                 .serdes_num     = ARRAY_SIZE(sm8150_ufsphy_serdes),
1223                 .tx             = sm8150_ufsphy_tx,
1224                 .tx_num         = ARRAY_SIZE(sm8150_ufsphy_tx),
1225                 .rx             = sm8150_ufsphy_rx,
1226                 .rx_num         = ARRAY_SIZE(sm8150_ufsphy_rx),
1227                 .pcs            = sm8150_ufsphy_pcs,
1228                 .pcs_num        = ARRAY_SIZE(sm8150_ufsphy_pcs),
1229         },
1230         .tbls_hs_b = {
1231                 .serdes         = sm8150_ufsphy_hs_b_serdes,
1232                 .serdes_num     = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
1233         },
1234         .tbls_hs_g4 = {
1235                 .tx             = sm8150_ufsphy_hs_g4_tx,
1236                 .tx_num         = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
1237                 .rx             = sm8150_ufsphy_hs_g4_rx,
1238                 .rx_num         = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx),
1239                 .pcs            = sm8150_ufsphy_hs_g4_pcs,
1240                 .pcs_num        = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
1241         },
1242         .clk_list               = sdm845_ufs_phy_clk_l,
1243         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1244         .vreg_list              = qmp_phy_vreg_l,
1245         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1246         .regs                   = ufsphy_v4_regs_layout,
1247 };
1248
1249 static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
1250         .lanes                  = 2,
1251
1252         .offsets                = &qmp_ufs_offsets,
1253
1254         .tbls = {
1255                 .serdes         = sm8150_ufsphy_serdes,
1256                 .serdes_num     = ARRAY_SIZE(sm8150_ufsphy_serdes),
1257                 .tx             = sm8150_ufsphy_tx,
1258                 .tx_num         = ARRAY_SIZE(sm8150_ufsphy_tx),
1259                 .rx             = sm8150_ufsphy_rx,
1260                 .rx_num         = ARRAY_SIZE(sm8150_ufsphy_rx),
1261                 .pcs            = sm8150_ufsphy_pcs,
1262                 .pcs_num        = ARRAY_SIZE(sm8150_ufsphy_pcs),
1263         },
1264         .tbls_hs_b = {
1265                 .serdes         = sm8150_ufsphy_hs_b_serdes,
1266                 .serdes_num     = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
1267         },
1268         .tbls_hs_g4 = {
1269                 .tx             = sm8250_ufsphy_hs_g4_tx,
1270                 .tx_num         = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
1271                 .rx             = sm8250_ufsphy_hs_g4_rx,
1272                 .rx_num         = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx),
1273                 .pcs            = sm8150_ufsphy_hs_g4_pcs,
1274                 .pcs_num        = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
1275         },
1276         .clk_list               = sdm845_ufs_phy_clk_l,
1277         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1278         .vreg_list              = qmp_phy_vreg_l,
1279         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1280         .regs                   = ufsphy_v4_regs_layout,
1281 };
1282
1283 static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
1284         .lanes                  = 2,
1285
1286         .offsets                = &qmp_ufs_offsets,
1287
1288         .tbls = {
1289                 .serdes         = sm8350_ufsphy_serdes,
1290                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_serdes),
1291                 .tx             = sm8350_ufsphy_tx,
1292                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_tx),
1293                 .rx             = sm8350_ufsphy_rx,
1294                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_rx),
1295                 .pcs            = sm8350_ufsphy_pcs,
1296                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_pcs),
1297         },
1298         .tbls_hs_b = {
1299                 .serdes         = sm8350_ufsphy_hs_b_serdes,
1300                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1301         },
1302         .tbls_hs_g4 = {
1303                 .tx             = sm8350_ufsphy_g4_tx,
1304                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1305                 .rx             = sm8350_ufsphy_g4_rx,
1306                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1307                 .pcs            = sm8350_ufsphy_g4_pcs,
1308                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1309         },
1310         .clk_list               = sdm845_ufs_phy_clk_l,
1311         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1312         .vreg_list              = qmp_phy_vreg_l,
1313         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1314         .regs                   = ufsphy_v5_regs_layout,
1315 };
1316
1317 static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
1318         .lanes                  = 2,
1319
1320         .offsets                = &qmp_ufs_offsets,
1321
1322         .tbls = {
1323                 .serdes         = sm8350_ufsphy_serdes,
1324                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_serdes),
1325                 .tx             = sm8350_ufsphy_tx,
1326                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_tx),
1327                 .rx             = sm8350_ufsphy_rx,
1328                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_rx),
1329                 .pcs            = sm8350_ufsphy_pcs,
1330                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_pcs),
1331         },
1332         .tbls_hs_b = {
1333                 .serdes         = sm8350_ufsphy_hs_b_serdes,
1334                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1335         },
1336         .tbls_hs_g4 = {
1337                 .tx             = sm8350_ufsphy_g4_tx,
1338                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1339                 .rx             = sm8350_ufsphy_g4_rx,
1340                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1341                 .pcs            = sm8350_ufsphy_g4_pcs,
1342                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1343         },
1344         .clk_list               = sm8450_ufs_phy_clk_l,
1345         .num_clks               = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
1346         .vreg_list              = qmp_phy_vreg_l,
1347         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1348         .regs                   = ufsphy_v5_regs_layout,
1349 };
1350
1351 static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
1352         .lanes                  = 2,
1353
1354         .offsets                = &qmp_ufs_offsets_v6,
1355
1356         .tbls = {
1357                 .serdes         = sm8550_ufsphy_serdes,
1358                 .serdes_num     = ARRAY_SIZE(sm8550_ufsphy_serdes),
1359                 .tx             = sm8550_ufsphy_tx,
1360                 .tx_num         = ARRAY_SIZE(sm8550_ufsphy_tx),
1361                 .rx             = sm8550_ufsphy_rx,
1362                 .rx_num         = ARRAY_SIZE(sm8550_ufsphy_rx),
1363                 .pcs            = sm8550_ufsphy_pcs,
1364                 .pcs_num        = ARRAY_SIZE(sm8550_ufsphy_pcs),
1365         },
1366         .tbls_hs_b = {
1367                 .serdes         = sm8550_ufsphy_hs_b_serdes,
1368                 .serdes_num     = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
1369         },
1370         .clk_list               = sdm845_ufs_phy_clk_l,
1371         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1372         .vreg_list              = qmp_phy_vreg_l,
1373         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1374         .regs                   = ufsphy_v6_regs_layout,
1375 };
1376
1377 static const struct qmp_phy_cfg sm8650_ufsphy_cfg = {
1378         .lanes                  = 2,
1379
1380         .offsets                = &qmp_ufs_offsets_v6,
1381
1382         .tbls = {
1383                 .serdes         = sm8650_ufsphy_serdes,
1384                 .serdes_num     = ARRAY_SIZE(sm8650_ufsphy_serdes),
1385                 .tx             = sm8650_ufsphy_tx,
1386                 .tx_num         = ARRAY_SIZE(sm8650_ufsphy_tx),
1387                 .rx             = sm8650_ufsphy_rx,
1388                 .rx_num         = ARRAY_SIZE(sm8650_ufsphy_rx),
1389                 .pcs            = sm8650_ufsphy_pcs,
1390                 .pcs_num        = ARRAY_SIZE(sm8650_ufsphy_pcs),
1391         },
1392         .clk_list               = sdm845_ufs_phy_clk_l,
1393         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1394         .vreg_list              = qmp_phy_vreg_l,
1395         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1396         .regs                   = ufsphy_v6_regs_layout,
1397 };
1398
1399 static void qmp_ufs_configure_lane(void __iomem *base,
1400                                         const struct qmp_phy_init_tbl tbl[],
1401                                         int num,
1402                                         u8 lane_mask)
1403 {
1404         int i;
1405         const struct qmp_phy_init_tbl *t = tbl;
1406
1407         if (!t)
1408                 return;
1409
1410         for (i = 0; i < num; i++, t++) {
1411                 if (!(t->lane_mask & lane_mask))
1412                         continue;
1413
1414                 writel(t->val, base + t->offset);
1415         }
1416 }
1417
1418 static void qmp_ufs_configure(void __iomem *base,
1419                                    const struct qmp_phy_init_tbl tbl[],
1420                                    int num)
1421 {
1422         qmp_ufs_configure_lane(base, tbl, num, 0xff);
1423 }
1424
1425 static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1426 {
1427         void __iomem *serdes = qmp->serdes;
1428
1429         qmp_ufs_configure(serdes, tbls->serdes, tbls->serdes_num);
1430 }
1431
1432 static void qmp_ufs_lanes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1433 {
1434         const struct qmp_phy_cfg *cfg = qmp->cfg;
1435         void __iomem *tx = qmp->tx;
1436         void __iomem *rx = qmp->rx;
1437
1438         qmp_ufs_configure_lane(tx, tbls->tx, tbls->tx_num, 1);
1439         qmp_ufs_configure_lane(rx, tbls->rx, tbls->rx_num, 1);
1440
1441         if (cfg->lanes >= 2) {
1442                 qmp_ufs_configure_lane(qmp->tx2, tbls->tx, tbls->tx_num, 2);
1443                 qmp_ufs_configure_lane(qmp->rx2, tbls->rx, tbls->rx_num, 2);
1444         }
1445 }
1446
1447 static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1448 {
1449         void __iomem *pcs = qmp->pcs;
1450
1451         qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num);
1452 }
1453
1454 static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
1455 {
1456         qmp_ufs_serdes_init(qmp, &cfg->tbls);
1457         if (qmp->mode == PHY_MODE_UFS_HS_B)
1458                 qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
1459         qmp_ufs_lanes_init(qmp, &cfg->tbls);
1460         if (qmp->submode == UFS_HS_G4)
1461                 qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
1462         qmp_ufs_pcs_init(qmp, &cfg->tbls);
1463         if (qmp->submode == UFS_HS_G4)
1464                 qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
1465 }
1466
1467 static int qmp_ufs_com_init(struct qmp_ufs *qmp)
1468 {
1469         const struct qmp_phy_cfg *cfg = qmp->cfg;
1470         void __iomem *pcs = qmp->pcs;
1471         int ret;
1472
1473         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1474         if (ret) {
1475                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1476                 return ret;
1477         }
1478
1479         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1480         if (ret)
1481                 goto err_disable_regulators;
1482
1483         qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
1484
1485         return 0;
1486
1487 err_disable_regulators:
1488         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1489
1490         return ret;
1491 }
1492
1493 static int qmp_ufs_com_exit(struct qmp_ufs *qmp)
1494 {
1495         const struct qmp_phy_cfg *cfg = qmp->cfg;
1496
1497         reset_control_assert(qmp->ufs_reset);
1498
1499         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1500
1501         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1502
1503         return 0;
1504 }
1505
1506 static int qmp_ufs_init(struct phy *phy)
1507 {
1508         struct qmp_ufs *qmp = phy_get_drvdata(phy);
1509         const struct qmp_phy_cfg *cfg = qmp->cfg;
1510         int ret;
1511         dev_vdbg(qmp->dev, "Initializing QMP phy\n");
1512
1513         if (cfg->no_pcs_sw_reset) {
1514                 /*
1515                  * Get UFS reset, which is delayed until now to avoid a
1516                  * circular dependency where UFS needs its PHY, but the PHY
1517                  * needs this UFS reset.
1518                  */
1519                 if (!qmp->ufs_reset) {
1520                         qmp->ufs_reset =
1521                                 devm_reset_control_get_exclusive(qmp->dev,
1522                                                                  "ufsphy");
1523
1524                         if (IS_ERR(qmp->ufs_reset)) {
1525                                 ret = PTR_ERR(qmp->ufs_reset);
1526                                 dev_err(qmp->dev,
1527                                         "failed to get UFS reset: %d\n",
1528                                         ret);
1529
1530                                 qmp->ufs_reset = NULL;
1531                                 return ret;
1532                         }
1533                 }
1534
1535                 ret = reset_control_assert(qmp->ufs_reset);
1536                 if (ret)
1537                         return ret;
1538         }
1539
1540         ret = qmp_ufs_com_init(qmp);
1541         if (ret)
1542                 return ret;
1543
1544         return 0;
1545 }
1546
1547 static int qmp_ufs_power_on(struct phy *phy)
1548 {
1549         struct qmp_ufs *qmp = phy_get_drvdata(phy);
1550         const struct qmp_phy_cfg *cfg = qmp->cfg;
1551         void __iomem *pcs = qmp->pcs;
1552         void __iomem *status;
1553         unsigned int val;
1554         int ret;
1555
1556         qmp_ufs_init_registers(qmp, cfg);
1557
1558         ret = reset_control_deassert(qmp->ufs_reset);
1559         if (ret)
1560                 return ret;
1561
1562         /* Pull PHY out of reset state */
1563         if (!cfg->no_pcs_sw_reset)
1564                 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1565
1566         /* start SerDes */
1567         qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START);
1568
1569         status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
1570         ret = readl_poll_timeout(status, val, (val & PCS_READY), 200,
1571                                  PHY_INIT_COMPLETE_TIMEOUT);
1572         if (ret) {
1573                 dev_err(qmp->dev, "phy initialization timed-out\n");
1574                 return ret;
1575         }
1576
1577         return 0;
1578 }
1579
1580 static int qmp_ufs_power_off(struct phy *phy)
1581 {
1582         struct qmp_ufs *qmp = phy_get_drvdata(phy);
1583         const struct qmp_phy_cfg *cfg = qmp->cfg;
1584
1585         /* PHY reset */
1586         if (!cfg->no_pcs_sw_reset)
1587                 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1588
1589         /* stop SerDes */
1590         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START);
1591
1592         /* Put PHY into POWER DOWN state: active low */
1593         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
1594                         SW_PWRDN);
1595
1596         return 0;
1597 }
1598
1599 static int qmp_ufs_exit(struct phy *phy)
1600 {
1601         struct qmp_ufs *qmp = phy_get_drvdata(phy);
1602
1603         qmp_ufs_com_exit(qmp);
1604
1605         return 0;
1606 }
1607
1608 static int qmp_ufs_enable(struct phy *phy)
1609 {
1610         int ret;
1611
1612         ret = qmp_ufs_init(phy);
1613         if (ret)
1614                 return ret;
1615
1616         ret = qmp_ufs_power_on(phy);
1617         if (ret)
1618                 qmp_ufs_exit(phy);
1619
1620         return ret;
1621 }
1622
1623 static int qmp_ufs_disable(struct phy *phy)
1624 {
1625         int ret;
1626
1627         ret = qmp_ufs_power_off(phy);
1628         if (ret)
1629                 return ret;
1630         return qmp_ufs_exit(phy);
1631 }
1632
1633 static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
1634 {
1635         struct qmp_ufs *qmp = phy_get_drvdata(phy);
1636
1637         qmp->mode = mode;
1638         qmp->submode = submode;
1639
1640         return 0;
1641 }
1642
1643 static const struct phy_ops qcom_qmp_ufs_phy_ops = {
1644         .power_on       = qmp_ufs_enable,
1645         .power_off      = qmp_ufs_disable,
1646         .set_mode       = qmp_ufs_set_mode,
1647         .owner          = THIS_MODULE,
1648 };
1649
1650 static int qmp_ufs_vreg_init(struct qmp_ufs *qmp)
1651 {
1652         const struct qmp_phy_cfg *cfg = qmp->cfg;
1653         struct device *dev = qmp->dev;
1654         int num = cfg->num_vregs;
1655         int i;
1656
1657         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
1658         if (!qmp->vregs)
1659                 return -ENOMEM;
1660
1661         for (i = 0; i < num; i++)
1662                 qmp->vregs[i].supply = cfg->vreg_list[i];
1663
1664         return devm_regulator_bulk_get(dev, num, qmp->vregs);
1665 }
1666
1667 static int qmp_ufs_clk_init(struct qmp_ufs *qmp)
1668 {
1669         const struct qmp_phy_cfg *cfg = qmp->cfg;
1670         struct device *dev = qmp->dev;
1671         int num = cfg->num_clks;
1672         int i;
1673
1674         qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
1675         if (!qmp->clks)
1676                 return -ENOMEM;
1677
1678         for (i = 0; i < num; i++)
1679                 qmp->clks[i].id = cfg->clk_list[i];
1680
1681         return devm_clk_bulk_get(dev, num, qmp->clks);
1682 }
1683
1684 static void qmp_ufs_clk_release_provider(void *res)
1685 {
1686         of_clk_del_provider(res);
1687 }
1688
1689 #define UFS_SYMBOL_CLOCKS 3
1690
1691 static int qmp_ufs_register_clocks(struct qmp_ufs *qmp, struct device_node *np)
1692 {
1693         struct clk_hw_onecell_data *clk_data;
1694         struct clk_hw *hw;
1695         char name[64];
1696         int ret;
1697
1698         clk_data = devm_kzalloc(qmp->dev,
1699                                 struct_size(clk_data, hws, UFS_SYMBOL_CLOCKS),
1700                                 GFP_KERNEL);
1701         if (!clk_data)
1702                 return -ENOMEM;
1703
1704         clk_data->num = UFS_SYMBOL_CLOCKS;
1705
1706         snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev));
1707         hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
1708         if (IS_ERR(hw))
1709                 return PTR_ERR(hw);
1710
1711         clk_data->hws[0] = hw;
1712
1713         snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev));
1714         hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
1715         if (IS_ERR(hw))
1716                 return PTR_ERR(hw);
1717
1718         clk_data->hws[1] = hw;
1719
1720         snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev));
1721         hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
1722         if (IS_ERR(hw))
1723                 return PTR_ERR(hw);
1724
1725         clk_data->hws[2] = hw;
1726
1727         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
1728         if (ret)
1729                 return ret;
1730
1731         /*
1732          * Roll a devm action because the clock provider can be a child node.
1733          */
1734         return devm_add_action_or_reset(qmp->dev, qmp_ufs_clk_release_provider, np);
1735 }
1736
1737 static int qmp_ufs_parse_dt_legacy(struct qmp_ufs *qmp, struct device_node *np)
1738 {
1739         struct platform_device *pdev = to_platform_device(qmp->dev);
1740         const struct qmp_phy_cfg *cfg = qmp->cfg;
1741         struct device *dev = qmp->dev;
1742
1743         qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
1744         if (IS_ERR(qmp->serdes))
1745                 return PTR_ERR(qmp->serdes);
1746
1747         /*
1748          * Get memory resources for the PHY:
1749          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
1750          * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
1751          * For single lane PHYs: pcs_misc (optional) -> 3.
1752          */
1753         qmp->tx = devm_of_iomap(dev, np, 0, NULL);
1754         if (IS_ERR(qmp->tx))
1755                 return PTR_ERR(qmp->tx);
1756
1757         qmp->rx = devm_of_iomap(dev, np, 1, NULL);
1758         if (IS_ERR(qmp->rx))
1759                 return PTR_ERR(qmp->rx);
1760
1761         qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
1762         if (IS_ERR(qmp->pcs))
1763                 return PTR_ERR(qmp->pcs);
1764
1765         if (cfg->lanes >= 2) {
1766                 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
1767                 if (IS_ERR(qmp->tx2))
1768                         return PTR_ERR(qmp->tx2);
1769
1770                 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
1771                 if (IS_ERR(qmp->rx2))
1772                         return PTR_ERR(qmp->rx2);
1773
1774                 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
1775         } else {
1776                 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
1777         }
1778
1779         if (IS_ERR(qmp->pcs_misc))
1780                 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
1781
1782         return 0;
1783 }
1784
1785 static int qmp_ufs_parse_dt(struct qmp_ufs *qmp)
1786 {
1787         struct platform_device *pdev = to_platform_device(qmp->dev);
1788         const struct qmp_phy_cfg *cfg = qmp->cfg;
1789         const struct qmp_ufs_offsets *offs = cfg->offsets;
1790         void __iomem *base;
1791
1792         if (!offs)
1793                 return -EINVAL;
1794
1795         base = devm_platform_ioremap_resource(pdev, 0);
1796         if (IS_ERR(base))
1797                 return PTR_ERR(base);
1798
1799         qmp->serdes = base + offs->serdes;
1800         qmp->pcs = base + offs->pcs;
1801         qmp->tx = base + offs->tx;
1802         qmp->rx = base + offs->rx;
1803
1804         if (cfg->lanes >= 2) {
1805                 qmp->tx2 = base + offs->tx2;
1806                 qmp->rx2 = base + offs->rx2;
1807         }
1808
1809         return 0;
1810 }
1811
1812 static int qmp_ufs_probe(struct platform_device *pdev)
1813 {
1814         struct device *dev = &pdev->dev;
1815         struct phy_provider *phy_provider;
1816         struct device_node *np;
1817         struct qmp_ufs *qmp;
1818         int ret;
1819
1820         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
1821         if (!qmp)
1822                 return -ENOMEM;
1823
1824         qmp->dev = dev;
1825
1826         qmp->cfg = of_device_get_match_data(dev);
1827         if (!qmp->cfg)
1828                 return -EINVAL;
1829
1830         ret = qmp_ufs_clk_init(qmp);
1831         if (ret)
1832                 return ret;
1833
1834         ret = qmp_ufs_vreg_init(qmp);
1835         if (ret)
1836                 return ret;
1837
1838         /* Check for legacy binding with child node. */
1839         np = of_get_next_available_child(dev->of_node, NULL);
1840         if (np) {
1841                 ret = qmp_ufs_parse_dt_legacy(qmp, np);
1842         } else {
1843                 np = of_node_get(dev->of_node);
1844                 ret = qmp_ufs_parse_dt(qmp);
1845         }
1846         if (ret)
1847                 goto err_node_put;
1848
1849         ret = qmp_ufs_register_clocks(qmp, np);
1850         if (ret)
1851                 goto err_node_put;
1852
1853         qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops);
1854         if (IS_ERR(qmp->phy)) {
1855                 ret = PTR_ERR(qmp->phy);
1856                 dev_err(dev, "failed to create PHY: %d\n", ret);
1857                 goto err_node_put;
1858         }
1859
1860         phy_set_drvdata(qmp->phy, qmp);
1861
1862         of_node_put(np);
1863
1864         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1865
1866         return PTR_ERR_OR_ZERO(phy_provider);
1867
1868 err_node_put:
1869         of_node_put(np);
1870         return ret;
1871 }
1872
1873 static const struct of_device_id qmp_ufs_of_match_table[] = {
1874         {
1875                 .compatible = "qcom,msm8996-qmp-ufs-phy",
1876                 .data = &msm8996_ufsphy_cfg,
1877         }, {
1878                 .compatible = "qcom,msm8998-qmp-ufs-phy",
1879                 .data = &sdm845_ufsphy_cfg,
1880         }, {
1881                 .compatible = "qcom,sa8775p-qmp-ufs-phy",
1882                 .data = &sa8775p_ufsphy_cfg,
1883         }, {
1884                 .compatible = "qcom,sc7280-qmp-ufs-phy",
1885                 .data = &sc7280_ufsphy_cfg,
1886         }, {
1887                 .compatible = "qcom,sc8180x-qmp-ufs-phy",
1888                 .data = &sm8150_ufsphy_cfg,
1889         }, {
1890                 .compatible = "qcom,sc8280xp-qmp-ufs-phy",
1891                 .data = &sc8280xp_ufsphy_cfg,
1892         }, {
1893                 .compatible = "qcom,sdm845-qmp-ufs-phy",
1894                 .data = &sdm845_ufsphy_cfg,
1895         }, {
1896                 .compatible = "qcom,sm6115-qmp-ufs-phy",
1897                 .data = &sm6115_ufsphy_cfg,
1898         }, {
1899                 .compatible = "qcom,sm6125-qmp-ufs-phy",
1900                 .data = &sm6115_ufsphy_cfg,
1901         }, {
1902                 .compatible = "qcom,sm6350-qmp-ufs-phy",
1903                 .data = &sdm845_ufsphy_cfg,
1904         }, {
1905                 .compatible = "qcom,sm7150-qmp-ufs-phy",
1906                 .data = &sm7150_ufsphy_cfg,
1907         }, {
1908                 .compatible = "qcom,sm8150-qmp-ufs-phy",
1909                 .data = &sm8150_ufsphy_cfg,
1910         }, {
1911                 .compatible = "qcom,sm8250-qmp-ufs-phy",
1912                 .data = &sm8250_ufsphy_cfg,
1913         }, {
1914                 .compatible = "qcom,sm8350-qmp-ufs-phy",
1915                 .data = &sm8350_ufsphy_cfg,
1916         }, {
1917                 .compatible = "qcom,sm8450-qmp-ufs-phy",
1918                 .data = &sm8450_ufsphy_cfg,
1919         }, {
1920                 .compatible = "qcom,sm8550-qmp-ufs-phy",
1921                 .data = &sm8550_ufsphy_cfg,
1922         }, {
1923                 .compatible = "qcom,sm8650-qmp-ufs-phy",
1924                 .data = &sm8650_ufsphy_cfg,
1925         },
1926         { },
1927 };
1928 MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table);
1929
1930 static struct platform_driver qmp_ufs_driver = {
1931         .probe          = qmp_ufs_probe,
1932         .driver = {
1933                 .name   = "qcom-qmp-ufs-phy",
1934                 .of_match_table = qmp_ufs_of_match_table,
1935         },
1936 };
1937
1938 module_platform_driver(qmp_ufs_driver);
1939
1940 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
1941 MODULE_DESCRIPTION("Qualcomm QMP UFS PHY driver");
1942 MODULE_LICENSE("GPL v2");