drivers/pinctrl/intel/pinctrl-baytrail.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Pinctrl GPIO driver for Intel Baytrail
   4  *
   5  * Copyright (c) 2012-2013, Intel Corporation
   6  * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
   7  */
   8
   9 #include <linux/acpi.h>
  10 #include <linux/array_size.h>
  11 #include <linux/bitops.h>
  12 #include <linux/cleanup.h>
  13 #include <linux/gpio/driver.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/module.h>
  18 #include <linux/types.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm.h>
  21 #include <linux/property.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/string_helpers.h>
  24
  25 #include <linux/pinctrl/pinctrl.h>
  26 #include <linux/pinctrl/pinmux.h>
  27 #include <linux/pinctrl/pinconf.h>
  28 #include <linux/pinctrl/pinconf-generic.h>
  29
  30 #include "pinctrl-intel.h"
  31
  32 /* memory mapped register offsets */
  33 #define BYT_CONF0_REG           0x000
  34 #define BYT_CONF1_REG           0x004
  35 #define BYT_VAL_REG             0x008
  36 #define BYT_DFT_REG             0x00c
  37 #define BYT_INT_STAT_REG        0x800
  38 #define BYT_DIRECT_IRQ_REG      0x980
  39 #define BYT_DEBOUNCE_REG        0x9d0
  40
  41 /* BYT_CONF0_REG register bits */
  42 #define BYT_IODEN               BIT(31)
  43 #define BYT_DIRECT_IRQ_EN       BIT(27)
  44 #define BYT_TRIG_MASK           GENMASK(26, 24)
  45 #define BYT_TRIG_NEG            BIT(26)
  46 #define BYT_TRIG_POS            BIT(25)
  47 #define BYT_TRIG_LVL            BIT(24)
  48 #define BYT_DEBOUNCE_EN         BIT(20)
  49 #define BYT_GLITCH_FILTER_EN    BIT(19)
  50 #define BYT_GLITCH_F_SLOW_CLK   BIT(17)
  51 #define BYT_GLITCH_F_FAST_CLK   BIT(16)
  52 #define BYT_PULL_STR_SHIFT      9
  53 #define BYT_PULL_STR_MASK       GENMASK(10, 9)
  54 #define BYT_PULL_STR_2K         (0 << BYT_PULL_STR_SHIFT)
  55 #define BYT_PULL_STR_10K        (1 << BYT_PULL_STR_SHIFT)
  56 #define BYT_PULL_STR_20K        (2 << BYT_PULL_STR_SHIFT)
  57 #define BYT_PULL_STR_40K        (3 << BYT_PULL_STR_SHIFT)
  58 #define BYT_PULL_ASSIGN_MASK    GENMASK(8, 7)
  59 #define BYT_PULL_ASSIGN_DOWN    BIT(8)
  60 #define BYT_PULL_ASSIGN_UP      BIT(7)
  61 #define BYT_PIN_MUX             GENMASK(2, 0)
  62
  63 /* BYT_VAL_REG register bits */
  64 #define BYT_DIR_MASK            GENMASK(2, 1)
  65 #define BYT_INPUT_EN            BIT(2)  /* 0: input enabled (active low)*/
  66 #define BYT_OUTPUT_EN           BIT(1)  /* 0: output enabled (active low)*/
  67 #define BYT_LEVEL               BIT(0)
  68
  69 #define BYT_CONF0_RESTORE_MASK  (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX)
  70 #define BYT_VAL_RESTORE_MASK    (BYT_DIR_MASK | BYT_LEVEL)
  71
  72 /* BYT_DEBOUNCE_REG bits */
  73 #define BYT_DEBOUNCE_PULSE_MASK         GENMASK(2, 0)
  74 #define BYT_DEBOUNCE_PULSE_375US        1
  75 #define BYT_DEBOUNCE_PULSE_750US        2
  76 #define BYT_DEBOUNCE_PULSE_1500US       3
  77 #define BYT_DEBOUNCE_PULSE_3MS          4
  78 #define BYT_DEBOUNCE_PULSE_6MS          5
  79 #define BYT_DEBOUNCE_PULSE_12MS         6
  80 #define BYT_DEBOUNCE_PULSE_24MS         7
  81
  82 #define BYT_NGPIO_SCORE         102
  83 #define BYT_NGPIO_NCORE         28
  84 #define BYT_NGPIO_SUS           44
  85
  86 #define BYT_SCORE_ACPI_UID      "1"
  87 #define BYT_NCORE_ACPI_UID      "2"
  88 #define BYT_SUS_ACPI_UID        "3"
  89
  90 /*
  91  * This is the function value most pins have for GPIO muxing. If the value
  92  * differs from the default one, it must be explicitly mentioned. Otherwise, the
  93  * pin control implementation will set the muxing value to default GPIO if it
  94  * does not find a match for the requested function.
  95  */
  96 #define BYT_DEFAULT_GPIO_MUX    0
  97 #define BYT_ALTER_GPIO_MUX      1
  98
  99 struct intel_pad_context {
 100         u32 conf0;
 101         u32 val;
 102 };
 103
 104 #define COMMUNITY(p, n, map)            \
 105         {                               \
 106                 .pin_base       = (p),  \
 107                 .npins          = (n),  \
 108                 .pad_map        = (map),\
 109         }
 110
 111 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
 112 static const struct pinctrl_pin_desc byt_score_pins[] = {
 113         PINCTRL_PIN(0, "SATA_GP0"),
 114         PINCTRL_PIN(1, "SATA_GP1"),
 115         PINCTRL_PIN(2, "SATA_LED#"),
 116         PINCTRL_PIN(3, "PCIE_CLKREQ0"),
 117         PINCTRL_PIN(4, "PCIE_CLKREQ1"),
 118         PINCTRL_PIN(5, "PCIE_CLKREQ2"),
 119         PINCTRL_PIN(6, "PCIE_CLKREQ3"),
 120         PINCTRL_PIN(7, "SD3_WP"),
 121         PINCTRL_PIN(8, "HDA_RST"),
 122         PINCTRL_PIN(9, "HDA_SYNC"),
 123         PINCTRL_PIN(10, "HDA_CLK"),
 124         PINCTRL_PIN(11, "HDA_SDO"),
 125         PINCTRL_PIN(12, "HDA_SDI0"),
 126         PINCTRL_PIN(13, "HDA_SDI1"),
 127         PINCTRL_PIN(14, "GPIO_S0_SC14"),
 128         PINCTRL_PIN(15, "GPIO_S0_SC15"),
 129         PINCTRL_PIN(16, "MMC1_CLK"),
 130         PINCTRL_PIN(17, "MMC1_D0"),
 131         PINCTRL_PIN(18, "MMC1_D1"),
 132         PINCTRL_PIN(19, "MMC1_D2"),
 133         PINCTRL_PIN(20, "MMC1_D3"),
 134         PINCTRL_PIN(21, "MMC1_D4"),
 135         PINCTRL_PIN(22, "MMC1_D5"),
 136         PINCTRL_PIN(23, "MMC1_D6"),
 137         PINCTRL_PIN(24, "MMC1_D7"),
 138         PINCTRL_PIN(25, "MMC1_CMD"),
 139         PINCTRL_PIN(26, "MMC1_RST"),
 140         PINCTRL_PIN(27, "SD2_CLK"),
 141         PINCTRL_PIN(28, "SD2_D0"),
 142         PINCTRL_PIN(29, "SD2_D1"),
 143         PINCTRL_PIN(30, "SD2_D2"),
 144         PINCTRL_PIN(31, "SD2_D3_CD"),
 145         PINCTRL_PIN(32, "SD2_CMD"),
 146         PINCTRL_PIN(33, "SD3_CLK"),
 147         PINCTRL_PIN(34, "SD3_D0"),
 148         PINCTRL_PIN(35, "SD3_D1"),
 149         PINCTRL_PIN(36, "SD3_D2"),
 150         PINCTRL_PIN(37, "SD3_D3"),
 151         PINCTRL_PIN(38, "SD3_CD"),
 152         PINCTRL_PIN(39, "SD3_CMD"),
 153         PINCTRL_PIN(40, "SD3_1P8EN"),
 154         PINCTRL_PIN(41, "SD3_PWREN#"),
 155         PINCTRL_PIN(42, "ILB_LPC_AD0"),
 156         PINCTRL_PIN(43, "ILB_LPC_AD1"),
 157         PINCTRL_PIN(44, "ILB_LPC_AD2"),
 158         PINCTRL_PIN(45, "ILB_LPC_AD3"),
 159         PINCTRL_PIN(46, "ILB_LPC_FRAME"),
 160         PINCTRL_PIN(47, "ILB_LPC_CLK0"),
 161         PINCTRL_PIN(48, "ILB_LPC_CLK1"),
 162         PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
 163         PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
 164         PINCTRL_PIN(51, "PCU_SMB_DATA"),
 165         PINCTRL_PIN(52, "PCU_SMB_CLK"),
 166         PINCTRL_PIN(53, "PCU_SMB_ALERT"),
 167         PINCTRL_PIN(54, "ILB_8254_SPKR"),
 168         PINCTRL_PIN(55, "GPIO_S0_SC55"),
 169         PINCTRL_PIN(56, "GPIO_S0_SC56"),
 170         PINCTRL_PIN(57, "GPIO_S0_SC57"),
 171         PINCTRL_PIN(58, "GPIO_S0_SC58"),
 172         PINCTRL_PIN(59, "GPIO_S0_SC59"),
 173         PINCTRL_PIN(60, "GPIO_S0_SC60"),
 174         PINCTRL_PIN(61, "GPIO_S0_SC61"),
 175         PINCTRL_PIN(62, "LPE_I2S2_CLK"),
 176         PINCTRL_PIN(63, "LPE_I2S2_FRM"),
 177         PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
 178         PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
 179         PINCTRL_PIN(66, "SIO_SPI_CS"),
 180         PINCTRL_PIN(67, "SIO_SPI_MISO"),
 181         PINCTRL_PIN(68, "SIO_SPI_MOSI"),
 182         PINCTRL_PIN(69, "SIO_SPI_CLK"),
 183         PINCTRL_PIN(70, "SIO_UART1_RXD"),
 184         PINCTRL_PIN(71, "SIO_UART1_TXD"),
 185         PINCTRL_PIN(72, "SIO_UART1_RTS"),
 186         PINCTRL_PIN(73, "SIO_UART1_CTS"),
 187         PINCTRL_PIN(74, "SIO_UART2_RXD"),
 188         PINCTRL_PIN(75, "SIO_UART2_TXD"),
 189         PINCTRL_PIN(76, "SIO_UART2_RTS"),
 190         PINCTRL_PIN(77, "SIO_UART2_CTS"),
 191         PINCTRL_PIN(78, "SIO_I2C0_DATA"),
 192         PINCTRL_PIN(79, "SIO_I2C0_CLK"),
 193         PINCTRL_PIN(80, "SIO_I2C1_DATA"),
 194         PINCTRL_PIN(81, "SIO_I2C1_CLK"),
 195         PINCTRL_PIN(82, "SIO_I2C2_DATA"),
 196         PINCTRL_PIN(83, "SIO_I2C2_CLK"),
 197         PINCTRL_PIN(84, "SIO_I2C3_DATA"),
 198         PINCTRL_PIN(85, "SIO_I2C3_CLK"),
 199         PINCTRL_PIN(86, "SIO_I2C4_DATA"),
 200         PINCTRL_PIN(87, "SIO_I2C4_CLK"),
 201         PINCTRL_PIN(88, "SIO_I2C5_DATA"),
 202         PINCTRL_PIN(89, "SIO_I2C5_CLK"),
 203         PINCTRL_PIN(90, "SIO_I2C6_DATA"),
 204         PINCTRL_PIN(91, "SIO_I2C6_CLK"),
 205         PINCTRL_PIN(92, "GPIO_S0_SC92"),
 206         PINCTRL_PIN(93, "GPIO_S0_SC93"),
 207         PINCTRL_PIN(94, "SIO_PWM0"),
 208         PINCTRL_PIN(95, "SIO_PWM1"),
 209         PINCTRL_PIN(96, "PMC_PLT_CLK0"),
 210         PINCTRL_PIN(97, "PMC_PLT_CLK1"),
 211         PINCTRL_PIN(98, "PMC_PLT_CLK2"),
 212         PINCTRL_PIN(99, "PMC_PLT_CLK3"),
 213         PINCTRL_PIN(100, "PMC_PLT_CLK4"),
 214         PINCTRL_PIN(101, "PMC_PLT_CLK5"),
 215 };
 216
 217 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
 218         85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
 219         36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
 220         54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
 221         52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
 222         95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
 223         86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
 224         80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
 225         2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
 226         31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
 227         24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
 228         97, 100,
 229 };
 230
 231 /* SCORE groups */
 232 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
 233 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
 234 static const unsigned int byt_score_uart3_pins[] = { 57, 61 };
 235
 236 static const unsigned int byt_score_pwm0_pins[] = { 94 };
 237 static const unsigned int byt_score_pwm1_pins[] = { 95 };
 238
 239 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
 240
 241 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
 242 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
 243 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
 244 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
 245 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
 246 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
 247 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
 248
 249 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
 250 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
 251 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
 252
 253 static const unsigned int byt_score_sdcard_pins[] = {
 254         7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
 255 };
 256 static const unsigned int byt_score_sdcard_mux_values[] = {
 257         2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
 258 };
 259
 260 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
 261
 262 static const unsigned int byt_score_emmc_pins[] = {
 263         16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
 264 };
 265
 266 static const unsigned int byt_score_ilb_lpc_pins[] = {
 267         42, 43, 44, 45, 46, 47, 48, 49, 50,
 268 };
 269
 270 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
 271
 272 static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
 273 static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
 274 static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
 275 static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
 276 static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
 277 static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
 278
 279 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
 280
 281 static const struct intel_pingroup byt_score_groups[] = {
 282         PIN_GROUP_GPIO("uart1_grp", byt_score_uart1_pins, 1),
 283         PIN_GROUP_GPIO("uart2_grp", byt_score_uart2_pins, 1),
 284         PIN_GROUP_GPIO("uart3_grp", byt_score_uart3_pins, 1),
 285         PIN_GROUP_GPIO("pwm0_grp", byt_score_pwm0_pins, 1),
 286         PIN_GROUP_GPIO("pwm1_grp", byt_score_pwm1_pins, 1),
 287         PIN_GROUP_GPIO("ssp2_grp", byt_score_ssp2_pins, 1),
 288         PIN_GROUP_GPIO("sio_spi_grp", byt_score_sio_spi_pins, 1),
 289         PIN_GROUP_GPIO("i2c5_grp", byt_score_i2c5_pins, 1),
 290         PIN_GROUP_GPIO("i2c6_grp", byt_score_i2c6_pins, 1),
 291         PIN_GROUP_GPIO("i2c4_grp", byt_score_i2c4_pins, 1),
 292         PIN_GROUP_GPIO("i2c3_grp", byt_score_i2c3_pins, 1),
 293         PIN_GROUP_GPIO("i2c2_grp", byt_score_i2c2_pins, 1),
 294         PIN_GROUP_GPIO("i2c1_grp", byt_score_i2c1_pins, 1),
 295         PIN_GROUP_GPIO("i2c0_grp", byt_score_i2c0_pins, 1),
 296         PIN_GROUP_GPIO("ssp0_grp", byt_score_ssp0_pins, 1),
 297         PIN_GROUP_GPIO("ssp1_grp", byt_score_ssp1_pins, 1),
 298         PIN_GROUP_GPIO("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values),
 299         PIN_GROUP_GPIO("sdio_grp", byt_score_sdio_pins, 1),
 300         PIN_GROUP_GPIO("emmc_grp", byt_score_emmc_pins, 1),
 301         PIN_GROUP_GPIO("lpc_grp", byt_score_ilb_lpc_pins, 1),
 302         PIN_GROUP_GPIO("sata_grp", byt_score_sata_pins, 1),
 303         PIN_GROUP_GPIO("plt_clk0_grp", byt_score_plt_clk0_pins, 1),
 304         PIN_GROUP_GPIO("plt_clk1_grp", byt_score_plt_clk1_pins, 1),
 305         PIN_GROUP_GPIO("plt_clk2_grp", byt_score_plt_clk2_pins, 1),
 306         PIN_GROUP_GPIO("plt_clk3_grp", byt_score_plt_clk3_pins, 1),
 307         PIN_GROUP_GPIO("plt_clk4_grp", byt_score_plt_clk4_pins, 1),
 308         PIN_GROUP_GPIO("plt_clk5_grp", byt_score_plt_clk5_pins, 1),
 309         PIN_GROUP_GPIO("smbus_grp", byt_score_smbus_pins, 1),
 310 };
 311
 312 static const char * const byt_score_uart_groups[] = {
 313         "uart1_grp", "uart2_grp", "uart3_grp",
 314 };
 315 static const char * const byt_score_pwm_groups[] = {
 316         "pwm0_grp", "pwm1_grp",
 317 };
 318 static const char * const byt_score_ssp_groups[] = {
 319         "ssp0_grp", "ssp1_grp", "ssp2_grp",
 320 };
 321 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
 322 static const char * const byt_score_i2c_groups[] = {
 323         "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
 324         "i2c6_grp",
 325 };
 326 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
 327 static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
 328 static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
 329 static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
 330 static const char * const byt_score_sata_groups[] = { "sata_grp" };
 331 static const char * const byt_score_plt_clk_groups[] = {
 332         "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
 333         "plt_clk4_grp", "plt_clk5_grp",
 334 };
 335 static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
 336 static const char * const byt_score_gpio_groups[] = {
 337         "uart1_grp_gpio", "uart2_grp_gpio", "uart3_grp_gpio", "pwm0_grp_gpio",
 338         "pwm1_grp_gpio", "ssp0_grp_gpio", "ssp1_grp_gpio", "ssp2_grp_gpio",
 339         "sio_spi_grp_gpio", "i2c0_grp_gpio", "i2c1_grp_gpio", "i2c2_grp_gpio",
 340         "i2c3_grp_gpio", "i2c4_grp_gpio", "i2c5_grp_gpio", "i2c6_grp_gpio",
 341         "sdcard_grp_gpio", "sdio_grp_gpio", "emmc_grp_gpio", "lpc_grp_gpio",
 342         "sata_grp_gpio", "plt_clk0_grp_gpio", "plt_clk1_grp_gpio",
 343         "plt_clk2_grp_gpio", "plt_clk3_grp_gpio", "plt_clk4_grp_gpio",
 344         "plt_clk5_grp_gpio", "smbus_grp_gpio",
 345 };
 346
 347 static const struct intel_function byt_score_functions[] = {
 348         FUNCTION("uart", byt_score_uart_groups),
 349         FUNCTION("pwm", byt_score_pwm_groups),
 350         FUNCTION("ssp", byt_score_ssp_groups),
 351         FUNCTION("spi", byt_score_spi_groups),
 352         FUNCTION("i2c", byt_score_i2c_groups),
 353         FUNCTION("sdcard", byt_score_sdcard_groups),
 354         FUNCTION("sdio", byt_score_sdio_groups),
 355         FUNCTION("emmc", byt_score_emmc_groups),
 356         FUNCTION("lpc", byt_score_lpc_groups),
 357         FUNCTION("sata", byt_score_sata_groups),
 358         FUNCTION("plt_clk", byt_score_plt_clk_groups),
 359         FUNCTION("smbus", byt_score_smbus_groups),
 360         FUNCTION("gpio", byt_score_gpio_groups),
 361 };
 362
 363 static const struct intel_community byt_score_communities[] = {
 364         COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
 365 };
 366
 367 static const struct intel_pinctrl_soc_data byt_score_soc_data = {
 368         .uid            = BYT_SCORE_ACPI_UID,
 369         .pins           = byt_score_pins,
 370         .npins          = ARRAY_SIZE(byt_score_pins),
 371         .groups         = byt_score_groups,
 372         .ngroups        = ARRAY_SIZE(byt_score_groups),
 373         .functions      = byt_score_functions,
 374         .nfunctions     = ARRAY_SIZE(byt_score_functions),
 375         .communities    = byt_score_communities,
 376         .ncommunities   = ARRAY_SIZE(byt_score_communities),
 377 };
 378
 379 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>]  */
 380 static const struct pinctrl_pin_desc byt_sus_pins[] = {
 381         PINCTRL_PIN(0, "GPIO_S50"),
 382         PINCTRL_PIN(1, "GPIO_S51"),
 383         PINCTRL_PIN(2, "GPIO_S52"),
 384         PINCTRL_PIN(3, "GPIO_S53"),
 385         PINCTRL_PIN(4, "GPIO_S54"),
 386         PINCTRL_PIN(5, "GPIO_S55"),
 387         PINCTRL_PIN(6, "GPIO_S56"),
 388         PINCTRL_PIN(7, "GPIO_S57"),
 389         PINCTRL_PIN(8, "GPIO_S58"),
 390         PINCTRL_PIN(9, "GPIO_S59"),
 391         PINCTRL_PIN(10, "GPIO_S510"),
 392         PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
 393         PINCTRL_PIN(12, "PMC_SUSCLK0"),
 394         PINCTRL_PIN(13, "GPIO_S513"),
 395         PINCTRL_PIN(14, "USB_ULPI_RST"),
 396         PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
 397         PINCTRL_PIN(16, "PMC_PWRBTN"),
 398         PINCTRL_PIN(17, "GPIO_S517"),
 399         PINCTRL_PIN(18, "PMC_SUS_STAT"),
 400         PINCTRL_PIN(19, "USB_OC0"),
 401         PINCTRL_PIN(20, "USB_OC1"),
 402         PINCTRL_PIN(21, "PCU_SPI_CS1"),
 403         PINCTRL_PIN(22, "GPIO_S522"),
 404         PINCTRL_PIN(23, "GPIO_S523"),
 405         PINCTRL_PIN(24, "GPIO_S524"),
 406         PINCTRL_PIN(25, "GPIO_S525"),
 407         PINCTRL_PIN(26, "GPIO_S526"),
 408         PINCTRL_PIN(27, "GPIO_S527"),
 409         PINCTRL_PIN(28, "GPIO_S528"),
 410         PINCTRL_PIN(29, "GPIO_S529"),
 411         PINCTRL_PIN(30, "GPIO_S530"),
 412         PINCTRL_PIN(31, "USB_ULPI_CLK"),
 413         PINCTRL_PIN(32, "USB_ULPI_DATA0"),
 414         PINCTRL_PIN(33, "USB_ULPI_DATA1"),
 415         PINCTRL_PIN(34, "USB_ULPI_DATA2"),
 416         PINCTRL_PIN(35, "USB_ULPI_DATA3"),
 417         PINCTRL_PIN(36, "USB_ULPI_DATA4"),
 418         PINCTRL_PIN(37, "USB_ULPI_DATA5"),
 419         PINCTRL_PIN(38, "USB_ULPI_DATA6"),
 420         PINCTRL_PIN(39, "USB_ULPI_DATA7"),
 421         PINCTRL_PIN(40, "USB_ULPI_DIR"),
 422         PINCTRL_PIN(41, "USB_ULPI_NXT"),
 423         PINCTRL_PIN(42, "USB_ULPI_STP"),
 424         PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
 425 };
 426
 427 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
 428         29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
 429         18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
 430         0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
 431         26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
 432         52, 53, 59, 40,
 433 };
 434
 435 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
 436 static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 };
 437 static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 };
 438
 439 static const unsigned int byt_sus_usb_ulpi_pins[] = {
 440         14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
 441 };
 442 static const unsigned int byt_sus_usb_ulpi_mode_values[] = {
 443         2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
 444 };
 445 static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = {
 446         1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 447 };
 448
 449 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
 450 static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 };
 451 static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 };
 452
 453 static const unsigned int byt_sus_pmu_clk1_pins[] = { 5 };
 454 static const unsigned int byt_sus_pmu_clk2_pins[] = { 6 };
 455
 456 static const struct intel_pingroup byt_sus_groups[] = {
 457         PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values),
 458         PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values),
 459         PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values),
 460         PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values),
 461         PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values),
 462         PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values),
 463         PIN_GROUP_GPIO("pmu_clk1_grp", byt_sus_pmu_clk1_pins, 1),
 464         PIN_GROUP_GPIO("pmu_clk2_grp", byt_sus_pmu_clk2_pins, 1),
 465 };
 466
 467 static const char * const byt_sus_usb_groups[] = {
 468         "usb_oc_grp", "usb_ulpi_grp",
 469 };
 470 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
 471 static const char * const byt_sus_pmu_clk_groups[] = {
 472         "pmu_clk1_grp", "pmu_clk2_grp",
 473 };
 474 static const char * const byt_sus_gpio_groups[] = {
 475         "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio",
 476         "pmu_clk1_grp_gpio", "pmu_clk2_grp_gpio",
 477 };
 478
 479 static const struct intel_function byt_sus_functions[] = {
 480         FUNCTION("usb", byt_sus_usb_groups),
 481         FUNCTION("spi", byt_sus_spi_groups),
 482         FUNCTION("gpio", byt_sus_gpio_groups),
 483         FUNCTION("pmu_clk", byt_sus_pmu_clk_groups),
 484 };
 485
 486 static const struct intel_community byt_sus_communities[] = {
 487         COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
 488 };
 489
 490 static const struct intel_pinctrl_soc_data byt_sus_soc_data = {
 491         .uid            = BYT_SUS_ACPI_UID,
 492         .pins           = byt_sus_pins,
 493         .npins          = ARRAY_SIZE(byt_sus_pins),
 494         .groups         = byt_sus_groups,
 495         .ngroups        = ARRAY_SIZE(byt_sus_groups),
 496         .functions      = byt_sus_functions,
 497         .nfunctions     = ARRAY_SIZE(byt_sus_functions),
 498         .communities    = byt_sus_communities,
 499         .ncommunities   = ARRAY_SIZE(byt_sus_communities),
 500 };
 501
 502 static const struct pinctrl_pin_desc byt_ncore_pins[] = {
 503         PINCTRL_PIN(0, "HV_DDI0_HPD"),
 504         PINCTRL_PIN(1, "HV_DDI0_DDC_SDA"),
 505         PINCTRL_PIN(2, "HV_DDI0_DDC_SCL"),
 506         PINCTRL_PIN(3, "PANEL0_VDDEN"),
 507         PINCTRL_PIN(4, "PANEL0_BKLTEN"),
 508         PINCTRL_PIN(5, "PANEL0_BKLTCTL"),
 509         PINCTRL_PIN(6, "HV_DDI1_HPD"),
 510         PINCTRL_PIN(7, "HV_DDI1_DDC_SDA"),
 511         PINCTRL_PIN(8, "HV_DDI1_DDC_SCL"),
 512         PINCTRL_PIN(9, "PANEL1_VDDEN"),
 513         PINCTRL_PIN(10, "PANEL1_BKLTEN"),
 514         PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
 515         PINCTRL_PIN(12, "GP_INTD_DSI_TE1"),
 516         PINCTRL_PIN(13, "HV_DDI2_DDC_SDA"),
 517         PINCTRL_PIN(14, "HV_DDI2_DDC_SCL"),
 518         PINCTRL_PIN(15, "GP_CAMERASB00"),
 519         PINCTRL_PIN(16, "GP_CAMERASB01"),
 520         PINCTRL_PIN(17, "GP_CAMERASB02"),
 521         PINCTRL_PIN(18, "GP_CAMERASB03"),
 522         PINCTRL_PIN(19, "GP_CAMERASB04"),
 523         PINCTRL_PIN(20, "GP_CAMERASB05"),
 524         PINCTRL_PIN(21, "GP_CAMERASB06"),
 525         PINCTRL_PIN(22, "GP_CAMERASB07"),
 526         PINCTRL_PIN(23, "GP_CAMERASB08"),
 527         PINCTRL_PIN(24, "GP_CAMERASB09"),
 528         PINCTRL_PIN(25, "GP_CAMERASB10"),
 529         PINCTRL_PIN(26, "GP_CAMERASB11"),
 530         PINCTRL_PIN(27, "GP_INTD_DSI_TE2"),
 531 };
 532
 533 static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
 534         19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
 535         14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
 536         3, 6, 10, 13, 2, 5, 9, 7,
 537 };
 538
 539 static const struct intel_community byt_ncore_communities[] = {
 540         COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
 541 };
 542
 543 static const struct intel_pinctrl_soc_data byt_ncore_soc_data = {
 544         .uid            = BYT_NCORE_ACPI_UID,
 545         .pins           = byt_ncore_pins,
 546         .npins          = ARRAY_SIZE(byt_ncore_pins),
 547         .communities    = byt_ncore_communities,
 548         .ncommunities   = ARRAY_SIZE(byt_ncore_communities),
 549 };
 550
 551 static const struct intel_pinctrl_soc_data *byt_soc_data[] = {
 552         &byt_score_soc_data,
 553         &byt_sus_soc_data,
 554         &byt_ncore_soc_data,
 555         NULL
 556 };
 557
 558 static DEFINE_RAW_SPINLOCK(byt_lock);
 559
 560 static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset,
 561                                   int reg)
 562 {
 563         struct intel_community *comm = intel_get_community(vg, offset);
 564         u32 reg_offset;
 565
 566         if (!comm)
 567                 return NULL;
 568
 569         offset -= comm->pin_base;
 570         switch (reg) {
 571         case BYT_INT_STAT_REG:
 572                 reg_offset = (offset / 32) * 4;
 573                 break;
 574         case BYT_DEBOUNCE_REG:
 575                 reg_offset = 0;
 576                 break;
 577         default:
 578                 reg_offset = comm->pad_map[offset] * 16;
 579                 break;
 580         }
 581
 582         return comm->pad_regs + reg_offset + reg;
 583 }
 584
 585 static const struct pinctrl_ops byt_pinctrl_ops = {
 586         .get_groups_count       = intel_get_groups_count,
 587         .get_group_name         = intel_get_group_name,
 588         .get_group_pins         = intel_get_group_pins,
 589 };
 590
 591 static void byt_set_group_simple_mux(struct intel_pinctrl *vg,
 592                                      const struct intel_pingroup group,
 593                                      unsigned int func)
 594 {
 595         int i;
 596
 597         guard(raw_spinlock_irqsave)(&byt_lock);
 598
 599         for (i = 0; i < group.grp.npins; i++) {
 600                 void __iomem *padcfg0;
 601                 u32 value;
 602
 603                 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
 604                 if (!padcfg0) {
 605                         dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n",
 606                                  group.grp.name, i);
 607                         continue;
 608                 }
 609
 610                 value = readl(padcfg0);
 611                 value &= ~BYT_PIN_MUX;
 612                 value |= func;
 613                 writel(value, padcfg0);
 614         }
 615 }
 616
 617 static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,
 618                                     const struct intel_pingroup group,
 619                                     const unsigned int *func)
 620 {
 621         int i;
 622
 623         guard(raw_spinlock_irqsave)(&byt_lock);
 624
 625         for (i = 0; i < group.grp.npins; i++) {
 626                 void __iomem *padcfg0;
 627                 u32 value;
 628
 629                 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
 630                 if (!padcfg0) {
 631                         dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n",
 632                                  group.grp.name, i);
 633                         continue;
 634                 }
 635
 636                 value = readl(padcfg0);
 637                 value &= ~BYT_PIN_MUX;
 638                 value |= func[i];
 639                 writel(value, padcfg0);
 640         }
 641 }
 642
 643 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
 644                        unsigned int group_selector)
 645 {
 646         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
 647         const struct intel_function func = vg->soc->functions[func_selector];
 648         const struct intel_pingroup group = vg->soc->groups[group_selector];
 649
 650         if (group.modes)
 651                 byt_set_group_mixed_mux(vg, group, group.modes);
 652         else if (!strcmp(func.func.name, "gpio"))
 653                 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
 654         else
 655                 byt_set_group_simple_mux(vg, group, group.mode);
 656
 657         return 0;
 658 }
 659
 660 static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset)
 661 {
 662         /* SCORE pin 92-93 */
 663         if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) &&
 664             offset >= 92 && offset <= 93)
 665                 return BYT_ALTER_GPIO_MUX;
 666
 667         /* SUS pin 11-21 */
 668         if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) &&
 669             offset >= 11 && offset <= 21)
 670                 return BYT_ALTER_GPIO_MUX;
 671
 672         return BYT_DEFAULT_GPIO_MUX;
 673 }
 674
 675 static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset)
 676 {
 677         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 678         u32 value;
 679
 680         guard(raw_spinlock_irqsave)(&byt_lock);
 681
 682         value = readl(reg);
 683
 684         /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
 685         if (!(value & BYT_DIRECT_IRQ_EN))
 686                 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
 687
 688         writel(value, reg);
 689 }
 690
 691 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
 692                                    struct pinctrl_gpio_range *range,
 693                                    unsigned int offset)
 694 {
 695         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 696         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 697         u32 value, gpio_mux;
 698
 699         guard(raw_spinlock_irqsave)(&byt_lock);
 700
 701         /*
 702          * In most cases, func pin mux 000 means GPIO function.
 703          * But, some pins may have func pin mux 001 represents
 704          * GPIO function.
 705          *
 706          * Because there are devices out there where some pins were not
 707          * configured correctly we allow changing the mux value from
 708          * request (but print out warning about that).
 709          */
 710         value = readl(reg) & BYT_PIN_MUX;
 711         gpio_mux = byt_get_gpio_mux(vg, offset);
 712         if (gpio_mux == value)
 713                 return 0;
 714
 715         value = readl(reg) & ~BYT_PIN_MUX;
 716         value |= gpio_mux;
 717         writel(value, reg);
 718
 719         dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset);
 720
 721         return 0;
 722 }
 723
 724 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
 725                                   struct pinctrl_gpio_range *range,
 726                                   unsigned int offset)
 727 {
 728         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 729
 730         byt_gpio_clear_triggering(vg, offset);
 731 }
 732
 733 static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg,
 734                                       unsigned int offset)
 735 {
 736         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 737
 738         /*
 739          * Before making any direction modifications, do a check if gpio is set
 740          * for direct IRQ. On Bay Trail, setting GPIO to output does not make
 741          * sense, so let's at least inform the caller before they shoot
 742          * themselves in the foot.
 743          */
 744         if (readl(conf_reg) & BYT_DIRECT_IRQ_EN)
 745                 dev_info_once(vg->dev,
 746                               "Potential Error: Pin %i: forcibly set GPIO with DIRECT_IRQ_EN to output\n",
 747                               offset);
 748 }
 749
 750 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
 751                                   struct pinctrl_gpio_range *range,
 752                                   unsigned int offset,
 753                                   bool input)
 754 {
 755         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 756         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
 757         u32 value;
 758
 759         guard(raw_spinlock_irqsave)(&byt_lock);
 760
 761         value = readl(val_reg);
 762         value &= ~BYT_DIR_MASK;
 763         if (input)
 764                 value |= BYT_OUTPUT_EN;
 765         else
 766                 byt_gpio_direct_irq_check(vg, offset);
 767
 768         writel(value, val_reg);
 769
 770         return 0;
 771 }
 772
 773 static const struct pinmux_ops byt_pinmux_ops = {
 774         .get_functions_count    = intel_get_functions_count,
 775         .get_function_name      = intel_get_function_name,
 776         .get_function_groups    = intel_get_function_groups,
 777         .set_mux                = byt_set_mux,
 778         .gpio_request_enable    = byt_gpio_request_enable,
 779         .gpio_disable_free      = byt_gpio_disable_free,
 780         .gpio_set_direction     = byt_gpio_set_direction,
 781 };
 782
 783 static void byt_get_pull_strength(u32 reg, u16 *strength)
 784 {
 785         switch (reg & BYT_PULL_STR_MASK) {
 786         case BYT_PULL_STR_2K:
 787                 *strength = 2000;
 788                 break;
 789         case BYT_PULL_STR_10K:
 790                 *strength = 10000;
 791                 break;
 792         case BYT_PULL_STR_20K:
 793                 *strength = 20000;
 794                 break;
 795         case BYT_PULL_STR_40K:
 796                 *strength = 40000;
 797                 break;
 798         }
 799 }
 800
 801 static int byt_set_pull_strength(u32 *reg, u16 strength)
 802 {
 803         *reg &= ~BYT_PULL_STR_MASK;
 804
 805         switch (strength) {
 806         case 1: /* Set default strength value in case none is given */
 807         case 2000:
 808                 *reg |= BYT_PULL_STR_2K;
 809                 break;
 810         case 10000:
 811                 *reg |= BYT_PULL_STR_10K;
 812                 break;
 813         case 20000:
 814                 *reg |= BYT_PULL_STR_20K;
 815                 break;
 816         case 40000:
 817                 *reg |= BYT_PULL_STR_40K;
 818                 break;
 819         default:
 820                 return -EINVAL;
 821         }
 822
 823         return 0;
 824 }
 825
 826 static void byt_gpio_force_input_mode(struct intel_pinctrl *vg, unsigned int offset)
 827 {
 828         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
 829         u32 value;
 830
 831         value = readl(reg);
 832         if (!(value & BYT_INPUT_EN))
 833                 return;
 834
 835         /*
 836          * Pull assignment is only applicable in input mode. If
 837          * chip is not in input mode, set it and warn about it.
 838          */
 839         value &= ~BYT_INPUT_EN;
 840         writel(value, reg);
 841         dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
 842 }
 843
 844 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
 845                               unsigned long *config)
 846 {
 847         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 848         enum pin_config_param param = pinconf_to_config_param(*config);
 849         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 850         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
 851         void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
 852         u32 conf, pull, val, debounce;
 853         u16 arg = 0;
 854
 855         scoped_guard(raw_spinlock_irqsave, &byt_lock) {
 856                 conf = readl(conf_reg);
 857                 val = readl(val_reg);
 858         }
 859
 860         pull = conf & BYT_PULL_ASSIGN_MASK;
 861
 862         switch (param) {
 863         case PIN_CONFIG_BIAS_DISABLE:
 864                 if (pull)
 865                         return -EINVAL;
 866                 break;
 867         case PIN_CONFIG_BIAS_PULL_DOWN:
 868                 /* Pull assignment is only applicable in input mode */
 869                 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
 870                         return -EINVAL;
 871
 872                 byt_get_pull_strength(conf, &arg);
 873
 874                 break;
 875         case PIN_CONFIG_BIAS_PULL_UP:
 876                 /* Pull assignment is only applicable in input mode */
 877                 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
 878                         return -EINVAL;
 879
 880                 byt_get_pull_strength(conf, &arg);
 881
 882                 break;
 883         case PIN_CONFIG_INPUT_DEBOUNCE:
 884                 if (!(conf & BYT_DEBOUNCE_EN))
 885                         return -EINVAL;
 886
 887                 scoped_guard(raw_spinlock_irqsave, &byt_lock)
 888                         debounce = readl(db_reg);
 889
 890                 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
 891                 case BYT_DEBOUNCE_PULSE_375US:
 892                         arg = 375;
 893                         break;
 894                 case BYT_DEBOUNCE_PULSE_750US:
 895                         arg = 750;
 896                         break;
 897                 case BYT_DEBOUNCE_PULSE_1500US:
 898                         arg = 1500;
 899                         break;
 900                 case BYT_DEBOUNCE_PULSE_3MS:
 901                         arg = 3000;
 902                         break;
 903                 case BYT_DEBOUNCE_PULSE_6MS:
 904                         arg = 6000;
 905                         break;
 906                 case BYT_DEBOUNCE_PULSE_12MS:
 907                         arg = 12000;
 908                         break;
 909                 case BYT_DEBOUNCE_PULSE_24MS:
 910                         arg = 24000;
 911                         break;
 912                 default:
 913                         return -EINVAL;
 914                 }
 915
 916                 break;
 917         default:
 918                 return -ENOTSUPP;
 919         }
 920
 921         *config = pinconf_to_config_packed(param, arg);
 922
 923         return 0;
 924 }
 925
 926 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
 927                               unsigned int offset,
 928                               unsigned long *configs,
 929                               unsigned int num_configs)
 930 {
 931         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 932         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 933         void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
 934         u32 conf, db_pulse, debounce;
 935         enum pin_config_param param;
 936         int i, ret;
 937         u32 arg;
 938
 939         guard(raw_spinlock_irqsave)(&byt_lock);
 940
 941         conf = readl(conf_reg);
 942
 943         for (i = 0; i < num_configs; i++) {
 944                 param = pinconf_to_config_param(configs[i]);
 945                 arg = pinconf_to_config_argument(configs[i]);
 946
 947                 switch (param) {
 948                 case PIN_CONFIG_BIAS_DISABLE:
 949                         conf &= ~BYT_PULL_ASSIGN_MASK;
 950                         break;
 951                 case PIN_CONFIG_BIAS_PULL_DOWN:
 952                         byt_gpio_force_input_mode(vg, offset);
 953
 954                         conf &= ~BYT_PULL_ASSIGN_MASK;
 955                         conf |= BYT_PULL_ASSIGN_DOWN;
 956                         ret = byt_set_pull_strength(&conf, arg);
 957                         if (ret)
 958                                 return ret;
 959
 960                         break;
 961                 case PIN_CONFIG_BIAS_PULL_UP:
 962                         byt_gpio_force_input_mode(vg, offset);
 963
 964                         conf &= ~BYT_PULL_ASSIGN_MASK;
 965                         conf |= BYT_PULL_ASSIGN_UP;
 966                         ret = byt_set_pull_strength(&conf, arg);
 967                         if (ret)
 968                                 return ret;
 969
 970                         break;
 971                 case PIN_CONFIG_INPUT_DEBOUNCE:
 972                         switch (arg) {
 973                         case 0:
 974                                 db_pulse = 0;
 975                                 break;
 976                         case 375:
 977                                 db_pulse = BYT_DEBOUNCE_PULSE_375US;
 978                                 break;
 979                         case 750:
 980                                 db_pulse = BYT_DEBOUNCE_PULSE_750US;
 981                                 break;
 982                         case 1500:
 983                                 db_pulse = BYT_DEBOUNCE_PULSE_1500US;
 984                                 break;
 985                         case 3000:
 986                                 db_pulse = BYT_DEBOUNCE_PULSE_3MS;
 987                                 break;
 988                         case 6000:
 989                                 db_pulse = BYT_DEBOUNCE_PULSE_6MS;
 990                                 break;
 991                         case 12000:
 992                                 db_pulse = BYT_DEBOUNCE_PULSE_12MS;
 993                                 break;
 994                         case 24000:
 995                                 db_pulse = BYT_DEBOUNCE_PULSE_24MS;
 996                                 break;
 997                         default:
 998                                 return -EINVAL;
 999                         }
1000
1001                         if (db_pulse) {
1002                                 debounce = readl(db_reg);
1003                                 debounce = (debounce & ~BYT_DEBOUNCE_PULSE_MASK) | db_pulse;
1004                                 writel(debounce, db_reg);
1005
1006                                 conf |= BYT_DEBOUNCE_EN;
1007                         } else {
1008                                 conf &= ~BYT_DEBOUNCE_EN;
1009                         }
1010
1011                         break;
1012                 default:
1013                         return -ENOTSUPP;
1014                 }
1015         }
1016
1017         writel(conf, conf_reg);
1018
1019         return 0;
1020 }
1021
1022 static const struct pinconf_ops byt_pinconf_ops = {
1023         .is_generic     = true,
1024         .pin_config_get = byt_pin_config_get,
1025         .pin_config_set = byt_pin_config_set,
1026 };
1027
1028 static const struct pinctrl_desc byt_pinctrl_desc = {
1029         .pctlops        = &byt_pinctrl_ops,
1030         .pmxops         = &byt_pinmux_ops,
1031         .confops        = &byt_pinconf_ops,
1032         .owner          = THIS_MODULE,
1033 };
1034
1035 static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
1036 {
1037         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1038         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1039         u32 val;
1040
1041         scoped_guard(raw_spinlock_irqsave, &byt_lock)
1042                 val = readl(reg);
1043
1044         return !!(val & BYT_LEVEL);
1045 }
1046
1047 static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1048 {
1049         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1050         void __iomem *reg;
1051         u32 old_val;
1052
1053         reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1054         if (!reg)
1055                 return;
1056
1057         guard(raw_spinlock_irqsave)(&byt_lock);
1058
1059         old_val = readl(reg);
1060         if (value)
1061                 writel(old_val | BYT_LEVEL, reg);
1062         else
1063                 writel(old_val & ~BYT_LEVEL, reg);
1064 }
1065
1066 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1067 {
1068         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1069         void __iomem *reg;
1070         u32 value;
1071
1072         reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1073         if (!reg)
1074                 return -EINVAL;
1075
1076         scoped_guard(raw_spinlock_irqsave, &byt_lock)
1077                 value = readl(reg);
1078
1079         if (!(value & BYT_OUTPUT_EN))
1080                 return GPIO_LINE_DIRECTION_OUT;
1081         if (!(value & BYT_INPUT_EN))
1082                 return GPIO_LINE_DIRECTION_IN;
1083
1084         return -EINVAL;
1085 }
1086
1087 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1088 {
1089         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1090         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1091         u32 reg;
1092
1093         guard(raw_spinlock_irqsave)(&byt_lock);
1094
1095         reg = readl(val_reg);
1096         reg &= ~BYT_DIR_MASK;
1097         reg |= BYT_OUTPUT_EN;
1098         writel(reg, val_reg);
1099
1100         return 0;
1101 }
1102
1103 /*
1104  * Note despite the temptation this MUST NOT be converted into a call to
1105  * pinctrl_gpio_direction_output() + byt_gpio_set() that does not work this
1106  * MUST be done as a single BYT_VAL_REG register write.
1107  * See the commit message of the commit adding this comment for details.
1108  */
1109 static int byt_gpio_direction_output(struct gpio_chip *chip,
1110                                      unsigned int offset, int value)
1111 {
1112         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1113         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1114         u32 reg;
1115
1116         guard(raw_spinlock_irqsave)(&byt_lock);
1117
1118         byt_gpio_direct_irq_check(vg, offset);
1119
1120         reg = readl(val_reg);
1121         reg &= ~BYT_DIR_MASK;
1122         if (value)
1123                 reg |= BYT_LEVEL;
1124         else
1125                 reg &= ~BYT_LEVEL;
1126
1127         writel(reg, val_reg);
1128
1129         return 0;
1130 }
1131
1132 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1133 {
1134         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1135         int i;
1136         u32 conf0, val;
1137
1138         for (i = 0; i < vg->soc->npins; i++) {
1139                 const struct intel_community *comm;
1140                 void __iomem *conf_reg, *val_reg;
1141                 const char *pull_str = NULL;
1142                 const char *pull = NULL;
1143                 unsigned int pin;
1144
1145                 pin = vg->soc->pins[i].number;
1146
1147                 conf_reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1148                 if (!conf_reg) {
1149                         seq_printf(s, "Pin %i: can't retrieve CONF0\n", pin);
1150                         continue;
1151                 }
1152
1153                 val_reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1154                 if (!val_reg) {
1155                         seq_printf(s, "Pin %i: can't retrieve VAL\n", pin);
1156                         continue;
1157                 }
1158
1159                 scoped_guard(raw_spinlock_irqsave, &byt_lock) {
1160                         conf0 = readl(conf_reg);
1161                         val = readl(val_reg);
1162                 }
1163
1164                 comm = intel_get_community(vg, pin);
1165                 if (!comm) {
1166                         seq_printf(s, "Pin %i: can't retrieve community\n", pin);
1167                         continue;
1168                 }
1169
1170                 char *label __free(kfree) = gpiochip_dup_line_label(chip, i);
1171                 if (IS_ERR(label))
1172                         continue;
1173
1174                 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
1175                 case BYT_PULL_ASSIGN_UP:
1176                         pull = "up";
1177                         break;
1178                 case BYT_PULL_ASSIGN_DOWN:
1179                         pull = "down";
1180                         break;
1181                 }
1182
1183                 switch (conf0 & BYT_PULL_STR_MASK) {
1184                 case BYT_PULL_STR_2K:
1185                         pull_str = "2k";
1186                         break;
1187                 case BYT_PULL_STR_10K:
1188                         pull_str = "10k";
1189                         break;
1190                 case BYT_PULL_STR_20K:
1191                         pull_str = "20k";
1192                         break;
1193                 case BYT_PULL_STR_40K:
1194                         pull_str = "40k";
1195                         break;
1196                 }
1197
1198                 seq_printf(s,
1199                            " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
1200                            pin,
1201                            label ?: "Unrequested",
1202                            val & BYT_INPUT_EN ? "  " : "in",
1203                            val & BYT_OUTPUT_EN ? "   " : "out",
1204                            str_hi_lo(val & BYT_LEVEL),
1205                            comm->pad_map[i], comm->pad_map[i] * 16,
1206                            conf0 & 0x7,
1207                            conf0 & BYT_TRIG_NEG ? " fall" : "     ",
1208                            conf0 & BYT_TRIG_POS ? " rise" : "     ",
1209                            conf0 & BYT_TRIG_LVL ? " level" : "      ");
1210
1211                 if (pull && pull_str)
1212                         seq_printf(s, " %-4s %-3s", pull, pull_str);
1213                 else
1214                         seq_puts(s, "          ");
1215
1216                 if (conf0 & BYT_IODEN)
1217                         seq_puts(s, " open-drain");
1218
1219                 seq_puts(s, "\n");
1220         }
1221 }
1222
1223 static const struct gpio_chip byt_gpio_chip = {
1224         .owner                  = THIS_MODULE,
1225         .request                = gpiochip_generic_request,
1226         .free                   = gpiochip_generic_free,
1227         .get_direction          = byt_gpio_get_direction,
1228         .direction_input        = byt_gpio_direction_input,
1229         .direction_output       = byt_gpio_direction_output,
1230         .get                    = byt_gpio_get,
1231         .set                    = byt_gpio_set,
1232         .set_config             = gpiochip_generic_config,
1233         .dbg_show               = byt_gpio_dbg_show,
1234 };
1235
1236 static void byt_irq_ack(struct irq_data *d)
1237 {
1238         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1239         struct intel_pinctrl *vg = gpiochip_get_data(gc);
1240         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1241         void __iomem *reg;
1242
1243         reg = byt_gpio_reg(vg, hwirq, BYT_INT_STAT_REG);
1244         if (!reg)
1245                 return;
1246
1247         guard(raw_spinlock)(&byt_lock);
1248
1249         writel(BIT(hwirq % 32), reg);
1250 }
1251
1252 static void byt_irq_mask(struct irq_data *d)
1253 {
1254         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1255         struct intel_pinctrl *vg = gpiochip_get_data(gc);
1256         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1257
1258         byt_gpio_clear_triggering(vg, hwirq);
1259         gpiochip_disable_irq(gc, hwirq);
1260 }
1261
1262 static void byt_irq_unmask(struct irq_data *d)
1263 {
1264         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1265         struct intel_pinctrl *vg = gpiochip_get_data(gc);
1266         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1267         void __iomem *reg;
1268         u32 value;
1269
1270         gpiochip_enable_irq(gc, hwirq);
1271
1272         reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG);
1273         if (!reg)
1274                 return;
1275
1276         guard(raw_spinlock_irqsave)(&byt_lock);
1277
1278         value = readl(reg);
1279
1280         switch (irqd_get_trigger_type(d)) {
1281         case IRQ_TYPE_LEVEL_HIGH:
1282                 value |= BYT_TRIG_LVL;
1283                 fallthrough;
1284         case IRQ_TYPE_EDGE_RISING:
1285                 value |= BYT_TRIG_POS;
1286                 break;
1287         case IRQ_TYPE_LEVEL_LOW:
1288                 value |= BYT_TRIG_LVL;
1289                 fallthrough;
1290         case IRQ_TYPE_EDGE_FALLING:
1291                 value |= BYT_TRIG_NEG;
1292                 break;
1293         case IRQ_TYPE_EDGE_BOTH:
1294                 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1295                 break;
1296         }
1297
1298         writel(value, reg);
1299 }
1300
1301 static int byt_irq_type(struct irq_data *d, unsigned int type)
1302 {
1303         struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1304         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1305         void __iomem *reg;
1306         u32 value;
1307
1308         reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG);
1309         if (!reg)
1310                 return -EINVAL;
1311
1312         guard(raw_spinlock_irqsave)(&byt_lock);
1313
1314         value = readl(reg);
1315
1316         WARN(value & BYT_DIRECT_IRQ_EN,
1317              "Bad pad config for IO mode, force DIRECT_IRQ_EN bit clearing");
1318
1319         /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
1320          * are used to indicate high and low level triggering
1321          */
1322         value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1323                    BYT_TRIG_LVL);
1324         /* Enable glitch filtering */
1325         value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK |
1326                  BYT_GLITCH_F_FAST_CLK;
1327
1328         writel(value, reg);
1329
1330         if (type & IRQ_TYPE_EDGE_BOTH)
1331                 irq_set_handler_locked(d, handle_edge_irq);
1332         else if (type & IRQ_TYPE_LEVEL_MASK)
1333                 irq_set_handler_locked(d, handle_level_irq);
1334
1335         return 0;
1336 }
1337
1338 static const struct irq_chip byt_gpio_irq_chip = {
1339         .name           = "BYT-GPIO",
1340         .irq_ack        = byt_irq_ack,
1341         .irq_mask       = byt_irq_mask,
1342         .irq_unmask     = byt_irq_unmask,
1343         .irq_set_type   = byt_irq_type,
1344         .flags          = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE,
1345         GPIOCHIP_IRQ_RESOURCE_HELPERS,
1346 };
1347
1348 static void byt_gpio_irq_handler(struct irq_desc *desc)
1349 {
1350         struct irq_data *data = irq_desc_get_irq_data(desc);
1351         struct intel_pinctrl *vg = gpiochip_get_data(irq_desc_get_handler_data(desc));
1352         struct irq_chip *chip = irq_data_get_irq_chip(data);
1353         u32 base, pin;
1354         void __iomem *reg;
1355         unsigned long pending;
1356
1357         /* check from GPIO controller which pin triggered the interrupt */
1358         for (base = 0; base < vg->chip.ngpio; base += 32) {
1359                 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1360
1361                 if (!reg) {
1362                         dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base);
1363                         continue;
1364                 }
1365
1366                 scoped_guard(raw_spinlock, &byt_lock)
1367                         pending = readl(reg);
1368                 for_each_set_bit(pin, &pending, 32)
1369                         generic_handle_domain_irq(vg->chip.irq.domain, base + pin);
1370         }
1371         chip->irq_eoi(data);
1372 }
1373
1374 static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0)
1375 {
1376         int direct_irq, ioapic_direct_irq_base;
1377         u8 *match, direct_irq_mux[16];
1378         u32 trig;
1379
1380         memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG,
1381                       sizeof(direct_irq_mux));
1382         match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux));
1383         if (!match) {
1384                 dev_warn(vg->dev, FW_BUG "Pin %i: DIRECT_IRQ_EN set but no IRQ assigned, clearing\n", pin);
1385                 return false;
1386         }
1387
1388         direct_irq = match - direct_irq_mux;
1389         /* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */
1390         ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67;
1391         dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin,
1392                 direct_irq, direct_irq + ioapic_direct_irq_base);
1393
1394         /*
1395          * Testing has shown that the way direct IRQs work is that the combination of the
1396          * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ
1397          * trigger block, which normally sets the status flag in the IRQ status reg at
1398          * 0x800, to one of the IO-APIC pins according to the mux registers.
1399          *
1400          * This means that:
1401          * 1. The TRIG_MASK bits must be set to configure the GPIO's IRQ trigger block
1402          * 2. The TRIG_LVL bit *must* be set, so that the GPIO's input value is directly
1403          *    passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set,
1404          *    selecting edge mode operation then on the first edge the IO-APIC pin goes
1405          *    high, but since no write-to-clear write will be done to the IRQ status reg
1406          *    at 0x800, the detected edge condition will never get cleared.
1407          */
1408         trig = conf0 & BYT_TRIG_MASK;
1409         if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) &&
1410             trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) {
1411                 dev_warn(vg->dev,
1412                          FW_BUG "Pin %i: DIRECT_IRQ_EN set without trigger (CONF0: %#08x), clearing\n",
1413                          pin, conf0);
1414                 return false;
1415         }
1416
1417         return true;
1418 }
1419
1420 static void byt_init_irq_valid_mask(struct gpio_chip *chip,
1421                                     unsigned long *valid_mask,
1422                                     unsigned int ngpios)
1423 {
1424         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1425         void __iomem *reg;
1426         u32 value;
1427         int i;
1428
1429         /*
1430          * Clear interrupt triggers for all pins that are GPIOs and
1431          * do not use direct IRQ mode. This will prevent spurious
1432          * interrupts from misconfigured pins.
1433          */
1434         for (i = 0; i < vg->soc->npins; i++) {
1435                 unsigned int pin = vg->soc->pins[i].number;
1436
1437                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1438                 if (!reg) {
1439                         dev_warn(vg->dev, "Pin %i: could not retrieve CONF0\n", i);
1440                         continue;
1441                 }
1442
1443                 value = readl(reg);
1444                 if (value & BYT_DIRECT_IRQ_EN) {
1445                         if (byt_direct_irq_sanity_check(vg, i, value)) {
1446                                 clear_bit(i, valid_mask);
1447                         } else {
1448                                 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS |
1449                                            BYT_TRIG_NEG | BYT_TRIG_LVL);
1450                                 writel(value, reg);
1451                         }
1452                 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1453                         byt_gpio_clear_triggering(vg, i);
1454                         dev_dbg(vg->dev, "disabling GPIO %d\n", i);
1455                 }
1456         }
1457 }
1458
1459 static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
1460 {
1461         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1462         void __iomem *reg;
1463         u32 base, value;
1464
1465         /* clear interrupt status trigger registers */
1466         for (base = 0; base < vg->soc->npins; base += 32) {
1467                 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1468
1469                 if (!reg) {
1470                         dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base);
1471                         continue;
1472                 }
1473
1474                 writel(0xffffffff, reg);
1475                 /* make sure trigger bits are cleared, if not then a pin
1476                    might be misconfigured in bios */
1477                 value = readl(reg);
1478                 if (value)
1479                         dev_err(vg->dev,
1480                                 "GPIO interrupt error, pins misconfigured. INT_STAT%u: %#08x\n",
1481                                 base / 32, value);
1482         }
1483
1484         return 0;
1485 }
1486
1487 static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)
1488 {
1489         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1490         struct device *dev = vg->dev;
1491         int ret;
1492
1493         ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);
1494         if (ret)
1495                 dev_err(dev, "failed to add GPIO pin range\n");
1496
1497         return ret;
1498 }
1499
1500 static int byt_gpio_probe(struct intel_pinctrl *vg)
1501 {
1502         struct platform_device *pdev = to_platform_device(vg->dev);
1503         struct gpio_chip *gc;
1504         int irq, ret;
1505
1506         /* Set up gpio chip */
1507         vg->chip        = byt_gpio_chip;
1508         gc              = &vg->chip;
1509         gc->label       = dev_name(vg->dev);
1510         gc->base        = -1;
1511         gc->can_sleep   = false;
1512         gc->add_pin_ranges = byt_gpio_add_pin_ranges;
1513         gc->parent      = vg->dev;
1514         gc->ngpio       = vg->soc->npins;
1515
1516 #ifdef CONFIG_PM_SLEEP
1517         vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads),
1518                                         GFP_KERNEL);
1519         if (!vg->context.pads)
1520                 return -ENOMEM;
1521 #endif
1522
1523         /* set up interrupts  */
1524         irq = platform_get_irq_optional(pdev, 0);
1525         if (irq > 0) {
1526                 struct gpio_irq_chip *girq;
1527
1528                 girq = &gc->irq;
1529                 gpio_irq_chip_set_chip(girq, &byt_gpio_irq_chip);
1530                 girq->init_hw = byt_gpio_irq_init_hw;
1531                 girq->init_valid_mask = byt_init_irq_valid_mask;
1532                 girq->parent_handler = byt_gpio_irq_handler;
1533                 girq->num_parents = 1;
1534                 girq->parents = devm_kcalloc(vg->dev, girq->num_parents,
1535                                              sizeof(*girq->parents), GFP_KERNEL);
1536                 if (!girq->parents)
1537                         return -ENOMEM;
1538                 girq->parents[0] = irq;
1539                 girq->default_type = IRQ_TYPE_NONE;
1540                 girq->handler = handle_bad_irq;
1541         }
1542
1543         ret = devm_gpiochip_add_data(vg->dev, gc, vg);
1544         if (ret) {
1545                 dev_err(vg->dev, "failed adding byt-gpio chip\n");
1546                 return ret;
1547         }
1548
1549         return ret;
1550 }
1551
1552 static int byt_set_soc_data(struct intel_pinctrl *vg,
1553                             const struct intel_pinctrl_soc_data *soc)
1554 {
1555         struct platform_device *pdev = to_platform_device(vg->dev);
1556         int i;
1557
1558         vg->soc = soc;
1559
1560         vg->ncommunities = vg->soc->ncommunities;
1561         vg->communities = devm_kcalloc(vg->dev, vg->ncommunities,
1562                                        sizeof(*vg->communities), GFP_KERNEL);
1563         if (!vg->communities)
1564                 return -ENOMEM;
1565
1566         for (i = 0; i < vg->soc->ncommunities; i++) {
1567                 struct intel_community *comm = vg->communities + i;
1568
1569                 *comm = vg->soc->communities[i];
1570
1571                 comm->pad_regs = devm_platform_ioremap_resource(pdev, 0);
1572                 if (IS_ERR(comm->pad_regs))
1573                         return PTR_ERR(comm->pad_regs);
1574         }
1575
1576         return 0;
1577 }
1578
1579 static const struct acpi_device_id byt_gpio_acpi_match[] = {
1580         { "INT33B2", (kernel_ulong_t)byt_soc_data },
1581         { "INT33FC", (kernel_ulong_t)byt_soc_data },
1582         { }
1583 };
1584
1585 static int byt_pinctrl_probe(struct platform_device *pdev)
1586 {
1587         const struct intel_pinctrl_soc_data *soc_data;
1588         struct device *dev = &pdev->dev;
1589         struct intel_pinctrl *vg;
1590         int ret;
1591
1592         soc_data = intel_pinctrl_get_soc_data(pdev);
1593         if (IS_ERR(soc_data))
1594                 return PTR_ERR(soc_data);
1595
1596         vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL);
1597         if (!vg)
1598                 return -ENOMEM;
1599
1600         vg->dev = dev;
1601         ret = byt_set_soc_data(vg, soc_data);
1602         if (ret) {
1603                 dev_err(dev, "failed to set soc data\n");
1604                 return ret;
1605         }
1606
1607         vg->pctldesc            = byt_pinctrl_desc;
1608         vg->pctldesc.name       = dev_name(dev);
1609         vg->pctldesc.pins       = vg->soc->pins;
1610         vg->pctldesc.npins      = vg->soc->npins;
1611
1612         vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg);
1613         if (IS_ERR(vg->pctldev)) {
1614                 dev_err(dev, "failed to register pinctrl driver\n");
1615                 return PTR_ERR(vg->pctldev);
1616         }
1617
1618         ret = byt_gpio_probe(vg);
1619         if (ret)
1620                 return ret;
1621
1622         platform_set_drvdata(pdev, vg);
1623
1624         return 0;
1625 }
1626
1627 static int byt_gpio_suspend(struct device *dev)
1628 {
1629         struct intel_pinctrl *vg = dev_get_drvdata(dev);
1630         int i;
1631
1632         guard(raw_spinlock_irqsave)(&byt_lock);
1633
1634         for (i = 0; i < vg->soc->npins; i++) {
1635                 void __iomem *reg;
1636                 u32 value;
1637                 unsigned int pin = vg->soc->pins[i].number;
1638
1639                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1640                 if (!reg) {
1641                         dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i);
1642                         continue;
1643                 }
1644                 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1645                 vg->context.pads[i].conf0 = value;
1646
1647                 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1648                 if (!reg) {
1649                         dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i);
1650                         continue;
1651                 }
1652                 value = readl(reg) & BYT_VAL_RESTORE_MASK;
1653                 vg->context.pads[i].val = value;
1654         }
1655
1656         return 0;
1657 }
1658
1659 static int byt_gpio_resume(struct device *dev)
1660 {
1661         struct intel_pinctrl *vg = dev_get_drvdata(dev);
1662         int i;
1663
1664         guard(raw_spinlock_irqsave)(&byt_lock);
1665
1666         for (i = 0; i < vg->soc->npins; i++) {
1667                 void __iomem *reg;
1668                 u32 value;
1669                 unsigned int pin = vg->soc->pins[i].number;
1670
1671                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1672                 if (!reg) {
1673                         dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i);
1674                         continue;
1675                 }
1676                 value = readl(reg);
1677                 if ((value & BYT_CONF0_RESTORE_MASK) !=
1678                      vg->context.pads[i].conf0) {
1679                         value &= ~BYT_CONF0_RESTORE_MASK;
1680                         value |= vg->context.pads[i].conf0;
1681                         writel(value, reg);
1682                         dev_info(dev, "restored pin %d CONF0 %#08x", i, value);
1683                 }
1684
1685                 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1686                 if (!reg) {
1687                         dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i);
1688                         continue;
1689                 }
1690                 value = readl(reg);
1691                 if ((value & BYT_VAL_RESTORE_MASK) !=
1692                      vg->context.pads[i].val) {
1693                         u32 v;
1694
1695                         v = value & ~BYT_VAL_RESTORE_MASK;
1696                         v |= vg->context.pads[i].val;
1697                         if (v != value) {
1698                                 writel(v, reg);
1699                                 dev_dbg(dev, "restored pin %d VAL %#08x\n", i, v);
1700                         }
1701                 }
1702         }
1703
1704         return 0;
1705 }
1706
1707 static const struct dev_pm_ops byt_gpio_pm_ops = {
1708         LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
1709 };
1710
1711 static struct platform_driver byt_gpio_driver = {
1712         .probe          = byt_pinctrl_probe,
1713         .driver         = {
1714                 .name                   = "byt_gpio",
1715                 .pm                     = pm_sleep_ptr(&byt_gpio_pm_ops),
1716                 .acpi_match_table       = byt_gpio_acpi_match,
1717                 .suppress_bind_attrs    = true,
1718         },
1719 };
1720
1721 static int __init byt_gpio_init(void)
1722 {
1723         return platform_driver_register(&byt_gpio_driver);
1724 }
1725 subsys_initcall(byt_gpio_init);
1726
1727 MODULE_IMPORT_NS(PINCTRL_INTEL);