1 // SPDX-License-Identifier: GPL-2.0
3 * Driver core for Samsung SoC onboard UARTs.
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
6 * http://armlinux.simtec.co.uk/
9 /* Note on 2410 error handling
11 * The s3c2410 manual has a love/hate affair with the contents of the
12 * UERSTAT register in the UART blocks, and keeps marking some of the
13 * error bits as reserved. Having checked with the s3c2410x01,
14 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
15 * feature from the latter versions of the manual.
17 * If it becomes aparrent that latter versions of the 2410 remove these
18 * bits, then action will have to be taken to differentiate the versions
19 * and change the policy on BREAK
24 #include <linux/dmaengine.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/slab.h>
27 #include <linux/math.h>
28 #include <linux/module.h>
29 #include <linux/ioport.h>
31 #include <linux/platform_device.h>
32 #include <linux/init.h>
33 #include <linux/sysrq.h>
34 #include <linux/console.h>
35 #include <linux/tty.h>
36 #include <linux/tty_flip.h>
37 #include <linux/serial_core.h>
38 #include <linux/serial.h>
39 #include <linux/serial_s3c.h>
40 #include <linux/delay.h>
41 #include <linux/clk.h>
42 #include <linux/cpufreq.h>
46 /* UART name and device definitions */
48 #define S3C24XX_SERIAL_NAME "ttySAC"
49 #define S3C24XX_SERIAL_MAJOR 204
50 #define S3C24XX_SERIAL_MINOR 64
55 #define UART_NR CONFIG_SERIAL_SAMSUNG_UARTS
58 #define S3C24XX_TX_PIO 1
59 #define S3C24XX_TX_DMA 2
60 #define S3C24XX_RX_PIO 1
61 #define S3C24XX_RX_DMA 2
63 /* flag to ignore all characters coming in */
64 #define RXSTAT_DUMMY_READ (0x10000000)
66 enum s3c24xx_port_type {
71 struct s3c24xx_uart_info {
73 enum s3c24xx_port_type type;
74 unsigned int port_type;
75 unsigned int fifosize;
76 unsigned long rx_fifomask;
77 unsigned long rx_fifoshift;
78 unsigned long rx_fifofull;
79 unsigned long tx_fifomask;
80 unsigned long tx_fifoshift;
81 unsigned long tx_fifofull;
82 unsigned int def_clk_sel;
83 unsigned long num_clks;
84 unsigned long clksel_mask;
85 unsigned long clksel_shift;
86 unsigned long ucon_mask;
88 /* uart port features */
90 unsigned int has_divslot:1;
93 struct s3c24xx_serial_drv_data {
94 const struct s3c24xx_uart_info info;
95 const struct s3c2410_uartcfg def_cfg;
96 const unsigned int fifosize[UART_NR];
99 struct s3c24xx_uart_dma {
100 unsigned int rx_chan_id;
101 unsigned int tx_chan_id;
103 struct dma_slave_config rx_conf;
104 struct dma_slave_config tx_conf;
106 struct dma_chan *rx_chan;
107 struct dma_chan *tx_chan;
112 dma_cookie_t rx_cookie;
113 dma_cookie_t tx_cookie;
117 dma_addr_t tx_transfer_addr;
122 struct dma_async_tx_descriptor *tx_desc;
123 struct dma_async_tx_descriptor *rx_desc;
125 int tx_bytes_requested;
126 int rx_bytes_requested;
129 struct s3c24xx_uart_port {
130 unsigned char rx_enabled;
131 unsigned char tx_enabled;
132 unsigned int pm_level;
133 unsigned long baudclk_rate;
134 unsigned int min_dma_size;
139 unsigned int tx_in_progress;
140 unsigned int tx_mode;
141 unsigned int rx_mode;
143 const struct s3c24xx_uart_info *info;
146 struct uart_port port;
147 const struct s3c24xx_serial_drv_data *drv_data;
149 /* reference to platform data */
150 const struct s3c2410_uartcfg *cfg;
152 struct s3c24xx_uart_dma *dma;
155 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport);
157 /* conversion functions */
159 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
161 /* register access controls */
163 #define portaddr(port, reg) ((port)->membase + (reg))
164 #define portaddrl(port, reg) \
165 ((unsigned long *)(unsigned long)((port)->membase + (reg)))
167 static u32 rd_reg(const struct uart_port *port, u32 reg)
169 switch (port->iotype) {
171 return readb_relaxed(portaddr(port, reg));
173 return readl_relaxed(portaddr(port, reg));
180 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
182 static void wr_reg(const struct uart_port *port, u32 reg, u32 val)
184 switch (port->iotype) {
186 writeb_relaxed(val, portaddr(port, reg));
189 writel_relaxed(val, portaddr(port, reg));
194 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
196 /* Byte-order aware bit setting/clearing functions. */
198 static inline void s3c24xx_set_bit(const struct uart_port *port, int idx,
204 local_irq_save(flags);
205 val = rd_regl(port, reg);
207 wr_regl(port, reg, val);
208 local_irq_restore(flags);
211 static inline void s3c24xx_clear_bit(const struct uart_port *port, int idx,
217 local_irq_save(flags);
218 val = rd_regl(port, reg);
220 wr_regl(port, reg, val);
221 local_irq_restore(flags);
224 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
226 return container_of(port, struct s3c24xx_uart_port, port);
229 /* translate a port to the device name */
231 static inline const char *s3c24xx_serial_portname(const struct uart_port *port)
233 return to_platform_device(port->dev)->name;
236 static int s3c24xx_serial_txempty_nofifo(const struct uart_port *port)
238 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
241 static void s3c24xx_serial_rx_enable(struct uart_port *port)
243 struct s3c24xx_uart_port *ourport = to_ourport(port);
245 unsigned int ucon, ufcon;
248 uart_port_lock_irqsave(port, &flags);
250 while (--count && !s3c24xx_serial_txempty_nofifo(port))
253 ufcon = rd_regl(port, S3C2410_UFCON);
254 ufcon |= S3C2410_UFCON_RESETRX;
255 wr_regl(port, S3C2410_UFCON, ufcon);
257 ucon = rd_regl(port, S3C2410_UCON);
258 ucon |= S3C2410_UCON_RXIRQMODE;
259 wr_regl(port, S3C2410_UCON, ucon);
261 ourport->rx_enabled = 1;
262 uart_port_unlock_irqrestore(port, flags);
265 static void s3c24xx_serial_rx_disable(struct uart_port *port)
267 struct s3c24xx_uart_port *ourport = to_ourport(port);
271 uart_port_lock_irqsave(port, &flags);
273 ucon = rd_regl(port, S3C2410_UCON);
274 ucon &= ~S3C2410_UCON_RXIRQMODE;
275 wr_regl(port, S3C2410_UCON, ucon);
277 ourport->rx_enabled = 0;
278 uart_port_unlock_irqrestore(port, flags);
281 static void s3c24xx_serial_stop_tx(struct uart_port *port)
283 struct s3c24xx_uart_port *ourport = to_ourport(port);
284 struct s3c24xx_uart_dma *dma = ourport->dma;
285 struct dma_tx_state state;
288 if (!ourport->tx_enabled)
291 switch (ourport->info->type) {
293 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
296 s3c24xx_clear_bit(port, APPLE_S5L_UCON_TXTHRESH_ENA, S3C2410_UCON);
299 disable_irq_nosync(ourport->tx_irq);
303 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
304 dmaengine_pause(dma->tx_chan);
305 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
306 dmaengine_terminate_all(dma->tx_chan);
307 dma_sync_single_for_cpu(dma->tx_chan->device->dev,
308 dma->tx_transfer_addr, dma->tx_size,
310 async_tx_ack(dma->tx_desc);
311 count = dma->tx_bytes_requested - state.residue;
312 uart_xmit_advance(port, count);
315 ourport->tx_enabled = 0;
316 ourport->tx_in_progress = 0;
318 if (port->flags & UPF_CONS_FLOW)
319 s3c24xx_serial_rx_enable(port);
321 ourport->tx_mode = 0;
324 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
326 static void s3c24xx_serial_tx_dma_complete(void *args)
328 struct s3c24xx_uart_port *ourport = args;
329 struct uart_port *port = &ourport->port;
330 struct circ_buf *xmit = &port->state->xmit;
331 struct s3c24xx_uart_dma *dma = ourport->dma;
332 struct dma_tx_state state;
336 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
337 count = dma->tx_bytes_requested - state.residue;
338 async_tx_ack(dma->tx_desc);
340 dma_sync_single_for_cpu(dma->tx_chan->device->dev,
341 dma->tx_transfer_addr, dma->tx_size,
344 uart_port_lock_irqsave(port, &flags);
346 uart_xmit_advance(port, count);
347 ourport->tx_in_progress = 0;
349 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
350 uart_write_wakeup(port);
352 s3c24xx_serial_start_next_tx(ourport);
353 uart_port_unlock_irqrestore(port, flags);
356 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
358 const struct uart_port *port = &ourport->port;
361 /* Mask Tx interrupt */
362 switch (ourport->info->type) {
364 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
367 WARN_ON(1); // No DMA
370 disable_irq_nosync(ourport->tx_irq);
374 /* Enable tx dma mode */
375 ucon = rd_regl(port, S3C2410_UCON);
376 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
377 ucon |= S3C64XX_UCON_TXBURST_1;
378 ucon |= S3C64XX_UCON_TXMODE_DMA;
379 wr_regl(port, S3C2410_UCON, ucon);
381 ourport->tx_mode = S3C24XX_TX_DMA;
384 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
386 const struct uart_port *port = &ourport->port;
389 /* Set ufcon txtrig */
390 ourport->tx_in_progress = S3C24XX_TX_PIO;
391 ufcon = rd_regl(port, S3C2410_UFCON);
392 wr_regl(port, S3C2410_UFCON, ufcon);
394 /* Enable tx pio mode */
395 ucon = rd_regl(port, S3C2410_UCON);
396 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
397 ucon |= S3C64XX_UCON_TXMODE_CPU;
398 wr_regl(port, S3C2410_UCON, ucon);
400 /* Unmask Tx interrupt */
401 switch (ourport->info->type) {
403 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
407 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
408 wr_regl(port, S3C2410_UCON, ucon);
411 enable_irq(ourport->tx_irq);
415 ourport->tx_mode = S3C24XX_TX_PIO;
418 * The Apple version only has edge triggered TX IRQs, so we need
419 * to kick off the process by sending some characters here.
421 if (ourport->info->type == TYPE_APPLE_S5L)
422 s3c24xx_serial_tx_chars(ourport);
425 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
427 if (ourport->tx_mode != S3C24XX_TX_PIO)
428 enable_tx_pio(ourport);
431 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
434 struct uart_port *port = &ourport->port;
435 struct circ_buf *xmit = &port->state->xmit;
436 struct s3c24xx_uart_dma *dma = ourport->dma;
438 if (ourport->tx_mode != S3C24XX_TX_DMA)
439 enable_tx_dma(ourport);
441 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
442 dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
444 dma_sync_single_for_device(dma->tx_chan->device->dev,
445 dma->tx_transfer_addr, dma->tx_size,
448 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
449 dma->tx_transfer_addr, dma->tx_size,
450 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
452 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
456 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
457 dma->tx_desc->callback_param = ourport;
458 dma->tx_bytes_requested = dma->tx_size;
460 ourport->tx_in_progress = S3C24XX_TX_DMA;
461 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
462 dma_async_issue_pending(dma->tx_chan);
466 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
468 struct uart_port *port = &ourport->port;
469 struct circ_buf *xmit = &port->state->xmit;
472 /* Get data size up to the end of buffer */
473 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
476 s3c24xx_serial_stop_tx(port);
480 if (!ourport->dma || !ourport->dma->tx_chan ||
481 count < ourport->min_dma_size ||
482 xmit->tail & (dma_get_cache_alignment() - 1))
483 s3c24xx_serial_start_tx_pio(ourport);
485 s3c24xx_serial_start_tx_dma(ourport, count);
488 static void s3c24xx_serial_start_tx(struct uart_port *port)
490 struct s3c24xx_uart_port *ourport = to_ourport(port);
491 struct circ_buf *xmit = &port->state->xmit;
493 if (!ourport->tx_enabled) {
494 if (port->flags & UPF_CONS_FLOW)
495 s3c24xx_serial_rx_disable(port);
497 ourport->tx_enabled = 1;
498 if (!ourport->dma || !ourport->dma->tx_chan)
499 s3c24xx_serial_start_tx_pio(ourport);
502 if (ourport->dma && ourport->dma->tx_chan) {
503 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
504 s3c24xx_serial_start_next_tx(ourport);
508 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
509 struct tty_port *tty, int count)
511 struct s3c24xx_uart_dma *dma = ourport->dma;
517 dma_sync_single_for_cpu(dma->rx_chan->device->dev, dma->rx_addr,
518 dma->rx_size, DMA_FROM_DEVICE);
520 ourport->port.icount.rx += count;
522 dev_err(ourport->port.dev, "No tty port\n");
525 copied = tty_insert_flip_string(tty,
526 ((unsigned char *)(ourport->dma->rx_buf)), count);
527 if (copied != count) {
529 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
533 static void s3c24xx_serial_stop_rx(struct uart_port *port)
535 struct s3c24xx_uart_port *ourport = to_ourport(port);
536 struct s3c24xx_uart_dma *dma = ourport->dma;
537 struct tty_port *t = &port->state->port;
538 struct dma_tx_state state;
539 enum dma_status dma_status;
540 unsigned int received;
542 if (ourport->rx_enabled) {
543 dev_dbg(port->dev, "stopping rx\n");
544 switch (ourport->info->type) {
546 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
550 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
551 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
554 disable_irq_nosync(ourport->rx_irq);
557 ourport->rx_enabled = 0;
559 if (dma && dma->rx_chan) {
560 dmaengine_pause(dma->tx_chan);
561 dma_status = dmaengine_tx_status(dma->rx_chan,
562 dma->rx_cookie, &state);
563 if (dma_status == DMA_IN_PROGRESS ||
564 dma_status == DMA_PAUSED) {
565 received = dma->rx_bytes_requested - state.residue;
566 dmaengine_terminate_all(dma->rx_chan);
567 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
572 static inline const struct s3c24xx_uart_info
573 *s3c24xx_port_to_info(struct uart_port *port)
575 return to_ourport(port)->info;
578 static inline const struct s3c2410_uartcfg
579 *s3c24xx_port_to_cfg(const struct uart_port *port)
581 const struct s3c24xx_uart_port *ourport;
583 if (port->dev == NULL)
586 ourport = container_of(port, struct s3c24xx_uart_port, port);
590 static int s3c24xx_serial_rx_fifocnt(const struct s3c24xx_uart_port *ourport,
591 unsigned long ufstat)
593 const struct s3c24xx_uart_info *info = ourport->info;
595 if (ufstat & info->rx_fifofull)
596 return ourport->port.fifosize;
598 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
601 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
602 static void s3c24xx_serial_rx_dma_complete(void *args)
604 struct s3c24xx_uart_port *ourport = args;
605 struct uart_port *port = &ourport->port;
607 struct s3c24xx_uart_dma *dma = ourport->dma;
608 struct tty_port *t = &port->state->port;
609 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
611 struct dma_tx_state state;
615 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
616 received = dma->rx_bytes_requested - state.residue;
617 async_tx_ack(dma->rx_desc);
619 uart_port_lock_irqsave(port, &flags);
622 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
625 tty_flip_buffer_push(t);
629 s3c64xx_start_rx_dma(ourport);
631 uart_port_unlock_irqrestore(port, flags);
634 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
636 struct s3c24xx_uart_dma *dma = ourport->dma;
638 dma_sync_single_for_device(dma->rx_chan->device->dev, dma->rx_addr,
639 dma->rx_size, DMA_FROM_DEVICE);
641 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
642 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
645 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
649 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
650 dma->rx_desc->callback_param = ourport;
651 dma->rx_bytes_requested = dma->rx_size;
653 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
654 dma_async_issue_pending(dma->rx_chan);
657 /* ? - where has parity gone?? */
658 #define S3C2410_UERSTAT_PARITY (0x1000)
660 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
662 struct uart_port *port = &ourport->port;
665 /* set Rx mode to DMA mode */
666 ucon = rd_regl(port, S3C2410_UCON);
667 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
668 S3C64XX_UCON_TIMEOUT_MASK |
669 S3C64XX_UCON_EMPTYINT_EN |
670 S3C64XX_UCON_DMASUS_EN |
671 S3C64XX_UCON_TIMEOUT_EN |
672 S3C64XX_UCON_RXMODE_MASK);
673 ucon |= S3C64XX_UCON_RXBURST_1 |
674 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
675 S3C64XX_UCON_EMPTYINT_EN |
676 S3C64XX_UCON_TIMEOUT_EN |
677 S3C64XX_UCON_RXMODE_DMA;
678 wr_regl(port, S3C2410_UCON, ucon);
680 ourport->rx_mode = S3C24XX_RX_DMA;
683 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
685 struct uart_port *port = &ourport->port;
688 /* set Rx mode to DMA mode */
689 ucon = rd_regl(port, S3C2410_UCON);
690 ucon &= ~S3C64XX_UCON_RXMODE_MASK;
691 ucon |= S3C64XX_UCON_RXMODE_CPU;
693 /* Apple types use these bits for IRQ masks */
694 if (ourport->info->type != TYPE_APPLE_S5L) {
695 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
696 S3C64XX_UCON_EMPTYINT_EN |
697 S3C64XX_UCON_DMASUS_EN |
698 S3C64XX_UCON_TIMEOUT_EN);
699 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
700 S3C64XX_UCON_TIMEOUT_EN;
702 wr_regl(port, S3C2410_UCON, ucon);
704 ourport->rx_mode = S3C24XX_RX_PIO;
707 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
709 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
711 unsigned int utrstat, received;
712 struct s3c24xx_uart_port *ourport = dev_id;
713 struct uart_port *port = &ourport->port;
714 struct s3c24xx_uart_dma *dma = ourport->dma;
715 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
716 struct tty_port *t = &port->state->port;
717 struct dma_tx_state state;
719 utrstat = rd_regl(port, S3C2410_UTRSTAT);
720 rd_regl(port, S3C2410_UFSTAT);
722 uart_port_lock(port);
724 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
725 s3c64xx_start_rx_dma(ourport);
726 if (ourport->rx_mode == S3C24XX_RX_PIO)
727 enable_rx_dma(ourport);
731 if (ourport->rx_mode == S3C24XX_RX_DMA) {
732 dmaengine_pause(dma->rx_chan);
733 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
734 dmaengine_terminate_all(dma->rx_chan);
735 received = dma->rx_bytes_requested - state.residue;
736 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
738 enable_rx_pio(ourport);
741 s3c24xx_serial_rx_drain_fifo(ourport);
744 tty_flip_buffer_push(t);
748 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
751 uart_port_unlock(port);
756 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
758 struct uart_port *port = &ourport->port;
759 unsigned int ufcon, ufstat, uerstat;
760 unsigned int fifocnt = 0;
761 int max_count = port->fifosize;
764 while (max_count-- > 0) {
766 * Receive all characters known to be in FIFO
767 * before reading FIFO level again
770 ufstat = rd_regl(port, S3C2410_UFSTAT);
771 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
777 uerstat = rd_regl(port, S3C2410_UERSTAT);
778 ch = rd_reg(port, S3C2410_URXH);
780 if (port->flags & UPF_CONS_FLOW) {
781 int txe = s3c24xx_serial_txempty_nofifo(port);
783 if (ourport->rx_enabled) {
785 ourport->rx_enabled = 0;
790 ufcon = rd_regl(port, S3C2410_UFCON);
791 ufcon |= S3C2410_UFCON_RESETRX;
792 wr_regl(port, S3C2410_UFCON, ufcon);
793 ourport->rx_enabled = 1;
800 /* insert the character into the buffer */
805 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
807 "rxerr: port ch=0x%02x, rxs=0x%08x\n",
810 /* check for break */
811 if (uerstat & S3C2410_UERSTAT_BREAK) {
812 dev_dbg(port->dev, "break!\n");
814 if (uart_handle_break(port))
815 continue; /* Ignore character */
818 if (uerstat & S3C2410_UERSTAT_FRAME)
819 port->icount.frame++;
820 if (uerstat & S3C2410_UERSTAT_OVERRUN)
821 port->icount.overrun++;
823 uerstat &= port->read_status_mask;
825 if (uerstat & S3C2410_UERSTAT_BREAK)
827 else if (uerstat & S3C2410_UERSTAT_PARITY)
829 else if (uerstat & (S3C2410_UERSTAT_FRAME |
830 S3C2410_UERSTAT_OVERRUN))
834 if (uart_handle_sysrq_char(port, ch))
835 continue; /* Ignore character */
837 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
841 tty_flip_buffer_push(&port->state->port);
844 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
846 struct s3c24xx_uart_port *ourport = dev_id;
847 struct uart_port *port = &ourport->port;
849 uart_port_lock(port);
850 s3c24xx_serial_rx_drain_fifo(ourport);
851 uart_port_unlock(port);
856 static irqreturn_t s3c24xx_serial_rx_irq(int irq, void *dev_id)
858 struct s3c24xx_uart_port *ourport = dev_id;
860 if (ourport->dma && ourport->dma->rx_chan)
861 return s3c24xx_serial_rx_chars_dma(dev_id);
862 return s3c24xx_serial_rx_chars_pio(dev_id);
865 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport)
867 struct uart_port *port = &ourport->port;
868 struct circ_buf *xmit = &port->state->xmit;
869 int count, dma_count = 0;
871 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
873 if (ourport->dma && ourport->dma->tx_chan &&
874 count >= ourport->min_dma_size) {
875 int align = dma_get_cache_alignment() -
876 (xmit->tail & (dma_get_cache_alignment() - 1));
877 if (count - align >= ourport->min_dma_size) {
878 dma_count = count - align;
884 wr_reg(port, S3C2410_UTXH, port->x_char);
890 /* if there isn't anything more to transmit, or the uart is now
891 * stopped, disable the uart and exit
894 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
895 s3c24xx_serial_stop_tx(port);
899 /* try and drain the buffer... */
901 if (count > port->fifosize) {
902 count = port->fifosize;
906 while (!uart_circ_empty(xmit) && count > 0) {
907 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
910 wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
911 uart_xmit_advance(port, 1);
915 if (!count && dma_count) {
916 s3c24xx_serial_start_tx_dma(ourport, dma_count);
920 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
921 uart_write_wakeup(port);
923 if (uart_circ_empty(xmit))
924 s3c24xx_serial_stop_tx(port);
927 static irqreturn_t s3c24xx_serial_tx_irq(int irq, void *id)
929 struct s3c24xx_uart_port *ourport = id;
930 struct uart_port *port = &ourport->port;
932 uart_port_lock(port);
934 s3c24xx_serial_tx_chars(ourport);
936 uart_port_unlock(port);
940 /* interrupt handler for s3c64xx and later SoC's.*/
941 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
943 const struct s3c24xx_uart_port *ourport = id;
944 const struct uart_port *port = &ourport->port;
945 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
946 irqreturn_t ret = IRQ_HANDLED;
948 if (pend & S3C64XX_UINTM_RXD_MSK) {
949 ret = s3c24xx_serial_rx_irq(irq, id);
950 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
952 if (pend & S3C64XX_UINTM_TXD_MSK) {
953 ret = s3c24xx_serial_tx_irq(irq, id);
954 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
959 /* interrupt handler for Apple SoC's.*/
960 static irqreturn_t apple_serial_handle_irq(int irq, void *id)
962 const struct s3c24xx_uart_port *ourport = id;
963 const struct uart_port *port = &ourport->port;
964 unsigned int pend = rd_regl(port, S3C2410_UTRSTAT);
965 irqreturn_t ret = IRQ_NONE;
967 if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO)) {
968 wr_regl(port, S3C2410_UTRSTAT,
969 APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO);
970 ret = s3c24xx_serial_rx_irq(irq, id);
972 if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) {
973 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_TXTHRESH);
974 ret = s3c24xx_serial_tx_irq(irq, id);
980 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
982 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
983 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
984 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
986 if (ufcon & S3C2410_UFCON_FIFOMODE) {
987 if ((ufstat & info->tx_fifomask) != 0 ||
988 (ufstat & info->tx_fifofull))
994 return s3c24xx_serial_txempty_nofifo(port);
997 /* no modem control lines */
998 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
1000 unsigned int umstat = rd_reg(port, S3C2410_UMSTAT);
1002 if (umstat & S3C2410_UMSTAT_CTS)
1003 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1005 return TIOCM_CAR | TIOCM_DSR;
1008 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
1010 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
1011 unsigned int ucon = rd_regl(port, S3C2410_UCON);
1013 if (mctrl & TIOCM_RTS)
1014 umcon |= S3C2410_UMCOM_RTS_LOW;
1016 umcon &= ~S3C2410_UMCOM_RTS_LOW;
1018 wr_regl(port, S3C2410_UMCON, umcon);
1020 if (mctrl & TIOCM_LOOP)
1021 ucon |= S3C2410_UCON_LOOPBACK;
1023 ucon &= ~S3C2410_UCON_LOOPBACK;
1025 wr_regl(port, S3C2410_UCON, ucon);
1028 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
1030 unsigned long flags;
1033 uart_port_lock_irqsave(port, &flags);
1035 ucon = rd_regl(port, S3C2410_UCON);
1038 ucon |= S3C2410_UCON_SBREAK;
1040 ucon &= ~S3C2410_UCON_SBREAK;
1042 wr_regl(port, S3C2410_UCON, ucon);
1044 uart_port_unlock_irqrestore(port, flags);
1047 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
1049 struct s3c24xx_uart_dma *dma = p->dma;
1050 struct dma_slave_caps dma_caps;
1051 const char *reason = NULL;
1054 /* Default slave configuration parameters */
1055 dma->rx_conf.direction = DMA_DEV_TO_MEM;
1056 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1057 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
1058 dma->rx_conf.src_maxburst = 1;
1060 dma->tx_conf.direction = DMA_MEM_TO_DEV;
1061 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1062 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
1063 dma->tx_conf.dst_maxburst = 1;
1065 dma->rx_chan = dma_request_chan(p->port.dev, "rx");
1067 if (IS_ERR(dma->rx_chan)) {
1068 reason = "DMA RX channel request failed";
1069 ret = PTR_ERR(dma->rx_chan);
1073 ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
1075 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1076 reason = "insufficient DMA RX engine capabilities";
1078 goto err_release_rx;
1081 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
1083 dma->tx_chan = dma_request_chan(p->port.dev, "tx");
1084 if (IS_ERR(dma->tx_chan)) {
1085 reason = "DMA TX channel request failed";
1086 ret = PTR_ERR(dma->tx_chan);
1087 goto err_release_rx;
1090 ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
1092 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1093 reason = "insufficient DMA TX engine capabilities";
1095 goto err_release_tx;
1098 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
1101 dma->rx_size = PAGE_SIZE;
1103 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
1106 goto err_release_tx;
1109 dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
1110 dma->rx_size, DMA_FROM_DEVICE);
1111 if (dma_mapping_error(dma->rx_chan->device->dev, dma->rx_addr)) {
1112 reason = "DMA mapping error for RX buffer";
1118 dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
1119 p->port.state->xmit.buf, UART_XMIT_SIZE,
1121 if (dma_mapping_error(dma->tx_chan->device->dev, dma->tx_addr)) {
1122 reason = "DMA mapping error for TX buffer";
1130 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1131 dma->rx_size, DMA_FROM_DEVICE);
1135 dma_release_channel(dma->tx_chan);
1137 dma_release_channel(dma->rx_chan);
1140 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
1144 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
1146 struct s3c24xx_uart_dma *dma = p->dma;
1149 dmaengine_terminate_all(dma->rx_chan);
1150 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1151 dma->rx_size, DMA_FROM_DEVICE);
1153 dma_release_channel(dma->rx_chan);
1154 dma->rx_chan = NULL;
1158 dmaengine_terminate_all(dma->tx_chan);
1159 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
1160 UART_XMIT_SIZE, DMA_TO_DEVICE);
1161 dma_release_channel(dma->tx_chan);
1162 dma->tx_chan = NULL;
1166 static void s3c64xx_serial_shutdown(struct uart_port *port)
1168 struct s3c24xx_uart_port *ourport = to_ourport(port);
1170 ourport->tx_enabled = 0;
1171 ourport->tx_mode = 0;
1172 ourport->rx_enabled = 0;
1174 free_irq(port->irq, ourport);
1176 wr_regl(port, S3C64XX_UINTP, 0xf);
1177 wr_regl(port, S3C64XX_UINTM, 0xf);
1180 s3c24xx_serial_release_dma(ourport);
1182 ourport->tx_in_progress = 0;
1185 static void apple_s5l_serial_shutdown(struct uart_port *port)
1187 struct s3c24xx_uart_port *ourport = to_ourport(port);
1191 ucon = rd_regl(port, S3C2410_UCON);
1192 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
1193 APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
1194 APPLE_S5L_UCON_RXTO_ENA_MSK);
1195 wr_regl(port, S3C2410_UCON, ucon);
1197 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1199 free_irq(port->irq, ourport);
1201 ourport->tx_enabled = 0;
1202 ourport->tx_mode = 0;
1203 ourport->rx_enabled = 0;
1206 s3c24xx_serial_release_dma(ourport);
1208 ourport->tx_in_progress = 0;
1211 static int s3c64xx_serial_startup(struct uart_port *port)
1213 struct s3c24xx_uart_port *ourport = to_ourport(port);
1214 unsigned long flags;
1218 wr_regl(port, S3C64XX_UINTM, 0xf);
1220 ret = s3c24xx_serial_request_dma(ourport);
1222 devm_kfree(port->dev, ourport->dma);
1223 ourport->dma = NULL;
1227 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1228 s3c24xx_serial_portname(port), ourport);
1230 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1234 /* For compatibility with s3c24xx Soc's */
1235 ourport->rx_enabled = 1;
1236 ourport->tx_enabled = 0;
1238 uart_port_lock_irqsave(port, &flags);
1240 ufcon = rd_regl(port, S3C2410_UFCON);
1241 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1242 if (!uart_console(port))
1243 ufcon |= S3C2410_UFCON_RESETTX;
1244 wr_regl(port, S3C2410_UFCON, ufcon);
1246 enable_rx_pio(ourport);
1248 uart_port_unlock_irqrestore(port, flags);
1250 /* Enable Rx Interrupt */
1251 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1256 static int apple_s5l_serial_startup(struct uart_port *port)
1258 struct s3c24xx_uart_port *ourport = to_ourport(port);
1259 unsigned long flags;
1263 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1265 ret = request_irq(port->irq, apple_serial_handle_irq, 0,
1266 s3c24xx_serial_portname(port), ourport);
1268 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1272 /* For compatibility with s3c24xx Soc's */
1273 ourport->rx_enabled = 1;
1274 ourport->tx_enabled = 0;
1276 uart_port_lock_irqsave(port, &flags);
1278 ufcon = rd_regl(port, S3C2410_UFCON);
1279 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1280 if (!uart_console(port))
1281 ufcon |= S3C2410_UFCON_RESETTX;
1282 wr_regl(port, S3C2410_UFCON, ufcon);
1284 enable_rx_pio(ourport);
1286 uart_port_unlock_irqrestore(port, flags);
1288 /* Enable Rx Interrupt */
1289 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
1290 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
1295 /* power power management control */
1297 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1300 struct s3c24xx_uart_port *ourport = to_ourport(port);
1301 int timeout = 10000;
1303 ourport->pm_level = level;
1307 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1310 if (!IS_ERR(ourport->baudclk))
1311 clk_disable_unprepare(ourport->baudclk);
1313 clk_disable_unprepare(ourport->clk);
1317 clk_prepare_enable(ourport->clk);
1319 if (!IS_ERR(ourport->baudclk))
1320 clk_prepare_enable(ourport->baudclk);
1323 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1327 /* baud rate calculation
1329 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1330 * of different sources, including the peripheral clock ("pclk") and an
1331 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1332 * with a programmable extra divisor.
1334 * The following code goes through the clock sources, and calculates the
1335 * baud clocks (and the resultant actual baud rates) and then tries to
1336 * pick the closest one and select that.
1340 #define MAX_CLK_NAME_LENGTH 15
1342 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1344 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1347 if (info->num_clks == 1)
1350 ucon = rd_regl(port, S3C2410_UCON);
1351 ucon &= info->clksel_mask;
1352 return ucon >> info->clksel_shift;
1355 static void s3c24xx_serial_setsource(struct uart_port *port,
1356 unsigned int clk_sel)
1358 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1361 if (info->num_clks == 1)
1364 ucon = rd_regl(port, S3C2410_UCON);
1365 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1368 ucon &= ~info->clksel_mask;
1369 ucon |= clk_sel << info->clksel_shift;
1370 wr_regl(port, S3C2410_UCON, ucon);
1373 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1374 unsigned int req_baud, struct clk **best_clk,
1375 unsigned int *clk_num)
1377 const struct s3c24xx_uart_info *info = ourport->info;
1380 unsigned int cnt, baud, quot, best_quot = 0;
1381 char clkname[MAX_CLK_NAME_LENGTH];
1382 int calc_deviation, deviation = (1 << 30) - 1;
1384 for (cnt = 0; cnt < info->num_clks; cnt++) {
1385 /* Keep selected clock if provided */
1386 if (ourport->cfg->clk_sel &&
1387 !(ourport->cfg->clk_sel & (1 << cnt)))
1390 sprintf(clkname, "clk_uart_baud%d", cnt);
1391 clk = clk_get(ourport->port.dev, clkname);
1395 rate = clk_get_rate(clk);
1397 dev_err(ourport->port.dev,
1398 "Failed to get clock rate for %s.\n", clkname);
1403 if (ourport->info->has_divslot) {
1404 unsigned long div = rate / req_baud;
1406 /* The UDIVSLOT register on the newer UARTs allows us to
1407 * get a divisor adjustment of 1/16th on the baud clock.
1409 * We don't keep the UDIVSLOT value (the 16ths we
1410 * calculated by not multiplying the baud by 16) as it
1411 * is easy enough to recalculate.
1417 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1418 baud = rate / (quot * 16);
1422 calc_deviation = abs(req_baud - baud);
1424 if (calc_deviation < deviation) {
1426 * If we find a better clk, release the previous one, if
1429 if (!IS_ERR(*best_clk))
1434 deviation = calc_deviation;
1445 * This table takes the fractional value of the baud divisor and gives
1446 * the recommended setting for the UDIVSLOT register.
1448 static const u16 udivslot_table[16] = {
1467 static void s3c24xx_serial_set_termios(struct uart_port *port,
1468 struct ktermios *termios,
1469 const struct ktermios *old)
1471 const struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1472 struct s3c24xx_uart_port *ourport = to_ourport(port);
1473 struct clk *clk = ERR_PTR(-EINVAL);
1474 unsigned long flags;
1475 unsigned int baud, quot, clk_sel = 0;
1478 unsigned int udivslot = 0;
1481 * We don't support modem control lines.
1483 termios->c_cflag &= ~(HUPCL | CMSPAR);
1484 termios->c_cflag |= CLOCAL;
1487 * Ask the core to calculate the divisor for us.
1490 baud = uart_get_baud_rate(port, termios, old, 0, 3000000);
1491 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1492 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1493 quot = port->custom_divisor;
1497 /* check to see if we need to change clock source */
1499 if (ourport->baudclk != clk) {
1500 clk_prepare_enable(clk);
1502 s3c24xx_serial_setsource(port, clk_sel);
1504 if (!IS_ERR(ourport->baudclk)) {
1505 clk_disable_unprepare(ourport->baudclk);
1506 ourport->baudclk = ERR_PTR(-EINVAL);
1509 ourport->baudclk = clk;
1510 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1513 if (ourport->info->has_divslot) {
1514 unsigned int div = ourport->baudclk_rate / baud;
1516 if (cfg->has_fracval) {
1517 udivslot = (div & 15);
1518 dev_dbg(port->dev, "fracval = %04x\n", udivslot);
1520 udivslot = udivslot_table[div & 15];
1521 dev_dbg(port->dev, "udivslot = %04x (div %d)\n",
1522 udivslot, div & 15);
1526 switch (termios->c_cflag & CSIZE) {
1528 dev_dbg(port->dev, "config: 5bits/char\n");
1529 ulcon = S3C2410_LCON_CS5;
1532 dev_dbg(port->dev, "config: 6bits/char\n");
1533 ulcon = S3C2410_LCON_CS6;
1536 dev_dbg(port->dev, "config: 7bits/char\n");
1537 ulcon = S3C2410_LCON_CS7;
1541 dev_dbg(port->dev, "config: 8bits/char\n");
1542 ulcon = S3C2410_LCON_CS8;
1546 /* preserve original lcon IR settings */
1547 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1549 if (termios->c_cflag & CSTOPB)
1550 ulcon |= S3C2410_LCON_STOPB;
1552 if (termios->c_cflag & PARENB) {
1553 if (termios->c_cflag & PARODD)
1554 ulcon |= S3C2410_LCON_PODD;
1556 ulcon |= S3C2410_LCON_PEVEN;
1558 ulcon |= S3C2410_LCON_PNONE;
1561 uart_port_lock_irqsave(port, &flags);
1564 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1565 ulcon, quot, udivslot);
1567 wr_regl(port, S3C2410_ULCON, ulcon);
1568 wr_regl(port, S3C2410_UBRDIV, quot);
1570 port->status &= ~UPSTAT_AUTOCTS;
1572 umcon = rd_regl(port, S3C2410_UMCON);
1573 if (termios->c_cflag & CRTSCTS) {
1574 umcon |= S3C2410_UMCOM_AFC;
1575 /* Disable RTS when RX FIFO contains 63 bytes */
1576 umcon &= ~S3C2412_UMCON_AFC_8;
1577 port->status = UPSTAT_AUTOCTS;
1579 umcon &= ~S3C2410_UMCOM_AFC;
1581 wr_regl(port, S3C2410_UMCON, umcon);
1583 if (ourport->info->has_divslot)
1584 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1587 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1588 rd_regl(port, S3C2410_ULCON),
1589 rd_regl(port, S3C2410_UCON),
1590 rd_regl(port, S3C2410_UFCON));
1593 * Update the per-port timeout.
1595 uart_update_timeout(port, termios->c_cflag, baud);
1598 * Which character status flags are we interested in?
1600 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1601 if (termios->c_iflag & INPCK)
1602 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1603 S3C2410_UERSTAT_PARITY;
1605 * Which character status flags should we ignore?
1607 port->ignore_status_mask = 0;
1608 if (termios->c_iflag & IGNPAR)
1609 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1610 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1611 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1614 * Ignore all characters if CREAD is not set.
1616 if ((termios->c_cflag & CREAD) == 0)
1617 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1619 uart_port_unlock_irqrestore(port, flags);
1622 static const char *s3c24xx_serial_type(struct uart_port *port)
1624 const struct s3c24xx_uart_port *ourport = to_ourport(port);
1626 switch (ourport->info->type) {
1628 return "S3C6400/10";
1629 case TYPE_APPLE_S5L:
1636 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1638 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1640 if (flags & UART_CONFIG_TYPE)
1641 port->type = info->port_type;
1645 * verify the new serial_struct (for TIOCSSERIAL).
1648 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1650 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1652 if (ser->type != PORT_UNKNOWN && ser->type != info->port_type)
1658 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1660 static struct console s3c24xx_serial_console;
1662 static void __init s3c24xx_serial_register_console(void)
1664 register_console(&s3c24xx_serial_console);
1667 static void s3c24xx_serial_unregister_console(void)
1669 if (console_is_registered(&s3c24xx_serial_console))
1670 unregister_console(&s3c24xx_serial_console);
1673 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1675 static inline void s3c24xx_serial_register_console(void) { }
1676 static inline void s3c24xx_serial_unregister_console(void) { }
1677 #define S3C24XX_SERIAL_CONSOLE NULL
1680 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1681 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1682 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1686 static const struct uart_ops s3c64xx_serial_ops = {
1687 .pm = s3c24xx_serial_pm,
1688 .tx_empty = s3c24xx_serial_tx_empty,
1689 .get_mctrl = s3c24xx_serial_get_mctrl,
1690 .set_mctrl = s3c24xx_serial_set_mctrl,
1691 .stop_tx = s3c24xx_serial_stop_tx,
1692 .start_tx = s3c24xx_serial_start_tx,
1693 .stop_rx = s3c24xx_serial_stop_rx,
1694 .break_ctl = s3c24xx_serial_break_ctl,
1695 .startup = s3c64xx_serial_startup,
1696 .shutdown = s3c64xx_serial_shutdown,
1697 .set_termios = s3c24xx_serial_set_termios,
1698 .type = s3c24xx_serial_type,
1699 .config_port = s3c24xx_serial_config_port,
1700 .verify_port = s3c24xx_serial_verify_port,
1701 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1702 .poll_get_char = s3c24xx_serial_get_poll_char,
1703 .poll_put_char = s3c24xx_serial_put_poll_char,
1707 static const struct uart_ops apple_s5l_serial_ops = {
1708 .pm = s3c24xx_serial_pm,
1709 .tx_empty = s3c24xx_serial_tx_empty,
1710 .get_mctrl = s3c24xx_serial_get_mctrl,
1711 .set_mctrl = s3c24xx_serial_set_mctrl,
1712 .stop_tx = s3c24xx_serial_stop_tx,
1713 .start_tx = s3c24xx_serial_start_tx,
1714 .stop_rx = s3c24xx_serial_stop_rx,
1715 .break_ctl = s3c24xx_serial_break_ctl,
1716 .startup = apple_s5l_serial_startup,
1717 .shutdown = apple_s5l_serial_shutdown,
1718 .set_termios = s3c24xx_serial_set_termios,
1719 .type = s3c24xx_serial_type,
1720 .config_port = s3c24xx_serial_config_port,
1721 .verify_port = s3c24xx_serial_verify_port,
1722 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1723 .poll_get_char = s3c24xx_serial_get_poll_char,
1724 .poll_put_char = s3c24xx_serial_put_poll_char,
1728 static struct uart_driver s3c24xx_uart_drv = {
1729 .owner = THIS_MODULE,
1730 .driver_name = "s3c2410_serial",
1732 .cons = S3C24XX_SERIAL_CONSOLE,
1733 .dev_name = S3C24XX_SERIAL_NAME,
1734 .major = S3C24XX_SERIAL_MAJOR,
1735 .minor = S3C24XX_SERIAL_MINOR,
1738 static struct s3c24xx_uart_port s3c24xx_serial_ports[UART_NR];
1740 static void s3c24xx_serial_init_port_default(int index) {
1741 struct uart_port *port = &s3c24xx_serial_ports[index].port;
1743 spin_lock_init(&port->lock);
1745 port->iotype = UPIO_MEM;
1747 port->fifosize = 16;
1748 port->flags = UPF_BOOT_AUTOCONF;
1752 /* s3c24xx_serial_resetport
1754 * reset the fifos and other the settings.
1757 static void s3c24xx_serial_resetport(struct uart_port *port,
1758 const struct s3c2410_uartcfg *cfg)
1760 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1761 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1763 ucon &= (info->clksel_mask | info->ucon_mask);
1764 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1766 /* reset both fifos */
1767 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1768 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1770 /* some delay is required after fifo reset */
1774 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport)
1776 struct device *dev = ourport->port.dev;
1777 const struct s3c24xx_uart_info *info = ourport->info;
1778 char clk_name[MAX_CLK_NAME_LENGTH];
1779 unsigned int clk_sel;
1784 clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
1785 for (clk_num = 0; clk_num < info->num_clks; clk_num++) {
1786 if (!(clk_sel & (1 << clk_num)))
1789 sprintf(clk_name, "clk_uart_baud%d", clk_num);
1790 clk = clk_get(dev, clk_name);
1794 ret = clk_prepare_enable(clk);
1800 ourport->baudclk = clk;
1801 ourport->baudclk_rate = clk_get_rate(clk);
1802 s3c24xx_serial_setsource(&ourport->port, clk_num);
1810 /* s3c24xx_serial_init_port
1812 * initialise a single serial port from the platform device given
1815 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1816 struct platform_device *platdev)
1818 struct uart_port *port = &ourport->port;
1819 const struct s3c2410_uartcfg *cfg = ourport->cfg;
1820 struct resource *res;
1823 if (platdev == NULL)
1826 if (port->mapbase != 0)
1829 /* setup info for port */
1830 port->dev = &platdev->dev;
1834 if (cfg->uart_flags & UPF_CONS_FLOW) {
1835 dev_dbg(port->dev, "enabling flow control\n");
1836 port->flags |= UPF_CONS_FLOW;
1839 /* sort our the physical and virtual addresses for each UART */
1841 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1843 dev_err(port->dev, "failed to find memory resource for uart\n");
1847 dev_dbg(port->dev, "resource %pR)\n", res);
1849 port->membase = devm_ioremap_resource(port->dev, res);
1850 if (IS_ERR(port->membase)) {
1851 dev_err(port->dev, "failed to remap controller address\n");
1855 port->mapbase = res->start;
1856 ret = platform_get_irq(platdev, 0);
1861 ourport->rx_irq = ret;
1862 ourport->tx_irq = ret + 1;
1866 * DMA is currently supported only on DT platforms, if DMA properties
1869 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1871 ourport->dma = devm_kzalloc(port->dev,
1872 sizeof(*ourport->dma),
1874 if (!ourport->dma) {
1880 ourport->clk = clk_get(&platdev->dev, "uart");
1881 if (IS_ERR(ourport->clk)) {
1882 pr_err("%s: Controller clock not found\n",
1883 dev_name(&platdev->dev));
1884 ret = PTR_ERR(ourport->clk);
1888 ret = clk_prepare_enable(ourport->clk);
1890 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1891 clk_put(ourport->clk);
1895 ret = s3c24xx_serial_enable_baudclk(ourport);
1897 pr_warn("uart: failed to enable baudclk\n");
1899 /* Keep all interrupts masked and cleared */
1900 switch (ourport->info->type) {
1902 wr_regl(port, S3C64XX_UINTM, 0xf);
1903 wr_regl(port, S3C64XX_UINTP, 0xf);
1904 wr_regl(port, S3C64XX_UINTSP, 0xf);
1906 case TYPE_APPLE_S5L: {
1909 ucon = rd_regl(port, S3C2410_UCON);
1910 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
1911 APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
1912 APPLE_S5L_UCON_RXTO_ENA_MSK);
1913 wr_regl(port, S3C2410_UCON, ucon);
1915 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1922 dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1923 &port->mapbase, port->membase, port->irq,
1924 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1926 /* reset the fifos (and setup the uart) */
1927 s3c24xx_serial_resetport(port, cfg);
1936 /* Device driver serial port probe */
1938 static int probe_index;
1940 static inline const struct s3c24xx_serial_drv_data *
1941 s3c24xx_get_driver_data(struct platform_device *pdev)
1943 if (dev_of_node(&pdev->dev))
1944 return of_device_get_match_data(&pdev->dev);
1946 return (struct s3c24xx_serial_drv_data *)
1947 platform_get_device_id(pdev)->driver_data;
1950 static int s3c24xx_serial_probe(struct platform_device *pdev)
1952 struct device_node *np = pdev->dev.of_node;
1953 struct s3c24xx_uart_port *ourport;
1954 int index = probe_index;
1958 ret = of_alias_get_id(np, "serial");
1963 if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
1964 dev_err(&pdev->dev, "serial%d out of range\n", index);
1967 ourport = &s3c24xx_serial_ports[index];
1969 s3c24xx_serial_init_port_default(index);
1971 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1972 if (!ourport->drv_data) {
1973 dev_err(&pdev->dev, "could not find driver data\n");
1977 ourport->baudclk = ERR_PTR(-EINVAL);
1978 ourport->info = &ourport->drv_data->info;
1979 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1980 dev_get_platdata(&pdev->dev) :
1981 &ourport->drv_data->def_cfg;
1983 switch (ourport->info->type) {
1985 ourport->port.ops = &s3c64xx_serial_ops;
1987 case TYPE_APPLE_S5L:
1988 ourport->port.ops = &apple_s5l_serial_ops;
1993 of_property_read_u32(np,
1994 "samsung,uart-fifosize", &ourport->port.fifosize);
1996 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
1999 ourport->port.iotype = UPIO_MEM;
2002 ourport->port.iotype = UPIO_MEM32;
2005 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n",
2012 if (ourport->drv_data->fifosize[index])
2013 ourport->port.fifosize = ourport->drv_data->fifosize[index];
2014 else if (ourport->info->fifosize)
2015 ourport->port.fifosize = ourport->info->fifosize;
2016 ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE);
2019 * DMA transfers must be aligned at least to cache line size,
2020 * so find minimal transfer size suitable for DMA mode
2022 ourport->min_dma_size = max_t(int, ourport->port.fifosize,
2023 dma_get_cache_alignment());
2025 dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport);
2027 ret = s3c24xx_serial_init_port(ourport, pdev);
2031 if (!s3c24xx_uart_drv.state) {
2032 ret = uart_register_driver(&s3c24xx_uart_drv);
2034 pr_err("Failed to register Samsung UART driver\n");
2039 dev_dbg(&pdev->dev, "%s: adding port\n", __func__);
2040 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
2041 platform_set_drvdata(pdev, &ourport->port);
2044 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
2045 * so that a potential re-enablement through the pm-callback overlaps
2046 * and keeps the clock enabled in this case.
2048 clk_disable_unprepare(ourport->clk);
2049 if (!IS_ERR(ourport->baudclk))
2050 clk_disable_unprepare(ourport->baudclk);
2057 static void s3c24xx_serial_remove(struct platform_device *dev)
2059 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
2062 uart_remove_one_port(&s3c24xx_uart_drv, port);
2065 uart_unregister_driver(&s3c24xx_uart_drv);
2068 /* UART power management code */
2069 #ifdef CONFIG_PM_SLEEP
2070 static int s3c24xx_serial_suspend(struct device *dev)
2072 struct uart_port *port = s3c24xx_dev_to_port(dev);
2075 uart_suspend_port(&s3c24xx_uart_drv, port);
2080 static int s3c24xx_serial_resume(struct device *dev)
2082 struct uart_port *port = s3c24xx_dev_to_port(dev);
2083 struct s3c24xx_uart_port *ourport = to_ourport(port);
2086 clk_prepare_enable(ourport->clk);
2087 if (!IS_ERR(ourport->baudclk))
2088 clk_prepare_enable(ourport->baudclk);
2089 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
2090 if (!IS_ERR(ourport->baudclk))
2091 clk_disable_unprepare(ourport->baudclk);
2092 clk_disable_unprepare(ourport->clk);
2094 uart_resume_port(&s3c24xx_uart_drv, port);
2100 static int s3c24xx_serial_resume_noirq(struct device *dev)
2102 struct uart_port *port = s3c24xx_dev_to_port(dev);
2103 struct s3c24xx_uart_port *ourport = to_ourport(port);
2106 /* restore IRQ mask */
2107 switch (ourport->info->type) {
2108 case TYPE_S3C6400: {
2109 unsigned int uintm = 0xf;
2111 if (ourport->tx_enabled)
2112 uintm &= ~S3C64XX_UINTM_TXD_MSK;
2113 if (ourport->rx_enabled)
2114 uintm &= ~S3C64XX_UINTM_RXD_MSK;
2115 clk_prepare_enable(ourport->clk);
2116 if (!IS_ERR(ourport->baudclk))
2117 clk_prepare_enable(ourport->baudclk);
2118 wr_regl(port, S3C64XX_UINTM, uintm);
2119 if (!IS_ERR(ourport->baudclk))
2120 clk_disable_unprepare(ourport->baudclk);
2121 clk_disable_unprepare(ourport->clk);
2124 case TYPE_APPLE_S5L: {
2128 ret = clk_prepare_enable(ourport->clk);
2130 dev_err(dev, "clk_enable clk failed: %d\n", ret);
2133 if (!IS_ERR(ourport->baudclk)) {
2134 ret = clk_prepare_enable(ourport->baudclk);
2136 dev_err(dev, "clk_enable baudclk failed: %d\n", ret);
2137 clk_disable_unprepare(ourport->clk);
2142 ucon = rd_regl(port, S3C2410_UCON);
2144 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2145 APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2146 APPLE_S5L_UCON_RXTO_ENA_MSK);
2148 if (ourport->tx_enabled)
2149 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
2150 if (ourport->rx_enabled)
2151 ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2152 APPLE_S5L_UCON_RXTO_ENA_MSK;
2154 wr_regl(port, S3C2410_UCON, ucon);
2156 if (!IS_ERR(ourport->baudclk))
2157 clk_disable_unprepare(ourport->baudclk);
2158 clk_disable_unprepare(ourport->clk);
2169 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
2170 SET_SYSTEM_SLEEP_PM_OPS(s3c24xx_serial_suspend, s3c24xx_serial_resume)
2171 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, s3c24xx_serial_resume_noirq)
2173 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
2175 #else /* !CONFIG_PM_SLEEP */
2177 #define SERIAL_SAMSUNG_PM_OPS NULL
2178 #endif /* CONFIG_PM_SLEEP */
2182 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2184 static struct uart_port *cons_uart;
2187 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
2189 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2190 unsigned long ufstat, utrstat;
2192 if (ufcon & S3C2410_UFCON_FIFOMODE) {
2193 /* fifo mode - check amount of data in fifo registers... */
2195 ufstat = rd_regl(port, S3C2410_UFSTAT);
2196 return (ufstat & info->tx_fifofull) ? 0 : 1;
2199 /* in non-fifo mode, we go and use the tx buffer empty */
2201 utrstat = rd_regl(port, S3C2410_UTRSTAT);
2202 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2206 s3c24xx_port_configured(unsigned int ucon)
2208 /* consider the serial port configured if the tx/rx mode set */
2209 return (ucon & 0xf) != 0;
2212 #ifdef CONFIG_CONSOLE_POLL
2214 * Console polling routines for writing and reading from the uart while
2215 * in an interrupt or debug context.
2218 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2220 const struct s3c24xx_uart_port *ourport = to_ourport(port);
2221 unsigned int ufstat;
2223 ufstat = rd_regl(port, S3C2410_UFSTAT);
2224 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2225 return NO_POLL_CHAR;
2227 return rd_reg(port, S3C2410_URXH);
2230 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2233 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2234 unsigned int ucon = rd_regl(port, S3C2410_UCON);
2236 /* not possible to xmit on unconfigured port */
2237 if (!s3c24xx_port_configured(ucon))
2240 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2242 wr_reg(port, S3C2410_UTXH, c);
2245 #endif /* CONFIG_CONSOLE_POLL */
2248 s3c24xx_serial_console_putchar(struct uart_port *port, unsigned char ch)
2250 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2252 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2254 wr_reg(port, S3C2410_UTXH, ch);
2258 s3c24xx_serial_console_write(struct console *co, const char *s,
2261 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2262 unsigned long flags;
2265 /* not possible to xmit on unconfigured port */
2266 if (!s3c24xx_port_configured(ucon))
2269 if (cons_uart->sysrq)
2271 else if (oops_in_progress)
2272 locked = uart_port_trylock_irqsave(cons_uart, &flags);
2274 uart_port_lock_irqsave(cons_uart, &flags);
2276 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2279 uart_port_unlock_irqrestore(cons_uart, flags);
2282 /* Shouldn't be __init, as it can be instantiated from other module */
2284 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2285 int *parity, int *bits)
2290 unsigned int ubrdiv;
2292 unsigned int clk_sel;
2293 char clk_name[MAX_CLK_NAME_LENGTH];
2295 ulcon = rd_regl(port, S3C2410_ULCON);
2296 ucon = rd_regl(port, S3C2410_UCON);
2297 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2299 if (s3c24xx_port_configured(ucon)) {
2300 switch (ulcon & S3C2410_LCON_CSMASK) {
2301 case S3C2410_LCON_CS5:
2304 case S3C2410_LCON_CS6:
2307 case S3C2410_LCON_CS7:
2310 case S3C2410_LCON_CS8:
2316 switch (ulcon & S3C2410_LCON_PMASK) {
2317 case S3C2410_LCON_PEVEN:
2321 case S3C2410_LCON_PODD:
2325 case S3C2410_LCON_PNONE:
2330 /* now calculate the baud rate */
2332 clk_sel = s3c24xx_serial_getsource(port);
2333 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2335 clk = clk_get(port->dev, clk_name);
2337 rate = clk_get_rate(clk);
2341 *baud = rate / (16 * (ubrdiv + 1));
2342 dev_dbg(port->dev, "calculated baud %d\n", *baud);
2346 /* Shouldn't be __init, as it can be instantiated from other module */
2348 s3c24xx_serial_console_setup(struct console *co, char *options)
2350 struct uart_port *port;
2356 /* is this a valid port */
2358 if (co->index == -1 || co->index >= UART_NR)
2361 port = &s3c24xx_serial_ports[co->index].port;
2363 /* is the port configured? */
2365 if (port->mapbase == 0x0)
2371 * Check whether an invalid uart number has been specified, and
2372 * if so, search for the first available port that does have
2376 uart_parse_options(options, &baud, &parity, &bits, &flow);
2378 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2380 dev_dbg(port->dev, "baud %d\n", baud);
2382 return uart_set_options(port, co, baud, parity, bits, flow);
2385 static struct console s3c24xx_serial_console = {
2386 .name = S3C24XX_SERIAL_NAME,
2387 .device = uart_console_device,
2388 .flags = CON_PRINTBUFFER,
2390 .write = s3c24xx_serial_console_write,
2391 .setup = s3c24xx_serial_console_setup,
2392 .data = &s3c24xx_uart_drv,
2394 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2396 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2397 static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2399 .name = "Samsung S3C6400 UART",
2400 .type = TYPE_S3C6400,
2401 .port_type = PORT_S3C6400,
2404 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2405 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2406 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2407 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2408 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2409 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2410 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2412 .clksel_mask = S3C6400_UCON_CLKMASK,
2413 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2416 .ucon = S3C2410_UCON_DEFAULT,
2417 .ufcon = S3C2410_UFCON_DEFAULT,
2420 #define S3C6400_SERIAL_DRV_DATA (&s3c6400_serial_drv_data)
2422 #define S3C6400_SERIAL_DRV_DATA NULL
2425 #ifdef CONFIG_CPU_S5PV210
2426 static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2428 .name = "Samsung S5PV210 UART",
2429 .type = TYPE_S3C6400,
2430 .port_type = PORT_S3C6400,
2432 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2433 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2434 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2435 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2436 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2437 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2438 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2440 .clksel_mask = S5PV210_UCON_CLKMASK,
2441 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2444 .ucon = S5PV210_UCON_DEFAULT,
2445 .ufcon = S5PV210_UFCON_DEFAULT,
2447 .fifosize = { 256, 64, 16, 16 },
2449 #define S5PV210_SERIAL_DRV_DATA (&s5pv210_serial_drv_data)
2451 #define S5PV210_SERIAL_DRV_DATA NULL
2454 #if defined(CONFIG_ARCH_EXYNOS)
2455 #define EXYNOS_COMMON_SERIAL_DRV_DATA() \
2457 .name = "Samsung Exynos UART", \
2458 .type = TYPE_S3C6400, \
2459 .port_type = PORT_S3C6400, \
2461 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2462 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2463 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2464 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2465 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2466 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2467 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2470 .clksel_shift = 0, \
2473 .ucon = S5PV210_UCON_DEFAULT, \
2474 .ufcon = S5PV210_UFCON_DEFAULT, \
2478 static const struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2479 EXYNOS_COMMON_SERIAL_DRV_DATA(),
2480 .fifosize = { 256, 64, 16, 16 },
2483 static const struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2484 EXYNOS_COMMON_SERIAL_DRV_DATA(),
2485 .fifosize = { 64, 256, 16, 256 },
2488 static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
2489 EXYNOS_COMMON_SERIAL_DRV_DATA(),
2490 .fifosize = { 256, 64, 64, 64 },
2494 * Common drv_data struct for platforms that specify samsung,uart-fifosize in
2497 static const struct s3c24xx_serial_drv_data exynos_fifoszdt_serial_drv_data = {
2498 EXYNOS_COMMON_SERIAL_DRV_DATA(),
2502 #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data)
2503 #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data)
2504 #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data)
2505 #define EXYNOS_FIFOSZDT_DRV_DATA (&exynos_fifoszdt_serial_drv_data)
2508 #define EXYNOS4210_SERIAL_DRV_DATA NULL
2509 #define EXYNOS5433_SERIAL_DRV_DATA NULL
2510 #define EXYNOS850_SERIAL_DRV_DATA NULL
2511 #define EXYNOS_FIFOSZDT_DRV_DATA NULL
2514 #ifdef CONFIG_ARCH_APPLE
2515 static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = {
2517 .name = "Apple S5L UART",
2518 .type = TYPE_APPLE_S5L,
2519 .port_type = PORT_8250,
2521 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2522 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2523 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2524 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2525 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2526 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2527 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2531 .ucon_mask = APPLE_S5L_UCON_MASK,
2534 .ucon = APPLE_S5L_UCON_DEFAULT,
2535 .ufcon = S3C2410_UFCON_DEFAULT,
2538 #define S5L_SERIAL_DRV_DATA (&s5l_serial_drv_data)
2540 #define S5L_SERIAL_DRV_DATA NULL
2543 #if defined(CONFIG_ARCH_ARTPEC)
2544 static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = {
2546 .name = "Axis ARTPEC-8 UART",
2547 .type = TYPE_S3C6400,
2548 .port_type = PORT_S3C6400,
2551 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2552 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2553 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2554 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2555 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2556 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2557 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2563 .ucon = S5PV210_UCON_DEFAULT,
2564 .ufcon = S5PV210_UFCON_DEFAULT,
2568 #define ARTPEC8_SERIAL_DRV_DATA (&artpec8_serial_drv_data)
2570 #define ARTPEC8_SERIAL_DRV_DATA (NULL)
2573 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2575 .name = "s3c6400-uart",
2576 .driver_data = (kernel_ulong_t)S3C6400_SERIAL_DRV_DATA,
2578 .name = "s5pv210-uart",
2579 .driver_data = (kernel_ulong_t)S5PV210_SERIAL_DRV_DATA,
2581 .name = "exynos4210-uart",
2582 .driver_data = (kernel_ulong_t)EXYNOS4210_SERIAL_DRV_DATA,
2584 .name = "exynos5433-uart",
2585 .driver_data = (kernel_ulong_t)EXYNOS5433_SERIAL_DRV_DATA,
2588 .driver_data = (kernel_ulong_t)S5L_SERIAL_DRV_DATA,
2590 .name = "exynos850-uart",
2591 .driver_data = (kernel_ulong_t)EXYNOS850_SERIAL_DRV_DATA,
2593 .name = "artpec8-uart",
2594 .driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA,
2596 .name = "gs101-uart",
2597 .driver_data = (kernel_ulong_t)EXYNOS_FIFOSZDT_DRV_DATA,
2601 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2604 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2605 { .compatible = "samsung,s3c6400-uart",
2606 .data = S3C6400_SERIAL_DRV_DATA },
2607 { .compatible = "samsung,s5pv210-uart",
2608 .data = S5PV210_SERIAL_DRV_DATA },
2609 { .compatible = "samsung,exynos4210-uart",
2610 .data = EXYNOS4210_SERIAL_DRV_DATA },
2611 { .compatible = "samsung,exynos5433-uart",
2612 .data = EXYNOS5433_SERIAL_DRV_DATA },
2613 { .compatible = "apple,s5l-uart",
2614 .data = S5L_SERIAL_DRV_DATA },
2615 { .compatible = "samsung,exynos850-uart",
2616 .data = EXYNOS850_SERIAL_DRV_DATA },
2617 { .compatible = "axis,artpec8-uart",
2618 .data = ARTPEC8_SERIAL_DRV_DATA },
2619 { .compatible = "google,gs101-uart",
2620 .data = EXYNOS_FIFOSZDT_DRV_DATA },
2623 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2626 static struct platform_driver samsung_serial_driver = {
2627 .probe = s3c24xx_serial_probe,
2628 .remove_new = s3c24xx_serial_remove,
2629 .id_table = s3c24xx_serial_driver_ids,
2631 .name = "samsung-uart",
2632 .pm = SERIAL_SAMSUNG_PM_OPS,
2633 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2637 static int __init samsung_serial_init(void)
2641 s3c24xx_serial_register_console();
2643 ret = platform_driver_register(&samsung_serial_driver);
2645 s3c24xx_serial_unregister_console();
2652 static void __exit samsung_serial_exit(void)
2654 platform_driver_unregister(&samsung_serial_driver);
2655 s3c24xx_serial_unregister_console();
2658 module_init(samsung_serial_init);
2659 module_exit(samsung_serial_exit);
2661 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2666 static void wr_reg_barrier(const struct uart_port *port, u32 reg, u32 val)
2668 switch (port->iotype) {
2670 writeb(val, portaddr(port, reg));
2673 writel(val, portaddr(port, reg));
2678 struct samsung_early_console_data {
2683 static void samsung_early_busyuart(const struct uart_port *port)
2685 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2689 static void samsung_early_busyuart_fifo(const struct uart_port *port)
2691 const struct samsung_early_console_data *data = port->private_data;
2693 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2697 static void samsung_early_putc(struct uart_port *port, unsigned char c)
2699 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2700 samsung_early_busyuart_fifo(port);
2702 samsung_early_busyuart(port);
2704 wr_reg_barrier(port, S3C2410_UTXH, c);
2707 static void samsung_early_write(struct console *con, const char *s,
2710 struct earlycon_device *dev = con->data;
2712 uart_console_write(&dev->port, s, n, samsung_early_putc);
2715 static int samsung_early_read(struct console *con, char *s, unsigned int n)
2717 struct earlycon_device *dev = con->data;
2718 const struct samsung_early_console_data *data = dev->port.private_data;
2719 int ch, ufstat, num_read = 0;
2721 while (num_read < n) {
2722 ufstat = rd_regl(&dev->port, S3C2410_UFSTAT);
2723 if (!(ufstat & data->rxfifo_mask))
2725 ch = rd_reg(&dev->port, S3C2410_URXH);
2726 if (ch == NO_POLL_CHAR)
2735 static int __init samsung_early_console_setup(struct earlycon_device *device,
2738 if (!device->port.membase)
2741 device->con->write = samsung_early_write;
2742 device->con->read = samsung_early_read;
2747 static struct samsung_early_console_data s3c2410_early_console_data = {
2748 .txfull_mask = S3C2410_UFSTAT_TXFULL,
2749 .rxfifo_mask = S3C2410_UFSTAT_RXFULL | S3C2410_UFSTAT_RXMASK,
2753 static struct samsung_early_console_data s3c2440_early_console_data = {
2754 .txfull_mask = S3C2440_UFSTAT_TXFULL,
2755 .rxfifo_mask = S3C2440_UFSTAT_RXFULL | S3C2440_UFSTAT_RXMASK,
2758 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2761 device->port.private_data = &s3c2440_early_console_data;
2762 return samsung_early_console_setup(device, opt);
2765 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2766 s3c2440_early_console_setup);
2768 /* S5PV210, Exynos */
2769 static struct samsung_early_console_data s5pv210_early_console_data = {
2770 .txfull_mask = S5PV210_UFSTAT_TXFULL,
2771 .rxfifo_mask = S5PV210_UFSTAT_RXFULL | S5PV210_UFSTAT_RXMASK,
2774 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2777 device->port.private_data = &s5pv210_early_console_data;
2778 return samsung_early_console_setup(device, opt);
2781 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2782 s5pv210_early_console_setup);
2783 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2784 s5pv210_early_console_setup);
2785 OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart",
2786 s5pv210_early_console_setup);
2789 static int __init apple_s5l_early_console_setup(struct earlycon_device *device,
2792 /* Close enough to S3C2410 for earlycon... */
2793 device->port.private_data = &s3c2410_early_console_data;
2796 /* ... but we need to override the existing fixmap entry as nGnRnE */
2797 __set_fixmap(FIX_EARLYCON_MEM_BASE, device->port.mapbase,
2798 __pgprot(PROT_DEVICE_nGnRnE));
2800 return samsung_early_console_setup(device, opt);
2803 OF_EARLYCON_DECLARE(s5l, "apple,s5l-uart", apple_s5l_early_console_setup);
2806 MODULE_ALIAS("platform:samsung-uart");
2807 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2808 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2809 MODULE_LICENSE("GPL v2");