riscv: Fix Zbb alternative IDs
authorSamuel Holland <samuel@sholland.org>
Sun, 12 Feb 2023 02:15:33 +0000 (20:15 -0600)
committerPalmer Dabbelt <palmer@rivosinc.com>
Wed, 15 Feb 2023 00:10:36 +0000 (16:10 -0800)
commitd5a7fab7859dc88657372a448b78babcf134114e
tree1cc3864525de02f3439db5267a67ed36f904039f
parentbfd6fc5d80145e12d0ffa144c4bad89b8f9ddc5a
riscv: Fix Zbb alternative IDs

Commit 4bf8860760d9 ("riscv: cpufeature: extend
riscv_cpufeature_patch_func to all ISA extensions") switched ISA
extension alternatives to use the RISCV_ISA_EXT_* macros instead of
CPUFEATURE_*. This was mismerged when applied on top of the Zbb series,
so the Zbb alternatives referenced the wrong errata ID values.

Fixes: 9daca9a5b9ac ("Merge patch series "riscv: improve boot time isa extensions handling"")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230212021534.59121-3-samuel@sholland.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/include/asm/errata_list.h
arch/riscv/lib/strcmp.S
arch/riscv/lib/strlen.S
arch/riscv/lib/strncmp.S