clk: renesas: r8a779a0: Add PWM clock

Tested-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Link: https://lore.kernel.org/r/20230502170618.55967-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index fcc8279647a6090b2259ef1c6b0017ac379d85bd..4c2872f45387ff91dc76ac982dfce4019a8c153c 100644 (file)
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -170,6 +170,7 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
        DEF_MOD("msi3",         621,    R8A779A0_CLK_MSO),
        DEF_MOD("msi4",         622,    R8A779A0_CLK_MSO),
        DEF_MOD("msi5",         623,    R8A779A0_CLK_MSO),
+       DEF_MOD("pwm0",         628,    R8A779A0_CLK_S1D8),
        DEF_MOD("rpc-if",       629,    R8A779A0_CLK_RPCD2),
        DEF_MOD("scif0",        702,    R8A779A0_CLK_S1D8),
        DEF_MOD("scif1",        703,    R8A779A0_CLK_S1D8),