x86/apic/uv: Remove the private leaf 0xb parser

The package shift has been already evaluated by the early CPU init.

Put the mindless copy right next to the original leaf 0xb parser.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Tested-by: Sohil Mehta <sohil.mehta@intel.com>
Tested-by: Michael Kelley <mhklinux@outlook.com>
Tested-by: Zhang Rui <rui.zhang@intel.com>
Tested-by: Wang Wendy <wendy.wang@intel.com>
Tested-by: K Prateek Nayak <kprateek.nayak@amd.com>
Link: https://lore.kernel.org/r/20240212153625.637385562@linutronix.de

diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h
index 5d70618ca581beac9777d47fcb576d910762b299..cb6bafd329f1f292eedbc40221ccbd45802f6fdf 100644 (file)
--- a/arch/x86/include/asm/topology.h
+++ b/arch/x86/include/asm/topology.h
@@ -126,6 +126,11 @@ static inline unsigned int topology_get_domain_size(enum x86_topology_domains do
        return x86_topo_system.dom_size[dom];
 }
 
+static inline unsigned int topology_get_domain_shift(enum x86_topology_domains dom)
+{
+       return dom == TOPO_SMT_DOMAIN ? 0 : x86_topo_system.dom_shifts[dom - 1];
+}
+
 extern const struct cpumask *cpu_coregroup_mask(int cpu);
 extern const struct cpumask *cpu_clustergroup_mask(int cpu);
 

diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 51485f2c17b61763beaf2b9400180735535d0caa..3ae696f072bb3b1d3e5ff7fe82ce407e7c246959 100644 (file)
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -241,54 +241,20 @@ static void __init uv_tsc_check_sync(void)
        is_uv(UV3) ? sname.s3.field :           \
        undef)
 
-/* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
-
-#define SMT_LEVEL                      0       /* Leaf 0xb SMT level */
-#define INVALID_TYPE                   0       /* Leaf 0xb sub-leaf types */
-#define SMT_TYPE                       1
-#define CORE_TYPE                      2
-#define LEAFB_SUBTYPE(ecx)             (((ecx) >> 8) & 0xff)
-#define BITS_SHIFT_NEXT_LEVEL(eax)     ((eax) & 0x1f)
-
-static void set_x2apic_bits(void)
-{
-       unsigned int eax, ebx, ecx, edx, sub_index;
-       unsigned int sid_shift;
-
-       cpuid(0, &eax, &ebx, &ecx, &edx);
-       if (eax < 0xb) {
-               pr_info("UV: CPU does not have CPUID.11\n");
-               return;
-       }
-
-       cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
-       if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
-               pr_info("UV: CPUID.11 not implemented\n");
-               return;
-       }
-
-       sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
-       sub_index = 1;
-       do {
-               cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
-               if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
-                       sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
-                       break;
-               }
-               sub_index++;
-       } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
-
-       uv_cpuid.apicid_shift   = 0;
-       uv_cpuid.apicid_mask    = (~(-1 << sid_shift));
-       uv_cpuid.socketid_shift = sid_shift;
-}
-
 static void __init early_get_apic_socketid_shift(void)
 {
+       unsigned int sid_shift = topology_get_domain_shift(TOPO_PKG_DOMAIN);
+
        if (is_uv2_hub() || is_uv3_hub())
                uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
 
-       set_x2apic_bits();
+       if (sid_shift) {
+               uv_cpuid.apicid_shift   = 0;
+               uv_cpuid.apicid_mask    = (~(-1 << sid_shift));
+               uv_cpuid.socketid_shift = sid_shift;
+       } else {
+               pr_info("UV: CPU does not have valid CPUID.11\n");
+       }
 
        pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
        pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);