--- /dev/null
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _nbif_6_3_1_OFFSET_HEADER
+#define _nbif_6_3_1_OFFSET_HEADER
+
+
+// addressBlock: nbif_bif_cfg_dev0_rc_bifcfgdecp
+// base address: 0x0
+#define cfgIRQ_BRIDGE_CNTL 0x003e
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST 0x0048
+#define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID_W 0x004c
+#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP_LIST 0x0050
+#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP 0x0052
+#define cfgBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL 0x0054
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA 0x00aa
+#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 0x00ae
+#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST 0x0110
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 0x0114
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 0x0118
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL 0x011c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS 0x011e
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP 0x0120
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL 0x0124
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS 0x012a
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP 0x012c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL 0x0130
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS 0x0136
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 0x0144
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 0x0148
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST 0x0200
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP 0x0204
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL 0x0208
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP 0x020c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL 0x0210
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP 0x0214
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL 0x0218
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP 0x021c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL 0x0220
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP 0x0224
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL 0x0228
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP 0x022c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL 0x0230
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA 0x0248
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP 0x024c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST 0x0250
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP 0x0254
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR 0x0258
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS 0x025c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL 0x025e
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 0x0274
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS 0x0278
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST 0x02a0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP 0x02a4
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL 0x02a6
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST 0x02d0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP 0x02d4
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL 0x02d6
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST 0x0320
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x0324
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL 0x032e
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST 0x0330
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP 0x0334
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL 0x0338
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS 0x033a
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS 0x033c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS 0x033e
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS 0x0340
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE 0x0346
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID 0x034a
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST 0x0400
+#define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP 0x0404
+#define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS 0x0408
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_16GT 0x0414
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT 0x0418
+#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT 0x041c
+#define cfgBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420
+#define cfgBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424
+#define cfgBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428
+#define cfgBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430
+#define cfgBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431
+#define cfgBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432
+#define cfgBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433
+#define cfgBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434
+#define cfgBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435
+#define cfgBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436
+#define cfgBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437
+#define cfgBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438
+#define cfgBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439
+#define cfgBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a
+#define cfgBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b
+#define cfgBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c
+#define cfgBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d
+#define cfgBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e
+#define cfgBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST 0x0450
+#define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP 0x0454
+#define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS 0x0456
+#define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL 0x0458
+#define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS 0x045a
+#define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL 0x045c
+#define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS 0x045e
+#define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL 0x0460
+#define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS 0x0462
+#define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL 0x0464
+#define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS 0x0466
+#define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL 0x0468
+#define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS 0x046a
+#define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL 0x046c
+#define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS 0x046e
+#define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL 0x0470
+#define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS 0x0472
+#define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL 0x0474
+#define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS 0x0476
+#define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL 0x0478
+#define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS 0x047a
+#define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL 0x047c
+#define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS 0x047e
+#define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL 0x0480
+#define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS 0x0482
+#define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL 0x0484
+#define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS 0x0486
+#define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL 0x0488
+#define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS 0x048a
+#define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL 0x048c
+#define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS 0x048e
+#define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL 0x0490
+#define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS 0x0492
+#define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL 0x0494
+#define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS 0x0496
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP 0x04c4
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP 0x04cc
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP 0x04d4
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP 0x04dc
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP 0x04e4
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP 0x04ec
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_32GT 0x0504
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT 0x0508
+#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT 0x050c
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf0_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA 0x00aa
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 0x00ae
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf1_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF1_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF1_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF1_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF1_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF1_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA 0x00aa
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 0x00ae
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf2_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF2_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF2_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF2_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF2_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF2_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA 0x00aa
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 0x00ae
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf3_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF3_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF3_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF3_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF3_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF3_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA 0x00aa
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 0x00ae
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf4_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF4_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF4_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF4_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF4_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF4_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA 0x00aa
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 0x00ae
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf5_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF5_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF5_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF5_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF5_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF5_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA 0x00aa
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 0x00ae
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf6_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF6_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF6_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF6_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF6_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF6_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA 0x00aa
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 0x00ae
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf7_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF7_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF7_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF7_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF7_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF7_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA 0x00aa
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 0x00ae
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf1_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF1_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF1_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF1_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF1_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF1_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF1_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF1_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF1_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF1_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF1_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF1_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF1_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF1_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF1_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF1_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF1_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF1_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST 0x0048
+#define cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID_W 0x004c
+#define cfgBIF_CFG_DEV0_EPF1_PMI_CAP_LIST 0x0050
+#define cfgBIF_CFG_DEV0_EPF1_PMI_CAP 0x0052
+#define cfgBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL 0x0054
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF1_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF1_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF1_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF1_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF1_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF1_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF1_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA 0x00aa
+#define cfgBIF_CFG_DEV0_EPF1_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 0x00ae
+#define cfgBIF_CFG_DEV0_EPF1_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF1_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF1_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF1_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF1_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1 0x0144
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2 0x0148
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST 0x0200
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP 0x0204
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL 0x0208
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP 0x020c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL 0x0210
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP 0x0214
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL 0x0218
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP 0x021c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL 0x0220
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP 0x0224
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL 0x0228
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP 0x022c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL 0x0230
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT 0x0244
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA 0x0248
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP 0x024c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST 0x0250
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP 0x0254
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR 0x0258
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS 0x025c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL 0x025e
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST 0x0270
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3 0x0274
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS 0x0278
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST 0x02a0
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP 0x02a4
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL 0x02a6
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST 0x02d0
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP 0x02d4
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL 0x02d6
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST 0x0320
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LTR_CAP 0x0324
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL 0x032e
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST 0x0330
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP 0x0334
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL 0x0338
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS 0x033a
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS 0x033c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS 0x033e
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS 0x0340
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK 0x0342
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE 0x0346
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID 0x034a
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP 0x04c4
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP 0x04cc
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP 0x04d4
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP 0x04dc
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP 0x04e4
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP 0x04ec
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0
+
+
+// addressBlock: nbif_bif_bx_pf_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_PF0_MM_INDEX 0x0000
+#define regBIF_BX_PF0_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_PF0_MM_DATA 0x0001
+#define regBIF_BX_PF0_MM_DATA_BASE_IDX 0
+#define regBIF_BX_PF0_MM_INDEX_HI 0x0006
+#define regBIF_BX_PF0_MM_INDEX_HI_BASE_IDX 0
+#define regBIF_BX_PF0_RSMU_INDEX 0x0000
+#define regBIF_BX_PF0_RSMU_INDEX_BASE_IDX 1
+#define regBIF_BX_PF0_RSMU_DATA 0x0001
+#define regBIF_BX_PF0_RSMU_DATA_BASE_IDX 1
+#define regBIF_BX_PF0_RSMU_INDEX_HI 0x0002
+#define regBIF_BX_PF0_RSMU_INDEX_HI_BASE_IDX 1
+
+
+// addressBlock: nbif_bif_bx_SYSDEC
+// base address: 0x0
+#define regBIF_BX0_PCIE_INDEX 0x000c
+#define regBIF_BX0_PCIE_INDEX_BASE_IDX 0
+#define regBIF_BX0_PCIE_DATA 0x000d
+#define regBIF_BX0_PCIE_DATA_BASE_IDX 0
+#define regBIF_BX0_PCIE_INDEX2 0x000e
+#define regBIF_BX0_PCIE_INDEX2_BASE_IDX 0
+#define regBIF_BX0_PCIE_DATA2 0x000f
+#define regBIF_BX0_PCIE_DATA2_BASE_IDX 0
+#define regBIF_BX0_PCIE_INDEX_HI 0x0010
+#define regBIF_BX0_PCIE_INDEX_HI_BASE_IDX 0
+#define regBIF_BX0_PCIE_INDEX2_HI 0x0011
+#define regBIF_BX0_PCIE_INDEX2_HI_BASE_IDX 0
+#define regBIF_BX0_SBIOS_SCRATCH_0 0x0034
+#define regBIF_BX0_SBIOS_SCRATCH_0_BASE_IDX 1
+#define regBIF_BX0_SBIOS_SCRATCH_1 0x0035
+#define regBIF_BX0_SBIOS_SCRATCH_1_BASE_IDX 1
+#define regBIF_BX0_SBIOS_SCRATCH_2 0x0036
+#define regBIF_BX0_SBIOS_SCRATCH_2_BASE_IDX 1
+#define regBIF_BX0_SBIOS_SCRATCH_3 0x0037
+#define regBIF_BX0_SBIOS_SCRATCH_3_BASE_IDX 1
+#define regBIF_BX0_BIOS_SCRATCH_0 0x0038
+#define regBIF_BX0_BIOS_SCRATCH_0_BASE_IDX 1
+#define regBIF_BX0_BIOS_SCRATCH_1 0x0039
+#define regBIF_BX0_BIOS_SCRATCH_1_BASE_IDX 1
+#define regBIF_BX0_BIOS_SCRATCH_2 0x003a
+#define regBIF_BX0_BIOS_SCRATCH_2_BASE_IDX 1
+#define regBIF_BX0_BIOS_SCRATCH_3 0x003b
+#define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX 1
+#define regBIF_BX0_BIOS_SCRATCH_4 0x003c
+#define regBIF_BX0_BIOS_SCRATCH_4_BASE_IDX 1
+#define regBIF_BX0_BIOS_SCRATCH_5 0x003d
+#define regBIF_BX0_BIOS_SCRATCH_5_BASE_IDX 1
+#define regBIF_BX0_BIOS_SCRATCH_6 0x003e
+#define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX 1
+#define regBIF_BX0_BIOS_SCRATCH_7 0x003f
+#define regBIF_BX0_BIOS_SCRATCH_7_BASE_IDX 1
+#define regBIF_BX0_BIOS_SCRATCH_8 0x0040
+#define regBIF_BX0_BIOS_SCRATCH_8_BASE_IDX 1
+#define regBIF_BX0_BIOS_SCRATCH_9 0x0041
+#define regBIF_BX0_BIOS_SCRATCH_9_BASE_IDX 1
+#define regBIF_BX0_BIOS_SCRATCH_10 0x0042
+#define regBIF_BX0_BIOS_SCRATCH_10_BASE_IDX 1
+#define regBIF_BX0_BIOS_SCRATCH_11 0x0043
+#define regBIF_BX0_BIOS_SCRATCH_11_BASE_IDX 1
+#define regBIF_BX0_BIOS_SCRATCH_12 0x0044
+#define regBIF_BX0_BIOS_SCRATCH_12_BASE_IDX 1
+#define regBIF_BX0_BIOS_SCRATCH_13 0x0045
+#define regBIF_BX0_BIOS_SCRATCH_13_BASE_IDX 1
+#define regBIF_BX0_BIOS_SCRATCH_14 0x0046
+#define regBIF_BX0_BIOS_SCRATCH_14_BASE_IDX 1
+#define regBIF_BX0_BIOS_SCRATCH_15 0x0047
+#define regBIF_BX0_BIOS_SCRATCH_15_BASE_IDX 1
+#define regBIF_BX0_BIF_RLC_INTR_CNTL 0x004c
+#define regBIF_BX0_BIF_RLC_INTR_CNTL_BASE_IDX 1
+#define regBIF_BX0_BIF_VCE_INTR_CNTL 0x004d
+#define regBIF_BX0_BIF_VCE_INTR_CNTL_BASE_IDX 1
+#define regBIF_BX0_BIF_UVD_INTR_CNTL 0x004e
+#define regBIF_BX0_BIF_UVD_INTR_CNTL_BASE_IDX 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0 0x006c
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 0x006d
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1 0x006e
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 0x006f
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2 0x0070
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 0x0071
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3 0x0072
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 0x0073
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4 0x0074
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 0x0075
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5 0x0076
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 0x0077
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6 0x0078
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 0x0079
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7 0x007a
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 0x007b
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_CNTL 0x007c
+#define regBIF_BX0_GFX_MMIOREG_CAM_CNTL_BASE_IDX 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL 0x007d
+#define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL 0x007e
+#define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f
+#define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1
+#define regBIF_BX0_DRIVER_SCRATCH_0 0x0080
+#define regBIF_BX0_DRIVER_SCRATCH_0_BASE_IDX 1
+#define regBIF_BX0_DRIVER_SCRATCH_1 0x0081
+#define regBIF_BX0_DRIVER_SCRATCH_1_BASE_IDX 1
+#define regBIF_BX0_DRIVER_SCRATCH_2 0x0082
+#define regBIF_BX0_DRIVER_SCRATCH_2_BASE_IDX 1
+#define regBIF_BX0_DRIVER_SCRATCH_3 0x0083
+#define regBIF_BX0_DRIVER_SCRATCH_3_BASE_IDX 1
+#define regBIF_BX0_DRIVER_SCRATCH_4 0x0084
+#define regBIF_BX0_DRIVER_SCRATCH_4_BASE_IDX 1
+#define regBIF_BX0_DRIVER_SCRATCH_5 0x0085
+#define regBIF_BX0_DRIVER_SCRATCH_5_BASE_IDX 1
+#define regBIF_BX0_DRIVER_SCRATCH_6 0x0086
+#define regBIF_BX0_DRIVER_SCRATCH_6_BASE_IDX 1
+#define regBIF_BX0_DRIVER_SCRATCH_7 0x0087
+#define regBIF_BX0_DRIVER_SCRATCH_7_BASE_IDX 1
+#define regBIF_BX0_DRIVER_SCRATCH_8 0x0088
+#define regBIF_BX0_DRIVER_SCRATCH_8_BASE_IDX 1
+#define regBIF_BX0_DRIVER_SCRATCH_9 0x0089
+#define regBIF_BX0_DRIVER_SCRATCH_9_BASE_IDX 1
+#define regBIF_BX0_DRIVER_SCRATCH_10 0x008a
+#define regBIF_BX0_DRIVER_SCRATCH_10_BASE_IDX 1
+#define regBIF_BX0_DRIVER_SCRATCH_11 0x008b
+#define regBIF_BX0_DRIVER_SCRATCH_11_BASE_IDX 1
+#define regBIF_BX0_DRIVER_SCRATCH_12 0x008c
+#define regBIF_BX0_DRIVER_SCRATCH_12_BASE_IDX 1
+#define regBIF_BX0_DRIVER_SCRATCH_13 0x008d
+#define regBIF_BX0_DRIVER_SCRATCH_13_BASE_IDX 1
+#define regBIF_BX0_DRIVER_SCRATCH_14 0x008e
+#define regBIF_BX0_DRIVER_SCRATCH_14_BASE_IDX 1
+#define regBIF_BX0_DRIVER_SCRATCH_15 0x008f
+#define regBIF_BX0_DRIVER_SCRATCH_15_BASE_IDX 1
+#define regBIF_BX0_FW_SCRATCH_0 0x0090
+#define regBIF_BX0_FW_SCRATCH_0_BASE_IDX 1
+#define regBIF_BX0_FW_SCRATCH_1 0x0091
+#define regBIF_BX0_FW_SCRATCH_1_BASE_IDX 1
+#define regBIF_BX0_FW_SCRATCH_2 0x0092
+#define regBIF_BX0_FW_SCRATCH_2_BASE_IDX 1
+#define regBIF_BX0_FW_SCRATCH_3 0x0093
+#define regBIF_BX0_FW_SCRATCH_3_BASE_IDX 1
+#define regBIF_BX0_FW_SCRATCH_4 0x0094
+#define regBIF_BX0_FW_SCRATCH_4_BASE_IDX 1
+#define regBIF_BX0_FW_SCRATCH_5 0x0095
+#define regBIF_BX0_FW_SCRATCH_5_BASE_IDX 1
+#define regBIF_BX0_FW_SCRATCH_6 0x0096
+#define regBIF_BX0_FW_SCRATCH_6_BASE_IDX 1
+#define regBIF_BX0_FW_SCRATCH_7 0x0097
+#define regBIF_BX0_FW_SCRATCH_7_BASE_IDX 1
+#define regBIF_BX0_FW_SCRATCH_8 0x0098
+#define regBIF_BX0_FW_SCRATCH_8_BASE_IDX 1
+#define regBIF_BX0_FW_SCRATCH_9 0x0099
+#define regBIF_BX0_FW_SCRATCH_9_BASE_IDX 1
+#define regBIF_BX0_FW_SCRATCH_10 0x009a
+#define regBIF_BX0_FW_SCRATCH_10_BASE_IDX 1
+#define regBIF_BX0_FW_SCRATCH_11 0x009b
+#define regBIF_BX0_FW_SCRATCH_11_BASE_IDX 1
+#define regBIF_BX0_FW_SCRATCH_12 0x009c
+#define regBIF_BX0_FW_SCRATCH_12_BASE_IDX 1
+#define regBIF_BX0_FW_SCRATCH_13 0x009d
+#define regBIF_BX0_FW_SCRATCH_13_BASE_IDX 1
+#define regBIF_BX0_FW_SCRATCH_14 0x009e
+#define regBIF_BX0_FW_SCRATCH_14_BASE_IDX 1
+#define regBIF_BX0_FW_SCRATCH_15 0x009f
+#define regBIF_BX0_FW_SCRATCH_15_BASE_IDX 1
+#define regBIF_BX0_SBIOS_SCRATCH_4 0x00a0
+#define regBIF_BX0_SBIOS_SCRATCH_4_BASE_IDX 1
+#define regBIF_BX0_SBIOS_SCRATCH_5 0x00a1
+#define regBIF_BX0_SBIOS_SCRATCH_5_BASE_IDX 1
+#define regBIF_BX0_SBIOS_SCRATCH_6 0x00a2
+#define regBIF_BX0_SBIOS_SCRATCH_6_BASE_IDX 1
+#define regBIF_BX0_SBIOS_SCRATCH_7 0x00a3
+#define regBIF_BX0_SBIOS_SCRATCH_7_BASE_IDX 1
+#define regBIF_BX0_SBIOS_SCRATCH_8 0x00a4
+#define regBIF_BX0_SBIOS_SCRATCH_8_BASE_IDX 1
+#define regBIF_BX0_SBIOS_SCRATCH_9 0x00a5
+#define regBIF_BX0_SBIOS_SCRATCH_9_BASE_IDX 1
+#define regBIF_BX0_SBIOS_SCRATCH_10 0x00a6
+#define regBIF_BX0_SBIOS_SCRATCH_10_BASE_IDX 1
+#define regBIF_BX0_SBIOS_SCRATCH_11 0x00a7
+#define regBIF_BX0_SBIOS_SCRATCH_11_BASE_IDX 1
+#define regBIF_BX0_SBIOS_SCRATCH_12 0x00a8
+#define regBIF_BX0_SBIOS_SCRATCH_12_BASE_IDX 1
+#define regBIF_BX0_SBIOS_SCRATCH_13 0x00a9
+#define regBIF_BX0_SBIOS_SCRATCH_13_BASE_IDX 1
+#define regBIF_BX0_SBIOS_SCRATCH_14 0x00aa
+#define regBIF_BX0_SBIOS_SCRATCH_14_BASE_IDX 1
+#define regBIF_BX0_SBIOS_SCRATCH_15 0x00ab
+#define regBIF_BX0_SBIOS_SCRATCH_15_BASE_IDX 1
+
+
+// addressBlock: nbif_rcc_dwn_dev0_BIFDEC1
+// base address: 0x0
+#define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED 0x0060
+#define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED_BASE_IDX 2
+#define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH 0x0061
+#define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_BASE_IDX 2
+#define regRCC_DWN_DEV0_0_DN_PCIE_CNTL 0x0063
+#define regRCC_DWN_DEV0_0_DN_PCIE_CNTL_BASE_IDX 2
+#define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL 0x0064
+#define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_BASE_IDX 2
+#define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 0x0065
+#define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_BASE_IDX 2
+#define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL 0x0066
+#define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_BASE_IDX 2
+#define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL 0x0067
+#define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_BASE_IDX 2
+#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 0x0068
+#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_BASE_IDX 2
+#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC 0x0069
+#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_BASE_IDX 2
+#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 0x006a
+#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dwnp_dev0_BIFDEC1
+// base address: 0x0
+#define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL 0x006c
+#define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_BASE_IDX 2
+#define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL 0x006d
+#define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL_BASE_IDX 2
+#define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL 0x006e
+#define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_BASE_IDX 2
+#define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2 0x006f
+#define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_BASE_IDX 2
+#define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC 0x0070
+#define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_BASE_IDX 2
+#define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP 0x0071
+#define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_ep_dev0_BIFDEC1
+// base address: 0x0
+#define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH 0x0041
+#define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH_BASE_IDX 2
+#define regRCC_EP_DEV0_0_EP_PCIE_CNTL 0x0043
+#define regRCC_EP_DEV0_0_EP_PCIE_CNTL_BASE_IDX 2
+#define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL 0x0044
+#define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_BASE_IDX 2
+#define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS 0x0045
+#define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_BASE_IDX 2
+#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 0x0046
+#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_BASE_IDX 2
+#define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL 0x0047
+#define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_BASE_IDX 2
+#define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL 0x0048
+#define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_BASE_IDX 2
+#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x004a
+#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_BASE_IDX 2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x004b
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x004b
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x004b
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x004b
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x004c
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x004c
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x004c
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x004c
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2
+#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC 0x004d
+#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_BASE_IDX 2
+#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 0x004e
+#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_BASE_IDX 2
+#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP 0x0050
+#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_BASE_IDX 2
+#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0051
+#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2
+#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL 0x0051
+#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_BASE_IDX 2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0051
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0052
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0052
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0052
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0052
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0053
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0053
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0053
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2
+#define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL 0x0053
+#define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_BASE_IDX 2
+#define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED 0x0054
+#define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED_BASE_IDX 2
+#define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL 0x0056
+#define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_BASE_IDX 2
+#define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID 0x0057
+#define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 2
+#define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL 0x0058
+#define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_BASE_IDX 2
+#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL 0x0059
+#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_BASE_IDX 2
+#define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL 0x005a
+#define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_BIFDEC1
+// base address: 0x0
+#define regBIF_BX0_CC_BIF_BX_STRAP0 0x00e2
+#define regBIF_BX0_CC_BIF_BX_STRAP0_BASE_IDX 2
+#define regBIF_BX0_CC_BIF_BX_PINSTRAP0 0x00e4
+#define regBIF_BX0_CC_BIF_BX_PINSTRAP0_BASE_IDX 2
+#define regBIF_BX0_BIF_MM_INDACCESS_CNTL 0x00e6
+#define regBIF_BX0_BIF_MM_INDACCESS_CNTL_BASE_IDX 2
+#define regBIF_BX0_BUS_CNTL 0x00e7
+#define regBIF_BX0_BUS_CNTL_BASE_IDX 2
+#define regBIF_BX0_BIF_SCRATCH0 0x00e8
+#define regBIF_BX0_BIF_SCRATCH0_BASE_IDX 2
+#define regBIF_BX0_BIF_SCRATCH1 0x00e9
+#define regBIF_BX0_BIF_SCRATCH1_BASE_IDX 2
+#define regBIF_BX0_BX_RESET_EN 0x00ed
+#define regBIF_BX0_BX_RESET_EN_BASE_IDX 2
+#define regBIF_BX0_MM_CFGREGS_CNTL 0x00ee
+#define regBIF_BX0_MM_CFGREGS_CNTL_BASE_IDX 2
+#define regBIF_BX0_BX_RESET_CNTL 0x00f0
+#define regBIF_BX0_BX_RESET_CNTL_BASE_IDX 2
+#define regBIF_BX0_INTERRUPT_CNTL 0x00f1
+#define regBIF_BX0_INTERRUPT_CNTL_BASE_IDX 2
+#define regBIF_BX0_INTERRUPT_CNTL2 0x00f2
+#define regBIF_BX0_INTERRUPT_CNTL2_BASE_IDX 2
+#define regBIF_BX0_CLKREQB_PAD_CNTL 0x00f8
+#define regBIF_BX0_CLKREQB_PAD_CNTL_BASE_IDX 2
+#define regBIF_BX0_BIF_FEATURES_CONTROL_MISC 0x00fb
+#define regBIF_BX0_BIF_FEATURES_CONTROL_MISC_BASE_IDX 2
+#define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC 0x00fc
+#define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 2
+#define regBIF_BX0_BIF_DOORBELL_CNTL 0x00fd
+#define regBIF_BX0_BIF_DOORBELL_CNTL_BASE_IDX 2
+#define regBIF_BX0_BIF_DOORBELL_INT_CNTL 0x00fe
+#define regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX 2
+#define regBIF_BX0_BIF_FB_EN 0x0100
+#define regBIF_BX0_BIF_FB_EN_BASE_IDX 2
+#define regBIF_BX0_BIF_INTR_CNTL 0x0101
+#define regBIF_BX0_BIF_INTR_CNTL_BASE_IDX 2
+#define regBIF_BX0_BIF_MST_TRANS_PENDING_VF 0x0109
+#define regBIF_BX0_BIF_MST_TRANS_PENDING_VF_BASE_IDX 2
+#define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF 0x010a
+#define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 2
+#define regBIF_BX0_BACO_CNTL 0x010b
+#define regBIF_BX0_BACO_CNTL_BASE_IDX 2
+#define regBIF_BX0_BIF_BACO_EXIT_TIME0 0x010c
+#define regBIF_BX0_BIF_BACO_EXIT_TIME0_BASE_IDX 2
+#define regBIF_BX0_BIF_BACO_EXIT_TIMER1 0x010d
+#define regBIF_BX0_BIF_BACO_EXIT_TIMER1_BASE_IDX 2
+#define regBIF_BX0_BIF_BACO_EXIT_TIMER2 0x010e
+#define regBIF_BX0_BIF_BACO_EXIT_TIMER2_BASE_IDX 2
+#define regBIF_BX0_BIF_BACO_EXIT_TIMER3 0x010f
+#define regBIF_BX0_BIF_BACO_EXIT_TIMER3_BASE_IDX 2
+#define regBIF_BX0_BIF_BACO_EXIT_TIMER4 0x0110
+#define regBIF_BX0_BIF_BACO_EXIT_TIMER4_BASE_IDX 2
+#define regBIF_BX0_MEM_TYPE_CNTL 0x0111
+#define regBIF_BX0_MEM_TYPE_CNTL_BASE_IDX 2
+#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL 0x012d
+#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL 0x012e
+#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX0_BIF_RB_CNTL 0x012f
+#define regBIF_BX0_BIF_RB_CNTL_BASE_IDX 2
+#define regBIF_BX0_BIF_RB_BASE 0x0130
+#define regBIF_BX0_BIF_RB_BASE_BASE_IDX 2
+#define regBIF_BX0_BIF_RB_RPTR 0x0131
+#define regBIF_BX0_BIF_RB_RPTR_BASE_IDX 2
+#define regBIF_BX0_BIF_RB_WPTR 0x0132
+#define regBIF_BX0_BIF_RB_WPTR_BASE_IDX 2
+#define regBIF_BX0_BIF_RB_WPTR_ADDR_HI 0x0133
+#define regBIF_BX0_BIF_RB_WPTR_ADDR_HI_BASE_IDX 2
+#define regBIF_BX0_BIF_RB_WPTR_ADDR_LO 0x0134
+#define regBIF_BX0_BIF_RB_WPTR_ADDR_LO_BASE_IDX 2
+#define regBIF_BX0_MAILBOX_INDEX 0x0135
+#define regBIF_BX0_MAILBOX_INDEX_BASE_IDX 2
+#define regBIF_BX0_BIF_MP1_INTR_CTRL 0x0142
+#define regBIF_BX0_BIF_MP1_INTR_CTRL_BASE_IDX 2
+#define regBIF_BX0_BIF_PERSTB_PAD_CNTL 0x0145
+#define regBIF_BX0_BIF_PERSTB_PAD_CNTL_BASE_IDX 2
+#define regBIF_BX0_BIF_PX_EN_PAD_CNTL 0x0146
+#define regBIF_BX0_BIF_PX_EN_PAD_CNTL_BASE_IDX 2
+#define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL 0x0147
+#define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 2
+#define regBIF_BX0_BIF_CLKREQB_PAD_CNTL 0x0148
+#define regBIF_BX0_BIF_CLKREQB_PAD_CNTL_BASE_IDX 2
+#define regBIF_BX0_BIF_PWRBRK_PAD_CNTL 0x0149
+#define regBIF_BX0_BIF_PWRBRK_PAD_CNTL_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_BIFDEC1
+// base address: 0x0
+#define regRCC_DEV0_0_RCC_ERR_INT_CNTL 0x0086
+#define regRCC_DEV0_0_RCC_ERR_INT_CNTL_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_BACO_CNTL_MISC 0x0087
+#define regRCC_DEV0_0_RCC_BACO_CNTL_MISC_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_RESET_EN 0x0088
+#define regRCC_DEV0_0_RCC_RESET_EN_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_VDM_SUPPORT 0x0089
+#define regRCC_DEV0_0_RCC_VDM_SUPPORT_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 0x008a
+#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 0x008b
+#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_GPUIOV_REGION 0x008c
+#define regRCC_DEV0_0_RCC_GPUIOV_REGION_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN 0x008d
+#define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL 0x008e
+#define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x008f
+#define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE 0x008f
+#define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_PEER_REG_RANGE0 0x00be
+#define regRCC_DEV0_0_RCC_PEER_REG_RANGE0_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_PEER_REG_RANGE1 0x00bf
+#define regRCC_DEV0_0_RCC_PEER_REG_RANGE1_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_BUS_CNTL 0x00c1
+#define regRCC_DEV0_0_RCC_BUS_CNTL_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_CONFIG_CNTL 0x00c2
+#define regRCC_DEV0_0_RCC_CONFIG_CNTL_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_CONFIG_F0_BASE 0x00c6
+#define regRCC_DEV0_0_RCC_CONFIG_F0_BASE_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE 0x00c7
+#define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE 0x00c8
+#define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_XDMA_LO 0x00c9
+#define regRCC_DEV0_0_RCC_XDMA_LO_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_XDMA_HI 0x00ca
+#define regRCC_DEV0_0_RCC_XDMA_HI_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC 0x00cb
+#define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_BUSNUM_CNTL1 0x00cc
+#define regRCC_DEV0_0_RCC_BUSNUM_CNTL1_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_BUSNUM_LIST0 0x00cd
+#define regRCC_DEV0_0_RCC_BUSNUM_LIST0_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_BUSNUM_LIST1 0x00ce
+#define regRCC_DEV0_0_RCC_BUSNUM_LIST1_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_BUSNUM_CNTL2 0x00cf
+#define regRCC_DEV0_0_RCC_BUSNUM_CNTL2_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM 0x00d0
+#define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_HOST_BUSNUM 0x00d1
+#define regRCC_DEV0_0_RCC_HOST_BUSNUM_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI 0x00d2
+#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO 0x00d3
+#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI 0x00d4
+#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO 0x00d5
+#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI 0x00d6
+#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO 0x00d7
+#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI 0x00d8
+#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO 0x00d9
+#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0 0x00da
+#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1 0x00db
+#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL 0x00dd
+#define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_CMN_LINK_CNTL 0x00de
+#define regRCC_DEV0_0_RCC_CMN_LINK_CNTL_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE 0x00df
+#define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL 0x00e0
+#define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_BASE_IDX 2
+#define regRCC_DEV0_0_RCC_MH_ARB_CNTL 0x00e1
+#define regRCC_DEV0_0_RCC_MH_ARB_CNTL_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_rcc_strap_BIFDEC1
+// base address: 0x0
+#define regRCC_STRAP0_RCC_BIF_STRAP0 0x0000
+#define regRCC_STRAP0_RCC_BIF_STRAP0_BASE_IDX 2
+#define regRCC_STRAP0_RCC_BIF_STRAP1 0x0001
+#define regRCC_STRAP0_RCC_BIF_STRAP1_BASE_IDX 2
+#define regRCC_STRAP0_RCC_BIF_STRAP2 0x0005
+#define regRCC_STRAP0_RCC_BIF_STRAP2_BASE_IDX 2
+#define regRCC_STRAP0_RCC_BIF_STRAP3 0x0006
+#define regRCC_STRAP0_RCC_BIF_STRAP3_BASE_IDX 2
+#define regRCC_STRAP0_RCC_BIF_STRAP4 0x0007
+#define regRCC_STRAP0_RCC_BIF_STRAP4_BASE_IDX 2
+#define regRCC_STRAP0_RCC_BIF_STRAP5 0x0008
+#define regRCC_STRAP0_RCC_BIF_STRAP5_BASE_IDX 2
+#define regRCC_STRAP0_RCC_BIF_STRAP6 0x0009
+#define regRCC_STRAP0_RCC_BIF_STRAP6_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0 0x000d
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1 0x000e
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10 0x000f
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11 0x0010
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12 0x0011
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13 0x0012
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14 0x0013
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2 0x0014
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3 0x0015
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4 0x0016
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5 0x0017
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6 0x0018
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7 0x0019
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8 0x001a
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9 0x001b
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0 0x001c
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1 0x001d
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13 0x001e
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14 0x001f
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15 0x0020
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16 0x0021
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17 0x0022
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18 0x0023
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2 0x0024
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3 0x0026
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4 0x0027
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5 0x0028
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8 0x0029
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9 0x002a
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0 0x002b
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2 0x0036
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20 0x0037
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21 0x0038
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3 0x0039
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4 0x003a
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5 0x003b
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6 0x003c
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7 0x003d
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_pf_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_PF0_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
+#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
+#define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_PF0_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_PF0_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_PF0_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_PF0_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_PF0_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_PF0_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_PF0_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_gdc_GDCDEC
+// base address: 0x0
+#define regGDC0_SHUB_REGS_IF_CTL 0x0181
+#define regGDC0_SHUB_REGS_IF_CTL_BASE_IDX 2
+#define regGDC0_A2S_QUEUE_FIFO_ARB_CNTL 0x0182
+#define regGDC0_A2S_QUEUE_FIFO_ARB_CNTL_BASE_IDX 2
+#define regGDC0_NGDC_MGCG_CTRL 0x0187
+#define regGDC0_NGDC_MGCG_CTRL_BASE_IDX 2
+#define regGDC0_S2A_MISC_CNTL 0x0188
+#define regGDC0_S2A_MISC_CNTL_BASE_IDX 2
+#define regGDC0_NGDC_PG_MISC_CTRL 0x0190
+#define regGDC0_NGDC_PG_MISC_CTRL_BASE_IDX 2
+#define regGDC0_NGDC_PGMST_CTRL 0x0191
+#define regGDC0_NGDC_PGMST_CTRL_BASE_IDX 2
+#define regGDC0_NGDC_PGSLV_CTRL 0x0192
+#define regGDC0_NGDC_PGSLV_CTRL_BASE_IDX 2
+#define regGDC0_ATDMA_MISC_CNTL 0x01e1
+#define regGDC0_ATDMA_MISC_CNTL_BASE_IDX 2
+
+
+// addressBlock: nbif_gdc_s2a_GDCS2A_DEC
+// base address: 0x0
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL 0x01cb
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL 0x01cc
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL 0x01cd
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL 0x01ce
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL 0x01cf
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL 0x01d0
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL 0x01d1
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL 0x01d2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL 0x01d3
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL 0x01d4
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL 0x01d5
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL 0x01d6
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL 0x01d7
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL 0x01d8
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL 0x01d9
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL 0x01da
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX 2
+#define regGDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG 0x01db
+#define regGDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX 2
+#define regGDC_S2A0_NBIF_GFX_DOORBELL_STATUS 0x01dc
+#define regGDC_S2A0_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_cfg_dev0_rc_bifcfgdecp
+// base address: 0x10100000
+#define regIRQ_BRIDGE_CNTL 0x000f
+#define regIRQ_BRIDGE_CNTL_BASE_IDX 5
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_bifcfgdecp
+// base address: 0x10140000
+#define regBIF_CFG_DEV0_EPF0_VENDOR_ID 0x10000
+#define regBIF_CFG_DEV0_EPF0_VENDOR_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_DEVICE_ID 0x10000
+#define regBIF_CFG_DEV0_EPF0_DEVICE_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_COMMAND 0x10001
+#define regBIF_CFG_DEV0_EPF0_COMMAND_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_STATUS 0x10001
+#define regBIF_CFG_DEV0_EPF0_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_REVISION_ID 0x10002
+#define regBIF_CFG_DEV0_EPF0_REVISION_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x10002
+#define regBIF_CFG_DEV0_EPF0_PROG_INTERFACE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_SUB_CLASS 0x10002
+#define regBIF_CFG_DEV0_EPF0_SUB_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_BASE_CLASS 0x10002
+#define regBIF_CFG_DEV0_EPF0_BASE_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_CACHE_LINE 0x10003
+#define regBIF_CFG_DEV0_EPF0_CACHE_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LATENCY 0x10003
+#define regBIF_CFG_DEV0_EPF0_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_HEADER 0x10003
+#define regBIF_CFG_DEV0_EPF0_HEADER_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_BIST 0x10003
+#define regBIF_CFG_DEV0_EPF0_BIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_1 0x10004
+#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_2 0x10005
+#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_3 0x10006
+#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_4 0x10007
+#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_4_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_5 0x10008
+#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_5_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_6 0x10009
+#define regBIF_CFG_DEV0_EPF0_BASE_ADDR_6_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR 0x1000a
+#define regBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_ADAPTER_ID 0x1000b
+#define regBIF_CFG_DEV0_EPF0_ADAPTER_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR 0x1000c
+#define regBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_CAP_PTR 0x1000d
+#define regBIF_CFG_DEV0_EPF0_CAP_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_INTERRUPT_LINE 0x1000f
+#define regBIF_CFG_DEV0_EPF0_INTERRUPT_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_INTERRUPT_PIN 0x1000f
+#define regBIF_CFG_DEV0_EPF0_INTERRUPT_PIN_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_MIN_GRANT 0x1000f
+#define regBIF_CFG_DEV0_EPF0_MIN_GRANT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_MAX_LATENCY 0x1000f
+#define regBIF_CFG_DEV0_EPF0_MAX_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST 0x10012
+#define regBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_ADAPTER_ID_W 0x10013
+#define regBIF_CFG_DEV0_EPF0_ADAPTER_ID_W_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PMI_CAP_LIST 0x10014
+#define regBIF_CFG_DEV0_EPF0_PMI_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PMI_CAP 0x10014
+#define regBIF_CFG_DEV0_EPF0_PMI_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL 0x10015
+#define regBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST 0x10019
+#define regBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_CAP 0x10019
+#define regBIF_CFG_DEV0_EPF0_PCIE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_DEVICE_CAP 0x1001a
+#define regBIF_CFG_DEV0_EPF0_DEVICE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_DEVICE_CNTL 0x1001b
+#define regBIF_CFG_DEV0_EPF0_DEVICE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_DEVICE_STATUS 0x1001b
+#define regBIF_CFG_DEV0_EPF0_DEVICE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LINK_CAP 0x1001c
+#define regBIF_CFG_DEV0_EPF0_LINK_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LINK_CNTL 0x1001d
+#define regBIF_CFG_DEV0_EPF0_LINK_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LINK_STATUS 0x1001d
+#define regBIF_CFG_DEV0_EPF0_LINK_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_DEVICE_CAP2 0x10022
+#define regBIF_CFG_DEV0_EPF0_DEVICE_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x10023
+#define regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_DEVICE_STATUS2 0x10023
+#define regBIF_CFG_DEV0_EPF0_DEVICE_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LINK_CAP2 0x10024
+#define regBIF_CFG_DEV0_EPF0_LINK_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LINK_CNTL2 0x10025
+#define regBIF_CFG_DEV0_EPF0_LINK_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LINK_STATUS2 0x10025
+#define regBIF_CFG_DEV0_EPF0_LINK_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_MSI_CAP_LIST 0x10028
+#define regBIF_CFG_DEV0_EPF0_MSI_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL 0x10028
+#define regBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO 0x10029
+#define regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI 0x1002a
+#define regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA 0x1002a
+#define regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA 0x1002a
+#define regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_MSI_MASK 0x1002b
+#define regBIF_CFG_DEV0_EPF0_MSI_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 0x1002b
+#define regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 0x1002b
+#define regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_MSI_MASK_64 0x1002c
+#define regBIF_CFG_DEV0_EPF0_MSI_MASK_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_MSI_PENDING 0x1002c
+#define regBIF_CFG_DEV0_EPF0_MSI_PENDING_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_MSI_PENDING_64 0x1002d
+#define regBIF_CFG_DEV0_EPF0_MSI_PENDING_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST 0x10030
+#define regBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL 0x10030
+#define regBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_MSIX_TABLE 0x10031
+#define regBIF_CFG_DEV0_EPF0_MSIX_TABLE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_MSIX_PBA 0x10032
+#define regBIF_CFG_DEV0_EPF0_MSIX_PBA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040
+#define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR 0x10041
+#define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 0x10042
+#define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 0x10043
+#define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST 0x10044
+#define regBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 0x10045
+#define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 0x10046
+#define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL 0x10047
+#define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS 0x10047
+#define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP 0x10048
+#define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL 0x10049
+#define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS 0x1004a
+#define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP 0x1004b
+#define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL 0x1004c
+#define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS 0x1004d
+#define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x10050
+#define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 0x10051
+#define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 0x10052
+#define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10054
+#define regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS 0x10055
+#define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK 0x10056
+#define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY 0x10057
+#define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS 0x10058
+#define regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK 0x10059
+#define regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL 0x1005a
+#define regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 0x1005b
+#define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 0x1005c
+#define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 0x1005d
+#define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 0x1005e
+#define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 0x10062
+#define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 0x10063
+#define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 0x10064
+#define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 0x10065
+#define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST 0x10080
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP 0x10081
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL 0x10082
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP 0x10083
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL 0x10084
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP 0x10085
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL 0x10086
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP 0x10087
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL 0x10088
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP 0x10089
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL 0x1008a
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP 0x1008b
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL 0x1008c
+#define regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10090
+#define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT 0x10091
+#define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA 0x10092
+#define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP 0x10093
+#define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST 0x10094
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP 0x10095
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR 0x10096
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS 0x10097
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL 0x10097
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10098
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10098
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10098
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10098
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10099
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10099
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10099
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10099
+#define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST 0x1009c
+#define regBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 0x1009d
+#define regBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS 0x1009e
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL 0x1009f
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL 0x1009f
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL 0x100a0
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL 0x100a0
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL 0x100a1
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL 0x100a1
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL 0x100a2
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL 0x100a2
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL 0x100a3
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL 0x100a3
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL 0x100a4
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL 0x100a4
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL 0x100a5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL 0x100a5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL 0x100a6
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL 0x100a6
+#define regBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST 0x100a8
+#define regBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP 0x100a9
+#define regBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL 0x100a9
+#define regBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST 0x100b4
+#define regBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP 0x100b5
+#define regBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL 0x100b5
+#define regBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST 0x100c8
+#define regBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x100c9
+#define regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST 0x100ca
+#define regBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP 0x100cb
+#define regBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL 0x100cb
+#define regBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST 0x100cc
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP 0x100cd
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL 0x100ce
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS 0x100ce
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS 0x100cf
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS 0x100cf
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS 0x100d0
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK 0x100d0
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET 0x100d1
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE 0x100d1
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID 0x100d2
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x100d3
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x100d4
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0 0x100d5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1 0x100d6
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2 0x100d7
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3 0x100d8
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4 0x100d9
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5 0x100da
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x100db
+#define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST 0x10100
+#define regBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP 0x10101
+#define regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS 0x10102
+#define regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST 0x10104
+#define regBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LINK_CAP_16GT 0x10105
+#define regBIF_CFG_DEV0_EPF0_LINK_CAP_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT 0x10106
+#define regBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT 0x10107
+#define regBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x10108
+#define regBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x10109
+#define regBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x1010a
+#define regBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT 0x1010c
+#define regBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT 0x1010c
+#define regBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT 0x1010c
+#define regBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT 0x1010c
+#define regBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT 0x1010d
+#define regBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT 0x1010d
+#define regBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT 0x1010d
+#define regBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT 0x1010d
+#define regBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT 0x1010e
+#define regBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT 0x1010e
+#define regBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT 0x1010e
+#define regBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT 0x1010e
+#define regBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT 0x1010f
+#define regBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT 0x1010f
+#define regBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT 0x1010f
+#define regBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT 0x1010f
+#define regBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST 0x10114
+#define regBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP 0x10115
+#define regBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS 0x10115
+#define regBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL 0x10116
+#define regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS 0x10116
+#define regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL 0x10117
+#define regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS 0x10117
+#define regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL 0x10118
+#define regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS 0x10118
+#define regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL 0x10119
+#define regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS 0x10119
+#define regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL 0x1011a
+#define regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS 0x1011a
+#define regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL 0x1011b
+#define regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS 0x1011b
+#define regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL 0x1011c
+#define regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS 0x1011c
+#define regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL 0x1011d
+#define regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS 0x1011d
+#define regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL 0x1011e
+#define regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS 0x1011e
+#define regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL 0x1011f
+#define regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS 0x1011f
+#define regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL 0x10120
+#define regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS 0x10120
+#define regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL 0x10121
+#define regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS 0x10121
+#define regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL 0x10122
+#define regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS 0x10122
+#define regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL 0x10123
+#define regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS 0x10123
+#define regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL 0x10124
+#define regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS 0x10124
+#define regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL 0x10125
+#define regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS 0x10125
+#define regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x10130
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP 0x10131
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL 0x10132
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP 0x10133
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL 0x10134
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP 0x10135
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL 0x10136
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP 0x10137
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL 0x10138
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP 0x10139
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL 0x1013a
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP 0x1013b
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL 0x1013c
+#define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LINK_CAP_32GT 0x10141
+#define regBIF_CFG_DEV0_EPF0_LINK_CAP_32GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT 0x10142
+#define regBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT 0x10143
+#define regBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT_BASE_IDX 5
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf0_bifcfgdecp
+// base address: 0x10160000
+#define regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID 0x18000
+#define regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID 0x18000
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_COMMAND 0x18001
+#define regBIF_CFG_DEV0_EPF0_VF0_COMMAND_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_STATUS 0x18001
+#define regBIF_CFG_DEV0_EPF0_VF0_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID 0x18002
+#define regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE 0x18002
+#define regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS 0x18002
+#define regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS 0x18002
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE 0x18003
+#define regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_LATENCY 0x18003
+#define regBIF_CFG_DEV0_EPF0_VF0_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_HEADER 0x18003
+#define regBIF_CFG_DEV0_EPF0_VF0_HEADER_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_BIST 0x18003
+#define regBIF_CFG_DEV0_EPF0_VF0_BIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 0x18004
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 0x18005
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 0x18006
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 0x18007
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 0x18008
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 0x18009
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR 0x1800a
+#define regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID 0x1800b
+#define regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR 0x1800c
+#define regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR 0x1800d
+#define regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE 0x1800f
+#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN 0x1800f
+#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT 0x1800f
+#define regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY 0x1800f
+#define regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST 0x18019
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP 0x18019
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP 0x1801a
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL 0x1801b
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS 0x1801b
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP 0x1801c
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL 0x1801d
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS 0x1801d
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 0x18022
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 0x18023
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 0x18023
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 0x18024
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 0x18025
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 0x18025
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST 0x18028
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL 0x18028
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO 0x18029
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI 0x1802a
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA 0x1802a
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA 0x1802a
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK 0x1802b
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 0x1802b
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 0x1802b
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 0x1802c
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING 0x1802c
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 0x1802d
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST 0x18030
+#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL 0x18030
+#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE 0x18031
+#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA 0x18032
+#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x18040
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x18041
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 0x18042
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 0x18043
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x18054
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS 0x18055
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK 0x18056
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY 0x18057
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS 0x18058
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK 0x18059
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL 0x1805a
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 0x1805b
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 0x1805c
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 0x1805d
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 0x1805e
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 0x18062
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 0x18063
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 0x18064
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 0x18065
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST 0x180ca
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP 0x180cb
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL 0x180cb
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL_BASE_IDX 5
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf1_bifcfgdecp
+// base address: 0x10161000
+#define regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID 0x18400
+#define regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID 0x18400
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_COMMAND 0x18401
+#define regBIF_CFG_DEV0_EPF0_VF1_COMMAND_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_STATUS 0x18401
+#define regBIF_CFG_DEV0_EPF0_VF1_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID 0x18402
+#define regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE 0x18402
+#define regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS 0x18402
+#define regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS 0x18402
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE 0x18403
+#define regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_LATENCY 0x18403
+#define regBIF_CFG_DEV0_EPF0_VF1_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_HEADER 0x18403
+#define regBIF_CFG_DEV0_EPF0_VF1_HEADER_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_BIST 0x18403
+#define regBIF_CFG_DEV0_EPF0_VF1_BIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 0x18404
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 0x18405
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 0x18406
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 0x18407
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 0x18408
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 0x18409
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR 0x1840a
+#define regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID 0x1840b
+#define regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR 0x1840c
+#define regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR 0x1840d
+#define regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE 0x1840f
+#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN 0x1840f
+#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT 0x1840f
+#define regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY 0x1840f
+#define regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST 0x18419
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP 0x18419
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP 0x1841a
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL 0x1841b
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS 0x1841b
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP 0x1841c
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL 0x1841d
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS 0x1841d
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 0x18422
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 0x18423
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 0x18423
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 0x18424
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 0x18425
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 0x18425
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST 0x18428
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL 0x18428
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO 0x18429
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI 0x1842a
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA 0x1842a
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA 0x1842a
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK 0x1842b
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 0x1842b
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 0x1842b
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 0x1842c
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING 0x1842c
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 0x1842d
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST 0x18430
+#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL 0x18430
+#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE 0x18431
+#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA 0x18432
+#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x18440
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR 0x18441
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 0x18442
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 0x18443
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x18454
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS 0x18455
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK 0x18456
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY 0x18457
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS 0x18458
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK 0x18459
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL 0x1845a
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 0x1845b
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 0x1845c
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 0x1845d
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 0x1845e
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 0x18462
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 0x18463
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 0x18464
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 0x18465
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST 0x184ca
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP 0x184cb
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL 0x184cb
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL_BASE_IDX 5
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf2_bifcfgdecp
+// base address: 0x10162000
+#define regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID 0x18800
+#define regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID 0x18800
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_COMMAND 0x18801
+#define regBIF_CFG_DEV0_EPF0_VF2_COMMAND_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_STATUS 0x18801
+#define regBIF_CFG_DEV0_EPF0_VF2_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID 0x18802
+#define regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE 0x18802
+#define regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS 0x18802
+#define regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS 0x18802
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE 0x18803
+#define regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_LATENCY 0x18803
+#define regBIF_CFG_DEV0_EPF0_VF2_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_HEADER 0x18803
+#define regBIF_CFG_DEV0_EPF0_VF2_HEADER_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_BIST 0x18803
+#define regBIF_CFG_DEV0_EPF0_VF2_BIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 0x18804
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 0x18805
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 0x18806
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 0x18807
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 0x18808
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 0x18809
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR 0x1880a
+#define regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID 0x1880b
+#define regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR 0x1880c
+#define regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR 0x1880d
+#define regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE 0x1880f
+#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN 0x1880f
+#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT 0x1880f
+#define regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY 0x1880f
+#define regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST 0x18819
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP 0x18819
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP 0x1881a
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL 0x1881b
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS 0x1881b
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP 0x1881c
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL 0x1881d
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS 0x1881d
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 0x18822
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 0x18823
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 0x18823
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 0x18824
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 0x18825
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 0x18825
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST 0x18828
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL 0x18828
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO 0x18829
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI 0x1882a
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA 0x1882a
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA 0x1882a
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK 0x1882b
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 0x1882b
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 0x1882b
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 0x1882c
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING 0x1882c
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 0x1882d
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST 0x18830
+#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL 0x18830
+#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE 0x18831
+#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA 0x18832
+#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x18840
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR 0x18841
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 0x18842
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 0x18843
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x18854
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS 0x18855
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK 0x18856
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY 0x18857
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS 0x18858
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK 0x18859
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL 0x1885a
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 0x1885b
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 0x1885c
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 0x1885d
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 0x1885e
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 0x18862
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 0x18863
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 0x18864
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 0x18865
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST 0x188ca
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP 0x188cb
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL 0x188cb
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL_BASE_IDX 5
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf3_bifcfgdecp
+// base address: 0x10163000
+#define regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID 0x18c00
+#define regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID 0x18c00
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_COMMAND 0x18c01
+#define regBIF_CFG_DEV0_EPF0_VF3_COMMAND_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_STATUS 0x18c01
+#define regBIF_CFG_DEV0_EPF0_VF3_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID 0x18c02
+#define regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE 0x18c02
+#define regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS 0x18c02
+#define regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS 0x18c02
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE 0x18c03
+#define regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_LATENCY 0x18c03
+#define regBIF_CFG_DEV0_EPF0_VF3_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_HEADER 0x18c03
+#define regBIF_CFG_DEV0_EPF0_VF3_HEADER_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_BIST 0x18c03
+#define regBIF_CFG_DEV0_EPF0_VF3_BIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 0x18c04
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 0x18c05
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 0x18c06
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 0x18c07
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 0x18c08
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 0x18c09
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR 0x18c0a
+#define regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID 0x18c0b
+#define regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR 0x18c0c
+#define regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR 0x18c0d
+#define regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE 0x18c0f
+#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN 0x18c0f
+#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT 0x18c0f
+#define regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY 0x18c0f
+#define regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST 0x18c19
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP 0x18c19
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP 0x18c1a
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL 0x18c1b
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS 0x18c1b
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP 0x18c1c
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL 0x18c1d
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS 0x18c1d
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 0x18c22
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 0x18c23
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 0x18c23
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 0x18c24
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 0x18c25
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 0x18c25
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST 0x18c28
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL 0x18c28
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO 0x18c29
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI 0x18c2a
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA 0x18c2a
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA 0x18c2a
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK 0x18c2b
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 0x18c2b
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 0x18c2b
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 0x18c2c
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING 0x18c2c
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 0x18c2d
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST 0x18c30
+#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL 0x18c30
+#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE 0x18c31
+#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA 0x18c32
+#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x18c40
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR 0x18c41
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 0x18c42
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 0x18c43
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x18c54
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS 0x18c55
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK 0x18c56
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY 0x18c57
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS 0x18c58
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK 0x18c59
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL 0x18c5a
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 0x18c5b
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 0x18c5c
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 0x18c5d
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 0x18c5e
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 0x18c62
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 0x18c63
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 0x18c64
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 0x18c65
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST 0x18cca
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP 0x18ccb
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL 0x18ccb
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL_BASE_IDX 5
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf4_bifcfgdecp
+// base address: 0x10164000
+#define regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID 0x19000
+#define regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID 0x19000
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_COMMAND 0x19001
+#define regBIF_CFG_DEV0_EPF0_VF4_COMMAND_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_STATUS 0x19001
+#define regBIF_CFG_DEV0_EPF0_VF4_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID 0x19002
+#define regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE 0x19002
+#define regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS 0x19002
+#define regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS 0x19002
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE 0x19003
+#define regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_LATENCY 0x19003
+#define regBIF_CFG_DEV0_EPF0_VF4_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_HEADER 0x19003
+#define regBIF_CFG_DEV0_EPF0_VF4_HEADER_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_BIST 0x19003
+#define regBIF_CFG_DEV0_EPF0_VF4_BIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 0x19004
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 0x19005
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 0x19006
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 0x19007
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 0x19008
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 0x19009
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR 0x1900a
+#define regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID 0x1900b
+#define regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR 0x1900c
+#define regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR 0x1900d
+#define regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE 0x1900f
+#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN 0x1900f
+#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT 0x1900f
+#define regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY 0x1900f
+#define regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST 0x19019
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP 0x19019
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP 0x1901a
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL 0x1901b
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS 0x1901b
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP 0x1901c
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL 0x1901d
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS 0x1901d
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 0x19022
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 0x19023
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 0x19023
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 0x19024
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 0x19025
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 0x19025
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST 0x19028
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL 0x19028
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO 0x19029
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI 0x1902a
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA 0x1902a
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA 0x1902a
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK 0x1902b
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 0x1902b
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 0x1902b
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 0x1902c
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING 0x1902c
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 0x1902d
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST 0x19030
+#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL 0x19030
+#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE 0x19031
+#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA 0x19032
+#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x19040
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR 0x19041
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 0x19042
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 0x19043
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x19054
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS 0x19055
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK 0x19056
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY 0x19057
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS 0x19058
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK 0x19059
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL 0x1905a
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 0x1905b
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 0x1905c
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 0x1905d
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 0x1905e
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 0x19062
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 0x19063
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 0x19064
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 0x19065
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST 0x190ca
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP 0x190cb
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL 0x190cb
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL_BASE_IDX 5
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf5_bifcfgdecp
+// base address: 0x10165000
+#define regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID 0x19400
+#define regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID 0x19400
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_COMMAND 0x19401
+#define regBIF_CFG_DEV0_EPF0_VF5_COMMAND_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_STATUS 0x19401
+#define regBIF_CFG_DEV0_EPF0_VF5_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID 0x19402
+#define regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE 0x19402
+#define regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS 0x19402
+#define regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS 0x19402
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE 0x19403
+#define regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_LATENCY 0x19403
+#define regBIF_CFG_DEV0_EPF0_VF5_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_HEADER 0x19403
+#define regBIF_CFG_DEV0_EPF0_VF5_HEADER_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_BIST 0x19403
+#define regBIF_CFG_DEV0_EPF0_VF5_BIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 0x19404
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 0x19405
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 0x19406
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 0x19407
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 0x19408
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 0x19409
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR 0x1940a
+#define regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID 0x1940b
+#define regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR 0x1940c
+#define regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR 0x1940d
+#define regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE 0x1940f
+#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN 0x1940f
+#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT 0x1940f
+#define regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY 0x1940f
+#define regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST 0x19419
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP 0x19419
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP 0x1941a
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL 0x1941b
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS 0x1941b
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP 0x1941c
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL 0x1941d
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS 0x1941d
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 0x19422
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 0x19423
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 0x19423
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 0x19424
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 0x19425
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 0x19425
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST 0x19428
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL 0x19428
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO 0x19429
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI 0x1942a
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA 0x1942a
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA 0x1942a
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK 0x1942b
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 0x1942b
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 0x1942b
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 0x1942c
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING 0x1942c
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 0x1942d
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST 0x19430
+#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL 0x19430
+#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE 0x19431
+#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA 0x19432
+#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x19440
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR 0x19441
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 0x19442
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 0x19443
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x19454
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS 0x19455
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK 0x19456
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY 0x19457
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS 0x19458
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK 0x19459
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL 0x1945a
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 0x1945b
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 0x1945c
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 0x1945d
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 0x1945e
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 0x19462
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 0x19463
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 0x19464
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 0x19465
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST 0x194ca
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP 0x194cb
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL 0x194cb
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL_BASE_IDX 5
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf6_bifcfgdecp
+// base address: 0x10166000
+#define regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID 0x19800
+#define regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID 0x19800
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_COMMAND 0x19801
+#define regBIF_CFG_DEV0_EPF0_VF6_COMMAND_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_STATUS 0x19801
+#define regBIF_CFG_DEV0_EPF0_VF6_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID 0x19802
+#define regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE 0x19802
+#define regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS 0x19802
+#define regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS 0x19802
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE 0x19803
+#define regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_LATENCY 0x19803
+#define regBIF_CFG_DEV0_EPF0_VF6_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_HEADER 0x19803
+#define regBIF_CFG_DEV0_EPF0_VF6_HEADER_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_BIST 0x19803
+#define regBIF_CFG_DEV0_EPF0_VF6_BIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 0x19804
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 0x19805
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 0x19806
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 0x19807
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 0x19808
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 0x19809
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR 0x1980a
+#define regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID 0x1980b
+#define regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR 0x1980c
+#define regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR 0x1980d
+#define regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE 0x1980f
+#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN 0x1980f
+#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT 0x1980f
+#define regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY 0x1980f
+#define regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST 0x19819
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP 0x19819
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP 0x1981a
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL 0x1981b
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS 0x1981b
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP 0x1981c
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL 0x1981d
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS 0x1981d
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 0x19822
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 0x19823
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 0x19823
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 0x19824
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 0x19825
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 0x19825
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST 0x19828
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL 0x19828
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO 0x19829
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI 0x1982a
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA 0x1982a
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA 0x1982a
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK 0x1982b
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 0x1982b
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 0x1982b
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 0x1982c
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING 0x1982c
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 0x1982d
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST 0x19830
+#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL 0x19830
+#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE 0x19831
+#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA 0x19832
+#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x19840
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR 0x19841
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 0x19842
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 0x19843
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x19854
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS 0x19855
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK 0x19856
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY 0x19857
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS 0x19858
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK 0x19859
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL 0x1985a
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 0x1985b
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 0x1985c
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 0x1985d
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 0x1985e
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 0x19862
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 0x19863
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 0x19864
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 0x19865
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST 0x198ca
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP 0x198cb
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL 0x198cb
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL_BASE_IDX 5
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf7_bifcfgdecp
+// base address: 0x10167000
+#define regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID 0x19c00
+#define regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID 0x19c00
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_COMMAND 0x19c01
+#define regBIF_CFG_DEV0_EPF0_VF7_COMMAND_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_STATUS 0x19c01
+#define regBIF_CFG_DEV0_EPF0_VF7_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID 0x19c02
+#define regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE 0x19c02
+#define regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS 0x19c02
+#define regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS 0x19c02
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE 0x19c03
+#define regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_LATENCY 0x19c03
+#define regBIF_CFG_DEV0_EPF0_VF7_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_HEADER 0x19c03
+#define regBIF_CFG_DEV0_EPF0_VF7_HEADER_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_BIST 0x19c03
+#define regBIF_CFG_DEV0_EPF0_VF7_BIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 0x19c04
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 0x19c05
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 0x19c06
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 0x19c07
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 0x19c08
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 0x19c09
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR 0x19c0a
+#define regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID 0x19c0b
+#define regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR 0x19c0c
+#define regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR 0x19c0d
+#define regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE 0x19c0f
+#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN 0x19c0f
+#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT 0x19c0f
+#define regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY 0x19c0f
+#define regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST 0x19c19
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP 0x19c19
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP 0x19c1a
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL 0x19c1b
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS 0x19c1b
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP 0x19c1c
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL 0x19c1d
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS 0x19c1d
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 0x19c22
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 0x19c23
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 0x19c23
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 0x19c24
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 0x19c25
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 0x19c25
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST 0x19c28
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL 0x19c28
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO 0x19c29
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI 0x19c2a
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA 0x19c2a
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA 0x19c2a
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK 0x19c2b
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 0x19c2b
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 0x19c2b
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 0x19c2c
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING 0x19c2c
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 0x19c2d
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST 0x19c30
+#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL 0x19c30
+#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE 0x19c31
+#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA 0x19c32
+#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x19c40
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR 0x19c41
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 0x19c42
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 0x19c43
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x19c54
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS 0x19c55
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK 0x19c56
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY 0x19c57
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS 0x19c58
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK 0x19c59
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL 0x19c5a
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 0x19c5b
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 0x19c5c
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 0x19c5d
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 0x19c5e
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 0x19c62
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 0x19c63
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 0x19c64
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 0x19c65
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST 0x19cca
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP 0x19ccb
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL 0x19ccb
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL_BASE_IDX 5
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf1_bifcfgdecp
+// base address: 0x10141000
+#define regBIF_CFG_DEV0_EPF1_VENDOR_ID 0x10400
+#define regBIF_CFG_DEV0_EPF1_VENDOR_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_DEVICE_ID 0x10400
+#define regBIF_CFG_DEV0_EPF1_DEVICE_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_COMMAND 0x10401
+#define regBIF_CFG_DEV0_EPF1_COMMAND_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_STATUS 0x10401
+#define regBIF_CFG_DEV0_EPF1_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_REVISION_ID 0x10402
+#define regBIF_CFG_DEV0_EPF1_REVISION_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PROG_INTERFACE 0x10402
+#define regBIF_CFG_DEV0_EPF1_PROG_INTERFACE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_SUB_CLASS 0x10402
+#define regBIF_CFG_DEV0_EPF1_SUB_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_BASE_CLASS 0x10402
+#define regBIF_CFG_DEV0_EPF1_BASE_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_CACHE_LINE 0x10403
+#define regBIF_CFG_DEV0_EPF1_CACHE_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_LATENCY 0x10403
+#define regBIF_CFG_DEV0_EPF1_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_HEADER 0x10403
+#define regBIF_CFG_DEV0_EPF1_HEADER_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_BIST 0x10403
+#define regBIF_CFG_DEV0_EPF1_BIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_1 0x10404
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_2 0x10405
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_3 0x10406
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_4 0x10407
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_4_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_5 0x10408
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_5_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_6 0x10409
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_6_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR 0x1040a
+#define regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID 0x1040b
+#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR 0x1040c
+#define regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_CAP_PTR 0x1040d
+#define regBIF_CFG_DEV0_EPF1_CAP_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE 0x1040f
+#define regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN 0x1040f
+#define regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_MIN_GRANT 0x1040f
+#define regBIF_CFG_DEV0_EPF1_MIN_GRANT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_MAX_LATENCY 0x1040f
+#define regBIF_CFG_DEV0_EPF1_MAX_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST 0x10412
+#define regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W 0x10413
+#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST 0x10414
+#define regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PMI_CAP 0x10414
+#define regBIF_CFG_DEV0_EPF1_PMI_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL 0x10415
+#define regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST 0x10419
+#define regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_CAP 0x10419
+#define regBIF_CFG_DEV0_EPF1_PCIE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP 0x1041a
+#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL 0x1041b
+#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS 0x1041b
+#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_LINK_CAP 0x1041c
+#define regBIF_CFG_DEV0_EPF1_LINK_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_LINK_CNTL 0x1041d
+#define regBIF_CFG_DEV0_EPF1_LINK_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_LINK_STATUS 0x1041d
+#define regBIF_CFG_DEV0_EPF1_LINK_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP2 0x10422
+#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2 0x10423
+#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2 0x10423
+#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_LINK_CAP2 0x10424
+#define regBIF_CFG_DEV0_EPF1_LINK_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_LINK_CNTL2 0x10425
+#define regBIF_CFG_DEV0_EPF1_LINK_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_LINK_STATUS2 0x10425
+#define regBIF_CFG_DEV0_EPF1_LINK_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST 0x10428
+#define regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL 0x10428
+#define regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO 0x10429
+#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI 0x1042a
+#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA 0x1042a
+#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA 0x1042a
+#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_MSI_MASK 0x1042b
+#define regBIF_CFG_DEV0_EPF1_MSI_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 0x1042b
+#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 0x1042b
+#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_MSI_MASK_64 0x1042c
+#define regBIF_CFG_DEV0_EPF1_MSI_MASK_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_MSI_PENDING 0x1042c
+#define regBIF_CFG_DEV0_EPF1_MSI_PENDING_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_MSI_PENDING_64 0x1042d
+#define regBIF_CFG_DEV0_EPF1_MSI_PENDING_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST 0x10430
+#define regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL 0x10430
+#define regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_MSIX_TABLE 0x10431
+#define regBIF_CFG_DEV0_EPF1_MSIX_TABLE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_MSIX_PBA 0x10432
+#define regBIF_CFG_DEV0_EPF1_MSIX_PBA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10440
+#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR 0x10441
+#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 0x10442
+#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 0x10443
+#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x10450
+#define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1 0x10451
+#define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2 0x10452
+#define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10454
+#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS 0x10455
+#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK 0x10456
+#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY 0x10457
+#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS 0x10458
+#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK 0x10459
+#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL 0x1045a
+#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 0x1045b
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 0x1045c
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 0x1045d
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 0x1045e
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 0x10462
+#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 0x10463
+#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 0x10464
+#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 0x10465
+#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST 0x10480
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP 0x10481
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL 0x10482
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP 0x10483
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL 0x10484
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP 0x10485
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL 0x10486
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP 0x10487
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL 0x10488
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP 0x10489
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL 0x1048a
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP 0x1048b
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL 0x1048c
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10490
+#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT 0x10491
+#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA 0x10492
+#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP 0x10493
+#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST 0x10494
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP 0x10495
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR 0x10496
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS 0x10497
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL 0x10497
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10498
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10498
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10498
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10498
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10499
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10499
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10499
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10499
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST 0x1049c
+#define regBIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3 0x1049d
+#define regBIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS 0x1049e
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL 0x1049f
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL 0x1049f
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL 0x104a0
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL 0x104a0
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL 0x104a1
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL 0x104a1
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL 0x104a2
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL 0x104a2
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL 0x104a3
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL 0x104a3
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL 0x104a4
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL 0x104a4
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL 0x104a5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL 0x104a5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL 0x104a6
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL 0x104a6
+#define regBIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST 0x104a8
+#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP 0x104a9
+#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL 0x104a9
+#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST 0x104b4
+#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP 0x104b5
+#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL 0x104b5
+#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST 0x104c8
+#define regBIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_LTR_CAP 0x104c9
+#define regBIF_CFG_DEV0_EPF1_PCIE_LTR_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST 0x104ca
+#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP 0x104cb
+#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL 0x104cb
+#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST 0x104cc
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP 0x104cd
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL 0x104ce
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS 0x104ce
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS 0x104cf
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS 0x104cf
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS 0x104d0
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK 0x104d0
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET 0x104d1
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE 0x104d1
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID 0x104d2
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x104d3
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x104d4
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0 0x104d5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1 0x104d6
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2 0x104d7
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3 0x104d8
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4 0x104d9
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5 0x104da
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x104db
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x10530
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP 0x10531
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL 0x10532
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP 0x10533
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL 0x10534
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP 0x10535
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL 0x10536
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP 0x10537
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL 0x10538
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP 0x10539
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL 0x1053a
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP 0x1053b
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL 0x1053c
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX 5
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf2_bifcfgdecp
+// base address: 0x10142000
+#define regBIF_CFG_DEV0_EPF2_VENDOR_ID 0x10800
+#define regBIF_CFG_DEV0_EPF2_VENDOR_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_DEVICE_ID 0x10800
+#define regBIF_CFG_DEV0_EPF2_DEVICE_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_COMMAND 0x10801
+#define regBIF_CFG_DEV0_EPF2_COMMAND_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_STATUS 0x10801
+#define regBIF_CFG_DEV0_EPF2_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_REVISION_ID 0x10802
+#define regBIF_CFG_DEV0_EPF2_REVISION_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PROG_INTERFACE 0x10802
+#define regBIF_CFG_DEV0_EPF2_PROG_INTERFACE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_SUB_CLASS 0x10802
+#define regBIF_CFG_DEV0_EPF2_SUB_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_BASE_CLASS 0x10802
+#define regBIF_CFG_DEV0_EPF2_BASE_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_CACHE_LINE 0x10803
+#define regBIF_CFG_DEV0_EPF2_CACHE_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_LATENCY 0x10803
+#define regBIF_CFG_DEV0_EPF2_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_HEADER 0x10803
+#define regBIF_CFG_DEV0_EPF2_HEADER_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_BIST 0x10803
+#define regBIF_CFG_DEV0_EPF2_BIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_1 0x10804
+#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_2 0x10805
+#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_3 0x10806
+#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_4 0x10807
+#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_4_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_5 0x10808
+#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_5_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_6 0x10809
+#define regBIF_CFG_DEV0_EPF2_BASE_ADDR_6_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR 0x1080a
+#define regBIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_ADAPTER_ID 0x1080b
+#define regBIF_CFG_DEV0_EPF2_ADAPTER_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_ROM_BASE_ADDR 0x1080c
+#define regBIF_CFG_DEV0_EPF2_ROM_BASE_ADDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_CAP_PTR 0x1080d
+#define regBIF_CFG_DEV0_EPF2_CAP_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_INTERRUPT_LINE 0x1080f
+#define regBIF_CFG_DEV0_EPF2_INTERRUPT_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_INTERRUPT_PIN 0x1080f
+#define regBIF_CFG_DEV0_EPF2_INTERRUPT_PIN_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_MIN_GRANT 0x1080f
+#define regBIF_CFG_DEV0_EPF2_MIN_GRANT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_MAX_LATENCY 0x1080f
+#define regBIF_CFG_DEV0_EPF2_MAX_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST 0x10812
+#define regBIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_ADAPTER_ID_W 0x10813
+#define regBIF_CFG_DEV0_EPF2_ADAPTER_ID_W_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PMI_CAP_LIST 0x10814
+#define regBIF_CFG_DEV0_EPF2_PMI_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PMI_CAP 0x10814
+#define regBIF_CFG_DEV0_EPF2_PMI_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL 0x10815
+#define regBIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_SBRN 0x10818
+#define regBIF_CFG_DEV0_EPF2_SBRN_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_FLADJ 0x10818
+#define regBIF_CFG_DEV0_EPF2_FLADJ_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_DBESL_DBESLD 0x10818
+#define regBIF_CFG_DEV0_EPF2_DBESL_DBESLD_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_CAP_LIST 0x10819
+#define regBIF_CFG_DEV0_EPF2_PCIE_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_CAP 0x10819
+#define regBIF_CFG_DEV0_EPF2_PCIE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_DEVICE_CAP 0x1081a
+#define regBIF_CFG_DEV0_EPF2_DEVICE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_DEVICE_CNTL 0x1081b
+#define regBIF_CFG_DEV0_EPF2_DEVICE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_DEVICE_STATUS 0x1081b
+#define regBIF_CFG_DEV0_EPF2_DEVICE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_LINK_CAP 0x1081c
+#define regBIF_CFG_DEV0_EPF2_LINK_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_LINK_CNTL 0x1081d
+#define regBIF_CFG_DEV0_EPF2_LINK_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_LINK_STATUS 0x1081d
+#define regBIF_CFG_DEV0_EPF2_LINK_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_DEVICE_CAP2 0x10822
+#define regBIF_CFG_DEV0_EPF2_DEVICE_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_DEVICE_CNTL2 0x10823
+#define regBIF_CFG_DEV0_EPF2_DEVICE_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_DEVICE_STATUS2 0x10823
+#define regBIF_CFG_DEV0_EPF2_DEVICE_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_LINK_CAP2 0x10824
+#define regBIF_CFG_DEV0_EPF2_LINK_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_LINK_CNTL2 0x10825
+#define regBIF_CFG_DEV0_EPF2_LINK_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_LINK_STATUS2 0x10825
+#define regBIF_CFG_DEV0_EPF2_LINK_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_MSI_CAP_LIST 0x10828
+#define regBIF_CFG_DEV0_EPF2_MSI_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_MSI_MSG_CNTL 0x10828
+#define regBIF_CFG_DEV0_EPF2_MSI_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO 0x10829
+#define regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI 0x1082a
+#define regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA 0x1082a
+#define regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA 0x1082a
+#define regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_MSI_MASK 0x1082b
+#define regBIF_CFG_DEV0_EPF2_MSI_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64 0x1082b
+#define regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64 0x1082b
+#define regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_MSI_MASK_64 0x1082c
+#define regBIF_CFG_DEV0_EPF2_MSI_MASK_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_MSI_PENDING 0x1082c
+#define regBIF_CFG_DEV0_EPF2_MSI_PENDING_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_MSI_PENDING_64 0x1082d
+#define regBIF_CFG_DEV0_EPF2_MSI_PENDING_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_MSIX_CAP_LIST 0x10830
+#define regBIF_CFG_DEV0_EPF2_MSIX_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL 0x10830
+#define regBIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_MSIX_TABLE 0x10831
+#define regBIF_CFG_DEV0_EPF2_MSIX_TABLE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_MSIX_PBA 0x10832
+#define regBIF_CFG_DEV0_EPF2_MSIX_PBA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10840
+#define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR 0x10841
+#define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1 0x10842
+#define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2 0x10843
+#define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10854
+#define regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS 0x10855
+#define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK 0x10856
+#define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY 0x10857
+#define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS 0x10858
+#define regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK 0x10859
+#define regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL 0x1085a
+#define regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0 0x1085b
+#define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1 0x1085c
+#define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2 0x1085d
+#define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3 0x1085e
+#define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0 0x10862
+#define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1 0x10863
+#define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2 0x10864
+#define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3 0x10865
+#define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST 0x10880
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP 0x10881
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL 0x10882
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP 0x10883
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL 0x10884
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP 0x10885
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL 0x10886
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP 0x10887
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL 0x10888
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP 0x10889
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL 0x1088a
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP 0x1088b
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL 0x1088c
+#define regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10890
+#define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT 0x10891
+#define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA 0x10892
+#define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP 0x10893
+#define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST 0x10894
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_CAP 0x10895
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR 0x10896
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS 0x10897
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL 0x10897
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10898
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10898
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10898
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10898
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10899
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10899
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10899
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10899
+#define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST 0x108a8
+#define regBIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_ACS_CAP 0x108a9
+#define regBIF_CFG_DEV0_EPF2_PCIE_ACS_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL 0x108a9
+#define regBIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST 0x108b4
+#define regBIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_PASID_CAP 0x108b5
+#define regBIF_CFG_DEV0_EPF2_PCIE_PASID_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL 0x108b5
+#define regBIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST 0x108ca
+#define regBIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_ARI_CAP 0x108cb
+#define regBIF_CFG_DEV0_EPF2_PCIE_ARI_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL 0x108cb
+#define regBIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL_BASE_IDX 5
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf3_bifcfgdecp
+// base address: 0x10143000
+#define regBIF_CFG_DEV0_EPF3_VENDOR_ID 0x10c00
+#define regBIF_CFG_DEV0_EPF3_VENDOR_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_DEVICE_ID 0x10c00
+#define regBIF_CFG_DEV0_EPF3_DEVICE_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_COMMAND 0x10c01
+#define regBIF_CFG_DEV0_EPF3_COMMAND_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_STATUS 0x10c01
+#define regBIF_CFG_DEV0_EPF3_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_REVISION_ID 0x10c02
+#define regBIF_CFG_DEV0_EPF3_REVISION_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PROG_INTERFACE 0x10c02
+#define regBIF_CFG_DEV0_EPF3_PROG_INTERFACE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_SUB_CLASS 0x10c02
+#define regBIF_CFG_DEV0_EPF3_SUB_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_BASE_CLASS 0x10c02
+#define regBIF_CFG_DEV0_EPF3_BASE_CLASS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_CACHE_LINE 0x10c03
+#define regBIF_CFG_DEV0_EPF3_CACHE_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_LATENCY 0x10c03
+#define regBIF_CFG_DEV0_EPF3_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_HEADER 0x10c03
+#define regBIF_CFG_DEV0_EPF3_HEADER_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_BIST 0x10c03
+#define regBIF_CFG_DEV0_EPF3_BIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_1 0x10c04
+#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_2 0x10c05
+#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_3 0x10c06
+#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_4 0x10c07
+#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_4_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_5 0x10c08
+#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_5_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_6 0x10c09
+#define regBIF_CFG_DEV0_EPF3_BASE_ADDR_6_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR 0x10c0a
+#define regBIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_ADAPTER_ID 0x10c0b
+#define regBIF_CFG_DEV0_EPF3_ADAPTER_ID_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_ROM_BASE_ADDR 0x10c0c
+#define regBIF_CFG_DEV0_EPF3_ROM_BASE_ADDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_CAP_PTR 0x10c0d
+#define regBIF_CFG_DEV0_EPF3_CAP_PTR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_INTERRUPT_LINE 0x10c0f
+#define regBIF_CFG_DEV0_EPF3_INTERRUPT_LINE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_INTERRUPT_PIN 0x10c0f
+#define regBIF_CFG_DEV0_EPF3_INTERRUPT_PIN_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_MIN_GRANT 0x10c0f
+#define regBIF_CFG_DEV0_EPF3_MIN_GRANT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_MAX_LATENCY 0x10c0f
+#define regBIF_CFG_DEV0_EPF3_MAX_LATENCY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST 0x10c12
+#define regBIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_ADAPTER_ID_W 0x10c13
+#define regBIF_CFG_DEV0_EPF3_ADAPTER_ID_W_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PMI_CAP_LIST 0x10c14
+#define regBIF_CFG_DEV0_EPF3_PMI_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PMI_CAP 0x10c14
+#define regBIF_CFG_DEV0_EPF3_PMI_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL 0x10c15
+#define regBIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_SBRN 0x10c18
+#define regBIF_CFG_DEV0_EPF3_SBRN_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_FLADJ 0x10c18
+#define regBIF_CFG_DEV0_EPF3_FLADJ_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_DBESL_DBESLD 0x10c18
+#define regBIF_CFG_DEV0_EPF3_DBESL_DBESLD_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_CAP_LIST 0x10c19
+#define regBIF_CFG_DEV0_EPF3_PCIE_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_CAP 0x10c19
+#define regBIF_CFG_DEV0_EPF3_PCIE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_DEVICE_CAP 0x10c1a
+#define regBIF_CFG_DEV0_EPF3_DEVICE_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_DEVICE_CNTL 0x10c1b
+#define regBIF_CFG_DEV0_EPF3_DEVICE_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_DEVICE_STATUS 0x10c1b
+#define regBIF_CFG_DEV0_EPF3_DEVICE_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_LINK_CAP 0x10c1c
+#define regBIF_CFG_DEV0_EPF3_LINK_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_LINK_CNTL 0x10c1d
+#define regBIF_CFG_DEV0_EPF3_LINK_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_LINK_STATUS 0x10c1d
+#define regBIF_CFG_DEV0_EPF3_LINK_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_DEVICE_CAP2 0x10c22
+#define regBIF_CFG_DEV0_EPF3_DEVICE_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_DEVICE_CNTL2 0x10c23
+#define regBIF_CFG_DEV0_EPF3_DEVICE_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_DEVICE_STATUS2 0x10c23
+#define regBIF_CFG_DEV0_EPF3_DEVICE_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_LINK_CAP2 0x10c24
+#define regBIF_CFG_DEV0_EPF3_LINK_CAP2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_LINK_CNTL2 0x10c25
+#define regBIF_CFG_DEV0_EPF3_LINK_CNTL2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_LINK_STATUS2 0x10c25
+#define regBIF_CFG_DEV0_EPF3_LINK_STATUS2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_MSI_CAP_LIST 0x10c28
+#define regBIF_CFG_DEV0_EPF3_MSI_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_MSI_MSG_CNTL 0x10c28
+#define regBIF_CFG_DEV0_EPF3_MSI_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO 0x10c29
+#define regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI 0x10c2a
+#define regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA 0x10c2a
+#define regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA 0x10c2a
+#define regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_MSI_MASK 0x10c2b
+#define regBIF_CFG_DEV0_EPF3_MSI_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64 0x10c2b
+#define regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64 0x10c2b
+#define regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_MSI_MASK_64 0x10c2c
+#define regBIF_CFG_DEV0_EPF3_MSI_MASK_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_MSI_PENDING 0x10c2c
+#define regBIF_CFG_DEV0_EPF3_MSI_PENDING_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_MSI_PENDING_64 0x10c2d
+#define regBIF_CFG_DEV0_EPF3_MSI_PENDING_64_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_MSIX_CAP_LIST 0x10c30
+#define regBIF_CFG_DEV0_EPF3_MSIX_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL 0x10c30
+#define regBIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_MSIX_TABLE 0x10c31
+#define regBIF_CFG_DEV0_EPF3_MSIX_TABLE_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_MSIX_PBA 0x10c32
+#define regBIF_CFG_DEV0_EPF3_MSIX_PBA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10c40
+#define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR 0x10c41
+#define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1 0x10c42
+#define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2 0x10c43
+#define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10c54
+#define regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS 0x10c55
+#define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK 0x10c56
+#define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY 0x10c57
+#define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS 0x10c58
+#define regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK 0x10c59
+#define regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL 0x10c5a
+#define regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0 0x10c5b
+#define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1 0x10c5c
+#define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2 0x10c5d
+#define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3 0x10c5e
+#define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0 0x10c62
+#define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1 0x10c63
+#define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2 0x10c64
+#define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3 0x10c65
+#define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST 0x10c80
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP 0x10c81
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL 0x10c82
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP 0x10c83
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL 0x10c84
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP 0x10c85
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL 0x10c86
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP 0x10c87
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL 0x10c88
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP 0x10c89
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL 0x10c8a
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP 0x10c8b
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL 0x10c8c
+#define regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10c90
+#define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT 0x10c91
+#define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA 0x10c92
+#define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP 0x10c93
+#define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST 0x10c94
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_CAP 0x10c95
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR 0x10c96
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS 0x10c97
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL 0x10c97
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10c98
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10c98
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10c98
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10c98
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10c99
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10c99
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10c99
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10c99
+#define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST 0x10ca8
+#define regBIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_ACS_CAP 0x10ca9
+#define regBIF_CFG_DEV0_EPF3_PCIE_ACS_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL 0x10ca9
+#define regBIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST 0x10cb4
+#define regBIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_PASID_CAP 0x10cb5
+#define regBIF_CFG_DEV0_EPF3_PCIE_PASID_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL 0x10cb5
+#define regBIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST 0x10cca
+#define regBIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_ARI_CAP 0x10ccb
+#define regBIF_CFG_DEV0_EPF3_PCIE_ARI_CAP_BASE_IDX 5
+#define regBIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL 0x10ccb
+#define regBIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL_BASE_IDX 5
+
+
+// addressBlock: nbif_rcc_dev0_RCCPORTDEC
+// base address: 0x10131000
+#define regRCC_DEV0_1_RCC_VDM_SUPPORT 0xc440
+#define regRCC_DEV0_1_RCC_VDM_SUPPORT_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_BUS_CNTL 0xc441
+#define regRCC_DEV0_1_RCC_BUS_CNTL_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC 0xc442
+#define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL 0xc443
+#define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_CMN_LINK_CNTL 0xc444
+#define regRCC_DEV0_1_RCC_CMN_LINK_CNTL_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE 0xc445
+#define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL 0xc446
+#define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_MH_ARB_CNTL 0xc447
+#define regRCC_DEV0_1_RCC_MH_ARB_CNTL_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 0xc448
+#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 0xc449
+#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 5
+
+
+// addressBlock: nbif_rcc_ep_dev0_RCCPORTDEC
+// base address: 0x10131000
+#define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH 0xc44c
+#define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH_BASE_IDX 5
+#define regRCC_EP_DEV0_1_EP_PCIE_CNTL 0xc44e
+#define regRCC_EP_DEV0_1_EP_PCIE_CNTL_BASE_IDX 5
+#define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL 0xc44f
+#define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_BASE_IDX 5
+#define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS 0xc450
+#define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_BASE_IDX 5
+#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 0xc451
+#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_BASE_IDX 5
+#define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL 0xc452
+#define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_BASE_IDX 5
+#define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL 0xc453
+#define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_BASE_IDX 5
+#define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL 0xc454
+#define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_BASE_IDX 5
+#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC 0xc455
+#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_BASE_IDX 5
+#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 0xc456
+#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_BASE_IDX 5
+#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP 0xc457
+#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_BASE_IDX 5
+#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0xc458
+#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 5
+#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL 0xc458
+#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_BASE_IDX 5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0xc458
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0xc459
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0xc459
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0xc459
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0xc459
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0xc45a
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0xc45a
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0xc45a
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5
+#define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL 0xc45c
+#define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_BASE_IDX 5
+#define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED 0xc45d
+#define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED_BASE_IDX 5
+#define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL 0xc45f
+#define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_BASE_IDX 5
+#define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID 0xc460
+#define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 5
+#define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL 0xc461
+#define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_BASE_IDX 5
+#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL 0xc462
+#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_BASE_IDX 5
+#define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL 0xc463
+#define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 5
+
+
+// addressBlock: nbif_rcc_dwn_dev0_RCCPORTDEC
+// base address: 0x10131000
+#define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED 0xc468
+#define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED_BASE_IDX 5
+#define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH 0xc469
+#define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_BASE_IDX 5
+#define regRCC_DWN_DEV0_1_DN_PCIE_CNTL 0xc46b
+#define regRCC_DWN_DEV0_1_DN_PCIE_CNTL_BASE_IDX 5
+#define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL 0xc46c
+#define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_BASE_IDX 5
+#define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 0xc46d
+#define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_BASE_IDX 5
+#define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL 0xc46e
+#define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_BASE_IDX 5
+#define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL 0xc46f
+#define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_BASE_IDX 5
+#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 0xc470
+#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_BASE_IDX 5
+#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC 0xc471
+#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_BASE_IDX 5
+#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 0xc472
+#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_BASE_IDX 5
+
+
+// addressBlock: nbif_rcc_dwnp_dev0_RCCPORTDEC
+// base address: 0x10131000
+#define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL 0xc475
+#define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_BASE_IDX 5
+#define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL 0xc476
+#define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL_BASE_IDX 5
+#define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL 0xc477
+#define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_BASE_IDX 5
+#define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2 0xc478
+#define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_BASE_IDX 5
+#define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC 0xc479
+#define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_BASE_IDX 5
+#define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP 0xc47a
+#define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_BASE_IDX 5
+
+
+// addressBlock: nbif_rcc_pfc_amdgfx_RCCPFCDEC
+// base address: 0x10134000
+#define regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL 0xd040
+#define regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL_BASE_IDX 5
+#define regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE 0xd041
+#define regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE_BASE_IDX 5
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0 0xd042
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0_BASE_IDX 5
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1 0xd043
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1_BASE_IDX 5
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2 0xd044
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2_BASE_IDX 5
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3 0xd045
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3_BASE_IDX 5
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4 0xd046
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4_BASE_IDX 5
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5 0xd047
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5_BASE_IDX 5
+#define regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL 0xd048
+#define regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL_BASE_IDX 5
+
+
+// addressBlock: nbif_rcc_pfc_amdgfxaz_RCCPFCDEC
+// base address: 0x10134200
+#define regRCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL 0xd0c0
+#define regRCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL_BASE_IDX 5
+#define regRCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE 0xd0c1
+#define regRCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE_BASE_IDX 5
+#define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0 0xd0c2
+#define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0_BASE_IDX 5
+#define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1 0xd0c3
+#define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1_BASE_IDX 5
+#define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2 0xd0c4
+#define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2_BASE_IDX 5
+#define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3 0xd0c5
+#define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3_BASE_IDX 5
+#define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4 0xd0c6
+#define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4_BASE_IDX 5
+#define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5 0xd0c7
+#define regRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5_BASE_IDX 5
+#define regRCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL 0xd0c8
+#define regRCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL_BASE_IDX 5
+
+
+// addressBlock: nbif_pciemsix_0_usb_MSIXTDEC
+// base address: 0x10178000
+#define regPCIEMSIX_VECT0_ADDR_LO 0x1e000
+#define regPCIEMSIX_VECT0_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT0_ADDR_HI 0x1e001
+#define regPCIEMSIX_VECT0_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT0_MSG_DATA 0x1e002
+#define regPCIEMSIX_VECT0_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT0_CONTROL 0x1e003
+#define regPCIEMSIX_VECT0_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT1_ADDR_LO 0x1e004
+#define regPCIEMSIX_VECT1_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT1_ADDR_HI 0x1e005
+#define regPCIEMSIX_VECT1_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT1_MSG_DATA 0x1e006
+#define regPCIEMSIX_VECT1_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT1_CONTROL 0x1e007
+#define regPCIEMSIX_VECT1_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT2_ADDR_LO 0x1e008
+#define regPCIEMSIX_VECT2_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT2_ADDR_HI 0x1e009
+#define regPCIEMSIX_VECT2_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT2_MSG_DATA 0x1e00a
+#define regPCIEMSIX_VECT2_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT2_CONTROL 0x1e00b
+#define regPCIEMSIX_VECT2_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT3_ADDR_LO 0x1e00c
+#define regPCIEMSIX_VECT3_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT3_ADDR_HI 0x1e00d
+#define regPCIEMSIX_VECT3_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT3_MSG_DATA 0x1e00e
+#define regPCIEMSIX_VECT3_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT3_CONTROL 0x1e00f
+#define regPCIEMSIX_VECT3_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT4_ADDR_LO 0x1e010
+#define regPCIEMSIX_VECT4_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT4_ADDR_HI 0x1e011
+#define regPCIEMSIX_VECT4_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT4_MSG_DATA 0x1e012
+#define regPCIEMSIX_VECT4_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT4_CONTROL 0x1e013
+#define regPCIEMSIX_VECT4_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT5_ADDR_LO 0x1e014
+#define regPCIEMSIX_VECT5_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT5_ADDR_HI 0x1e015
+#define regPCIEMSIX_VECT5_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT5_MSG_DATA 0x1e016
+#define regPCIEMSIX_VECT5_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT5_CONTROL 0x1e017
+#define regPCIEMSIX_VECT5_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT6_ADDR_LO 0x1e018
+#define regPCIEMSIX_VECT6_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT6_ADDR_HI 0x1e019
+#define regPCIEMSIX_VECT6_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT6_MSG_DATA 0x1e01a
+#define regPCIEMSIX_VECT6_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT6_CONTROL 0x1e01b
+#define regPCIEMSIX_VECT6_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT7_ADDR_LO 0x1e01c
+#define regPCIEMSIX_VECT7_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT7_ADDR_HI 0x1e01d
+#define regPCIEMSIX_VECT7_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT7_MSG_DATA 0x1e01e
+#define regPCIEMSIX_VECT7_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT7_CONTROL 0x1e01f
+#define regPCIEMSIX_VECT7_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT8_ADDR_LO 0x1e020
+#define regPCIEMSIX_VECT8_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT8_ADDR_HI 0x1e021
+#define regPCIEMSIX_VECT8_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT8_MSG_DATA 0x1e022
+#define regPCIEMSIX_VECT8_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT8_CONTROL 0x1e023
+#define regPCIEMSIX_VECT8_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT9_ADDR_LO 0x1e024
+#define regPCIEMSIX_VECT9_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT9_ADDR_HI 0x1e025
+#define regPCIEMSIX_VECT9_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT9_MSG_DATA 0x1e026
+#define regPCIEMSIX_VECT9_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT9_CONTROL 0x1e027
+#define regPCIEMSIX_VECT9_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT10_ADDR_LO 0x1e028
+#define regPCIEMSIX_VECT10_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT10_ADDR_HI 0x1e029
+#define regPCIEMSIX_VECT10_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT10_MSG_DATA 0x1e02a
+#define regPCIEMSIX_VECT10_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT10_CONTROL 0x1e02b
+#define regPCIEMSIX_VECT10_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT11_ADDR_LO 0x1e02c
+#define regPCIEMSIX_VECT11_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT11_ADDR_HI 0x1e02d
+#define regPCIEMSIX_VECT11_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT11_MSG_DATA 0x1e02e
+#define regPCIEMSIX_VECT11_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT11_CONTROL 0x1e02f
+#define regPCIEMSIX_VECT11_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT12_ADDR_LO 0x1e030
+#define regPCIEMSIX_VECT12_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT12_ADDR_HI 0x1e031
+#define regPCIEMSIX_VECT12_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT12_MSG_DATA 0x1e032
+#define regPCIEMSIX_VECT12_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT12_CONTROL 0x1e033
+#define regPCIEMSIX_VECT12_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT13_ADDR_LO 0x1e034
+#define regPCIEMSIX_VECT13_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT13_ADDR_HI 0x1e035
+#define regPCIEMSIX_VECT13_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT13_MSG_DATA 0x1e036
+#define regPCIEMSIX_VECT13_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT13_CONTROL 0x1e037
+#define regPCIEMSIX_VECT13_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT14_ADDR_LO 0x1e038
+#define regPCIEMSIX_VECT14_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT14_ADDR_HI 0x1e039
+#define regPCIEMSIX_VECT14_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT14_MSG_DATA 0x1e03a
+#define regPCIEMSIX_VECT14_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT14_CONTROL 0x1e03b
+#define regPCIEMSIX_VECT14_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT15_ADDR_LO 0x1e03c
+#define regPCIEMSIX_VECT15_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT15_ADDR_HI 0x1e03d
+#define regPCIEMSIX_VECT15_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT15_MSG_DATA 0x1e03e
+#define regPCIEMSIX_VECT15_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT15_CONTROL 0x1e03f
+#define regPCIEMSIX_VECT15_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT16_ADDR_LO 0x1e040
+#define regPCIEMSIX_VECT16_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT16_ADDR_HI 0x1e041
+#define regPCIEMSIX_VECT16_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT16_MSG_DATA 0x1e042
+#define regPCIEMSIX_VECT16_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT16_CONTROL 0x1e043
+#define regPCIEMSIX_VECT16_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT17_ADDR_LO 0x1e044
+#define regPCIEMSIX_VECT17_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT17_ADDR_HI 0x1e045
+#define regPCIEMSIX_VECT17_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT17_MSG_DATA 0x1e046
+#define regPCIEMSIX_VECT17_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT17_CONTROL 0x1e047
+#define regPCIEMSIX_VECT17_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT18_ADDR_LO 0x1e048
+#define regPCIEMSIX_VECT18_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT18_ADDR_HI 0x1e049
+#define regPCIEMSIX_VECT18_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT18_MSG_DATA 0x1e04a
+#define regPCIEMSIX_VECT18_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT18_CONTROL 0x1e04b
+#define regPCIEMSIX_VECT18_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT19_ADDR_LO 0x1e04c
+#define regPCIEMSIX_VECT19_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT19_ADDR_HI 0x1e04d
+#define regPCIEMSIX_VECT19_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT19_MSG_DATA 0x1e04e
+#define regPCIEMSIX_VECT19_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT19_CONTROL 0x1e04f
+#define regPCIEMSIX_VECT19_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT20_ADDR_LO 0x1e050
+#define regPCIEMSIX_VECT20_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT20_ADDR_HI 0x1e051
+#define regPCIEMSIX_VECT20_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT20_MSG_DATA 0x1e052
+#define regPCIEMSIX_VECT20_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT20_CONTROL 0x1e053
+#define regPCIEMSIX_VECT20_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT21_ADDR_LO 0x1e054
+#define regPCIEMSIX_VECT21_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT21_ADDR_HI 0x1e055
+#define regPCIEMSIX_VECT21_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT21_MSG_DATA 0x1e056
+#define regPCIEMSIX_VECT21_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT21_CONTROL 0x1e057
+#define regPCIEMSIX_VECT21_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT22_ADDR_LO 0x1e058
+#define regPCIEMSIX_VECT22_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT22_ADDR_HI 0x1e059
+#define regPCIEMSIX_VECT22_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT22_MSG_DATA 0x1e05a
+#define regPCIEMSIX_VECT22_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT22_CONTROL 0x1e05b
+#define regPCIEMSIX_VECT22_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT23_ADDR_LO 0x1e05c
+#define regPCIEMSIX_VECT23_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT23_ADDR_HI 0x1e05d
+#define regPCIEMSIX_VECT23_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT23_MSG_DATA 0x1e05e
+#define regPCIEMSIX_VECT23_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT23_CONTROL 0x1e05f
+#define regPCIEMSIX_VECT23_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT24_ADDR_LO 0x1e060
+#define regPCIEMSIX_VECT24_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT24_ADDR_HI 0x1e061
+#define regPCIEMSIX_VECT24_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT24_MSG_DATA 0x1e062
+#define regPCIEMSIX_VECT24_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT24_CONTROL 0x1e063
+#define regPCIEMSIX_VECT24_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT25_ADDR_LO 0x1e064
+#define regPCIEMSIX_VECT25_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT25_ADDR_HI 0x1e065
+#define regPCIEMSIX_VECT25_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT25_MSG_DATA 0x1e066
+#define regPCIEMSIX_VECT25_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT25_CONTROL 0x1e067
+#define regPCIEMSIX_VECT25_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT26_ADDR_LO 0x1e068
+#define regPCIEMSIX_VECT26_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT26_ADDR_HI 0x1e069
+#define regPCIEMSIX_VECT26_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT26_MSG_DATA 0x1e06a
+#define regPCIEMSIX_VECT26_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT26_CONTROL 0x1e06b
+#define regPCIEMSIX_VECT26_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT27_ADDR_LO 0x1e06c
+#define regPCIEMSIX_VECT27_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT27_ADDR_HI 0x1e06d
+#define regPCIEMSIX_VECT27_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT27_MSG_DATA 0x1e06e
+#define regPCIEMSIX_VECT27_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT27_CONTROL 0x1e06f
+#define regPCIEMSIX_VECT27_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT28_ADDR_LO 0x1e070
+#define regPCIEMSIX_VECT28_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT28_ADDR_HI 0x1e071
+#define regPCIEMSIX_VECT28_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT28_MSG_DATA 0x1e072
+#define regPCIEMSIX_VECT28_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT28_CONTROL 0x1e073
+#define regPCIEMSIX_VECT28_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT29_ADDR_LO 0x1e074
+#define regPCIEMSIX_VECT29_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT29_ADDR_HI 0x1e075
+#define regPCIEMSIX_VECT29_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT29_MSG_DATA 0x1e076
+#define regPCIEMSIX_VECT29_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT29_CONTROL 0x1e077
+#define regPCIEMSIX_VECT29_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT30_ADDR_LO 0x1e078
+#define regPCIEMSIX_VECT30_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT30_ADDR_HI 0x1e079
+#define regPCIEMSIX_VECT30_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT30_MSG_DATA 0x1e07a
+#define regPCIEMSIX_VECT30_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT30_CONTROL 0x1e07b
+#define regPCIEMSIX_VECT30_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT31_ADDR_LO 0x1e07c
+#define regPCIEMSIX_VECT31_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT31_ADDR_HI 0x1e07d
+#define regPCIEMSIX_VECT31_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT31_MSG_DATA 0x1e07e
+#define regPCIEMSIX_VECT31_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT31_CONTROL 0x1e07f
+#define regPCIEMSIX_VECT31_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT32_ADDR_LO 0x1e080
+#define regPCIEMSIX_VECT32_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT32_ADDR_HI 0x1e081
+#define regPCIEMSIX_VECT32_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT32_MSG_DATA 0x1e082
+#define regPCIEMSIX_VECT32_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT32_CONTROL 0x1e083
+#define regPCIEMSIX_VECT32_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT33_ADDR_LO 0x1e084
+#define regPCIEMSIX_VECT33_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT33_ADDR_HI 0x1e085
+#define regPCIEMSIX_VECT33_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT33_MSG_DATA 0x1e086
+#define regPCIEMSIX_VECT33_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT33_CONTROL 0x1e087
+#define regPCIEMSIX_VECT33_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT34_ADDR_LO 0x1e088
+#define regPCIEMSIX_VECT34_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT34_ADDR_HI 0x1e089
+#define regPCIEMSIX_VECT34_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT34_MSG_DATA 0x1e08a
+#define regPCIEMSIX_VECT34_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT34_CONTROL 0x1e08b
+#define regPCIEMSIX_VECT34_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT35_ADDR_LO 0x1e08c
+#define regPCIEMSIX_VECT35_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT35_ADDR_HI 0x1e08d
+#define regPCIEMSIX_VECT35_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT35_MSG_DATA 0x1e08e
+#define regPCIEMSIX_VECT35_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT35_CONTROL 0x1e08f
+#define regPCIEMSIX_VECT35_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT36_ADDR_LO 0x1e090
+#define regPCIEMSIX_VECT36_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT36_ADDR_HI 0x1e091
+#define regPCIEMSIX_VECT36_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT36_MSG_DATA 0x1e092
+#define regPCIEMSIX_VECT36_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT36_CONTROL 0x1e093
+#define regPCIEMSIX_VECT36_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT37_ADDR_LO 0x1e094
+#define regPCIEMSIX_VECT37_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT37_ADDR_HI 0x1e095
+#define regPCIEMSIX_VECT37_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT37_MSG_DATA 0x1e096
+#define regPCIEMSIX_VECT37_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT37_CONTROL 0x1e097
+#define regPCIEMSIX_VECT37_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT38_ADDR_LO 0x1e098
+#define regPCIEMSIX_VECT38_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT38_ADDR_HI 0x1e099
+#define regPCIEMSIX_VECT38_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT38_MSG_DATA 0x1e09a
+#define regPCIEMSIX_VECT38_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT38_CONTROL 0x1e09b
+#define regPCIEMSIX_VECT38_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT39_ADDR_LO 0x1e09c
+#define regPCIEMSIX_VECT39_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT39_ADDR_HI 0x1e09d
+#define regPCIEMSIX_VECT39_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT39_MSG_DATA 0x1e09e
+#define regPCIEMSIX_VECT39_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT39_CONTROL 0x1e09f
+#define regPCIEMSIX_VECT39_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT40_ADDR_LO 0x1e0a0
+#define regPCIEMSIX_VECT40_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT40_ADDR_HI 0x1e0a1
+#define regPCIEMSIX_VECT40_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT40_MSG_DATA 0x1e0a2
+#define regPCIEMSIX_VECT40_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT40_CONTROL 0x1e0a3
+#define regPCIEMSIX_VECT40_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT41_ADDR_LO 0x1e0a4
+#define regPCIEMSIX_VECT41_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT41_ADDR_HI 0x1e0a5
+#define regPCIEMSIX_VECT41_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT41_MSG_DATA 0x1e0a6
+#define regPCIEMSIX_VECT41_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT41_CONTROL 0x1e0a7
+#define regPCIEMSIX_VECT41_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT42_ADDR_LO 0x1e0a8
+#define regPCIEMSIX_VECT42_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT42_ADDR_HI 0x1e0a9
+#define regPCIEMSIX_VECT42_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT42_MSG_DATA 0x1e0aa
+#define regPCIEMSIX_VECT42_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT42_CONTROL 0x1e0ab
+#define regPCIEMSIX_VECT42_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT43_ADDR_LO 0x1e0ac
+#define regPCIEMSIX_VECT43_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT43_ADDR_HI 0x1e0ad
+#define regPCIEMSIX_VECT43_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT43_MSG_DATA 0x1e0ae
+#define regPCIEMSIX_VECT43_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT43_CONTROL 0x1e0af
+#define regPCIEMSIX_VECT43_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT44_ADDR_LO 0x1e0b0
+#define regPCIEMSIX_VECT44_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT44_ADDR_HI 0x1e0b1
+#define regPCIEMSIX_VECT44_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT44_MSG_DATA 0x1e0b2
+#define regPCIEMSIX_VECT44_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT44_CONTROL 0x1e0b3
+#define regPCIEMSIX_VECT44_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT45_ADDR_LO 0x1e0b4
+#define regPCIEMSIX_VECT45_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT45_ADDR_HI 0x1e0b5
+#define regPCIEMSIX_VECT45_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT45_MSG_DATA 0x1e0b6
+#define regPCIEMSIX_VECT45_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT45_CONTROL 0x1e0b7
+#define regPCIEMSIX_VECT45_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT46_ADDR_LO 0x1e0b8
+#define regPCIEMSIX_VECT46_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT46_ADDR_HI 0x1e0b9
+#define regPCIEMSIX_VECT46_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT46_MSG_DATA 0x1e0ba
+#define regPCIEMSIX_VECT46_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT46_CONTROL 0x1e0bb
+#define regPCIEMSIX_VECT46_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT47_ADDR_LO 0x1e0bc
+#define regPCIEMSIX_VECT47_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT47_ADDR_HI 0x1e0bd
+#define regPCIEMSIX_VECT47_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT47_MSG_DATA 0x1e0be
+#define regPCIEMSIX_VECT47_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT47_CONTROL 0x1e0bf
+#define regPCIEMSIX_VECT47_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT48_ADDR_LO 0x1e0c0
+#define regPCIEMSIX_VECT48_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT48_ADDR_HI 0x1e0c1
+#define regPCIEMSIX_VECT48_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT48_MSG_DATA 0x1e0c2
+#define regPCIEMSIX_VECT48_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT48_CONTROL 0x1e0c3
+#define regPCIEMSIX_VECT48_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT49_ADDR_LO 0x1e0c4
+#define regPCIEMSIX_VECT49_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT49_ADDR_HI 0x1e0c5
+#define regPCIEMSIX_VECT49_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT49_MSG_DATA 0x1e0c6
+#define regPCIEMSIX_VECT49_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT49_CONTROL 0x1e0c7
+#define regPCIEMSIX_VECT49_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT50_ADDR_LO 0x1e0c8
+#define regPCIEMSIX_VECT50_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT50_ADDR_HI 0x1e0c9
+#define regPCIEMSIX_VECT50_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT50_MSG_DATA 0x1e0ca
+#define regPCIEMSIX_VECT50_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT50_CONTROL 0x1e0cb
+#define regPCIEMSIX_VECT50_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT51_ADDR_LO 0x1e0cc
+#define regPCIEMSIX_VECT51_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT51_ADDR_HI 0x1e0cd
+#define regPCIEMSIX_VECT51_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT51_MSG_DATA 0x1e0ce
+#define regPCIEMSIX_VECT51_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT51_CONTROL 0x1e0cf
+#define regPCIEMSIX_VECT51_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT52_ADDR_LO 0x1e0d0
+#define regPCIEMSIX_VECT52_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT52_ADDR_HI 0x1e0d1
+#define regPCIEMSIX_VECT52_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT52_MSG_DATA 0x1e0d2
+#define regPCIEMSIX_VECT52_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT52_CONTROL 0x1e0d3
+#define regPCIEMSIX_VECT52_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT53_ADDR_LO 0x1e0d4
+#define regPCIEMSIX_VECT53_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT53_ADDR_HI 0x1e0d5
+#define regPCIEMSIX_VECT53_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT53_MSG_DATA 0x1e0d6
+#define regPCIEMSIX_VECT53_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT53_CONTROL 0x1e0d7
+#define regPCIEMSIX_VECT53_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT54_ADDR_LO 0x1e0d8
+#define regPCIEMSIX_VECT54_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT54_ADDR_HI 0x1e0d9
+#define regPCIEMSIX_VECT54_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT54_MSG_DATA 0x1e0da
+#define regPCIEMSIX_VECT54_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT54_CONTROL 0x1e0db
+#define regPCIEMSIX_VECT54_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT55_ADDR_LO 0x1e0dc
+#define regPCIEMSIX_VECT55_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT55_ADDR_HI 0x1e0dd
+#define regPCIEMSIX_VECT55_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT55_MSG_DATA 0x1e0de
+#define regPCIEMSIX_VECT55_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT55_CONTROL 0x1e0df
+#define regPCIEMSIX_VECT55_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT56_ADDR_LO 0x1e0e0
+#define regPCIEMSIX_VECT56_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT56_ADDR_HI 0x1e0e1
+#define regPCIEMSIX_VECT56_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT56_MSG_DATA 0x1e0e2
+#define regPCIEMSIX_VECT56_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT56_CONTROL 0x1e0e3
+#define regPCIEMSIX_VECT56_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT57_ADDR_LO 0x1e0e4
+#define regPCIEMSIX_VECT57_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT57_ADDR_HI 0x1e0e5
+#define regPCIEMSIX_VECT57_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT57_MSG_DATA 0x1e0e6
+#define regPCIEMSIX_VECT57_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT57_CONTROL 0x1e0e7
+#define regPCIEMSIX_VECT57_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT58_ADDR_LO 0x1e0e8
+#define regPCIEMSIX_VECT58_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT58_ADDR_HI 0x1e0e9
+#define regPCIEMSIX_VECT58_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT58_MSG_DATA 0x1e0ea
+#define regPCIEMSIX_VECT58_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT58_CONTROL 0x1e0eb
+#define regPCIEMSIX_VECT58_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT59_ADDR_LO 0x1e0ec
+#define regPCIEMSIX_VECT59_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT59_ADDR_HI 0x1e0ed
+#define regPCIEMSIX_VECT59_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT59_MSG_DATA 0x1e0ee
+#define regPCIEMSIX_VECT59_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT59_CONTROL 0x1e0ef
+#define regPCIEMSIX_VECT59_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT60_ADDR_LO 0x1e0f0
+#define regPCIEMSIX_VECT60_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT60_ADDR_HI 0x1e0f1
+#define regPCIEMSIX_VECT60_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT60_MSG_DATA 0x1e0f2
+#define regPCIEMSIX_VECT60_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT60_CONTROL 0x1e0f3
+#define regPCIEMSIX_VECT60_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT61_ADDR_LO 0x1e0f4
+#define regPCIEMSIX_VECT61_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT61_ADDR_HI 0x1e0f5
+#define regPCIEMSIX_VECT61_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT61_MSG_DATA 0x1e0f6
+#define regPCIEMSIX_VECT61_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT61_CONTROL 0x1e0f7
+#define regPCIEMSIX_VECT61_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT62_ADDR_LO 0x1e0f8
+#define regPCIEMSIX_VECT62_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT62_ADDR_HI 0x1e0f9
+#define regPCIEMSIX_VECT62_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT62_MSG_DATA 0x1e0fa
+#define regPCIEMSIX_VECT62_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT62_CONTROL 0x1e0fb
+#define regPCIEMSIX_VECT62_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT63_ADDR_LO 0x1e0fc
+#define regPCIEMSIX_VECT63_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT63_ADDR_HI 0x1e0fd
+#define regPCIEMSIX_VECT63_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT63_MSG_DATA 0x1e0fe
+#define regPCIEMSIX_VECT63_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT63_CONTROL 0x1e0ff
+#define regPCIEMSIX_VECT63_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT64_ADDR_LO 0x1e100
+#define regPCIEMSIX_VECT64_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT64_ADDR_HI 0x1e101
+#define regPCIEMSIX_VECT64_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT64_MSG_DATA 0x1e102
+#define regPCIEMSIX_VECT64_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT64_CONTROL 0x1e103
+#define regPCIEMSIX_VECT64_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT65_ADDR_LO 0x1e104
+#define regPCIEMSIX_VECT65_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT65_ADDR_HI 0x1e105
+#define regPCIEMSIX_VECT65_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT65_MSG_DATA 0x1e106
+#define regPCIEMSIX_VECT65_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT65_CONTROL 0x1e107
+#define regPCIEMSIX_VECT65_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT66_ADDR_LO 0x1e108
+#define regPCIEMSIX_VECT66_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT66_ADDR_HI 0x1e109
+#define regPCIEMSIX_VECT66_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT66_MSG_DATA 0x1e10a
+#define regPCIEMSIX_VECT66_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT66_CONTROL 0x1e10b
+#define regPCIEMSIX_VECT66_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT67_ADDR_LO 0x1e10c
+#define regPCIEMSIX_VECT67_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT67_ADDR_HI 0x1e10d
+#define regPCIEMSIX_VECT67_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT67_MSG_DATA 0x1e10e
+#define regPCIEMSIX_VECT67_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT67_CONTROL 0x1e10f
+#define regPCIEMSIX_VECT67_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT68_ADDR_LO 0x1e110
+#define regPCIEMSIX_VECT68_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT68_ADDR_HI 0x1e111
+#define regPCIEMSIX_VECT68_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT68_MSG_DATA 0x1e112
+#define regPCIEMSIX_VECT68_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT68_CONTROL 0x1e113
+#define regPCIEMSIX_VECT68_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT69_ADDR_LO 0x1e114
+#define regPCIEMSIX_VECT69_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT69_ADDR_HI 0x1e115
+#define regPCIEMSIX_VECT69_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT69_MSG_DATA 0x1e116
+#define regPCIEMSIX_VECT69_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT69_CONTROL 0x1e117
+#define regPCIEMSIX_VECT69_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT70_ADDR_LO 0x1e118
+#define regPCIEMSIX_VECT70_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT70_ADDR_HI 0x1e119
+#define regPCIEMSIX_VECT70_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT70_MSG_DATA 0x1e11a
+#define regPCIEMSIX_VECT70_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT70_CONTROL 0x1e11b
+#define regPCIEMSIX_VECT70_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT71_ADDR_LO 0x1e11c
+#define regPCIEMSIX_VECT71_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT71_ADDR_HI 0x1e11d
+#define regPCIEMSIX_VECT71_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT71_MSG_DATA 0x1e11e
+#define regPCIEMSIX_VECT71_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT71_CONTROL 0x1e11f
+#define regPCIEMSIX_VECT71_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT72_ADDR_LO 0x1e120
+#define regPCIEMSIX_VECT72_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT72_ADDR_HI 0x1e121
+#define regPCIEMSIX_VECT72_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT72_MSG_DATA 0x1e122
+#define regPCIEMSIX_VECT72_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT72_CONTROL 0x1e123
+#define regPCIEMSIX_VECT72_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT73_ADDR_LO 0x1e124
+#define regPCIEMSIX_VECT73_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT73_ADDR_HI 0x1e125
+#define regPCIEMSIX_VECT73_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT73_MSG_DATA 0x1e126
+#define regPCIEMSIX_VECT73_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT73_CONTROL 0x1e127
+#define regPCIEMSIX_VECT73_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT74_ADDR_LO 0x1e128
+#define regPCIEMSIX_VECT74_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT74_ADDR_HI 0x1e129
+#define regPCIEMSIX_VECT74_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT74_MSG_DATA 0x1e12a
+#define regPCIEMSIX_VECT74_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT74_CONTROL 0x1e12b
+#define regPCIEMSIX_VECT74_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT75_ADDR_LO 0x1e12c
+#define regPCIEMSIX_VECT75_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT75_ADDR_HI 0x1e12d
+#define regPCIEMSIX_VECT75_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT75_MSG_DATA 0x1e12e
+#define regPCIEMSIX_VECT75_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT75_CONTROL 0x1e12f
+#define regPCIEMSIX_VECT75_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT76_ADDR_LO 0x1e130
+#define regPCIEMSIX_VECT76_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT76_ADDR_HI 0x1e131
+#define regPCIEMSIX_VECT76_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT76_MSG_DATA 0x1e132
+#define regPCIEMSIX_VECT76_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT76_CONTROL 0x1e133
+#define regPCIEMSIX_VECT76_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT77_ADDR_LO 0x1e134
+#define regPCIEMSIX_VECT77_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT77_ADDR_HI 0x1e135
+#define regPCIEMSIX_VECT77_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT77_MSG_DATA 0x1e136
+#define regPCIEMSIX_VECT77_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT77_CONTROL 0x1e137
+#define regPCIEMSIX_VECT77_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT78_ADDR_LO 0x1e138
+#define regPCIEMSIX_VECT78_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT78_ADDR_HI 0x1e139
+#define regPCIEMSIX_VECT78_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT78_MSG_DATA 0x1e13a
+#define regPCIEMSIX_VECT78_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT78_CONTROL 0x1e13b
+#define regPCIEMSIX_VECT78_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT79_ADDR_LO 0x1e13c
+#define regPCIEMSIX_VECT79_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT79_ADDR_HI 0x1e13d
+#define regPCIEMSIX_VECT79_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT79_MSG_DATA 0x1e13e
+#define regPCIEMSIX_VECT79_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT79_CONTROL 0x1e13f
+#define regPCIEMSIX_VECT79_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT80_ADDR_LO 0x1e140
+#define regPCIEMSIX_VECT80_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT80_ADDR_HI 0x1e141
+#define regPCIEMSIX_VECT80_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT80_MSG_DATA 0x1e142
+#define regPCIEMSIX_VECT80_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT80_CONTROL 0x1e143
+#define regPCIEMSIX_VECT80_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT81_ADDR_LO 0x1e144
+#define regPCIEMSIX_VECT81_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT81_ADDR_HI 0x1e145
+#define regPCIEMSIX_VECT81_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT81_MSG_DATA 0x1e146
+#define regPCIEMSIX_VECT81_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT81_CONTROL 0x1e147
+#define regPCIEMSIX_VECT81_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT82_ADDR_LO 0x1e148
+#define regPCIEMSIX_VECT82_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT82_ADDR_HI 0x1e149
+#define regPCIEMSIX_VECT82_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT82_MSG_DATA 0x1e14a
+#define regPCIEMSIX_VECT82_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT82_CONTROL 0x1e14b
+#define regPCIEMSIX_VECT82_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT83_ADDR_LO 0x1e14c
+#define regPCIEMSIX_VECT83_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT83_ADDR_HI 0x1e14d
+#define regPCIEMSIX_VECT83_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT83_MSG_DATA 0x1e14e
+#define regPCIEMSIX_VECT83_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT83_CONTROL 0x1e14f
+#define regPCIEMSIX_VECT83_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT84_ADDR_LO 0x1e150
+#define regPCIEMSIX_VECT84_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT84_ADDR_HI 0x1e151
+#define regPCIEMSIX_VECT84_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT84_MSG_DATA 0x1e152
+#define regPCIEMSIX_VECT84_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT84_CONTROL 0x1e153
+#define regPCIEMSIX_VECT84_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT85_ADDR_LO 0x1e154
+#define regPCIEMSIX_VECT85_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT85_ADDR_HI 0x1e155
+#define regPCIEMSIX_VECT85_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT85_MSG_DATA 0x1e156
+#define regPCIEMSIX_VECT85_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT85_CONTROL 0x1e157
+#define regPCIEMSIX_VECT85_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT86_ADDR_LO 0x1e158
+#define regPCIEMSIX_VECT86_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT86_ADDR_HI 0x1e159
+#define regPCIEMSIX_VECT86_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT86_MSG_DATA 0x1e15a
+#define regPCIEMSIX_VECT86_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT86_CONTROL 0x1e15b
+#define regPCIEMSIX_VECT86_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT87_ADDR_LO 0x1e15c
+#define regPCIEMSIX_VECT87_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT87_ADDR_HI 0x1e15d
+#define regPCIEMSIX_VECT87_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT87_MSG_DATA 0x1e15e
+#define regPCIEMSIX_VECT87_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT87_CONTROL 0x1e15f
+#define regPCIEMSIX_VECT87_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT88_ADDR_LO 0x1e160
+#define regPCIEMSIX_VECT88_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT88_ADDR_HI 0x1e161
+#define regPCIEMSIX_VECT88_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT88_MSG_DATA 0x1e162
+#define regPCIEMSIX_VECT88_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT88_CONTROL 0x1e163
+#define regPCIEMSIX_VECT88_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT89_ADDR_LO 0x1e164
+#define regPCIEMSIX_VECT89_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT89_ADDR_HI 0x1e165
+#define regPCIEMSIX_VECT89_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT89_MSG_DATA 0x1e166
+#define regPCIEMSIX_VECT89_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT89_CONTROL 0x1e167
+#define regPCIEMSIX_VECT89_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT90_ADDR_LO 0x1e168
+#define regPCIEMSIX_VECT90_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT90_ADDR_HI 0x1e169
+#define regPCIEMSIX_VECT90_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT90_MSG_DATA 0x1e16a
+#define regPCIEMSIX_VECT90_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT90_CONTROL 0x1e16b
+#define regPCIEMSIX_VECT90_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT91_ADDR_LO 0x1e16c
+#define regPCIEMSIX_VECT91_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT91_ADDR_HI 0x1e16d
+#define regPCIEMSIX_VECT91_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT91_MSG_DATA 0x1e16e
+#define regPCIEMSIX_VECT91_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT91_CONTROL 0x1e16f
+#define regPCIEMSIX_VECT91_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT92_ADDR_LO 0x1e170
+#define regPCIEMSIX_VECT92_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT92_ADDR_HI 0x1e171
+#define regPCIEMSIX_VECT92_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT92_MSG_DATA 0x1e172
+#define regPCIEMSIX_VECT92_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT92_CONTROL 0x1e173
+#define regPCIEMSIX_VECT92_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT93_ADDR_LO 0x1e174
+#define regPCIEMSIX_VECT93_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT93_ADDR_HI 0x1e175
+#define regPCIEMSIX_VECT93_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT93_MSG_DATA 0x1e176
+#define regPCIEMSIX_VECT93_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT93_CONTROL 0x1e177
+#define regPCIEMSIX_VECT93_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT94_ADDR_LO 0x1e178
+#define regPCIEMSIX_VECT94_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT94_ADDR_HI 0x1e179
+#define regPCIEMSIX_VECT94_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT94_MSG_DATA 0x1e17a
+#define regPCIEMSIX_VECT94_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT94_CONTROL 0x1e17b
+#define regPCIEMSIX_VECT94_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT95_ADDR_LO 0x1e17c
+#define regPCIEMSIX_VECT95_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT95_ADDR_HI 0x1e17d
+#define regPCIEMSIX_VECT95_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT95_MSG_DATA 0x1e17e
+#define regPCIEMSIX_VECT95_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT95_CONTROL 0x1e17f
+#define regPCIEMSIX_VECT95_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT96_ADDR_LO 0x1e180
+#define regPCIEMSIX_VECT96_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT96_ADDR_HI 0x1e181
+#define regPCIEMSIX_VECT96_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT96_MSG_DATA 0x1e182
+#define regPCIEMSIX_VECT96_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT96_CONTROL 0x1e183
+#define regPCIEMSIX_VECT96_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT97_ADDR_LO 0x1e184
+#define regPCIEMSIX_VECT97_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT97_ADDR_HI 0x1e185
+#define regPCIEMSIX_VECT97_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT97_MSG_DATA 0x1e186
+#define regPCIEMSIX_VECT97_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT97_CONTROL 0x1e187
+#define regPCIEMSIX_VECT97_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT98_ADDR_LO 0x1e188
+#define regPCIEMSIX_VECT98_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT98_ADDR_HI 0x1e189
+#define regPCIEMSIX_VECT98_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT98_MSG_DATA 0x1e18a
+#define regPCIEMSIX_VECT98_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT98_CONTROL 0x1e18b
+#define regPCIEMSIX_VECT98_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT99_ADDR_LO 0x1e18c
+#define regPCIEMSIX_VECT99_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT99_ADDR_HI 0x1e18d
+#define regPCIEMSIX_VECT99_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT99_MSG_DATA 0x1e18e
+#define regPCIEMSIX_VECT99_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT99_CONTROL 0x1e18f
+#define regPCIEMSIX_VECT99_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT100_ADDR_LO 0x1e190
+#define regPCIEMSIX_VECT100_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT100_ADDR_HI 0x1e191
+#define regPCIEMSIX_VECT100_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT100_MSG_DATA 0x1e192
+#define regPCIEMSIX_VECT100_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT100_CONTROL 0x1e193
+#define regPCIEMSIX_VECT100_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT101_ADDR_LO 0x1e194
+#define regPCIEMSIX_VECT101_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT101_ADDR_HI 0x1e195
+#define regPCIEMSIX_VECT101_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT101_MSG_DATA 0x1e196
+#define regPCIEMSIX_VECT101_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT101_CONTROL 0x1e197
+#define regPCIEMSIX_VECT101_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT102_ADDR_LO 0x1e198
+#define regPCIEMSIX_VECT102_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT102_ADDR_HI 0x1e199
+#define regPCIEMSIX_VECT102_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT102_MSG_DATA 0x1e19a
+#define regPCIEMSIX_VECT102_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT102_CONTROL 0x1e19b
+#define regPCIEMSIX_VECT102_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT103_ADDR_LO 0x1e19c
+#define regPCIEMSIX_VECT103_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT103_ADDR_HI 0x1e19d
+#define regPCIEMSIX_VECT103_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT103_MSG_DATA 0x1e19e
+#define regPCIEMSIX_VECT103_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT103_CONTROL 0x1e19f
+#define regPCIEMSIX_VECT103_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT104_ADDR_LO 0x1e1a0
+#define regPCIEMSIX_VECT104_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT104_ADDR_HI 0x1e1a1
+#define regPCIEMSIX_VECT104_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT104_MSG_DATA 0x1e1a2
+#define regPCIEMSIX_VECT104_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT104_CONTROL 0x1e1a3
+#define regPCIEMSIX_VECT104_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT105_ADDR_LO 0x1e1a4
+#define regPCIEMSIX_VECT105_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT105_ADDR_HI 0x1e1a5
+#define regPCIEMSIX_VECT105_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT105_MSG_DATA 0x1e1a6
+#define regPCIEMSIX_VECT105_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT105_CONTROL 0x1e1a7
+#define regPCIEMSIX_VECT105_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT106_ADDR_LO 0x1e1a8
+#define regPCIEMSIX_VECT106_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT106_ADDR_HI 0x1e1a9
+#define regPCIEMSIX_VECT106_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT106_MSG_DATA 0x1e1aa
+#define regPCIEMSIX_VECT106_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT106_CONTROL 0x1e1ab
+#define regPCIEMSIX_VECT106_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT107_ADDR_LO 0x1e1ac
+#define regPCIEMSIX_VECT107_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT107_ADDR_HI 0x1e1ad
+#define regPCIEMSIX_VECT107_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT107_MSG_DATA 0x1e1ae
+#define regPCIEMSIX_VECT107_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT107_CONTROL 0x1e1af
+#define regPCIEMSIX_VECT107_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT108_ADDR_LO 0x1e1b0
+#define regPCIEMSIX_VECT108_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT108_ADDR_HI 0x1e1b1
+#define regPCIEMSIX_VECT108_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT108_MSG_DATA 0x1e1b2
+#define regPCIEMSIX_VECT108_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT108_CONTROL 0x1e1b3
+#define regPCIEMSIX_VECT108_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT109_ADDR_LO 0x1e1b4
+#define regPCIEMSIX_VECT109_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT109_ADDR_HI 0x1e1b5
+#define regPCIEMSIX_VECT109_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT109_MSG_DATA 0x1e1b6
+#define regPCIEMSIX_VECT109_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT109_CONTROL 0x1e1b7
+#define regPCIEMSIX_VECT109_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT110_ADDR_LO 0x1e1b8
+#define regPCIEMSIX_VECT110_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT110_ADDR_HI 0x1e1b9
+#define regPCIEMSIX_VECT110_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT110_MSG_DATA 0x1e1ba
+#define regPCIEMSIX_VECT110_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT110_CONTROL 0x1e1bb
+#define regPCIEMSIX_VECT110_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT111_ADDR_LO 0x1e1bc
+#define regPCIEMSIX_VECT111_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT111_ADDR_HI 0x1e1bd
+#define regPCIEMSIX_VECT111_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT111_MSG_DATA 0x1e1be
+#define regPCIEMSIX_VECT111_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT111_CONTROL 0x1e1bf
+#define regPCIEMSIX_VECT111_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT112_ADDR_LO 0x1e1c0
+#define regPCIEMSIX_VECT112_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT112_ADDR_HI 0x1e1c1
+#define regPCIEMSIX_VECT112_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT112_MSG_DATA 0x1e1c2
+#define regPCIEMSIX_VECT112_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT112_CONTROL 0x1e1c3
+#define regPCIEMSIX_VECT112_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT113_ADDR_LO 0x1e1c4
+#define regPCIEMSIX_VECT113_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT113_ADDR_HI 0x1e1c5
+#define regPCIEMSIX_VECT113_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT113_MSG_DATA 0x1e1c6
+#define regPCIEMSIX_VECT113_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT113_CONTROL 0x1e1c7
+#define regPCIEMSIX_VECT113_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT114_ADDR_LO 0x1e1c8
+#define regPCIEMSIX_VECT114_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT114_ADDR_HI 0x1e1c9
+#define regPCIEMSIX_VECT114_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT114_MSG_DATA 0x1e1ca
+#define regPCIEMSIX_VECT114_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT114_CONTROL 0x1e1cb
+#define regPCIEMSIX_VECT114_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT115_ADDR_LO 0x1e1cc
+#define regPCIEMSIX_VECT115_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT115_ADDR_HI 0x1e1cd
+#define regPCIEMSIX_VECT115_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT115_MSG_DATA 0x1e1ce
+#define regPCIEMSIX_VECT115_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT115_CONTROL 0x1e1cf
+#define regPCIEMSIX_VECT115_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT116_ADDR_LO 0x1e1d0
+#define regPCIEMSIX_VECT116_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT116_ADDR_HI 0x1e1d1
+#define regPCIEMSIX_VECT116_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT116_MSG_DATA 0x1e1d2
+#define regPCIEMSIX_VECT116_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT116_CONTROL 0x1e1d3
+#define regPCIEMSIX_VECT116_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT117_ADDR_LO 0x1e1d4
+#define regPCIEMSIX_VECT117_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT117_ADDR_HI 0x1e1d5
+#define regPCIEMSIX_VECT117_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT117_MSG_DATA 0x1e1d6
+#define regPCIEMSIX_VECT117_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT117_CONTROL 0x1e1d7
+#define regPCIEMSIX_VECT117_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT118_ADDR_LO 0x1e1d8
+#define regPCIEMSIX_VECT118_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT118_ADDR_HI 0x1e1d9
+#define regPCIEMSIX_VECT118_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT118_MSG_DATA 0x1e1da
+#define regPCIEMSIX_VECT118_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT118_CONTROL 0x1e1db
+#define regPCIEMSIX_VECT118_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT119_ADDR_LO 0x1e1dc
+#define regPCIEMSIX_VECT119_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT119_ADDR_HI 0x1e1dd
+#define regPCIEMSIX_VECT119_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT119_MSG_DATA 0x1e1de
+#define regPCIEMSIX_VECT119_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT119_CONTROL 0x1e1df
+#define regPCIEMSIX_VECT119_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT120_ADDR_LO 0x1e1e0
+#define regPCIEMSIX_VECT120_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT120_ADDR_HI 0x1e1e1
+#define regPCIEMSIX_VECT120_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT120_MSG_DATA 0x1e1e2
+#define regPCIEMSIX_VECT120_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT120_CONTROL 0x1e1e3
+#define regPCIEMSIX_VECT120_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT121_ADDR_LO 0x1e1e4
+#define regPCIEMSIX_VECT121_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT121_ADDR_HI 0x1e1e5
+#define regPCIEMSIX_VECT121_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT121_MSG_DATA 0x1e1e6
+#define regPCIEMSIX_VECT121_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT121_CONTROL 0x1e1e7
+#define regPCIEMSIX_VECT121_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT122_ADDR_LO 0x1e1e8
+#define regPCIEMSIX_VECT122_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT122_ADDR_HI 0x1e1e9
+#define regPCIEMSIX_VECT122_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT122_MSG_DATA 0x1e1ea
+#define regPCIEMSIX_VECT122_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT122_CONTROL 0x1e1eb
+#define regPCIEMSIX_VECT122_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT123_ADDR_LO 0x1e1ec
+#define regPCIEMSIX_VECT123_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT123_ADDR_HI 0x1e1ed
+#define regPCIEMSIX_VECT123_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT123_MSG_DATA 0x1e1ee
+#define regPCIEMSIX_VECT123_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT123_CONTROL 0x1e1ef
+#define regPCIEMSIX_VECT123_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT124_ADDR_LO 0x1e1f0
+#define regPCIEMSIX_VECT124_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT124_ADDR_HI 0x1e1f1
+#define regPCIEMSIX_VECT124_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT124_MSG_DATA 0x1e1f2
+#define regPCIEMSIX_VECT124_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT124_CONTROL 0x1e1f3
+#define regPCIEMSIX_VECT124_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT125_ADDR_LO 0x1e1f4
+#define regPCIEMSIX_VECT125_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT125_ADDR_HI 0x1e1f5
+#define regPCIEMSIX_VECT125_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT125_MSG_DATA 0x1e1f6
+#define regPCIEMSIX_VECT125_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT125_CONTROL 0x1e1f7
+#define regPCIEMSIX_VECT125_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT126_ADDR_LO 0x1e1f8
+#define regPCIEMSIX_VECT126_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT126_ADDR_HI 0x1e1f9
+#define regPCIEMSIX_VECT126_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT126_MSG_DATA 0x1e1fa
+#define regPCIEMSIX_VECT126_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT126_CONTROL 0x1e1fb
+#define regPCIEMSIX_VECT126_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT127_ADDR_LO 0x1e1fc
+#define regPCIEMSIX_VECT127_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT127_ADDR_HI 0x1e1fd
+#define regPCIEMSIX_VECT127_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT127_MSG_DATA 0x1e1fe
+#define regPCIEMSIX_VECT127_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT127_CONTROL 0x1e1ff
+#define regPCIEMSIX_VECT127_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT128_ADDR_LO 0x1e200
+#define regPCIEMSIX_VECT128_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT128_ADDR_HI 0x1e201
+#define regPCIEMSIX_VECT128_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT128_MSG_DATA 0x1e202
+#define regPCIEMSIX_VECT128_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT128_CONTROL 0x1e203
+#define regPCIEMSIX_VECT128_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT129_ADDR_LO 0x1e204
+#define regPCIEMSIX_VECT129_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT129_ADDR_HI 0x1e205
+#define regPCIEMSIX_VECT129_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT129_MSG_DATA 0x1e206
+#define regPCIEMSIX_VECT129_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT129_CONTROL 0x1e207
+#define regPCIEMSIX_VECT129_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT130_ADDR_LO 0x1e208
+#define regPCIEMSIX_VECT130_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT130_ADDR_HI 0x1e209
+#define regPCIEMSIX_VECT130_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT130_MSG_DATA 0x1e20a
+#define regPCIEMSIX_VECT130_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT130_CONTROL 0x1e20b
+#define regPCIEMSIX_VECT130_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT131_ADDR_LO 0x1e20c
+#define regPCIEMSIX_VECT131_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT131_ADDR_HI 0x1e20d
+#define regPCIEMSIX_VECT131_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT131_MSG_DATA 0x1e20e
+#define regPCIEMSIX_VECT131_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT131_CONTROL 0x1e20f
+#define regPCIEMSIX_VECT131_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT132_ADDR_LO 0x1e210
+#define regPCIEMSIX_VECT132_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT132_ADDR_HI 0x1e211
+#define regPCIEMSIX_VECT132_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT132_MSG_DATA 0x1e212
+#define regPCIEMSIX_VECT132_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT132_CONTROL 0x1e213
+#define regPCIEMSIX_VECT132_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT133_ADDR_LO 0x1e214
+#define regPCIEMSIX_VECT133_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT133_ADDR_HI 0x1e215
+#define regPCIEMSIX_VECT133_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT133_MSG_DATA 0x1e216
+#define regPCIEMSIX_VECT133_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT133_CONTROL 0x1e217
+#define regPCIEMSIX_VECT133_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT134_ADDR_LO 0x1e218
+#define regPCIEMSIX_VECT134_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT134_ADDR_HI 0x1e219
+#define regPCIEMSIX_VECT134_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT134_MSG_DATA 0x1e21a
+#define regPCIEMSIX_VECT134_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT134_CONTROL 0x1e21b
+#define regPCIEMSIX_VECT134_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT135_ADDR_LO 0x1e21c
+#define regPCIEMSIX_VECT135_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT135_ADDR_HI 0x1e21d
+#define regPCIEMSIX_VECT135_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT135_MSG_DATA 0x1e21e
+#define regPCIEMSIX_VECT135_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT135_CONTROL 0x1e21f
+#define regPCIEMSIX_VECT135_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT136_ADDR_LO 0x1e220
+#define regPCIEMSIX_VECT136_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT136_ADDR_HI 0x1e221
+#define regPCIEMSIX_VECT136_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT136_MSG_DATA 0x1e222
+#define regPCIEMSIX_VECT136_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT136_CONTROL 0x1e223
+#define regPCIEMSIX_VECT136_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT137_ADDR_LO 0x1e224
+#define regPCIEMSIX_VECT137_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT137_ADDR_HI 0x1e225
+#define regPCIEMSIX_VECT137_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT137_MSG_DATA 0x1e226
+#define regPCIEMSIX_VECT137_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT137_CONTROL 0x1e227
+#define regPCIEMSIX_VECT137_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT138_ADDR_LO 0x1e228
+#define regPCIEMSIX_VECT138_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT138_ADDR_HI 0x1e229
+#define regPCIEMSIX_VECT138_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT138_MSG_DATA 0x1e22a
+#define regPCIEMSIX_VECT138_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT138_CONTROL 0x1e22b
+#define regPCIEMSIX_VECT138_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT139_ADDR_LO 0x1e22c
+#define regPCIEMSIX_VECT139_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT139_ADDR_HI 0x1e22d
+#define regPCIEMSIX_VECT139_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT139_MSG_DATA 0x1e22e
+#define regPCIEMSIX_VECT139_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT139_CONTROL 0x1e22f
+#define regPCIEMSIX_VECT139_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT140_ADDR_LO 0x1e230
+#define regPCIEMSIX_VECT140_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT140_ADDR_HI 0x1e231
+#define regPCIEMSIX_VECT140_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT140_MSG_DATA 0x1e232
+#define regPCIEMSIX_VECT140_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT140_CONTROL 0x1e233
+#define regPCIEMSIX_VECT140_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT141_ADDR_LO 0x1e234
+#define regPCIEMSIX_VECT141_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT141_ADDR_HI 0x1e235
+#define regPCIEMSIX_VECT141_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT141_MSG_DATA 0x1e236
+#define regPCIEMSIX_VECT141_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT141_CONTROL 0x1e237
+#define regPCIEMSIX_VECT141_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT142_ADDR_LO 0x1e238
+#define regPCIEMSIX_VECT142_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT142_ADDR_HI 0x1e239
+#define regPCIEMSIX_VECT142_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT142_MSG_DATA 0x1e23a
+#define regPCIEMSIX_VECT142_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT142_CONTROL 0x1e23b
+#define regPCIEMSIX_VECT142_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT143_ADDR_LO 0x1e23c
+#define regPCIEMSIX_VECT143_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT143_ADDR_HI 0x1e23d
+#define regPCIEMSIX_VECT143_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT143_MSG_DATA 0x1e23e
+#define regPCIEMSIX_VECT143_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT143_CONTROL 0x1e23f
+#define regPCIEMSIX_VECT143_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT144_ADDR_LO 0x1e240
+#define regPCIEMSIX_VECT144_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT144_ADDR_HI 0x1e241
+#define regPCIEMSIX_VECT144_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT144_MSG_DATA 0x1e242
+#define regPCIEMSIX_VECT144_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT144_CONTROL 0x1e243
+#define regPCIEMSIX_VECT144_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT145_ADDR_LO 0x1e244
+#define regPCIEMSIX_VECT145_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT145_ADDR_HI 0x1e245
+#define regPCIEMSIX_VECT145_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT145_MSG_DATA 0x1e246
+#define regPCIEMSIX_VECT145_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT145_CONTROL 0x1e247
+#define regPCIEMSIX_VECT145_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT146_ADDR_LO 0x1e248
+#define regPCIEMSIX_VECT146_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT146_ADDR_HI 0x1e249
+#define regPCIEMSIX_VECT146_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT146_MSG_DATA 0x1e24a
+#define regPCIEMSIX_VECT146_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT146_CONTROL 0x1e24b
+#define regPCIEMSIX_VECT146_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT147_ADDR_LO 0x1e24c
+#define regPCIEMSIX_VECT147_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT147_ADDR_HI 0x1e24d
+#define regPCIEMSIX_VECT147_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT147_MSG_DATA 0x1e24e
+#define regPCIEMSIX_VECT147_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT147_CONTROL 0x1e24f
+#define regPCIEMSIX_VECT147_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT148_ADDR_LO 0x1e250
+#define regPCIEMSIX_VECT148_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT148_ADDR_HI 0x1e251
+#define regPCIEMSIX_VECT148_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT148_MSG_DATA 0x1e252
+#define regPCIEMSIX_VECT148_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT148_CONTROL 0x1e253
+#define regPCIEMSIX_VECT148_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT149_ADDR_LO 0x1e254
+#define regPCIEMSIX_VECT149_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT149_ADDR_HI 0x1e255
+#define regPCIEMSIX_VECT149_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT149_MSG_DATA 0x1e256
+#define regPCIEMSIX_VECT149_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT149_CONTROL 0x1e257
+#define regPCIEMSIX_VECT149_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT150_ADDR_LO 0x1e258
+#define regPCIEMSIX_VECT150_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT150_ADDR_HI 0x1e259
+#define regPCIEMSIX_VECT150_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT150_MSG_DATA 0x1e25a
+#define regPCIEMSIX_VECT150_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT150_CONTROL 0x1e25b
+#define regPCIEMSIX_VECT150_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT151_ADDR_LO 0x1e25c
+#define regPCIEMSIX_VECT151_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT151_ADDR_HI 0x1e25d
+#define regPCIEMSIX_VECT151_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT151_MSG_DATA 0x1e25e
+#define regPCIEMSIX_VECT151_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT151_CONTROL 0x1e25f
+#define regPCIEMSIX_VECT151_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT152_ADDR_LO 0x1e260
+#define regPCIEMSIX_VECT152_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT152_ADDR_HI 0x1e261
+#define regPCIEMSIX_VECT152_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT152_MSG_DATA 0x1e262
+#define regPCIEMSIX_VECT152_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT152_CONTROL 0x1e263
+#define regPCIEMSIX_VECT152_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT153_ADDR_LO 0x1e264
+#define regPCIEMSIX_VECT153_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT153_ADDR_HI 0x1e265
+#define regPCIEMSIX_VECT153_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT153_MSG_DATA 0x1e266
+#define regPCIEMSIX_VECT153_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT153_CONTROL 0x1e267
+#define regPCIEMSIX_VECT153_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT154_ADDR_LO 0x1e268
+#define regPCIEMSIX_VECT154_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT154_ADDR_HI 0x1e269
+#define regPCIEMSIX_VECT154_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT154_MSG_DATA 0x1e26a
+#define regPCIEMSIX_VECT154_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT154_CONTROL 0x1e26b
+#define regPCIEMSIX_VECT154_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT155_ADDR_LO 0x1e26c
+#define regPCIEMSIX_VECT155_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT155_ADDR_HI 0x1e26d
+#define regPCIEMSIX_VECT155_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT155_MSG_DATA 0x1e26e
+#define regPCIEMSIX_VECT155_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT155_CONTROL 0x1e26f
+#define regPCIEMSIX_VECT155_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT156_ADDR_LO 0x1e270
+#define regPCIEMSIX_VECT156_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT156_ADDR_HI 0x1e271
+#define regPCIEMSIX_VECT156_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT156_MSG_DATA 0x1e272
+#define regPCIEMSIX_VECT156_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT156_CONTROL 0x1e273
+#define regPCIEMSIX_VECT156_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT157_ADDR_LO 0x1e274
+#define regPCIEMSIX_VECT157_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT157_ADDR_HI 0x1e275
+#define regPCIEMSIX_VECT157_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT157_MSG_DATA 0x1e276
+#define regPCIEMSIX_VECT157_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT157_CONTROL 0x1e277
+#define regPCIEMSIX_VECT157_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT158_ADDR_LO 0x1e278
+#define regPCIEMSIX_VECT158_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT158_ADDR_HI 0x1e279
+#define regPCIEMSIX_VECT158_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT158_MSG_DATA 0x1e27a
+#define regPCIEMSIX_VECT158_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT158_CONTROL 0x1e27b
+#define regPCIEMSIX_VECT158_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT159_ADDR_LO 0x1e27c
+#define regPCIEMSIX_VECT159_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT159_ADDR_HI 0x1e27d
+#define regPCIEMSIX_VECT159_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT159_MSG_DATA 0x1e27e
+#define regPCIEMSIX_VECT159_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT159_CONTROL 0x1e27f
+#define regPCIEMSIX_VECT159_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT160_ADDR_LO 0x1e280
+#define regPCIEMSIX_VECT160_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT160_ADDR_HI 0x1e281
+#define regPCIEMSIX_VECT160_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT160_MSG_DATA 0x1e282
+#define regPCIEMSIX_VECT160_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT160_CONTROL 0x1e283
+#define regPCIEMSIX_VECT160_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT161_ADDR_LO 0x1e284
+#define regPCIEMSIX_VECT161_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT161_ADDR_HI 0x1e285
+#define regPCIEMSIX_VECT161_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT161_MSG_DATA 0x1e286
+#define regPCIEMSIX_VECT161_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT161_CONTROL 0x1e287
+#define regPCIEMSIX_VECT161_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT162_ADDR_LO 0x1e288
+#define regPCIEMSIX_VECT162_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT162_ADDR_HI 0x1e289
+#define regPCIEMSIX_VECT162_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT162_MSG_DATA 0x1e28a
+#define regPCIEMSIX_VECT162_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT162_CONTROL 0x1e28b
+#define regPCIEMSIX_VECT162_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT163_ADDR_LO 0x1e28c
+#define regPCIEMSIX_VECT163_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT163_ADDR_HI 0x1e28d
+#define regPCIEMSIX_VECT163_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT163_MSG_DATA 0x1e28e
+#define regPCIEMSIX_VECT163_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT163_CONTROL 0x1e28f
+#define regPCIEMSIX_VECT163_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT164_ADDR_LO 0x1e290
+#define regPCIEMSIX_VECT164_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT164_ADDR_HI 0x1e291
+#define regPCIEMSIX_VECT164_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT164_MSG_DATA 0x1e292
+#define regPCIEMSIX_VECT164_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT164_CONTROL 0x1e293
+#define regPCIEMSIX_VECT164_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT165_ADDR_LO 0x1e294
+#define regPCIEMSIX_VECT165_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT165_ADDR_HI 0x1e295
+#define regPCIEMSIX_VECT165_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT165_MSG_DATA 0x1e296
+#define regPCIEMSIX_VECT165_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT165_CONTROL 0x1e297
+#define regPCIEMSIX_VECT165_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT166_ADDR_LO 0x1e298
+#define regPCIEMSIX_VECT166_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT166_ADDR_HI 0x1e299
+#define regPCIEMSIX_VECT166_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT166_MSG_DATA 0x1e29a
+#define regPCIEMSIX_VECT166_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT166_CONTROL 0x1e29b
+#define regPCIEMSIX_VECT166_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT167_ADDR_LO 0x1e29c
+#define regPCIEMSIX_VECT167_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT167_ADDR_HI 0x1e29d
+#define regPCIEMSIX_VECT167_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT167_MSG_DATA 0x1e29e
+#define regPCIEMSIX_VECT167_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT167_CONTROL 0x1e29f
+#define regPCIEMSIX_VECT167_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT168_ADDR_LO 0x1e2a0
+#define regPCIEMSIX_VECT168_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT168_ADDR_HI 0x1e2a1
+#define regPCIEMSIX_VECT168_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT168_MSG_DATA 0x1e2a2
+#define regPCIEMSIX_VECT168_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT168_CONTROL 0x1e2a3
+#define regPCIEMSIX_VECT168_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT169_ADDR_LO 0x1e2a4
+#define regPCIEMSIX_VECT169_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT169_ADDR_HI 0x1e2a5
+#define regPCIEMSIX_VECT169_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT169_MSG_DATA 0x1e2a6
+#define regPCIEMSIX_VECT169_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT169_CONTROL 0x1e2a7
+#define regPCIEMSIX_VECT169_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT170_ADDR_LO 0x1e2a8
+#define regPCIEMSIX_VECT170_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT170_ADDR_HI 0x1e2a9
+#define regPCIEMSIX_VECT170_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT170_MSG_DATA 0x1e2aa
+#define regPCIEMSIX_VECT170_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT170_CONTROL 0x1e2ab
+#define regPCIEMSIX_VECT170_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT171_ADDR_LO 0x1e2ac
+#define regPCIEMSIX_VECT171_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT171_ADDR_HI 0x1e2ad
+#define regPCIEMSIX_VECT171_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT171_MSG_DATA 0x1e2ae
+#define regPCIEMSIX_VECT171_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT171_CONTROL 0x1e2af
+#define regPCIEMSIX_VECT171_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT172_ADDR_LO 0x1e2b0
+#define regPCIEMSIX_VECT172_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT172_ADDR_HI 0x1e2b1
+#define regPCIEMSIX_VECT172_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT172_MSG_DATA 0x1e2b2
+#define regPCIEMSIX_VECT172_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT172_CONTROL 0x1e2b3
+#define regPCIEMSIX_VECT172_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT173_ADDR_LO 0x1e2b4
+#define regPCIEMSIX_VECT173_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT173_ADDR_HI 0x1e2b5
+#define regPCIEMSIX_VECT173_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT173_MSG_DATA 0x1e2b6
+#define regPCIEMSIX_VECT173_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT173_CONTROL 0x1e2b7
+#define regPCIEMSIX_VECT173_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT174_ADDR_LO 0x1e2b8
+#define regPCIEMSIX_VECT174_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT174_ADDR_HI 0x1e2b9
+#define regPCIEMSIX_VECT174_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT174_MSG_DATA 0x1e2ba
+#define regPCIEMSIX_VECT174_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT174_CONTROL 0x1e2bb
+#define regPCIEMSIX_VECT174_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT175_ADDR_LO 0x1e2bc
+#define regPCIEMSIX_VECT175_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT175_ADDR_HI 0x1e2bd
+#define regPCIEMSIX_VECT175_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT175_MSG_DATA 0x1e2be
+#define regPCIEMSIX_VECT175_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT175_CONTROL 0x1e2bf
+#define regPCIEMSIX_VECT175_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT176_ADDR_LO 0x1e2c0
+#define regPCIEMSIX_VECT176_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT176_ADDR_HI 0x1e2c1
+#define regPCIEMSIX_VECT176_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT176_MSG_DATA 0x1e2c2
+#define regPCIEMSIX_VECT176_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT176_CONTROL 0x1e2c3
+#define regPCIEMSIX_VECT176_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT177_ADDR_LO 0x1e2c4
+#define regPCIEMSIX_VECT177_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT177_ADDR_HI 0x1e2c5
+#define regPCIEMSIX_VECT177_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT177_MSG_DATA 0x1e2c6
+#define regPCIEMSIX_VECT177_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT177_CONTROL 0x1e2c7
+#define regPCIEMSIX_VECT177_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT178_ADDR_LO 0x1e2c8
+#define regPCIEMSIX_VECT178_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT178_ADDR_HI 0x1e2c9
+#define regPCIEMSIX_VECT178_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT178_MSG_DATA 0x1e2ca
+#define regPCIEMSIX_VECT178_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT178_CONTROL 0x1e2cb
+#define regPCIEMSIX_VECT178_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT179_ADDR_LO 0x1e2cc
+#define regPCIEMSIX_VECT179_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT179_ADDR_HI 0x1e2cd
+#define regPCIEMSIX_VECT179_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT179_MSG_DATA 0x1e2ce
+#define regPCIEMSIX_VECT179_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT179_CONTROL 0x1e2cf
+#define regPCIEMSIX_VECT179_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT180_ADDR_LO 0x1e2d0
+#define regPCIEMSIX_VECT180_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT180_ADDR_HI 0x1e2d1
+#define regPCIEMSIX_VECT180_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT180_MSG_DATA 0x1e2d2
+#define regPCIEMSIX_VECT180_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT180_CONTROL 0x1e2d3
+#define regPCIEMSIX_VECT180_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT181_ADDR_LO 0x1e2d4
+#define regPCIEMSIX_VECT181_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT181_ADDR_HI 0x1e2d5
+#define regPCIEMSIX_VECT181_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT181_MSG_DATA 0x1e2d6
+#define regPCIEMSIX_VECT181_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT181_CONTROL 0x1e2d7
+#define regPCIEMSIX_VECT181_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT182_ADDR_LO 0x1e2d8
+#define regPCIEMSIX_VECT182_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT182_ADDR_HI 0x1e2d9
+#define regPCIEMSIX_VECT182_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT182_MSG_DATA 0x1e2da
+#define regPCIEMSIX_VECT182_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT182_CONTROL 0x1e2db
+#define regPCIEMSIX_VECT182_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT183_ADDR_LO 0x1e2dc
+#define regPCIEMSIX_VECT183_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT183_ADDR_HI 0x1e2dd
+#define regPCIEMSIX_VECT183_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT183_MSG_DATA 0x1e2de
+#define regPCIEMSIX_VECT183_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT183_CONTROL 0x1e2df
+#define regPCIEMSIX_VECT183_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT184_ADDR_LO 0x1e2e0
+#define regPCIEMSIX_VECT184_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT184_ADDR_HI 0x1e2e1
+#define regPCIEMSIX_VECT184_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT184_MSG_DATA 0x1e2e2
+#define regPCIEMSIX_VECT184_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT184_CONTROL 0x1e2e3
+#define regPCIEMSIX_VECT184_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT185_ADDR_LO 0x1e2e4
+#define regPCIEMSIX_VECT185_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT185_ADDR_HI 0x1e2e5
+#define regPCIEMSIX_VECT185_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT185_MSG_DATA 0x1e2e6
+#define regPCIEMSIX_VECT185_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT185_CONTROL 0x1e2e7
+#define regPCIEMSIX_VECT185_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT186_ADDR_LO 0x1e2e8
+#define regPCIEMSIX_VECT186_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT186_ADDR_HI 0x1e2e9
+#define regPCIEMSIX_VECT186_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT186_MSG_DATA 0x1e2ea
+#define regPCIEMSIX_VECT186_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT186_CONTROL 0x1e2eb
+#define regPCIEMSIX_VECT186_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT187_ADDR_LO 0x1e2ec
+#define regPCIEMSIX_VECT187_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT187_ADDR_HI 0x1e2ed
+#define regPCIEMSIX_VECT187_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT187_MSG_DATA 0x1e2ee
+#define regPCIEMSIX_VECT187_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT187_CONTROL 0x1e2ef
+#define regPCIEMSIX_VECT187_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT188_ADDR_LO 0x1e2f0
+#define regPCIEMSIX_VECT188_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT188_ADDR_HI 0x1e2f1
+#define regPCIEMSIX_VECT188_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT188_MSG_DATA 0x1e2f2
+#define regPCIEMSIX_VECT188_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT188_CONTROL 0x1e2f3
+#define regPCIEMSIX_VECT188_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT189_ADDR_LO 0x1e2f4
+#define regPCIEMSIX_VECT189_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT189_ADDR_HI 0x1e2f5
+#define regPCIEMSIX_VECT189_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT189_MSG_DATA 0x1e2f6
+#define regPCIEMSIX_VECT189_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT189_CONTROL 0x1e2f7
+#define regPCIEMSIX_VECT189_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT190_ADDR_LO 0x1e2f8
+#define regPCIEMSIX_VECT190_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT190_ADDR_HI 0x1e2f9
+#define regPCIEMSIX_VECT190_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT190_MSG_DATA 0x1e2fa
+#define regPCIEMSIX_VECT190_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT190_CONTROL 0x1e2fb
+#define regPCIEMSIX_VECT190_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT191_ADDR_LO 0x1e2fc
+#define regPCIEMSIX_VECT191_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT191_ADDR_HI 0x1e2fd
+#define regPCIEMSIX_VECT191_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT191_MSG_DATA 0x1e2fe
+#define regPCIEMSIX_VECT191_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT191_CONTROL 0x1e2ff
+#define regPCIEMSIX_VECT191_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT192_ADDR_LO 0x1e300
+#define regPCIEMSIX_VECT192_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT192_ADDR_HI 0x1e301
+#define regPCIEMSIX_VECT192_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT192_MSG_DATA 0x1e302
+#define regPCIEMSIX_VECT192_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT192_CONTROL 0x1e303
+#define regPCIEMSIX_VECT192_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT193_ADDR_LO 0x1e304
+#define regPCIEMSIX_VECT193_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT193_ADDR_HI 0x1e305
+#define regPCIEMSIX_VECT193_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT193_MSG_DATA 0x1e306
+#define regPCIEMSIX_VECT193_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT193_CONTROL 0x1e307
+#define regPCIEMSIX_VECT193_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT194_ADDR_LO 0x1e308
+#define regPCIEMSIX_VECT194_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT194_ADDR_HI 0x1e309
+#define regPCIEMSIX_VECT194_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT194_MSG_DATA 0x1e30a
+#define regPCIEMSIX_VECT194_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT194_CONTROL 0x1e30b
+#define regPCIEMSIX_VECT194_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT195_ADDR_LO 0x1e30c
+#define regPCIEMSIX_VECT195_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT195_ADDR_HI 0x1e30d
+#define regPCIEMSIX_VECT195_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT195_MSG_DATA 0x1e30e
+#define regPCIEMSIX_VECT195_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT195_CONTROL 0x1e30f
+#define regPCIEMSIX_VECT195_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT196_ADDR_LO 0x1e310
+#define regPCIEMSIX_VECT196_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT196_ADDR_HI 0x1e311
+#define regPCIEMSIX_VECT196_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT196_MSG_DATA 0x1e312
+#define regPCIEMSIX_VECT196_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT196_CONTROL 0x1e313
+#define regPCIEMSIX_VECT196_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT197_ADDR_LO 0x1e314
+#define regPCIEMSIX_VECT197_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT197_ADDR_HI 0x1e315
+#define regPCIEMSIX_VECT197_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT197_MSG_DATA 0x1e316
+#define regPCIEMSIX_VECT197_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT197_CONTROL 0x1e317
+#define regPCIEMSIX_VECT197_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT198_ADDR_LO 0x1e318
+#define regPCIEMSIX_VECT198_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT198_ADDR_HI 0x1e319
+#define regPCIEMSIX_VECT198_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT198_MSG_DATA 0x1e31a
+#define regPCIEMSIX_VECT198_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT198_CONTROL 0x1e31b
+#define regPCIEMSIX_VECT198_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT199_ADDR_LO 0x1e31c
+#define regPCIEMSIX_VECT199_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT199_ADDR_HI 0x1e31d
+#define regPCIEMSIX_VECT199_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT199_MSG_DATA 0x1e31e
+#define regPCIEMSIX_VECT199_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT199_CONTROL 0x1e31f
+#define regPCIEMSIX_VECT199_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT200_ADDR_LO 0x1e320
+#define regPCIEMSIX_VECT200_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT200_ADDR_HI 0x1e321
+#define regPCIEMSIX_VECT200_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT200_MSG_DATA 0x1e322
+#define regPCIEMSIX_VECT200_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT200_CONTROL 0x1e323
+#define regPCIEMSIX_VECT200_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT201_ADDR_LO 0x1e324
+#define regPCIEMSIX_VECT201_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT201_ADDR_HI 0x1e325
+#define regPCIEMSIX_VECT201_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT201_MSG_DATA 0x1e326
+#define regPCIEMSIX_VECT201_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT201_CONTROL 0x1e327
+#define regPCIEMSIX_VECT201_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT202_ADDR_LO 0x1e328
+#define regPCIEMSIX_VECT202_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT202_ADDR_HI 0x1e329
+#define regPCIEMSIX_VECT202_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT202_MSG_DATA 0x1e32a
+#define regPCIEMSIX_VECT202_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT202_CONTROL 0x1e32b
+#define regPCIEMSIX_VECT202_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT203_ADDR_LO 0x1e32c
+#define regPCIEMSIX_VECT203_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT203_ADDR_HI 0x1e32d
+#define regPCIEMSIX_VECT203_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT203_MSG_DATA 0x1e32e
+#define regPCIEMSIX_VECT203_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT203_CONTROL 0x1e32f
+#define regPCIEMSIX_VECT203_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT204_ADDR_LO 0x1e330
+#define regPCIEMSIX_VECT204_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT204_ADDR_HI 0x1e331
+#define regPCIEMSIX_VECT204_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT204_MSG_DATA 0x1e332
+#define regPCIEMSIX_VECT204_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT204_CONTROL 0x1e333
+#define regPCIEMSIX_VECT204_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT205_ADDR_LO 0x1e334
+#define regPCIEMSIX_VECT205_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT205_ADDR_HI 0x1e335
+#define regPCIEMSIX_VECT205_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT205_MSG_DATA 0x1e336
+#define regPCIEMSIX_VECT205_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT205_CONTROL 0x1e337
+#define regPCIEMSIX_VECT205_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT206_ADDR_LO 0x1e338
+#define regPCIEMSIX_VECT206_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT206_ADDR_HI 0x1e339
+#define regPCIEMSIX_VECT206_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT206_MSG_DATA 0x1e33a
+#define regPCIEMSIX_VECT206_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT206_CONTROL 0x1e33b
+#define regPCIEMSIX_VECT206_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT207_ADDR_LO 0x1e33c
+#define regPCIEMSIX_VECT207_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT207_ADDR_HI 0x1e33d
+#define regPCIEMSIX_VECT207_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT207_MSG_DATA 0x1e33e
+#define regPCIEMSIX_VECT207_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT207_CONTROL 0x1e33f
+#define regPCIEMSIX_VECT207_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT208_ADDR_LO 0x1e340
+#define regPCIEMSIX_VECT208_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT208_ADDR_HI 0x1e341
+#define regPCIEMSIX_VECT208_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT208_MSG_DATA 0x1e342
+#define regPCIEMSIX_VECT208_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT208_CONTROL 0x1e343
+#define regPCIEMSIX_VECT208_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT209_ADDR_LO 0x1e344
+#define regPCIEMSIX_VECT209_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT209_ADDR_HI 0x1e345
+#define regPCIEMSIX_VECT209_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT209_MSG_DATA 0x1e346
+#define regPCIEMSIX_VECT209_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT209_CONTROL 0x1e347
+#define regPCIEMSIX_VECT209_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT210_ADDR_LO 0x1e348
+#define regPCIEMSIX_VECT210_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT210_ADDR_HI 0x1e349
+#define regPCIEMSIX_VECT210_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT210_MSG_DATA 0x1e34a
+#define regPCIEMSIX_VECT210_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT210_CONTROL 0x1e34b
+#define regPCIEMSIX_VECT210_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT211_ADDR_LO 0x1e34c
+#define regPCIEMSIX_VECT211_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT211_ADDR_HI 0x1e34d
+#define regPCIEMSIX_VECT211_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT211_MSG_DATA 0x1e34e
+#define regPCIEMSIX_VECT211_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT211_CONTROL 0x1e34f
+#define regPCIEMSIX_VECT211_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT212_ADDR_LO 0x1e350
+#define regPCIEMSIX_VECT212_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT212_ADDR_HI 0x1e351
+#define regPCIEMSIX_VECT212_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT212_MSG_DATA 0x1e352
+#define regPCIEMSIX_VECT212_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT212_CONTROL 0x1e353
+#define regPCIEMSIX_VECT212_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT213_ADDR_LO 0x1e354
+#define regPCIEMSIX_VECT213_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT213_ADDR_HI 0x1e355
+#define regPCIEMSIX_VECT213_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT213_MSG_DATA 0x1e356
+#define regPCIEMSIX_VECT213_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT213_CONTROL 0x1e357
+#define regPCIEMSIX_VECT213_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT214_ADDR_LO 0x1e358
+#define regPCIEMSIX_VECT214_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT214_ADDR_HI 0x1e359
+#define regPCIEMSIX_VECT214_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT214_MSG_DATA 0x1e35a
+#define regPCIEMSIX_VECT214_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT214_CONTROL 0x1e35b
+#define regPCIEMSIX_VECT214_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT215_ADDR_LO 0x1e35c
+#define regPCIEMSIX_VECT215_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT215_ADDR_HI 0x1e35d
+#define regPCIEMSIX_VECT215_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT215_MSG_DATA 0x1e35e
+#define regPCIEMSIX_VECT215_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT215_CONTROL 0x1e35f
+#define regPCIEMSIX_VECT215_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT216_ADDR_LO 0x1e360
+#define regPCIEMSIX_VECT216_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT216_ADDR_HI 0x1e361
+#define regPCIEMSIX_VECT216_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT216_MSG_DATA 0x1e362
+#define regPCIEMSIX_VECT216_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT216_CONTROL 0x1e363
+#define regPCIEMSIX_VECT216_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT217_ADDR_LO 0x1e364
+#define regPCIEMSIX_VECT217_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT217_ADDR_HI 0x1e365
+#define regPCIEMSIX_VECT217_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT217_MSG_DATA 0x1e366
+#define regPCIEMSIX_VECT217_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT217_CONTROL 0x1e367
+#define regPCIEMSIX_VECT217_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT218_ADDR_LO 0x1e368
+#define regPCIEMSIX_VECT218_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT218_ADDR_HI 0x1e369
+#define regPCIEMSIX_VECT218_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT218_MSG_DATA 0x1e36a
+#define regPCIEMSIX_VECT218_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT218_CONTROL 0x1e36b
+#define regPCIEMSIX_VECT218_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT219_ADDR_LO 0x1e36c
+#define regPCIEMSIX_VECT219_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT219_ADDR_HI 0x1e36d
+#define regPCIEMSIX_VECT219_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT219_MSG_DATA 0x1e36e
+#define regPCIEMSIX_VECT219_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT219_CONTROL 0x1e36f
+#define regPCIEMSIX_VECT219_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT220_ADDR_LO 0x1e370
+#define regPCIEMSIX_VECT220_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT220_ADDR_HI 0x1e371
+#define regPCIEMSIX_VECT220_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT220_MSG_DATA 0x1e372
+#define regPCIEMSIX_VECT220_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT220_CONTROL 0x1e373
+#define regPCIEMSIX_VECT220_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT221_ADDR_LO 0x1e374
+#define regPCIEMSIX_VECT221_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT221_ADDR_HI 0x1e375
+#define regPCIEMSIX_VECT221_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT221_MSG_DATA 0x1e376
+#define regPCIEMSIX_VECT221_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT221_CONTROL 0x1e377
+#define regPCIEMSIX_VECT221_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT222_ADDR_LO 0x1e378
+#define regPCIEMSIX_VECT222_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT222_ADDR_HI 0x1e379
+#define regPCIEMSIX_VECT222_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT222_MSG_DATA 0x1e37a
+#define regPCIEMSIX_VECT222_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT222_CONTROL 0x1e37b
+#define regPCIEMSIX_VECT222_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT223_ADDR_LO 0x1e37c
+#define regPCIEMSIX_VECT223_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT223_ADDR_HI 0x1e37d
+#define regPCIEMSIX_VECT223_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT223_MSG_DATA 0x1e37e
+#define regPCIEMSIX_VECT223_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT223_CONTROL 0x1e37f
+#define regPCIEMSIX_VECT223_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT224_ADDR_LO 0x1e380
+#define regPCIEMSIX_VECT224_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT224_ADDR_HI 0x1e381
+#define regPCIEMSIX_VECT224_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT224_MSG_DATA 0x1e382
+#define regPCIEMSIX_VECT224_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT224_CONTROL 0x1e383
+#define regPCIEMSIX_VECT224_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT225_ADDR_LO 0x1e384
+#define regPCIEMSIX_VECT225_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT225_ADDR_HI 0x1e385
+#define regPCIEMSIX_VECT225_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT225_MSG_DATA 0x1e386
+#define regPCIEMSIX_VECT225_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT225_CONTROL 0x1e387
+#define regPCIEMSIX_VECT225_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT226_ADDR_LO 0x1e388
+#define regPCIEMSIX_VECT226_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT226_ADDR_HI 0x1e389
+#define regPCIEMSIX_VECT226_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT226_MSG_DATA 0x1e38a
+#define regPCIEMSIX_VECT226_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT226_CONTROL 0x1e38b
+#define regPCIEMSIX_VECT226_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT227_ADDR_LO 0x1e38c
+#define regPCIEMSIX_VECT227_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT227_ADDR_HI 0x1e38d
+#define regPCIEMSIX_VECT227_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT227_MSG_DATA 0x1e38e
+#define regPCIEMSIX_VECT227_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT227_CONTROL 0x1e38f
+#define regPCIEMSIX_VECT227_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT228_ADDR_LO 0x1e390
+#define regPCIEMSIX_VECT228_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT228_ADDR_HI 0x1e391
+#define regPCIEMSIX_VECT228_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT228_MSG_DATA 0x1e392
+#define regPCIEMSIX_VECT228_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT228_CONTROL 0x1e393
+#define regPCIEMSIX_VECT228_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT229_ADDR_LO 0x1e394
+#define regPCIEMSIX_VECT229_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT229_ADDR_HI 0x1e395
+#define regPCIEMSIX_VECT229_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT229_MSG_DATA 0x1e396
+#define regPCIEMSIX_VECT229_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT229_CONTROL 0x1e397
+#define regPCIEMSIX_VECT229_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT230_ADDR_LO 0x1e398
+#define regPCIEMSIX_VECT230_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT230_ADDR_HI 0x1e399
+#define regPCIEMSIX_VECT230_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT230_MSG_DATA 0x1e39a
+#define regPCIEMSIX_VECT230_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT230_CONTROL 0x1e39b
+#define regPCIEMSIX_VECT230_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT231_ADDR_LO 0x1e39c
+#define regPCIEMSIX_VECT231_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT231_ADDR_HI 0x1e39d
+#define regPCIEMSIX_VECT231_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT231_MSG_DATA 0x1e39e
+#define regPCIEMSIX_VECT231_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT231_CONTROL 0x1e39f
+#define regPCIEMSIX_VECT231_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT232_ADDR_LO 0x1e3a0
+#define regPCIEMSIX_VECT232_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT232_ADDR_HI 0x1e3a1
+#define regPCIEMSIX_VECT232_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT232_MSG_DATA 0x1e3a2
+#define regPCIEMSIX_VECT232_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT232_CONTROL 0x1e3a3
+#define regPCIEMSIX_VECT232_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT233_ADDR_LO 0x1e3a4
+#define regPCIEMSIX_VECT233_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT233_ADDR_HI 0x1e3a5
+#define regPCIEMSIX_VECT233_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT233_MSG_DATA 0x1e3a6
+#define regPCIEMSIX_VECT233_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT233_CONTROL 0x1e3a7
+#define regPCIEMSIX_VECT233_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT234_ADDR_LO 0x1e3a8
+#define regPCIEMSIX_VECT234_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT234_ADDR_HI 0x1e3a9
+#define regPCIEMSIX_VECT234_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT234_MSG_DATA 0x1e3aa
+#define regPCIEMSIX_VECT234_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT234_CONTROL 0x1e3ab
+#define regPCIEMSIX_VECT234_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT235_ADDR_LO 0x1e3ac
+#define regPCIEMSIX_VECT235_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT235_ADDR_HI 0x1e3ad
+#define regPCIEMSIX_VECT235_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT235_MSG_DATA 0x1e3ae
+#define regPCIEMSIX_VECT235_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT235_CONTROL 0x1e3af
+#define regPCIEMSIX_VECT235_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT236_ADDR_LO 0x1e3b0
+#define regPCIEMSIX_VECT236_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT236_ADDR_HI 0x1e3b1
+#define regPCIEMSIX_VECT236_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT236_MSG_DATA 0x1e3b2
+#define regPCIEMSIX_VECT236_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT236_CONTROL 0x1e3b3
+#define regPCIEMSIX_VECT236_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT237_ADDR_LO 0x1e3b4
+#define regPCIEMSIX_VECT237_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT237_ADDR_HI 0x1e3b5
+#define regPCIEMSIX_VECT237_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT237_MSG_DATA 0x1e3b6
+#define regPCIEMSIX_VECT237_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT237_CONTROL 0x1e3b7
+#define regPCIEMSIX_VECT237_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT238_ADDR_LO 0x1e3b8
+#define regPCIEMSIX_VECT238_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT238_ADDR_HI 0x1e3b9
+#define regPCIEMSIX_VECT238_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT238_MSG_DATA 0x1e3ba
+#define regPCIEMSIX_VECT238_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT238_CONTROL 0x1e3bb
+#define regPCIEMSIX_VECT238_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT239_ADDR_LO 0x1e3bc
+#define regPCIEMSIX_VECT239_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT239_ADDR_HI 0x1e3bd
+#define regPCIEMSIX_VECT239_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT239_MSG_DATA 0x1e3be
+#define regPCIEMSIX_VECT239_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT239_CONTROL 0x1e3bf
+#define regPCIEMSIX_VECT239_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT240_ADDR_LO 0x1e3c0
+#define regPCIEMSIX_VECT240_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT240_ADDR_HI 0x1e3c1
+#define regPCIEMSIX_VECT240_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT240_MSG_DATA 0x1e3c2
+#define regPCIEMSIX_VECT240_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT240_CONTROL 0x1e3c3
+#define regPCIEMSIX_VECT240_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT241_ADDR_LO 0x1e3c4
+#define regPCIEMSIX_VECT241_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT241_ADDR_HI 0x1e3c5
+#define regPCIEMSIX_VECT241_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT241_MSG_DATA 0x1e3c6
+#define regPCIEMSIX_VECT241_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT241_CONTROL 0x1e3c7
+#define regPCIEMSIX_VECT241_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT242_ADDR_LO 0x1e3c8
+#define regPCIEMSIX_VECT242_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT242_ADDR_HI 0x1e3c9
+#define regPCIEMSIX_VECT242_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT242_MSG_DATA 0x1e3ca
+#define regPCIEMSIX_VECT242_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT242_CONTROL 0x1e3cb
+#define regPCIEMSIX_VECT242_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT243_ADDR_LO 0x1e3cc
+#define regPCIEMSIX_VECT243_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT243_ADDR_HI 0x1e3cd
+#define regPCIEMSIX_VECT243_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT243_MSG_DATA 0x1e3ce
+#define regPCIEMSIX_VECT243_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT243_CONTROL 0x1e3cf
+#define regPCIEMSIX_VECT243_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT244_ADDR_LO 0x1e3d0
+#define regPCIEMSIX_VECT244_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT244_ADDR_HI 0x1e3d1
+#define regPCIEMSIX_VECT244_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT244_MSG_DATA 0x1e3d2
+#define regPCIEMSIX_VECT244_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT244_CONTROL 0x1e3d3
+#define regPCIEMSIX_VECT244_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT245_ADDR_LO 0x1e3d4
+#define regPCIEMSIX_VECT245_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT245_ADDR_HI 0x1e3d5
+#define regPCIEMSIX_VECT245_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT245_MSG_DATA 0x1e3d6
+#define regPCIEMSIX_VECT245_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT245_CONTROL 0x1e3d7
+#define regPCIEMSIX_VECT245_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT246_ADDR_LO 0x1e3d8
+#define regPCIEMSIX_VECT246_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT246_ADDR_HI 0x1e3d9
+#define regPCIEMSIX_VECT246_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT246_MSG_DATA 0x1e3da
+#define regPCIEMSIX_VECT246_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT246_CONTROL 0x1e3db
+#define regPCIEMSIX_VECT246_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT247_ADDR_LO 0x1e3dc
+#define regPCIEMSIX_VECT247_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT247_ADDR_HI 0x1e3dd
+#define regPCIEMSIX_VECT247_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT247_MSG_DATA 0x1e3de
+#define regPCIEMSIX_VECT247_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT247_CONTROL 0x1e3df
+#define regPCIEMSIX_VECT247_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT248_ADDR_LO 0x1e3e0
+#define regPCIEMSIX_VECT248_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT248_ADDR_HI 0x1e3e1
+#define regPCIEMSIX_VECT248_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT248_MSG_DATA 0x1e3e2
+#define regPCIEMSIX_VECT248_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT248_CONTROL 0x1e3e3
+#define regPCIEMSIX_VECT248_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT249_ADDR_LO 0x1e3e4
+#define regPCIEMSIX_VECT249_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT249_ADDR_HI 0x1e3e5
+#define regPCIEMSIX_VECT249_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT249_MSG_DATA 0x1e3e6
+#define regPCIEMSIX_VECT249_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT249_CONTROL 0x1e3e7
+#define regPCIEMSIX_VECT249_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT250_ADDR_LO 0x1e3e8
+#define regPCIEMSIX_VECT250_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT250_ADDR_HI 0x1e3e9
+#define regPCIEMSIX_VECT250_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT250_MSG_DATA 0x1e3ea
+#define regPCIEMSIX_VECT250_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT250_CONTROL 0x1e3eb
+#define regPCIEMSIX_VECT250_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT251_ADDR_LO 0x1e3ec
+#define regPCIEMSIX_VECT251_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT251_ADDR_HI 0x1e3ed
+#define regPCIEMSIX_VECT251_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT251_MSG_DATA 0x1e3ee
+#define regPCIEMSIX_VECT251_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT251_CONTROL 0x1e3ef
+#define regPCIEMSIX_VECT251_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT252_ADDR_LO 0x1e3f0
+#define regPCIEMSIX_VECT252_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT252_ADDR_HI 0x1e3f1
+#define regPCIEMSIX_VECT252_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT252_MSG_DATA 0x1e3f2
+#define regPCIEMSIX_VECT252_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT252_CONTROL 0x1e3f3
+#define regPCIEMSIX_VECT252_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT253_ADDR_LO 0x1e3f4
+#define regPCIEMSIX_VECT253_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT253_ADDR_HI 0x1e3f5
+#define regPCIEMSIX_VECT253_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT253_MSG_DATA 0x1e3f6
+#define regPCIEMSIX_VECT253_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT253_CONTROL 0x1e3f7
+#define regPCIEMSIX_VECT253_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT254_ADDR_LO 0x1e3f8
+#define regPCIEMSIX_VECT254_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT254_ADDR_HI 0x1e3f9
+#define regPCIEMSIX_VECT254_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT254_MSG_DATA 0x1e3fa
+#define regPCIEMSIX_VECT254_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT254_CONTROL 0x1e3fb
+#define regPCIEMSIX_VECT254_CONTROL_BASE_IDX 5
+#define regPCIEMSIX_VECT255_ADDR_LO 0x1e3fc
+#define regPCIEMSIX_VECT255_ADDR_LO_BASE_IDX 5
+#define regPCIEMSIX_VECT255_ADDR_HI 0x1e3fd
+#define regPCIEMSIX_VECT255_ADDR_HI_BASE_IDX 5
+#define regPCIEMSIX_VECT255_MSG_DATA 0x1e3fe
+#define regPCIEMSIX_VECT255_MSG_DATA_BASE_IDX 5
+#define regPCIEMSIX_VECT255_CONTROL 0x1e3ff
+#define regPCIEMSIX_VECT255_CONTROL_BASE_IDX 5
+
+
+// addressBlock: nbif_rcc_pfc_usb_RCCPFCDEC
+// base address: 0x10134400
+#define regRCC_PFC_USB_RCC_PFC_LTR_CNTL 0xd140
+#define regRCC_PFC_USB_RCC_PFC_LTR_CNTL_BASE_IDX 5
+#define regRCC_PFC_USB_RCC_PFC_PME_RESTORE 0xd141
+#define regRCC_PFC_USB_RCC_PFC_PME_RESTORE_BASE_IDX 5
+#define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0 0xd142
+#define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0_BASE_IDX 5
+#define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_1 0xd143
+#define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_1_BASE_IDX 5
+#define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_2 0xd144
+#define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_2_BASE_IDX 5
+#define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_3 0xd145
+#define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_3_BASE_IDX 5
+#define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_4 0xd146
+#define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_4_BASE_IDX 5
+#define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_5 0xd147
+#define regRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_5_BASE_IDX 5
+#define regRCC_PFC_USB_RCC_PFC_AUXPWR_CNTL 0xd148
+#define regRCC_PFC_USB_RCC_PFC_AUXPWR_CNTL_BASE_IDX 5
+
+
+// addressBlock: nbif_rcc_pfc_pd_controller_RCCPFCDEC
+// base address: 0x10134600
+#define regRCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL 0xd1c0
+#define regRCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL_BASE_IDX 5
+#define regRCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE 0xd1c1
+#define regRCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE_BASE_IDX 5
+#define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0 0xd1c2
+#define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0_BASE_IDX 5
+#define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_1 0xd1c3
+#define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_1_BASE_IDX 5
+#define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_2 0xd1c4
+#define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_2_BASE_IDX 5
+#define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_3 0xd1c5
+#define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_3_BASE_IDX 5
+#define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_4 0xd1c6
+#define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_4_BASE_IDX 5
+#define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_5 0xd1c7
+#define regRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_5_BASE_IDX 5
+#define regRCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL 0xd1c8
+#define regRCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL_BASE_IDX 5
+
+
+// addressBlock: nbif_pciemsix_0_usb_MSIXPDEC
+// base address: 0x10179000
+#define regPCIEMSIX_PBA_0 0x1e400
+#define regPCIEMSIX_PBA_0_BASE_IDX 5
+#define regPCIEMSIX_PBA_1 0x1e401
+#define regPCIEMSIX_PBA_1_BASE_IDX 5
+#define regPCIEMSIX_PBA_2 0x1e402
+#define regPCIEMSIX_PBA_2_BASE_IDX 5
+#define regPCIEMSIX_PBA_3 0x1e403
+#define regPCIEMSIX_PBA_3_BASE_IDX 5
+#define regPCIEMSIX_PBA_4 0x1e404
+#define regPCIEMSIX_PBA_4_BASE_IDX 5
+#define regPCIEMSIX_PBA_5 0x1e405
+#define regPCIEMSIX_PBA_5_BASE_IDX 5
+#define regPCIEMSIX_PBA_6 0x1e406
+#define regPCIEMSIX_PBA_6_BASE_IDX 5
+#define regPCIEMSIX_PBA_7 0x1e407
+#define regPCIEMSIX_PBA_7_BASE_IDX 5
+
+
+// addressBlock: nbif_rcc_shadow_reg_shadowdec
+// base address: 0x10130000
+#define regSHADOW_COMMAND 0xc001
+#define regSHADOW_COMMAND_BASE_IDX 5
+#define regSHADOW_BASE_ADDR_1 0xc004
+#define regSHADOW_BASE_ADDR_1_BASE_IDX 5
+#define regSHADOW_BASE_ADDR_2 0xc005
+#define regSHADOW_BASE_ADDR_2_BASE_IDX 5
+#define regSHADOW_IRQ_BRIDGE_CNTL 0xc00f
+#define regSHADOW_IRQ_BRIDGE_CNTL_BASE_IDX 5
+#define regSUC_INDEX 0xc038
+#define regSUC_INDEX_BASE_IDX 5
+#define regSUC_DATA 0xc039
+#define regSUC_DATA_BASE_IDX 5
+
+
+// addressBlock: nbif_bif_swus_SUMDEC
+// base address: 0x1013b000
+#define regSUM_INDEX 0xec38
+#define regSUM_INDEX_BASE_IDX 5
+#define regSUM_DATA 0xec39
+#define regSUM_DATA_BASE_IDX 5
+#define regSUM_INDEX_HI 0xec3b
+#define regSUM_INDEX_HI_BASE_IDX 5
+
+
+// addressBlock: nbif_rcc_strap_rcc_strap_internal
+// base address: 0x10100000
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0 0xc400
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1 0xc401
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2 0xc402
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3 0xc403
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4 0xc404
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5 0xc405
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6 0xc406
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7 0xc407
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8 0xc408
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9 0xc409
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10 0xc40a
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11 0xc40b
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12 0xc40c
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13 0xc40d
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14 0xc40e
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14_BASE_IDX 5
+#define regRCC_DEV1_PORT_STRAP0 0xc480
+#define regRCC_DEV1_PORT_STRAP0_BASE_IDX 5
+#define regRCC_DEV1_PORT_STRAP1 0xc481
+#define regRCC_DEV1_PORT_STRAP1_BASE_IDX 5
+#define regRCC_DEV1_PORT_STRAP2 0xc482
+#define regRCC_DEV1_PORT_STRAP2_BASE_IDX 5
+#define regRCC_DEV1_PORT_STRAP3 0xc483
+#define regRCC_DEV1_PORT_STRAP3_BASE_IDX 5
+#define regRCC_DEV1_PORT_STRAP4 0xc484
+#define regRCC_DEV1_PORT_STRAP4_BASE_IDX 5
+#define regRCC_DEV1_PORT_STRAP5 0xc485
+#define regRCC_DEV1_PORT_STRAP5_BASE_IDX 5
+#define regRCC_DEV1_PORT_STRAP6 0xc486
+#define regRCC_DEV1_PORT_STRAP6_BASE_IDX 5
+#define regRCC_DEV1_PORT_STRAP7 0xc487
+#define regRCC_DEV1_PORT_STRAP7_BASE_IDX 5
+#define regRCC_DEV1_PORT_STRAP8 0xc488
+#define regRCC_DEV1_PORT_STRAP8_BASE_IDX 5
+#define regRCC_DEV1_PORT_STRAP9 0xc489
+#define regRCC_DEV1_PORT_STRAP9_BASE_IDX 5
+#define regRCC_DEV1_PORT_STRAP10 0xc48a
+#define regRCC_DEV1_PORT_STRAP10_BASE_IDX 5
+#define regRCC_DEV1_PORT_STRAP11 0xc48b
+#define regRCC_DEV1_PORT_STRAP11_BASE_IDX 5
+#define regRCC_DEV1_PORT_STRAP12 0xc48c
+#define regRCC_DEV1_PORT_STRAP12_BASE_IDX 5
+#define regRCC_DEV1_PORT_STRAP13 0xc48d
+#define regRCC_DEV1_PORT_STRAP13_BASE_IDX 5
+#define regRCC_DEV1_PORT_STRAP14 0xc48e
+#define regRCC_DEV1_PORT_STRAP14_BASE_IDX 5
+#define regRCC_DEV2_PORT_STRAP0 0xc500
+#define regRCC_DEV2_PORT_STRAP0_BASE_IDX 5
+#define regRCC_DEV2_PORT_STRAP1 0xc501
+#define regRCC_DEV2_PORT_STRAP1_BASE_IDX 5
+#define regRCC_DEV2_PORT_STRAP2 0xc502
+#define regRCC_DEV2_PORT_STRAP2_BASE_IDX 5
+#define regRCC_DEV2_PORT_STRAP3 0xc503
+#define regRCC_DEV2_PORT_STRAP3_BASE_IDX 5
+#define regRCC_DEV2_PORT_STRAP4 0xc504
+#define regRCC_DEV2_PORT_STRAP4_BASE_IDX 5
+#define regRCC_DEV2_PORT_STRAP5 0xc505
+#define regRCC_DEV2_PORT_STRAP5_BASE_IDX 5
+#define regRCC_DEV2_PORT_STRAP6 0xc506
+#define regRCC_DEV2_PORT_STRAP6_BASE_IDX 5
+#define regRCC_DEV2_PORT_STRAP7 0xc507
+#define regRCC_DEV2_PORT_STRAP7_BASE_IDX 5
+#define regRCC_DEV2_PORT_STRAP8 0xc508
+#define regRCC_DEV2_PORT_STRAP8_BASE_IDX 5
+#define regRCC_DEV2_PORT_STRAP9 0xc509
+#define regRCC_DEV2_PORT_STRAP9_BASE_IDX 5
+#define regRCC_DEV2_PORT_STRAP10 0xc50a
+#define regRCC_DEV2_PORT_STRAP10_BASE_IDX 5
+#define regRCC_DEV2_PORT_STRAP11 0xc50b
+#define regRCC_DEV2_PORT_STRAP11_BASE_IDX 5
+#define regRCC_DEV2_PORT_STRAP12 0xc50c
+#define regRCC_DEV2_PORT_STRAP12_BASE_IDX 5
+#define regRCC_DEV2_PORT_STRAP13 0xc50d
+#define regRCC_DEV2_PORT_STRAP13_BASE_IDX 5
+#define regRCC_DEV2_PORT_STRAP14 0xc50e
+#define regRCC_DEV2_PORT_STRAP14_BASE_IDX 5
+#define regRCC_STRAP1_RCC_BIF_STRAP0 0xc600
+#define regRCC_STRAP1_RCC_BIF_STRAP0_BASE_IDX 5
+#define regRCC_STRAP1_RCC_BIF_STRAP1 0xc601
+#define regRCC_STRAP1_RCC_BIF_STRAP1_BASE_IDX 5
+#define regRCC_STRAP1_RCC_BIF_STRAP2 0xc602
+#define regRCC_STRAP1_RCC_BIF_STRAP2_BASE_IDX 5
+#define regRCC_STRAP1_RCC_BIF_STRAP3 0xc603
+#define regRCC_STRAP1_RCC_BIF_STRAP3_BASE_IDX 5
+#define regRCC_STRAP1_RCC_BIF_STRAP4 0xc604
+#define regRCC_STRAP1_RCC_BIF_STRAP4_BASE_IDX 5
+#define regRCC_STRAP1_RCC_BIF_STRAP5 0xc605
+#define regRCC_STRAP1_RCC_BIF_STRAP5_BASE_IDX 5
+#define regRCC_STRAP1_RCC_BIF_STRAP6 0xc606
+#define regRCC_STRAP1_RCC_BIF_STRAP6_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0 0xd000
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1 0xd001
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2 0xd002
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3 0xd003
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4 0xd004
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5 0xd005
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8 0xd008
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9 0xd009
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13 0xd00d
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14 0xd00e
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15 0xd00f
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16 0xd010
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17 0xd011
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18 0xd012
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0 0xd080
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2 0xd082
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3 0xd083
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4 0xd084
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5 0xd085
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6 0xd086
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7 0xd087
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20 0xd094
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20_BASE_IDX 5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21 0xd095
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21_BASE_IDX 5
+#define regRCC_DEV0_EPF2_STRAP0 0xd100
+#define regRCC_DEV0_EPF2_STRAP0_BASE_IDX 5
+#define regRCC_DEV0_EPF2_STRAP2 0xd102
+#define regRCC_DEV0_EPF2_STRAP2_BASE_IDX 5
+#define regRCC_DEV0_EPF2_STRAP3 0xd103
+#define regRCC_DEV0_EPF2_STRAP3_BASE_IDX 5
+#define regRCC_DEV0_EPF2_STRAP4 0xd104
+#define regRCC_DEV0_EPF2_STRAP4_BASE_IDX 5
+#define regRCC_DEV0_EPF2_STRAP5 0xd105
+#define regRCC_DEV0_EPF2_STRAP5_BASE_IDX 5
+#define regRCC_DEV0_EPF2_STRAP6 0xd106
+#define regRCC_DEV0_EPF2_STRAP6_BASE_IDX 5
+#define regRCC_DEV0_EPF2_STRAP7 0xd107
+#define regRCC_DEV0_EPF2_STRAP7_BASE_IDX 5
+#define regRCC_DEV0_EPF2_STRAP10 0xd10a
+#define regRCC_DEV0_EPF2_STRAP10_BASE_IDX 5
+#define regRCC_DEV0_EPF2_STRAP11 0xd10b
+#define regRCC_DEV0_EPF2_STRAP11_BASE_IDX 5
+#define regRCC_DEV0_EPF2_STRAP12 0xd10c
+#define regRCC_DEV0_EPF2_STRAP12_BASE_IDX 5
+#define regRCC_DEV0_EPF2_STRAP13 0xd10d
+#define regRCC_DEV0_EPF2_STRAP13_BASE_IDX 5
+#define regRCC_DEV0_EPF2_STRAP14 0xd10e
+#define regRCC_DEV0_EPF2_STRAP14_BASE_IDX 5
+#define regRCC_DEV0_EPF2_STRAP20 0xd114
+#define regRCC_DEV0_EPF2_STRAP20_BASE_IDX 5
+#define regRCC_DEV0_EPF3_STRAP0 0xd180
+#define regRCC_DEV0_EPF3_STRAP0_BASE_IDX 5
+#define regRCC_DEV0_EPF3_STRAP2 0xd182
+#define regRCC_DEV0_EPF3_STRAP2_BASE_IDX 5
+#define regRCC_DEV0_EPF3_STRAP3 0xd183
+#define regRCC_DEV0_EPF3_STRAP3_BASE_IDX 5
+#define regRCC_DEV0_EPF3_STRAP4 0xd184
+#define regRCC_DEV0_EPF3_STRAP4_BASE_IDX 5
+#define regRCC_DEV0_EPF3_STRAP5 0xd185
+#define regRCC_DEV0_EPF3_STRAP5_BASE_IDX 5
+#define regRCC_DEV0_EPF3_STRAP6 0xd186
+#define regRCC_DEV0_EPF3_STRAP6_BASE_IDX 5
+#define regRCC_DEV0_EPF3_STRAP7 0xd187
+#define regRCC_DEV0_EPF3_STRAP7_BASE_IDX 5
+#define regRCC_DEV0_EPF3_STRAP10 0xd18a
+#define regRCC_DEV0_EPF3_STRAP10_BASE_IDX 5
+#define regRCC_DEV0_EPF3_STRAP11 0xd18b
+#define regRCC_DEV0_EPF3_STRAP11_BASE_IDX 5
+#define regRCC_DEV0_EPF3_STRAP12 0xd18c
+#define regRCC_DEV0_EPF3_STRAP12_BASE_IDX 5
+#define regRCC_DEV0_EPF3_STRAP13 0xd18d
+#define regRCC_DEV0_EPF3_STRAP13_BASE_IDX 5
+#define regRCC_DEV0_EPF3_STRAP14 0xd18e
+#define regRCC_DEV0_EPF3_STRAP14_BASE_IDX 5
+#define regRCC_DEV0_EPF3_STRAP20 0xd194
+#define regRCC_DEV0_EPF3_STRAP20_BASE_IDX 5
+#define regRCC_DEV0_EPF4_STRAP0 0xd200
+#define regRCC_DEV0_EPF4_STRAP0_BASE_IDX 5
+#define regRCC_DEV0_EPF4_STRAP2 0xd202
+#define regRCC_DEV0_EPF4_STRAP2_BASE_IDX 5
+#define regRCC_DEV0_EPF4_STRAP3 0xd203
+#define regRCC_DEV0_EPF4_STRAP3_BASE_IDX 5
+#define regRCC_DEV0_EPF4_STRAP4 0xd204
+#define regRCC_DEV0_EPF4_STRAP4_BASE_IDX 5
+#define regRCC_DEV0_EPF4_STRAP5 0xd205
+#define regRCC_DEV0_EPF4_STRAP5_BASE_IDX 5
+#define regRCC_DEV0_EPF4_STRAP6 0xd206
+#define regRCC_DEV0_EPF4_STRAP6_BASE_IDX 5
+#define regRCC_DEV0_EPF4_STRAP7 0xd207
+#define regRCC_DEV0_EPF4_STRAP7_BASE_IDX 5
+#define regRCC_DEV0_EPF4_STRAP13 0xd20d
+#define regRCC_DEV0_EPF4_STRAP13_BASE_IDX 5
+#define regRCC_DEV0_EPF4_STRAP14 0xd20e
+#define regRCC_DEV0_EPF4_STRAP14_BASE_IDX 5
+#define regRCC_DEV0_EPF5_STRAP0 0xd280
+#define regRCC_DEV0_EPF5_STRAP0_BASE_IDX 5
+#define regRCC_DEV0_EPF5_STRAP2 0xd282
+#define regRCC_DEV0_EPF5_STRAP2_BASE_IDX 5
+#define regRCC_DEV0_EPF5_STRAP3 0xd283
+#define regRCC_DEV0_EPF5_STRAP3_BASE_IDX 5
+#define regRCC_DEV0_EPF5_STRAP4 0xd284
+#define regRCC_DEV0_EPF5_STRAP4_BASE_IDX 5
+#define regRCC_DEV0_EPF5_STRAP5 0xd285
+#define regRCC_DEV0_EPF5_STRAP5_BASE_IDX 5
+#define regRCC_DEV0_EPF5_STRAP6 0xd286
+#define regRCC_DEV0_EPF5_STRAP6_BASE_IDX 5
+#define regRCC_DEV0_EPF5_STRAP7 0xd287
+#define regRCC_DEV0_EPF5_STRAP7_BASE_IDX 5
+#define regRCC_DEV0_EPF5_STRAP13 0xd28d
+#define regRCC_DEV0_EPF5_STRAP13_BASE_IDX 5
+#define regRCC_DEV0_EPF5_STRAP14 0xd28e
+#define regRCC_DEV0_EPF5_STRAP14_BASE_IDX 5
+#define regRCC_DEV0_EPF6_STRAP0 0xd300
+#define regRCC_DEV0_EPF6_STRAP0_BASE_IDX 5
+#define regRCC_DEV0_EPF6_STRAP2 0xd302
+#define regRCC_DEV0_EPF6_STRAP2_BASE_IDX 5
+#define regRCC_DEV0_EPF6_STRAP3 0xd303
+#define regRCC_DEV0_EPF6_STRAP3_BASE_IDX 5
+#define regRCC_DEV0_EPF6_STRAP4 0xd304
+#define regRCC_DEV0_EPF6_STRAP4_BASE_IDX 5
+#define regRCC_DEV0_EPF6_STRAP5 0xd305
+#define regRCC_DEV0_EPF6_STRAP5_BASE_IDX 5
+#define regRCC_DEV0_EPF6_STRAP6 0xd306
+#define regRCC_DEV0_EPF6_STRAP6_BASE_IDX 5
+#define regRCC_DEV0_EPF6_STRAP13 0xd30d
+#define regRCC_DEV0_EPF6_STRAP13_BASE_IDX 5
+#define regRCC_DEV0_EPF6_STRAP14 0xd30e
+#define regRCC_DEV0_EPF6_STRAP14_BASE_IDX 5
+#define regRCC_DEV0_EPF7_STRAP0 0xd380
+#define regRCC_DEV0_EPF7_STRAP0_BASE_IDX 5
+#define regRCC_DEV0_EPF7_STRAP2 0xd382
+#define regRCC_DEV0_EPF7_STRAP2_BASE_IDX 5
+#define regRCC_DEV0_EPF7_STRAP3 0xd383
+#define regRCC_DEV0_EPF7_STRAP3_BASE_IDX 5
+#define regRCC_DEV0_EPF7_STRAP4 0xd384
+#define regRCC_DEV0_EPF7_STRAP4_BASE_IDX 5
+#define regRCC_DEV0_EPF7_STRAP5 0xd385
+#define regRCC_DEV0_EPF7_STRAP5_BASE_IDX 5
+#define regRCC_DEV0_EPF7_STRAP6 0xd386
+#define regRCC_DEV0_EPF7_STRAP6_BASE_IDX 5
+#define regRCC_DEV0_EPF7_STRAP13 0xd38d
+#define regRCC_DEV0_EPF7_STRAP13_BASE_IDX 5
+#define regRCC_DEV0_EPF7_STRAP14 0xd38e
+#define regRCC_DEV0_EPF7_STRAP14_BASE_IDX 5
+#define regRCC_DEV1_EPF0_STRAP0 0xd400
+#define regRCC_DEV1_EPF0_STRAP0_BASE_IDX 5
+#define regRCC_DEV1_EPF0_STRAP2 0xd402
+#define regRCC_DEV1_EPF0_STRAP2_BASE_IDX 5
+#define regRCC_DEV1_EPF0_STRAP3 0xd403
+#define regRCC_DEV1_EPF0_STRAP3_BASE_IDX 5
+#define regRCC_DEV1_EPF0_STRAP4 0xd404
+#define regRCC_DEV1_EPF0_STRAP4_BASE_IDX 5
+#define regRCC_DEV1_EPF0_STRAP5 0xd405
+#define regRCC_DEV1_EPF0_STRAP5_BASE_IDX 5
+#define regRCC_DEV1_EPF0_STRAP6 0xd406
+#define regRCC_DEV1_EPF0_STRAP6_BASE_IDX 5
+#define regRCC_DEV1_EPF0_STRAP13 0xd40d
+#define regRCC_DEV1_EPF0_STRAP13_BASE_IDX 5
+#define regRCC_DEV1_EPF0_STRAP14 0xd40e
+#define regRCC_DEV1_EPF0_STRAP14_BASE_IDX 5
+#define regRCC_DEV1_EPF1_STRAP0 0xd480
+#define regRCC_DEV1_EPF1_STRAP0_BASE_IDX 5
+#define regRCC_DEV1_EPF1_STRAP2 0xd482
+#define regRCC_DEV1_EPF1_STRAP2_BASE_IDX 5
+#define regRCC_DEV1_EPF1_STRAP3 0xd483
+#define regRCC_DEV1_EPF1_STRAP3_BASE_IDX 5
+#define regRCC_DEV1_EPF1_STRAP4 0xd484
+#define regRCC_DEV1_EPF1_STRAP4_BASE_IDX 5
+#define regRCC_DEV1_EPF1_STRAP5 0xd485
+#define regRCC_DEV1_EPF1_STRAP5_BASE_IDX 5
+#define regRCC_DEV1_EPF1_STRAP6 0xd486
+#define regRCC_DEV1_EPF1_STRAP6_BASE_IDX 5
+#define regRCC_DEV1_EPF1_STRAP13 0xd48d
+#define regRCC_DEV1_EPF1_STRAP13_BASE_IDX 5
+#define regRCC_DEV1_EPF1_STRAP14 0xd48e
+#define regRCC_DEV1_EPF1_STRAP14_BASE_IDX 5
+#define regRCC_DEV1_EPF2_STRAP0 0xd500
+#define regRCC_DEV1_EPF2_STRAP0_BASE_IDX 5
+#define regRCC_DEV1_EPF2_STRAP2 0xd502
+#define regRCC_DEV1_EPF2_STRAP2_BASE_IDX 5
+#define regRCC_DEV1_EPF2_STRAP3 0xd503
+#define regRCC_DEV1_EPF2_STRAP3_BASE_IDX 5
+#define regRCC_DEV1_EPF2_STRAP4 0xd504
+#define regRCC_DEV1_EPF2_STRAP4_BASE_IDX 5
+#define regRCC_DEV1_EPF2_STRAP5 0xd505
+#define regRCC_DEV1_EPF2_STRAP5_BASE_IDX 5
+#define regRCC_DEV1_EPF2_STRAP13 0xd50d
+#define regRCC_DEV1_EPF2_STRAP13_BASE_IDX 5
+#define regRCC_DEV1_EPF2_STRAP14 0xd50e
+#define regRCC_DEV1_EPF2_STRAP14_BASE_IDX 5
+#define regRCC_DEV1_EPF3_STRAP0 0xd580
+#define regRCC_DEV1_EPF3_STRAP0_BASE_IDX 5
+#define regRCC_DEV1_EPF3_STRAP2 0xd582
+#define regRCC_DEV1_EPF3_STRAP2_BASE_IDX 5
+#define regRCC_DEV1_EPF3_STRAP3 0xd583
+#define regRCC_DEV1_EPF3_STRAP3_BASE_IDX 5
+#define regRCC_DEV1_EPF3_STRAP4 0xd584
+#define regRCC_DEV1_EPF3_STRAP4_BASE_IDX 5
+#define regRCC_DEV1_EPF3_STRAP5 0xd585
+#define regRCC_DEV1_EPF3_STRAP5_BASE_IDX 5
+#define regRCC_DEV1_EPF3_STRAP13 0xd58d
+#define regRCC_DEV1_EPF3_STRAP13_BASE_IDX 5
+#define regRCC_DEV1_EPF3_STRAP14 0xd58e
+#define regRCC_DEV1_EPF3_STRAP14_BASE_IDX 5
+#define regRCC_DEV1_EPF4_STRAP0 0xd600
+#define regRCC_DEV1_EPF4_STRAP0_BASE_IDX 5
+#define regRCC_DEV1_EPF4_STRAP2 0xd602
+#define regRCC_DEV1_EPF4_STRAP2_BASE_IDX 5
+#define regRCC_DEV1_EPF4_STRAP3 0xd603
+#define regRCC_DEV1_EPF4_STRAP3_BASE_IDX 5
+#define regRCC_DEV1_EPF4_STRAP4 0xd604
+#define regRCC_DEV1_EPF4_STRAP4_BASE_IDX 5
+#define regRCC_DEV1_EPF4_STRAP5 0xd605
+#define regRCC_DEV1_EPF4_STRAP5_BASE_IDX 5
+#define regRCC_DEV1_EPF4_STRAP13 0xd60d
+#define regRCC_DEV1_EPF4_STRAP13_BASE_IDX 5
+#define regRCC_DEV1_EPF4_STRAP14 0xd60e
+#define regRCC_DEV1_EPF4_STRAP14_BASE_IDX 5
+#define regRCC_DEV1_EPF5_STRAP0 0xd680
+#define regRCC_DEV1_EPF5_STRAP0_BASE_IDX 5
+#define regRCC_DEV1_EPF5_STRAP2 0xd682
+#define regRCC_DEV1_EPF5_STRAP2_BASE_IDX 5
+#define regRCC_DEV1_EPF5_STRAP3 0xd683
+#define regRCC_DEV1_EPF5_STRAP3_BASE_IDX 5
+#define regRCC_DEV1_EPF5_STRAP4 0xd684
+#define regRCC_DEV1_EPF5_STRAP4_BASE_IDX 5
+#define regRCC_DEV1_EPF5_STRAP5 0xd685
+#define regRCC_DEV1_EPF5_STRAP5_BASE_IDX 5
+#define regRCC_DEV1_EPF5_STRAP13 0xd68d
+#define regRCC_DEV1_EPF5_STRAP13_BASE_IDX 5
+#define regRCC_DEV1_EPF5_STRAP14 0xd68e
+#define regRCC_DEV1_EPF5_STRAP14_BASE_IDX 5
+#define regRCC_DEV2_EPF0_STRAP0 0xd800
+#define regRCC_DEV2_EPF0_STRAP0_BASE_IDX 5
+#define regRCC_DEV2_EPF0_STRAP2 0xd802
+#define regRCC_DEV2_EPF0_STRAP2_BASE_IDX 5
+#define regRCC_DEV2_EPF0_STRAP3 0xd803
+#define regRCC_DEV2_EPF0_STRAP3_BASE_IDX 5
+#define regRCC_DEV2_EPF0_STRAP4 0xd804
+#define regRCC_DEV2_EPF0_STRAP4_BASE_IDX 5
+#define regRCC_DEV2_EPF0_STRAP5 0xd805
+#define regRCC_DEV2_EPF0_STRAP5_BASE_IDX 5
+#define regRCC_DEV2_EPF0_STRAP6 0xd806
+#define regRCC_DEV2_EPF0_STRAP6_BASE_IDX 5
+#define regRCC_DEV2_EPF0_STRAP7 0xd807
+#define regRCC_DEV2_EPF0_STRAP7_BASE_IDX 5
+#define regRCC_DEV2_EPF0_STRAP13 0xd80d
+#define regRCC_DEV2_EPF0_STRAP13_BASE_IDX 5
+#define regRCC_DEV2_EPF0_STRAP14 0xd80e
+#define regRCC_DEV2_EPF0_STRAP14_BASE_IDX 5
+#define regRCC_DEV2_EPF1_STRAP0 0xd880
+#define regRCC_DEV2_EPF1_STRAP0_BASE_IDX 5
+#define regRCC_DEV2_EPF1_STRAP2 0xd882
+#define regRCC_DEV2_EPF1_STRAP2_BASE_IDX 5
+#define regRCC_DEV2_EPF1_STRAP3 0xd883
+#define regRCC_DEV2_EPF1_STRAP3_BASE_IDX 5
+#define regRCC_DEV2_EPF1_STRAP4 0xd884
+#define regRCC_DEV2_EPF1_STRAP4_BASE_IDX 5
+#define regRCC_DEV2_EPF1_STRAP5 0xd885
+#define regRCC_DEV2_EPF1_STRAP5_BASE_IDX 5
+#define regRCC_DEV2_EPF1_STRAP6 0xd886
+#define regRCC_DEV2_EPF1_STRAP6_BASE_IDX 5
+#define regRCC_DEV2_EPF1_STRAP13 0xd88d
+#define regRCC_DEV2_EPF1_STRAP13_BASE_IDX 5
+#define regRCC_DEV2_EPF1_STRAP14 0xd88e
+#define regRCC_DEV2_EPF1_STRAP14_BASE_IDX 5
+#define regRCC_DEV2_EPF2_STRAP0 0xd900
+#define regRCC_DEV2_EPF2_STRAP0_BASE_IDX 5
+#define regRCC_DEV2_EPF2_STRAP2 0xd902
+#define regRCC_DEV2_EPF2_STRAP2_BASE_IDX 5
+#define regRCC_DEV2_EPF2_STRAP3 0xd903
+#define regRCC_DEV2_EPF2_STRAP3_BASE_IDX 5
+#define regRCC_DEV2_EPF2_STRAP4 0xd904
+#define regRCC_DEV2_EPF2_STRAP4_BASE_IDX 5
+#define regRCC_DEV2_EPF2_STRAP5 0xd905
+#define regRCC_DEV2_EPF2_STRAP5_BASE_IDX 5
+#define regRCC_DEV2_EPF2_STRAP6 0xd906
+#define regRCC_DEV2_EPF2_STRAP6_BASE_IDX 5
+#define regRCC_DEV2_EPF2_STRAP13 0xd90d
+#define regRCC_DEV2_EPF2_STRAP13_BASE_IDX 5
+#define regRCC_DEV2_EPF2_STRAP14 0xd90e
+#define regRCC_DEV2_EPF2_STRAP14_BASE_IDX 5
+
+
+// addressBlock: nbif_bif_rst_bif_rst_regblk
+// base address: 0x10100000
+#define regHARD_RST_CTRL 0xe000
+#define regHARD_RST_CTRL_BASE_IDX 5
+#define regRSMU_SOFT_RST_CTRL 0xe001
+#define regRSMU_SOFT_RST_CTRL_BASE_IDX 5
+#define regSELF_SOFT_RST 0xe002
+#define regSELF_SOFT_RST_BASE_IDX 5
+#define regBIF_GFX_DRV_VPU_RST 0xe003
+#define regBIF_GFX_DRV_VPU_RST_BASE_IDX 5
+#define regBIF_RST_MISC_CTRL 0xe004
+#define regBIF_RST_MISC_CTRL_BASE_IDX 5
+#define regBIF_RST_MISC_CTRL2 0xe005
+#define regBIF_RST_MISC_CTRL2_BASE_IDX 5
+#define regBIF_RST_MISC_CTRL3 0xe006
+#define regBIF_RST_MISC_CTRL3_BASE_IDX 5
+#define regDEV0_PF0_FLR_RST_CTRL 0xe008
+#define regDEV0_PF0_FLR_RST_CTRL_BASE_IDX 5
+#define regDEV0_PF1_FLR_RST_CTRL 0xe009
+#define regDEV0_PF1_FLR_RST_CTRL_BASE_IDX 5
+#define regDEV0_PF2_FLR_RST_CTRL 0xe00a
+#define regDEV0_PF2_FLR_RST_CTRL_BASE_IDX 5
+#define regDEV0_PF3_FLR_RST_CTRL 0xe00b
+#define regDEV0_PF3_FLR_RST_CTRL_BASE_IDX 5
+#define regDEV0_PF4_FLR_RST_CTRL 0xe00c
+#define regDEV0_PF4_FLR_RST_CTRL_BASE_IDX 5
+#define regDEV0_PF5_FLR_RST_CTRL 0xe00d
+#define regDEV0_PF5_FLR_RST_CTRL_BASE_IDX 5
+#define regDEV0_PF6_FLR_RST_CTRL 0xe00e
+#define regDEV0_PF6_FLR_RST_CTRL_BASE_IDX 5
+#define regBIF_INST_RESET_INTR_STS 0xe010
+#define regBIF_INST_RESET_INTR_STS_BASE_IDX 5
+#define regBIF_PF_FLR_INTR_STS 0xe011
+#define regBIF_PF_FLR_INTR_STS_BASE_IDX 5
+#define regBIF_D3HOTD0_INTR_STS 0xe012
+#define regBIF_D3HOTD0_INTR_STS_BASE_IDX 5
+#define regBIF_POWER_INTR_STS 0xe014
+#define regBIF_POWER_INTR_STS_BASE_IDX 5
+#define regBIF_PF_DSTATE_INTR_STS 0xe015
+#define regBIF_PF_DSTATE_INTR_STS_BASE_IDX 5
+#define regSELF_SOFT_RST_2 0xe016
+#define regSELF_SOFT_RST_2_BASE_IDX 5
+#define regBIF_INST_RESET_INTR_MASK 0xe020
+#define regBIF_INST_RESET_INTR_MASK_BASE_IDX 5
+#define regBIF_PF_FLR_INTR_MASK 0xe021
+#define regBIF_PF_FLR_INTR_MASK_BASE_IDX 5
+#define regBIF_D3HOTD0_INTR_MASK 0xe022
+#define regBIF_D3HOTD0_INTR_MASK_BASE_IDX 5
+#define regBIF_POWER_INTR_MASK 0xe024
+#define regBIF_POWER_INTR_MASK_BASE_IDX 5
+#define regBIF_PF_DSTATE_INTR_MASK 0xe025
+#define regBIF_PF_DSTATE_INTR_MASK_BASE_IDX 5
+#define regBIF_PF_FLR_RST 0xe040
+#define regBIF_PF_FLR_RST_BASE_IDX 5
+#define regBIF_DEV0_PF0_DSTATE_VALUE 0xe050
+#define regBIF_DEV0_PF0_DSTATE_VALUE_BASE_IDX 5
+#define regBIF_DEV0_PF1_DSTATE_VALUE 0xe051
+#define regBIF_DEV0_PF1_DSTATE_VALUE_BASE_IDX 5
+#define regBIF_DEV0_PF2_DSTATE_VALUE 0xe052
+#define regBIF_DEV0_PF2_DSTATE_VALUE_BASE_IDX 5
+#define regBIF_DEV0_PF3_DSTATE_VALUE 0xe053
+#define regBIF_DEV0_PF3_DSTATE_VALUE_BASE_IDX 5
+#define regBIF_DEV0_PF4_DSTATE_VALUE 0xe054
+#define regBIF_DEV0_PF4_DSTATE_VALUE_BASE_IDX 5
+#define regBIF_DEV0_PF5_DSTATE_VALUE 0xe055
+#define regBIF_DEV0_PF5_DSTATE_VALUE_BASE_IDX 5
+#define regBIF_DEV0_PF6_DSTATE_VALUE 0xe056
+#define regBIF_DEV0_PF6_DSTATE_VALUE_BASE_IDX 5
+#define regDEV0_PF0_D3HOTD0_RST_CTRL 0xe078
+#define regDEV0_PF0_D3HOTD0_RST_CTRL_BASE_IDX 5
+#define regDEV0_PF1_D3HOTD0_RST_CTRL 0xe079
+#define regDEV0_PF1_D3HOTD0_RST_CTRL_BASE_IDX 5
+#define regDEV0_PF2_D3HOTD0_RST_CTRL 0xe07a
+#define regDEV0_PF2_D3HOTD0_RST_CTRL_BASE_IDX 5
+#define regDEV0_PF3_D3HOTD0_RST_CTRL 0xe07b
+#define regDEV0_PF3_D3HOTD0_RST_CTRL_BASE_IDX 5
+#define regDEV0_PF4_D3HOTD0_RST_CTRL 0xe07c
+#define regDEV0_PF4_D3HOTD0_RST_CTRL_BASE_IDX 5
+#define regDEV0_PF5_D3HOTD0_RST_CTRL 0xe07d
+#define regDEV0_PF5_D3HOTD0_RST_CTRL_BASE_IDX 5
+#define regDEV0_PF6_D3HOTD0_RST_CTRL 0xe07e
+#define regDEV0_PF6_D3HOTD0_RST_CTRL_BASE_IDX 5
+#define regBIF_PORT0_DSTATE_VALUE 0xe230
+#define regBIF_PORT0_DSTATE_VALUE_BASE_IDX 5
+#define regBIF_USB_SHUB_RS_RESET_CNTL 0xe231
+#define regBIF_USB_SHUB_RS_RESET_CNTL_BASE_IDX 5
+
+
+// addressBlock: nbif_bif_misc_bif_misc_regblk
+// base address: 0x10100000
+#define regREGS_ROM_OFFSET_CTRL 0xcc23
+#define regREGS_ROM_OFFSET_CTRL_BASE_IDX 5
+#define regNBIF_STRAP_BIOS_CNTL 0xcc81
+#define regNBIF_STRAP_BIOS_CNTL_BASE_IDX 5
+#define regMISC_SCRATCH 0xe800
+#define regMISC_SCRATCH_BASE_IDX 5
+#define regINTR_LINE_POLARITY 0xe801
+#define regINTR_LINE_POLARITY_BASE_IDX 5
+#define regINTR_LINE_ENABLE 0xe802
+#define regINTR_LINE_ENABLE_BASE_IDX 5
+#define regOUTSTANDING_VC_ALLOC 0xe803
+#define regOUTSTANDING_VC_ALLOC_BASE_IDX 5
+#define regBIFC_MISC_CTRL0 0xe804
+#define regBIFC_MISC_CTRL0_BASE_IDX 5
+#define regBIFC_MISC_CTRL1 0xe805
+#define regBIFC_MISC_CTRL1_BASE_IDX 5
+#define regBIFC_BME_ERR_LOG_LB 0xe806
+#define regBIFC_BME_ERR_LOG_LB_BASE_IDX 5
+#define regBIFC_LC_TIMER_CTRL 0xe807
+#define regBIFC_LC_TIMER_CTRL_BASE_IDX 5
+#define regBIFC_RCCBIH_BME_ERR_LOG0 0xe808
+#define regBIFC_RCCBIH_BME_ERR_LOG0_BASE_IDX 5
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 0xe80a
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_BASE_IDX 5
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 0xe80b
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_BASE_IDX 5
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 0xe80c
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_BASE_IDX 5
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 0xe80d
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_BASE_IDX 5
+#define regBIFC_DMA_ATTR_CNTL2_DEV0 0xe81a
+#define regBIFC_DMA_ATTR_CNTL2_DEV0_BASE_IDX 5
+#define regBIFC_MISC_CTRL2 0xe822
+#define regBIFC_MISC_CTRL2_BASE_IDX 5
+#define regBME_DUMMY_CNTL_0 0xe825
+#define regBME_DUMMY_CNTL_0_BASE_IDX 5
+#define regBIFC_THT_CNTL 0xe827
+#define regBIFC_THT_CNTL_BASE_IDX 5
+#define regBIFC_HSTARB_CNTL 0xe828
+#define regBIFC_HSTARB_CNTL_BASE_IDX 5
+#define regBIFC_GSI_CNTL 0xe829
+#define regBIFC_GSI_CNTL_BASE_IDX 5
+#define regBIFC_PCIEFUNC_CNTL 0xe82a
+#define regBIFC_PCIEFUNC_CNTL_BASE_IDX 5
+#define regBIFC_PASID_CHECK_DIS 0xe82b
+#define regBIFC_PASID_CHECK_DIS_BASE_IDX 5
+#define regBIFC_SDP_CNTL_0 0xe82c
+#define regBIFC_SDP_CNTL_0_BASE_IDX 5
+#define regBIFC_SDP_CNTL_1 0xe82d
+#define regBIFC_SDP_CNTL_1_BASE_IDX 5
+#define regBIFC_PASID_STS 0xe82e
+#define regBIFC_PASID_STS_BASE_IDX 5
+#define regBIFC_ATHUB_ACT_CNTL 0xe82f
+#define regBIFC_ATHUB_ACT_CNTL_BASE_IDX 5
+#define regBIFC_PERF_CNTL_0 0xe830
+#define regBIFC_PERF_CNTL_0_BASE_IDX 5
+#define regBIFC_PERF_CNTL_1 0xe831
+#define regBIFC_PERF_CNTL_1_BASE_IDX 5
+#define regBIFC_PERF_CNT_MMIO_RD_L32BIT 0xe832
+#define regBIFC_PERF_CNT_MMIO_RD_L32BIT_BASE_IDX 5
+#define regBIFC_PERF_CNT_MMIO_WR_L32BIT 0xe833
+#define regBIFC_PERF_CNT_MMIO_WR_L32BIT_BASE_IDX 5
+#define regBIFC_PERF_CNT_DMA_RD_L32BIT 0xe834
+#define regBIFC_PERF_CNT_DMA_RD_L32BIT_BASE_IDX 5
+#define regBIFC_PERF_CNT_DMA_WR_L32BIT 0xe835
+#define regBIFC_PERF_CNT_DMA_WR_L32BIT_BASE_IDX 5
+#define regNBIF_REGIF_ERRSET_CTRL 0xe836
+#define regNBIF_REGIF_ERRSET_CTRL_BASE_IDX 5
+#define regBIFC_SDP_CNTL_2 0xe837
+#define regBIFC_SDP_CNTL_2_BASE_IDX 5
+#define regNBIF_PGMST_CTRL 0xe838
+#define regNBIF_PGMST_CTRL_BASE_IDX 5
+#define regNBIF_PGSLV_CTRL 0xe839
+#define regNBIF_PGSLV_CTRL_BASE_IDX 5
+#define regNBIF_PG_MISC_CTRL 0xe83a
+#define regNBIF_PG_MISC_CTRL_BASE_IDX 5
+#define regSMN_MST_EP_CNTL3 0xe83c
+#define regSMN_MST_EP_CNTL3_BASE_IDX 5
+#define regSMN_MST_EP_CNTL4 0xe83d
+#define regSMN_MST_EP_CNTL4_BASE_IDX 5
+#define regSMN_MST_CNTL1 0xe83e
+#define regSMN_MST_CNTL1_BASE_IDX 5
+#define regSMN_MST_EP_CNTL5 0xe83f
+#define regSMN_MST_EP_CNTL5_BASE_IDX 5
+#define regBIF_SELFRING_BUFFER_VID 0xe840
+#define regBIF_SELFRING_BUFFER_VID_BASE_IDX 5
+#define regBIF_SELFRING_VECTOR_CNTL 0xe841
+#define regBIF_SELFRING_VECTOR_CNTL_BASE_IDX 5
+#define regNBIF_STRAP_WRITE_CTRL 0xe845
+#define regNBIF_STRAP_WRITE_CTRL_BASE_IDX 5
+#define regNBIF_INTX_DSTATE_MISC_CNTL 0xe846
+#define regNBIF_INTX_DSTATE_MISC_CNTL_BASE_IDX 5
+#define regNBIF_PENDING_MISC_CNTL 0xe847
+#define regNBIF_PENDING_MISC_CNTL_BASE_IDX 5
+#define regBIF_GMI_WRR_WEIGHT 0xe848
+#define regBIF_GMI_WRR_WEIGHT_BASE_IDX 5
+#define regBIF_GMI_WRR_WEIGHT2 0xe849
+#define regBIF_GMI_WRR_WEIGHT2_BASE_IDX 5
+#define regBIF_GMI_WRR_WEIGHT3 0xe84a
+#define regBIF_GMI_WRR_WEIGHT3_BASE_IDX 5
+#define regNBIF_PWRBRK_REQUEST 0xe84c
+#define regNBIF_PWRBRK_REQUEST_BASE_IDX 5
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F0 0xe850
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F0_BASE_IDX 5
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F1 0xe851
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F1_BASE_IDX 5
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F2 0xe852
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F2_BASE_IDX 5
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F3 0xe853
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F3_BASE_IDX 5
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F4 0xe854
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F4_BASE_IDX 5
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F5 0xe855
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F5_BASE_IDX 5
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F6 0xe856
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F6_BASE_IDX 5
+#define regBIF_DMA_MP4_ERR_LOG 0xe870
+#define regBIF_DMA_MP4_ERR_LOG_BASE_IDX 5
+#define regBIF_PASID_ERR_LOG 0xe871
+#define regBIF_PASID_ERR_LOG_BASE_IDX 5
+#define regBIF_PASID_ERR_CLR 0xe872
+#define regBIF_PASID_ERR_CLR_BASE_IDX 5
+#define regNBIF_VWIRE_CTRL 0xe880
+#define regNBIF_VWIRE_CTRL_BASE_IDX 5
+#define regNBIF_SMN_VWR_VCHG_DIS_CTRL 0xe881
+#define regNBIF_SMN_VWR_VCHG_DIS_CTRL_BASE_IDX 5
+#define regNBIF_SMN_VWR_VCHG_RST_CTRL0 0xe882
+#define regNBIF_SMN_VWR_VCHG_RST_CTRL0_BASE_IDX 5
+#define regNBIF_SMN_VWR_VCHG_TRIG 0xe884
+#define regNBIF_SMN_VWR_VCHG_TRIG_BASE_IDX 5
+#define regNBIF_SMN_VWR_WTRIG_CNTL 0xe885
+#define regNBIF_SMN_VWR_WTRIG_CNTL_BASE_IDX 5
+#define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1 0xe886
+#define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1_BASE_IDX 5
+#define regNBIF_MGCG_CTRL_LCLK 0xe887
+#define regNBIF_MGCG_CTRL_LCLK_BASE_IDX 5
+#define regNBIF_DS_CTRL_LCLK 0xe888
+#define regNBIF_DS_CTRL_LCLK_BASE_IDX 5
+#define regSMN_MST_CNTL0 0xe889
+#define regSMN_MST_CNTL0_BASE_IDX 5
+#define regSMN_MST_EP_CNTL1 0xe88a
+#define regSMN_MST_EP_CNTL1_BASE_IDX 5
+#define regSMN_MST_EP_CNTL2 0xe88b
+#define regSMN_MST_EP_CNTL2_BASE_IDX 5
+#define regNBIF_SDP_VWR_VCHG_DIS_CTRL 0xe88c
+#define regNBIF_SDP_VWR_VCHG_DIS_CTRL_BASE_IDX 5
+#define regNBIF_SDP_VWR_VCHG_RST_CTRL0 0xe88d
+#define regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX 5
+#define regNBIF_SDP_VWR_VCHG_RST_CTRL1 0xe88e
+#define regNBIF_SDP_VWR_VCHG_RST_CTRL1_BASE_IDX 5
+#define regNBIF_SDP_VWR_VCHG_TRIG 0xe88f
+#define regNBIF_SDP_VWR_VCHG_TRIG_BASE_IDX 5
+#define regNBIF_SHUB_TODET_CTRL 0xe898
+#define regNBIF_SHUB_TODET_CTRL_BASE_IDX 5
+#define regNBIF_SHUB_TODET_CLIENT_CTRL 0xe899
+#define regNBIF_SHUB_TODET_CLIENT_CTRL_BASE_IDX 5
+#define regNBIF_SHUB_TODET_CLIENT_STATUS 0xe89a
+#define regNBIF_SHUB_TODET_CLIENT_STATUS_BASE_IDX 5
+#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL 0xe89b
+#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL_BASE_IDX 5
+#define regNBIF_SHUB_TODET_CLIENT_CTRL2 0xe89c
+#define regNBIF_SHUB_TODET_CLIENT_CTRL2_BASE_IDX 5
+#define regNBIF_SHUB_TODET_CLIENT_STATUS2 0xe89d
+#define regNBIF_SHUB_TODET_CLIENT_STATUS2_BASE_IDX 5
+#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2 0xe89e
+#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2_BASE_IDX 5
+#define regBIFC_BME_ERR_LOG_HB 0xe8ab
+#define regBIFC_BME_ERR_LOG_HB_BASE_IDX 5
+#define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC 0xe8c0
+#define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC_BASE_IDX 5
+#define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC 0xe8c1
+#define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC_BASE_IDX 5
+#define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC 0xe8c2
+#define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX 5
+#define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC 0xe8c3
+#define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX 5
+#define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC 0xe8c4
+#define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC_BASE_IDX 5
+#define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC 0xe8c5
+#define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC_BASE_IDX 5
+#define regDISCON_HYSTERESIS_HEAD_CTRL 0xe8c6
+#define regDISCON_HYSTERESIS_HEAD_CTRL_BASE_IDX 5
+#define regBIFC_EARLY_WAKEUP_CNTL 0xe8d2
+#define regBIFC_EARLY_WAKEUP_CNTL_BASE_IDX 5
+#define regBIFC_PERF_CNT_MMIO_RD_H16BIT 0xe8f0
+#define regBIFC_PERF_CNT_MMIO_RD_H16BIT_BASE_IDX 5
+#define regBIFC_PERF_CNT_MMIO_WR_H16BIT 0xe8f1
+#define regBIFC_PERF_CNT_MMIO_WR_H16BIT_BASE_IDX 5
+#define regBIFC_PERF_CNT_DMA_RD_H16BIT 0xe8f2
+#define regBIFC_PERF_CNT_DMA_RD_H16BIT_BASE_IDX 5
+#define regBIFC_PERF_CNT_DMA_WR_H16BIT 0xe8f3
+#define regBIFC_PERF_CNT_DMA_WR_H16BIT_BASE_IDX 5
+#define regNBIF_PERF_COM_COUNT_ENABLE 0xe8f4
+#define regNBIF_PERF_COM_COUNT_ENABLE_BASE_IDX 5
+#define regNBIF_BX_PERF_CNT_FSM 0xe8ff
+#define regNBIF_BX_PERF_CNT_FSM_BASE_IDX 5
+#define regNBIF_COM_COUNT_VALUE 0xe908
+#define regNBIF_COM_COUNT_VALUE_BASE_IDX 5
+#define regBIFC_A2S_SDP_PORT_CTRL 0xeb00
+#define regBIFC_A2S_SDP_PORT_CTRL_BASE_IDX 5
+#define regBIFC_A2S_CNTL_SW0 0xeb01
+#define regBIFC_A2S_CNTL_SW0_BASE_IDX 5
+#define regBIFC_A2S_MISC_CNTL 0xeb02
+#define regBIFC_A2S_MISC_CNTL_BASE_IDX 5
+#define regBIFC_A2S_TAG_ALLOC_0 0xeb03
+#define regBIFC_A2S_TAG_ALLOC_0_BASE_IDX 5
+#define regBIFC_A2S_TAG_ALLOC_1 0xeb04
+#define regBIFC_A2S_TAG_ALLOC_1_BASE_IDX 5
+
+
+// addressBlock: nbif_bif_ras_bif_ras_regblk
+// base address: 0x10100000
+#define regBIFL_RAS_CENTRAL_CNTL 0xe400
+#define regBIFL_RAS_CENTRAL_CNTL_BASE_IDX 5
+#define regBIFL_RAS_CENTRAL_STATUS 0xe410
+#define regBIFL_RAS_CENTRAL_STATUS_BASE_IDX 5
+#define regBIFL_RAS_LEAF0_CTRL 0xe420
+#define regBIFL_RAS_LEAF0_CTRL_BASE_IDX 5
+#define regBIFL_RAS_LEAF1_CTRL 0xe421
+#define regBIFL_RAS_LEAF1_CTRL_BASE_IDX 5
+#define regBIFL_RAS_LEAF2_CTRL 0xe422
+#define regBIFL_RAS_LEAF2_CTRL_BASE_IDX 5
+#define regBIFL_RAS_LEAF3_CTRL 0xe423
+#define regBIFL_RAS_LEAF3_CTRL_BASE_IDX 5
+#define regBIFL_RAS_LEAF0_STATUS 0xe430
+#define regBIFL_RAS_LEAF0_STATUS_BASE_IDX 5
+#define regBIFL_RAS_LEAF1_STATUS 0xe431
+#define regBIFL_RAS_LEAF1_STATUS_BASE_IDX 5
+#define regBIFL_RAS_LEAF2_STATUS 0xe432
+#define regBIFL_RAS_LEAF2_STATUS_BASE_IDX 5
+#define regBIFL_RAS_LEAF3_STATUS 0xe433
+#define regBIFL_RAS_LEAF3_STATUS_BASE_IDX 5
+#define regBIFL_IOHUB_RAS_IH_CNTL 0xe7fe
+#define regBIFL_IOHUB_RAS_IH_CNTL_BASE_IDX 5
+#define regBIFL_RAS_VWR_FROM_IOHUB 0xe7ff
+#define regBIFL_RAS_VWR_FROM_IOHUB_BASE_IDX 5
+
+
+// addressBlock: nbif_rcc_dwn_dev0_BIFDEC1
+// base address: 0x10120000
+#define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED 0x8d80
+#define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED_BASE_IDX 5
+#define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH 0x8d81
+#define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH_BASE_IDX 5
+#define regRCC_DWN_DEV0_2_DN_PCIE_CNTL 0x8d83
+#define regRCC_DWN_DEV0_2_DN_PCIE_CNTL_BASE_IDX 5
+#define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL 0x8d84
+#define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL_BASE_IDX 5
+#define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 0x8d85
+#define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2_BASE_IDX 5
+#define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL 0x8d86
+#define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL_BASE_IDX 5
+#define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL 0x8d87
+#define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL_BASE_IDX 5
+#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0 0x8d88
+#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0_BASE_IDX 5
+#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC 0x8d89
+#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC_BASE_IDX 5
+#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2 0x8d8a
+#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2_BASE_IDX 5
+
+
+// addressBlock: nbif_rcc_dwnp_dev0_BIFDEC1
+// base address: 0x10120000
+#define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL 0x8d8c
+#define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL_BASE_IDX 5
+#define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL 0x8d8d
+#define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL_BASE_IDX 5
+#define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL 0x8d8e
+#define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL_BASE_IDX 5
+#define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2 0x8d8f
+#define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2_BASE_IDX 5
+#define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC 0x8d90
+#define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC_BASE_IDX 5
+#define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP 0x8d91
+#define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP_BASE_IDX 5
+
+
+// addressBlock: nbif_rcc_ep_dev0_BIFDEC1
+// base address: 0x10120000
+#define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH 0x8d61
+#define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH_BASE_IDX 5
+#define regRCC_EP_DEV0_2_EP_PCIE_CNTL 0x8d63
+#define regRCC_EP_DEV0_2_EP_PCIE_CNTL_BASE_IDX 5
+#define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL 0x8d64
+#define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL_BASE_IDX 5
+#define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS 0x8d65
+#define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS_BASE_IDX 5
+#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 0x8d66
+#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2_BASE_IDX 5
+#define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL 0x8d67
+#define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL_BASE_IDX 5
+#define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL 0x8d68
+#define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL_BASE_IDX 5
+#define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL 0x8d6a
+#define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL_BASE_IDX 5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x8d6b
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x8d6b
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x8d6b
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x8d6b
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x8d6c
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x8d6c
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x8d6c
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x8d6c
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5
+#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC 0x8d6d
+#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC_BASE_IDX 5
+#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2 0x8d6e
+#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2_BASE_IDX 5
+#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP 0x8d70
+#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP_BASE_IDX 5
+#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x8d71
+#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 5
+#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL 0x8d71
+#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL_BASE_IDX 5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x8d71
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x8d72
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x8d72
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x8d72
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x8d72
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x8d73
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x8d73
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x8d73
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5
+#define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL 0x8d73
+#define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL_BASE_IDX 5
+#define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED 0x8d74
+#define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED_BASE_IDX 5
+#define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL 0x8d76
+#define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL_BASE_IDX 5
+#define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID 0x8d77
+#define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 5
+#define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL 0x8d78
+#define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL_BASE_IDX 5
+#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL 0x8d79
+#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL_BASE_IDX 5
+#define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL 0x8d7a
+#define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 5
+
+
+// addressBlock: nbif_rcc_dev0_BIFDEC1
+// base address: 0x10120000
+#define regRCC_DEV0_1_RCC_ERR_INT_CNTL 0x8da6
+#define regRCC_DEV0_1_RCC_ERR_INT_CNTL_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_BACO_CNTL_MISC 0x8da7
+#define regRCC_DEV0_1_RCC_BACO_CNTL_MISC_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_RESET_EN 0x8da8
+#define regRCC_DEV0_1_RCC_RESET_EN_BASE_IDX 5
+#define regRCC_DEV0_2_RCC_VDM_SUPPORT 0x8da9
+#define regRCC_DEV0_2_RCC_VDM_SUPPORT_BASE_IDX 5
+#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0 0x8daa
+#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 5
+#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1 0x8dab
+#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_GPUIOV_REGION 0x8dac
+#define regRCC_DEV0_1_RCC_GPUIOV_REGION_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN 0x8dad
+#define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL 0x8dae
+#define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x8daf
+#define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE 0x8daf
+#define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_PEER_REG_RANGE0 0x8dde
+#define regRCC_DEV0_1_RCC_PEER_REG_RANGE0_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_PEER_REG_RANGE1 0x8ddf
+#define regRCC_DEV0_1_RCC_PEER_REG_RANGE1_BASE_IDX 5
+#define regRCC_DEV0_2_RCC_BUS_CNTL 0x8de1
+#define regRCC_DEV0_2_RCC_BUS_CNTL_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_CONFIG_CNTL 0x8de2
+#define regRCC_DEV0_1_RCC_CONFIG_CNTL_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_CONFIG_F0_BASE 0x8de6
+#define regRCC_DEV0_1_RCC_CONFIG_F0_BASE_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE 0x8de7
+#define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE 0x8de8
+#define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_XDMA_LO 0x8de9
+#define regRCC_DEV0_1_RCC_XDMA_LO_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_XDMA_HI 0x8dea
+#define regRCC_DEV0_1_RCC_XDMA_HI_BASE_IDX 5
+#define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC 0x8deb
+#define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_BUSNUM_CNTL1 0x8dec
+#define regRCC_DEV0_1_RCC_BUSNUM_CNTL1_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_BUSNUM_LIST0 0x8ded
+#define regRCC_DEV0_1_RCC_BUSNUM_LIST0_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_BUSNUM_LIST1 0x8dee
+#define regRCC_DEV0_1_RCC_BUSNUM_LIST1_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_BUSNUM_CNTL2 0x8def
+#define regRCC_DEV0_1_RCC_BUSNUM_CNTL2_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM 0x8df0
+#define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_HOST_BUSNUM 0x8df1
+#define regRCC_DEV0_1_RCC_HOST_BUSNUM_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI 0x8df2
+#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO 0x8df3
+#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI 0x8df4
+#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO 0x8df5
+#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI 0x8df6
+#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO 0x8df7
+#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI 0x8df8
+#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO 0x8df9
+#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0 0x8dfa
+#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0_BASE_IDX 5
+#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1 0x8dfb
+#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1_BASE_IDX 5
+#define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL 0x8dfd
+#define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL_BASE_IDX 5
+#define regRCC_DEV0_2_RCC_CMN_LINK_CNTL 0x8dfe
+#define regRCC_DEV0_2_RCC_CMN_LINK_CNTL_BASE_IDX 5
+#define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE 0x8dff
+#define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 5
+#define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL 0x8e00
+#define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL_BASE_IDX 5
+#define regRCC_DEV0_2_RCC_MH_ARB_CNTL 0x8e01
+#define regRCC_DEV0_2_RCC_MH_ARB_CNTL_BASE_IDX 5
+
+
+// addressBlock: nbif_bif_bx_SYSDEC
+// base address: 0x10120000
+#define regBIF_BX1_PCIE_INDEX 0x800c
+#define regBIF_BX1_PCIE_INDEX_BASE_IDX 5
+#define regBIF_BX1_PCIE_DATA 0x800d
+#define regBIF_BX1_PCIE_DATA_BASE_IDX 5
+#define regBIF_BX1_PCIE_INDEX2 0x800e
+#define regBIF_BX1_PCIE_INDEX2_BASE_IDX 5
+#define regBIF_BX1_PCIE_DATA2 0x800f
+#define regBIF_BX1_PCIE_DATA2_BASE_IDX 5
+#define regBIF_BX1_PCIE_INDEX_HI 0x8010
+#define regBIF_BX1_PCIE_INDEX_HI_BASE_IDX 5
+#define regBIF_BX1_PCIE_INDEX2_HI 0x8011
+#define regBIF_BX1_PCIE_INDEX2_HI_BASE_IDX 5
+#define regBIF_BX1_SBIOS_SCRATCH_0 0x8048
+#define regBIF_BX1_SBIOS_SCRATCH_0_BASE_IDX 5
+#define regBIF_BX1_SBIOS_SCRATCH_1 0x8049
+#define regBIF_BX1_SBIOS_SCRATCH_1_BASE_IDX 5
+#define regBIF_BX1_SBIOS_SCRATCH_2 0x804a
+#define regBIF_BX1_SBIOS_SCRATCH_2_BASE_IDX 5
+#define regBIF_BX1_SBIOS_SCRATCH_3 0x804b
+#define regBIF_BX1_SBIOS_SCRATCH_3_BASE_IDX 5
+#define regBIF_BX1_BIOS_SCRATCH_0 0x804c
+#define regBIF_BX1_BIOS_SCRATCH_0_BASE_IDX 5
+#define regBIF_BX1_BIOS_SCRATCH_1 0x804d
+#define regBIF_BX1_BIOS_SCRATCH_1_BASE_IDX 5
+#define regBIF_BX1_BIOS_SCRATCH_2 0x804e
+#define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX 5
+#define regBIF_BX1_BIOS_SCRATCH_3 0x804f
+#define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX 5
+#define regBIF_BX1_BIOS_SCRATCH_4 0x8050
+#define regBIF_BX1_BIOS_SCRATCH_4_BASE_IDX 5
+#define regBIF_BX1_BIOS_SCRATCH_5 0x8051
+#define regBIF_BX1_BIOS_SCRATCH_5_BASE_IDX 5
+#define regBIF_BX1_BIOS_SCRATCH_6 0x8052
+#define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX 5
+#define regBIF_BX1_BIOS_SCRATCH_7 0x8053
+#define regBIF_BX1_BIOS_SCRATCH_7_BASE_IDX 5
+#define regBIF_BX1_BIOS_SCRATCH_8 0x8054
+#define regBIF_BX1_BIOS_SCRATCH_8_BASE_IDX 5
+#define regBIF_BX1_BIOS_SCRATCH_9 0x8055
+#define regBIF_BX1_BIOS_SCRATCH_9_BASE_IDX 5
+#define regBIF_BX1_BIOS_SCRATCH_10 0x8056
+#define regBIF_BX1_BIOS_SCRATCH_10_BASE_IDX 5
+#define regBIF_BX1_BIOS_SCRATCH_11 0x8057
+#define regBIF_BX1_BIOS_SCRATCH_11_BASE_IDX 5
+#define regBIF_BX1_BIOS_SCRATCH_12 0x8058
+#define regBIF_BX1_BIOS_SCRATCH_12_BASE_IDX 5
+#define regBIF_BX1_BIOS_SCRATCH_13 0x8059
+#define regBIF_BX1_BIOS_SCRATCH_13_BASE_IDX 5
+#define regBIF_BX1_BIOS_SCRATCH_14 0x805a
+#define regBIF_BX1_BIOS_SCRATCH_14_BASE_IDX 5
+#define regBIF_BX1_BIOS_SCRATCH_15 0x805b
+#define regBIF_BX1_BIOS_SCRATCH_15_BASE_IDX 5
+#define regBIF_BX1_BIF_RLC_INTR_CNTL 0x8060
+#define regBIF_BX1_BIF_RLC_INTR_CNTL_BASE_IDX 5
+#define regBIF_BX1_BIF_VCE_INTR_CNTL 0x8061
+#define regBIF_BX1_BIF_VCE_INTR_CNTL_BASE_IDX 5
+#define regBIF_BX1_BIF_UVD_INTR_CNTL 0x8062
+#define regBIF_BX1_BIF_UVD_INTR_CNTL_BASE_IDX 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0 0x8080
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 0x8081
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1 0x8082
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 0x8083
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2 0x8084
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 0x8085
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3 0x8086
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 0x8087
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4 0x8088
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 0x8089
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5 0x808a
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 0x808b
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6 0x808c
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 0x808d
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7 0x808e
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 0x808f
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_CNTL 0x8090
+#define regBIF_BX1_GFX_MMIOREG_CAM_CNTL_BASE_IDX 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL 0x8091
+#define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL 0x8092
+#define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x8093
+#define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 5
+#define regBIF_BX1_DRIVER_SCRATCH_0 0x8094
+#define regBIF_BX1_DRIVER_SCRATCH_0_BASE_IDX 5
+#define regBIF_BX1_DRIVER_SCRATCH_1 0x8095
+#define regBIF_BX1_DRIVER_SCRATCH_1_BASE_IDX 5
+#define regBIF_BX1_DRIVER_SCRATCH_2 0x8096
+#define regBIF_BX1_DRIVER_SCRATCH_2_BASE_IDX 5
+#define regBIF_BX1_DRIVER_SCRATCH_3 0x8097
+#define regBIF_BX1_DRIVER_SCRATCH_3_BASE_IDX 5
+#define regBIF_BX1_DRIVER_SCRATCH_4 0x8098
+#define regBIF_BX1_DRIVER_SCRATCH_4_BASE_IDX 5
+#define regBIF_BX1_DRIVER_SCRATCH_5 0x8099
+#define regBIF_BX1_DRIVER_SCRATCH_5_BASE_IDX 5
+#define regBIF_BX1_DRIVER_SCRATCH_6 0x809a
+#define regBIF_BX1_DRIVER_SCRATCH_6_BASE_IDX 5
+#define regBIF_BX1_DRIVER_SCRATCH_7 0x809b
+#define regBIF_BX1_DRIVER_SCRATCH_7_BASE_IDX 5
+#define regBIF_BX1_DRIVER_SCRATCH_8 0x809c
+#define regBIF_BX1_DRIVER_SCRATCH_8_BASE_IDX 5
+#define regBIF_BX1_DRIVER_SCRATCH_9 0x809d
+#define regBIF_BX1_DRIVER_SCRATCH_9_BASE_IDX 5
+#define regBIF_BX1_DRIVER_SCRATCH_10 0x809e
+#define regBIF_BX1_DRIVER_SCRATCH_10_BASE_IDX 5
+#define regBIF_BX1_DRIVER_SCRATCH_11 0x809f
+#define regBIF_BX1_DRIVER_SCRATCH_11_BASE_IDX 5
+#define regBIF_BX1_DRIVER_SCRATCH_12 0x80a0
+#define regBIF_BX1_DRIVER_SCRATCH_12_BASE_IDX 5
+#define regBIF_BX1_DRIVER_SCRATCH_13 0x80a1
+#define regBIF_BX1_DRIVER_SCRATCH_13_BASE_IDX 5
+#define regBIF_BX1_DRIVER_SCRATCH_14 0x80a2
+#define regBIF_BX1_DRIVER_SCRATCH_14_BASE_IDX 5
+#define regBIF_BX1_DRIVER_SCRATCH_15 0x80a3
+#define regBIF_BX1_DRIVER_SCRATCH_15_BASE_IDX 5
+#define regBIF_BX1_FW_SCRATCH_0 0x80a4
+#define regBIF_BX1_FW_SCRATCH_0_BASE_IDX 5
+#define regBIF_BX1_FW_SCRATCH_1 0x80a5
+#define regBIF_BX1_FW_SCRATCH_1_BASE_IDX 5
+#define regBIF_BX1_FW_SCRATCH_2 0x80a6
+#define regBIF_BX1_FW_SCRATCH_2_BASE_IDX 5
+#define regBIF_BX1_FW_SCRATCH_3 0x80a7
+#define regBIF_BX1_FW_SCRATCH_3_BASE_IDX 5
+#define regBIF_BX1_FW_SCRATCH_4 0x80a8
+#define regBIF_BX1_FW_SCRATCH_4_BASE_IDX 5
+#define regBIF_BX1_FW_SCRATCH_5 0x80a9
+#define regBIF_BX1_FW_SCRATCH_5_BASE_IDX 5
+#define regBIF_BX1_FW_SCRATCH_6 0x80aa
+#define regBIF_BX1_FW_SCRATCH_6_BASE_IDX 5
+#define regBIF_BX1_FW_SCRATCH_7 0x80ab
+#define regBIF_BX1_FW_SCRATCH_7_BASE_IDX 5
+#define regBIF_BX1_FW_SCRATCH_8 0x80ac
+#define regBIF_BX1_FW_SCRATCH_8_BASE_IDX 5
+#define regBIF_BX1_FW_SCRATCH_9 0x80ad
+#define regBIF_BX1_FW_SCRATCH_9_BASE_IDX 5
+#define regBIF_BX1_FW_SCRATCH_10 0x80ae
+#define regBIF_BX1_FW_SCRATCH_10_BASE_IDX 5
+#define regBIF_BX1_FW_SCRATCH_11 0x80af
+#define regBIF_BX1_FW_SCRATCH_11_BASE_IDX 5
+#define regBIF_BX1_FW_SCRATCH_12 0x80b0
+#define regBIF_BX1_FW_SCRATCH_12_BASE_IDX 5
+#define regBIF_BX1_FW_SCRATCH_13 0x80b1
+#define regBIF_BX1_FW_SCRATCH_13_BASE_IDX 5
+#define regBIF_BX1_FW_SCRATCH_14 0x80b2
+#define regBIF_BX1_FW_SCRATCH_14_BASE_IDX 5
+#define regBIF_BX1_FW_SCRATCH_15 0x80b3
+#define regBIF_BX1_FW_SCRATCH_15_BASE_IDX 5
+#define regBIF_BX1_SBIOS_SCRATCH_4 0x80b4
+#define regBIF_BX1_SBIOS_SCRATCH_4_BASE_IDX 5
+#define regBIF_BX1_SBIOS_SCRATCH_5 0x80b5
+#define regBIF_BX1_SBIOS_SCRATCH_5_BASE_IDX 5
+#define regBIF_BX1_SBIOS_SCRATCH_6 0x80b6
+#define regBIF_BX1_SBIOS_SCRATCH_6_BASE_IDX 5
+#define regBIF_BX1_SBIOS_SCRATCH_7 0x80b7
+#define regBIF_BX1_SBIOS_SCRATCH_7_BASE_IDX 5
+#define regBIF_BX1_SBIOS_SCRATCH_8 0x80b8
+#define regBIF_BX1_SBIOS_SCRATCH_8_BASE_IDX 5
+#define regBIF_BX1_SBIOS_SCRATCH_9 0x80b9
+#define regBIF_BX1_SBIOS_SCRATCH_9_BASE_IDX 5
+#define regBIF_BX1_SBIOS_SCRATCH_10 0x80ba
+#define regBIF_BX1_SBIOS_SCRATCH_10_BASE_IDX 5
+#define regBIF_BX1_SBIOS_SCRATCH_11 0x80bb
+#define regBIF_BX1_SBIOS_SCRATCH_11_BASE_IDX 5
+#define regBIF_BX1_SBIOS_SCRATCH_12 0x80bc
+#define regBIF_BX1_SBIOS_SCRATCH_12_BASE_IDX 5
+#define regBIF_BX1_SBIOS_SCRATCH_13 0x80bd
+#define regBIF_BX1_SBIOS_SCRATCH_13_BASE_IDX 5
+#define regBIF_BX1_SBIOS_SCRATCH_14 0x80be
+#define regBIF_BX1_SBIOS_SCRATCH_14_BASE_IDX 5
+#define regBIF_BX1_SBIOS_SCRATCH_15 0x80bf
+#define regBIF_BX1_SBIOS_SCRATCH_15_BASE_IDX 5
+
+
+// addressBlock: nbif_bif_bx_pf_SYSPFVFDEC
+// base address: 0x10120000
+#define regBIF_BX_PF1_MM_INDEX 0x8000
+#define regBIF_BX_PF1_MM_INDEX_BASE_IDX 5
+#define regBIF_BX_PF1_MM_DATA 0x8001
+#define regBIF_BX_PF1_MM_DATA_BASE_IDX 5
+#define regBIF_BX_PF1_MM_INDEX_HI 0x8006
+#define regBIF_BX_PF1_MM_INDEX_HI_BASE_IDX 5
+#define regBIF_BX_PF1_RSMU_INDEX 0x8014
+#define regBIF_BX_PF1_RSMU_INDEX_BASE_IDX 5
+#define regBIF_BX_PF1_RSMU_DATA 0x8015
+#define regBIF_BX_PF1_RSMU_DATA_BASE_IDX 5
+
+
+// addressBlock: nbif_bif_bx_BIFDEC1
+// base address: 0x10120000
+#define regBIF_BX1_CC_BIF_BX_STRAP0 0x8e02
+#define regBIF_BX1_CC_BIF_BX_STRAP0_BASE_IDX 5
+#define regBIF_BX1_CC_BIF_BX_PINSTRAP0 0x8e04
+#define regBIF_BX1_CC_BIF_BX_PINSTRAP0_BASE_IDX 5
+#define regBIF_BX1_BIF_MM_INDACCESS_CNTL 0x8e06
+#define regBIF_BX1_BIF_MM_INDACCESS_CNTL_BASE_IDX 5
+#define regBIF_BX1_BUS_CNTL 0x8e07
+#define regBIF_BX1_BUS_CNTL_BASE_IDX 5
+#define regBIF_BX1_BIF_SCRATCH0 0x8e08
+#define regBIF_BX1_BIF_SCRATCH0_BASE_IDX 5
+#define regBIF_BX1_BIF_SCRATCH1 0x8e09
+#define regBIF_BX1_BIF_SCRATCH1_BASE_IDX 5
+#define regBIF_BX1_BX_RESET_EN 0x8e0d
+#define regBIF_BX1_BX_RESET_EN_BASE_IDX 5
+#define regBIF_BX1_MM_CFGREGS_CNTL 0x8e0e
+#define regBIF_BX1_MM_CFGREGS_CNTL_BASE_IDX 5
+#define regBIF_BX1_BX_RESET_CNTL 0x8e10
+#define regBIF_BX1_BX_RESET_CNTL_BASE_IDX 5
+#define regBIF_BX1_INTERRUPT_CNTL 0x8e11
+#define regBIF_BX1_INTERRUPT_CNTL_BASE_IDX 5
+#define regBIF_BX1_INTERRUPT_CNTL2 0x8e12
+#define regBIF_BX1_INTERRUPT_CNTL2_BASE_IDX 5
+#define regBIF_BX1_CLKREQB_PAD_CNTL 0x8e18
+#define regBIF_BX1_CLKREQB_PAD_CNTL_BASE_IDX 5
+#define regBIF_BX1_BIF_FEATURES_CONTROL_MISC 0x8e1b
+#define regBIF_BX1_BIF_FEATURES_CONTROL_MISC_BASE_IDX 5
+#define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC 0x8e1c
+#define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 5
+#define regBIF_BX1_BIF_DOORBELL_CNTL 0x8e1d
+#define regBIF_BX1_BIF_DOORBELL_CNTL_BASE_IDX 5
+#define regBIF_BX1_BIF_DOORBELL_INT_CNTL 0x8e1e
+#define regBIF_BX1_BIF_DOORBELL_INT_CNTL_BASE_IDX 5
+#define regBIF_BX1_BIF_FB_EN 0x8e20
+#define regBIF_BX1_BIF_FB_EN_BASE_IDX 5
+#define regBIF_BX1_BIF_INTR_CNTL 0x8e21
+#define regBIF_BX1_BIF_INTR_CNTL_BASE_IDX 5
+#define regBIF_BX1_BIF_MST_TRANS_PENDING_VF 0x8e29
+#define regBIF_BX1_BIF_MST_TRANS_PENDING_VF_BASE_IDX 5
+#define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF 0x8e2a
+#define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 5
+#define regBIF_BX1_BACO_CNTL 0x8e2b
+#define regBIF_BX1_BACO_CNTL_BASE_IDX 5
+#define regBIF_BX1_BIF_BACO_EXIT_TIME0 0x8e2c
+#define regBIF_BX1_BIF_BACO_EXIT_TIME0_BASE_IDX 5
+#define regBIF_BX1_BIF_BACO_EXIT_TIMER1 0x8e2d
+#define regBIF_BX1_BIF_BACO_EXIT_TIMER1_BASE_IDX 5
+#define regBIF_BX1_BIF_BACO_EXIT_TIMER2 0x8e2e
+#define regBIF_BX1_BIF_BACO_EXIT_TIMER2_BASE_IDX 5
+#define regBIF_BX1_BIF_BACO_EXIT_TIMER3 0x8e2f
+#define regBIF_BX1_BIF_BACO_EXIT_TIMER3_BASE_IDX 5
+#define regBIF_BX1_BIF_BACO_EXIT_TIMER4 0x8e30
+#define regBIF_BX1_BIF_BACO_EXIT_TIMER4_BASE_IDX 5
+#define regBIF_BX1_MEM_TYPE_CNTL 0x8e31
+#define regBIF_BX1_MEM_TYPE_CNTL_BASE_IDX 5
+#define regBIF_BX1_VF_REGWR_EN 0x8e44
+#define regBIF_BX1_VF_REGWR_EN_BASE_IDX 5
+#define regBIF_BX1_VF_DOORBELL_EN 0x8e45
+#define regBIF_BX1_VF_DOORBELL_EN_BASE_IDX 5
+#define regBIF_BX1_VF_FB_EN 0x8e46
+#define regBIF_BX1_VF_FB_EN_BASE_IDX 5
+#define regBIF_BX1_VF_REGWR_STATUS 0x8e47
+#define regBIF_BX1_VF_REGWR_STATUS_BASE_IDX 5
+#define regBIF_BX1_VF_DOORBELL_STATUS 0x8e48
+#define regBIF_BX1_VF_DOORBELL_STATUS_BASE_IDX 5
+#define regBIF_BX1_VF_FB_STATUS 0x8e49
+#define regBIF_BX1_VF_FB_STATUS_BASE_IDX 5
+#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL 0x8e4d
+#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 5
+#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL 0x8e4e
+#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 5
+#define regBIF_BX1_BIF_RB_CNTL 0x8e4f
+#define regBIF_BX1_BIF_RB_CNTL_BASE_IDX 5
+#define regBIF_BX1_BIF_RB_BASE 0x8e50
+#define regBIF_BX1_BIF_RB_BASE_BASE_IDX 5
+#define regBIF_BX1_BIF_RB_RPTR 0x8e51
+#define regBIF_BX1_BIF_RB_RPTR_BASE_IDX 5
+#define regBIF_BX1_BIF_RB_WPTR 0x8e52
+#define regBIF_BX1_BIF_RB_WPTR_BASE_IDX 5
+#define regBIF_BX1_BIF_RB_WPTR_ADDR_HI 0x8e53
+#define regBIF_BX1_BIF_RB_WPTR_ADDR_HI_BASE_IDX 5
+#define regBIF_BX1_BIF_RB_WPTR_ADDR_LO 0x8e54
+#define regBIF_BX1_BIF_RB_WPTR_ADDR_LO_BASE_IDX 5
+#define regBIF_BX1_MAILBOX_INDEX 0x8e55
+#define regBIF_BX1_MAILBOX_INDEX_BASE_IDX 5
+#define regBIF_BX1_BIF_MP1_INTR_CTRL 0x8e62
+#define regBIF_BX1_BIF_MP1_INTR_CTRL_BASE_IDX 5
+#define regBIF_BX1_BIF_PERSTB_PAD_CNTL 0x8e65
+#define regBIF_BX1_BIF_PERSTB_PAD_CNTL_BASE_IDX 5
+#define regBIF_BX1_BIF_PX_EN_PAD_CNTL 0x8e66
+#define regBIF_BX1_BIF_PX_EN_PAD_CNTL_BASE_IDX 5
+#define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL 0x8e67
+#define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 5
+#define regBIF_BX1_BIF_CLKREQB_PAD_CNTL 0x8e68
+#define regBIF_BX1_BIF_CLKREQB_PAD_CNTL_BASE_IDX 5
+#define regBIF_BX1_BIF_PWRBRK_PAD_CNTL 0x8e69
+#define regBIF_BX1_BIF_PWRBRK_PAD_CNTL_BASE_IDX 5
+#define regBIF_BX1_BIF_WAKEB_PAD_CNTL 0x8e6d
+#define regBIF_BX1_BIF_WAKEB_PAD_CNTL_BASE_IDX 5
+#define regBIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL 0x8e6e
+#define regBIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL_BASE_IDX 5
+#define regBIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL 0x8e70
+#define regBIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL_BASE_IDX 5
+#define regBIF_BX1_BIF_S5_MEM_POWER_CTRL0 0x8e71
+#define regBIF_BX1_BIF_S5_MEM_POWER_CTRL0_BASE_IDX 5
+#define regBIF_BX1_BIF_S5_MEM_POWER_CTRL1 0x8e72
+#define regBIF_BX1_BIF_S5_MEM_POWER_CTRL1_BASE_IDX 5
+#define regBIF_BX1_BIF_S5_DUMMY_REGS 0x8e73
+#define regBIF_BX1_BIF_S5_DUMMY_REGS_BASE_IDX 5
+
+
+// addressBlock: nbif_bif_bx_pf_BIFPFVFDEC1
+// base address: 0x10120000
+#define regBIF_BX_PF1_BIF_BME_STATUS 0x8e0b
+#define regBIF_BX_PF1_BIF_BME_STATUS_BASE_IDX 5
+#define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG 0x8e0c
+#define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 5
+#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13
+#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5
+#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14
+#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5
+#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15
+#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5
+#define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16
+#define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5
+#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17
+#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5
+#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19
+#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5
+#define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a
+#define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5
+#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ 0x8e26
+#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_BASE_IDX 5
+#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE 0x8e27
+#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_BASE_IDX 5
+#define regBIF_BX_PF1_BIF_TRANS_PENDING 0x8e28
+#define regBIF_BX_PF1_BIF_TRANS_PENDING_BASE_IDX 5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 0x8e56
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 0x8e57
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 0x8e58
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 0x8e59
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 0x8e5a
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 0x8e5b
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 0x8e5c
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 0x8e5d
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5
+#define regBIF_BX_PF1_MAILBOX_CONTROL 0x8e5e
+#define regBIF_BX_PF1_MAILBOX_CONTROL_BASE_IDX 5
+#define regBIF_BX_PF1_MAILBOX_INT_CNTL 0x8e5f
+#define regBIF_BX_PF1_MAILBOX_INT_CNTL_BASE_IDX 5
+#define regBIF_BX_PF1_BIF_VMHV_MAILBOX 0x8e60
+#define regBIF_BX_PF1_BIF_VMHV_MAILBOX_BASE_IDX 5
+
+
+// addressBlock: nbif_rcc_strap_BIFDEC1:1
+// base address: 0x10120000
+#define regRCC_STRAP2_RCC_BIF_STRAP0 0x8d20
+#define regRCC_STRAP2_RCC_BIF_STRAP0_BASE_IDX 5
+#define regRCC_STRAP2_RCC_BIF_STRAP1 0x8d21
+#define regRCC_STRAP2_RCC_BIF_STRAP1_BASE_IDX 5
+#define regRCC_STRAP2_RCC_BIF_STRAP2 0x8d25
+#define regRCC_STRAP2_RCC_BIF_STRAP2_BASE_IDX 5
+#define regRCC_STRAP2_RCC_BIF_STRAP3 0x8d26
+#define regRCC_STRAP2_RCC_BIF_STRAP3_BASE_IDX 5
+#define regRCC_STRAP2_RCC_BIF_STRAP4 0x8d27
+#define regRCC_STRAP2_RCC_BIF_STRAP4_BASE_IDX 5
+#define regRCC_STRAP2_RCC_BIF_STRAP5 0x8d28
+#define regRCC_STRAP2_RCC_BIF_STRAP5_BASE_IDX 5
+#define regRCC_STRAP2_RCC_BIF_STRAP6 0x8d29
+#define regRCC_STRAP2_RCC_BIF_STRAP6_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0 0x8d2d
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1 0x8d2e
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10 0x8d2f
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11 0x8d30
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12 0x8d31
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13 0x8d32
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14 0x8d33
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2 0x8d34
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3 0x8d35
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4 0x8d36
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5 0x8d37
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6 0x8d38
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7 0x8d39
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8 0x8d3a
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9 0x8d3b
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0 0x8d3c
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1 0x8d3d
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13 0x8d3e
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14 0x8d3f
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15 0x8d40
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16 0x8d41
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17 0x8d42
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18 0x8d43
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2 0x8d44
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3 0x8d46
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4 0x8d47
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5 0x8d48
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8 0x8d49
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9 0x8d4a
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0 0x8d4b
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2 0x8d56
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20 0x8d57
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21 0x8d58
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3 0x8d59
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4 0x8d5a
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5 0x8d5b
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6 0x8d5c
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6_BASE_IDX 5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7 0x8d5d
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7_BASE_IDX 5
+
+
+// addressBlock: nbif_gdc_dma_sion_SIONDEC
+// base address: 0x1400000
+#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0 0x4f7400
+#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1 0x4f7401
+#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0 0x4f7402
+#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1 0x4f7403
+#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0 0x4f7404
+#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1 0x4f7405
+#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0 0x4f7406
+#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1 0x4f7407
+#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG0 0x4f7408
+#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG1 0x4f7409
+#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG0 0x4f740a
+#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG1 0x4f740b
+#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0 0x4f740c
+#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1 0x4f740d
+#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0 0x4f740e
+#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1 0x4f740f
+#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0 0x4f7410
+#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1 0x4f7411
+#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0 0x4f7412
+#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1 0x4f7413
+#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0 0x4f7414
+#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1 0x4f7415
+#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0 0x4f7416
+#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1 0x4f7417
+#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0 0x4f7418
+#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1 0x4f7419
+#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0 0x4f741a
+#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1 0x4f741b
+#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG0 0x4f741c
+#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG1 0x4f741d
+#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG0 0x4f741e
+#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG1 0x4f741f
+#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0 0x4f7420
+#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1 0x4f7421
+#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0 0x4f7422
+#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1 0x4f7423
+#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0 0x4f7424
+#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1 0x4f7425
+#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0 0x4f7426
+#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1 0x4f7427
+#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0 0x4f7428
+#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1 0x4f7429
+#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0 0x4f742a
+#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1 0x4f742b
+#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0 0x4f742c
+#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1 0x4f742d
+#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0 0x4f742e
+#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1 0x4f742f
+#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG0 0x4f7430
+#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG1 0x4f7431
+#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG0 0x4f7432
+#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG1 0x4f7433
+#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0 0x4f7434
+#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1 0x4f7435
+#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0 0x4f7436
+#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1 0x4f7437
+#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0 0x4f7438
+#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1 0x4f7439
+#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0 0x4f743a
+#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1 0x4f743b
+#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0 0x4f743c
+#define regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1 0x4f743d
+#define regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0 0x4f743e
+#define regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1 0x4f743f
+#define regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0 0x4f7440
+#define regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1 0x4f7441
+#define regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0 0x4f7442
+#define regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1 0x4f7443
+#define regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL3_Req_BurstTarget_REG0 0x4f7444
+#define regGDC_DMA_SION_CL3_Req_BurstTarget_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL3_Req_BurstTarget_REG1 0x4f7445
+#define regGDC_DMA_SION_CL3_Req_BurstTarget_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL3_Req_TimeSlot_REG0 0x4f7446
+#define regGDC_DMA_SION_CL3_Req_TimeSlot_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL3_Req_TimeSlot_REG1 0x4f7447
+#define regGDC_DMA_SION_CL3_Req_TimeSlot_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0 0x4f7448
+#define regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1 0x4f7449
+#define regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0 0x4f744a
+#define regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1 0x4f744b
+#define regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0 0x4f744c
+#define regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1 0x4f744d
+#define regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0 0x4f744e
+#define regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1 0x4f744f
+#define regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_DMA_SION_CNTL_REG0 0x4f7450
+#define regGDC_DMA_SION_CNTL_REG0_BASE_IDX 3
+#define regGDC_DMA_SION_CNTL_REG1 0x4f7451
+#define regGDC_DMA_SION_CNTL_REG1_BASE_IDX 3
+
+
+// addressBlock: nbif_gdc_hst_sion_SIONDEC
+// base address: 0x1400000
+#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0 0x4f7600
+#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX 3
+#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1 0x4f7601
+#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX 3
+#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0 0x4f7602
+#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX 3
+#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1 0x4f7603
+#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX 3
+#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0 0x4f7604
+#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX 3
+#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1 0x4f7605
+#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX 3
+#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0 0x4f7606
+#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX 3
+#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1 0x4f7607
+#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX 3
+#define regGDC_HST_SION_CL0_Req_BurstTarget_REG0 0x4f7608
+#define regGDC_HST_SION_CL0_Req_BurstTarget_REG0_BASE_IDX 3
+#define regGDC_HST_SION_CL0_Req_BurstTarget_REG1 0x4f7609
+#define regGDC_HST_SION_CL0_Req_BurstTarget_REG1_BASE_IDX 3
+#define regGDC_HST_SION_CL0_Req_TimeSlot_REG0 0x4f760a
+#define regGDC_HST_SION_CL0_Req_TimeSlot_REG0_BASE_IDX 3
+#define regGDC_HST_SION_CL0_Req_TimeSlot_REG1 0x4f760b
+#define regGDC_HST_SION_CL0_Req_TimeSlot_REG1_BASE_IDX 3
+#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0 0x4f760c
+#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1 0x4f760d
+#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0 0x4f760e
+#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1 0x4f760f
+#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0 0x4f7610
+#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1 0x4f7611
+#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0 0x4f7612
+#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1 0x4f7613
+#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0 0x4f7614
+#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX 3
+#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1 0x4f7615
+#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX 3
+#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0 0x4f7616
+#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX 3
+#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1 0x4f7617
+#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX 3
+#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0 0x4f7618
+#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX 3
+#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1 0x4f7619
+#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX 3
+#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0 0x4f761a
+#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX 3
+#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1 0x4f761b
+#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX 3
+#define regGDC_HST_SION_CL1_Req_BurstTarget_REG0 0x4f761c
+#define regGDC_HST_SION_CL1_Req_BurstTarget_REG0_BASE_IDX 3
+#define regGDC_HST_SION_CL1_Req_BurstTarget_REG1 0x4f761d
+#define regGDC_HST_SION_CL1_Req_BurstTarget_REG1_BASE_IDX 3
+#define regGDC_HST_SION_CL1_Req_TimeSlot_REG0 0x4f761e
+#define regGDC_HST_SION_CL1_Req_TimeSlot_REG0_BASE_IDX 3
+#define regGDC_HST_SION_CL1_Req_TimeSlot_REG1 0x4f761f
+#define regGDC_HST_SION_CL1_Req_TimeSlot_REG1_BASE_IDX 3
+#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0 0x4f7620
+#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1 0x4f7621
+#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0 0x4f7622
+#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1 0x4f7623
+#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0 0x4f7624
+#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1 0x4f7625
+#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0 0x4f7626
+#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3
+#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1 0x4f7627
+#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3
+#define regGDC_HST_SION_CNTL_REG0 0x4f7628
+#define regGDC_HST_SION_CNTL_REG0_BASE_IDX 3
+#define regGDC_HST_SION_CNTL_REG1 0x4f7629
+#define regGDC_HST_SION_CNTL_REG1_BASE_IDX 3
+
+
+// addressBlock: nbif_gdc_GDCDEC
+// base address: 0x1400000
+#define regGDC1_SHUB_REGS_IF_CTL 0x4f0aa1
+#define regGDC1_SHUB_REGS_IF_CTL_BASE_IDX 3
+#define regGDC1_A2S_QUEUE_FIFO_ARB_CNTL 0x4f0aa2
+#define regGDC1_A2S_QUEUE_FIFO_ARB_CNTL_BASE_IDX 3
+#define regGDC1_NGDC_MGCG_CTRL 0x4f0aa7
+#define regGDC1_NGDC_MGCG_CTRL_BASE_IDX 3
+#define regGDC1_S2A_MISC_CNTL 0x4f0aa8
+#define regGDC1_S2A_MISC_CNTL_BASE_IDX 3
+#define regGDC1_NGDC_EARLY_WAKEUP_CTRL 0x4f0aac
+#define regGDC1_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX 3
+#define regGDC1_NGDC_PG_MISC_CTRL 0x4f0ab0
+#define regGDC1_NGDC_PG_MISC_CTRL_BASE_IDX 3
+#define regGDC1_NGDC_PGMST_CTRL 0x4f0ab1
+#define regGDC1_NGDC_PGMST_CTRL_BASE_IDX 3
+#define regGDC1_NGDC_PGSLV_CTRL 0x4f0ab2
+#define regGDC1_NGDC_PGSLV_CTRL_BASE_IDX 3
+#define regGDC1_ATDMA_MISC_CNTL 0x4f0b01
+#define regGDC1_ATDMA_MISC_CNTL_BASE_IDX 3
+
+
+// addressBlock: nbif_gdc_ras_gdc_ras_regblk
+// base address: 0x1400000
+#define regGDCSOC_ERR_RSP_CNTL 0x4f5c00
+#define regGDCSOC_ERR_RSP_CNTL_BASE_IDX 3
+#define regGDCSOC_RAS_CENTRAL_STATUS 0x4f5c10
+#define regGDCSOC_RAS_CENTRAL_STATUS_BASE_IDX 3
+#define regGDCSOC_RAS_LEAF0_CTRL 0x4f5c20
+#define regGDCSOC_RAS_LEAF0_CTRL_BASE_IDX 3
+#define regGDCSOC_RAS_LEAF1_CTRL 0x4f5c21
+#define regGDCSOC_RAS_LEAF1_CTRL_BASE_IDX 3
+#define regGDCSOC_RAS_LEAF2_CTRL 0x4f5c22
+#define regGDCSOC_RAS_LEAF2_CTRL_BASE_IDX 3
+#define regGDCSOC_RAS_LEAF3_CTRL 0x4f5c23
+#define regGDCSOC_RAS_LEAF3_CTRL_BASE_IDX 3
+#define regGDCSOC_RAS_LEAF4_CTRL 0x4f5c24
+#define regGDCSOC_RAS_LEAF4_CTRL_BASE_IDX 3
+#define regGDCSOC_RAS_LEAF2_MISC_CTRL 0x4f5c2e
+#define regGDCSOC_RAS_LEAF2_MISC_CTRL_BASE_IDX 3
+#define regGDCSOC_RAS_LEAF2_MISC_CTRL2 0x4f5c2f
+#define regGDCSOC_RAS_LEAF2_MISC_CTRL2_BASE_IDX 3
+#define regGDCSOC_RAS_LEAF0_STATUS 0x4f5c30
+#define regGDCSOC_RAS_LEAF0_STATUS_BASE_IDX 3
+#define regGDCSOC_RAS_LEAF1_STATUS 0x4f5c31
+#define regGDCSOC_RAS_LEAF1_STATUS_BASE_IDX 3
+#define regGDCSOC_RAS_LEAF2_STATUS 0x4f5c32
+#define regGDCSOC_RAS_LEAF2_STATUS_BASE_IDX 3
+#define regGDCSOC_RAS_LEAF3_STATUS 0x4f5c33
+#define regGDCSOC_RAS_LEAF3_STATUS_BASE_IDX 3
+#define regGDCSOC_RAS_LEAF4_STATUS 0x4f5c34
+#define regGDCSOC_RAS_LEAF4_STATUS_BASE_IDX 3
+
+
+// addressBlock: nbif_gdc_rst_GDCRST_DEC
+// base address: 0x1400000
+#define regSHUB_PF_FLR_RST 0x4f7800
+#define regSHUB_PF_FLR_RST_BASE_IDX 3
+#define regSHUB_GFX_DRV_VPU_RST 0x4f7801
+#define regSHUB_GFX_DRV_VPU_RST_BASE_IDX 3
+#define regSHUB_LINK_RESET 0x4f7802
+#define regSHUB_LINK_RESET_BASE_IDX 3
+#define regSHUB_HARD_RST_CTRL 0x4f7810
+#define regSHUB_HARD_RST_CTRL_BASE_IDX 3
+#define regSHUB_SOFT_RST_CTRL 0x4f7811
+#define regSHUB_SOFT_RST_CTRL_BASE_IDX 3
+#define regSHUB_SDP_PORT_RST 0x4f7812
+#define regSHUB_SDP_PORT_RST_BASE_IDX 3
+#define regSHUB_RST_MISC_TRL 0x4f7813
+#define regSHUB_RST_MISC_TRL_BASE_IDX 3
+
+
+// addressBlock: nbif_gdc_s2a_GDCS2A_DEC
+// base address: 0x1400000
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL 0x4f0aeb
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL 0x4f0aec
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL 0x4f0aed
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL 0x4f0aee
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL 0x4f0aef
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL 0x4f0af0
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL 0x4f0af1
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL 0x4f0af2
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL 0x4f0af3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL 0x4f0af4
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL 0x4f0af5
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL 0x4f0af6
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL 0x4f0af7
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL 0x4f0af8
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL 0x4f0af9
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL 0x4f0afa
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX 3
+#define regGDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG 0x4f0afb
+#define regGDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX 3
+#define regGDC_S2A1_NBIF_GFX_DOORBELL_STATUS 0x4f0afc
+#define regGDC_S2A1_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 3
+
+
+// addressBlock: nbif_gdc_a2s_GDCA2S_DEC
+// base address: 0x1400000
+#define regA2S_CNTL_SW0 0x4f0c40
+#define regA2S_CNTL_SW0_BASE_IDX 3
+#define regA2S_CNTL_SW1 0x4f0c41
+#define regA2S_CNTL_SW1_BASE_IDX 3
+#define regA2S_MISC_CNTL 0x4f0c72
+#define regA2S_MISC_CNTL_BASE_IDX 3
+#define regA2S_TAG_ALLOC_0 0x4f0c74
+#define regA2S_TAG_ALLOC_0_BASE_IDX 3
+#define regA2S_TAG_ALLOC_1 0x4f0c75
+#define regA2S_TAG_ALLOC_1_BASE_IDX 3
+
+
+// addressBlock: nbif_syshub_mmreg_syshubdirect
+// base address: 0x1400000
+#define regHST_CLK0_SW0_CL0_CNTL 0x4f3d40
+#define regHST_CLK0_SW0_CL0_CNTL_BASE_IDX 3
+#define regHST_CLK0_SW1_CL0_CNTL 0x4f3d60
+#define regHST_CLK0_SW1_CL0_CNTL_BASE_IDX 3
+#define regDMA_CLK0_SW0_CL0_CNTL 0x4f3e40
+#define regDMA_CLK0_SW0_CL0_CNTL_BASE_IDX 3
+#define regNIC400_1_ASIB_0_FN_MOD 0x4fbc42
+#define regNIC400_1_ASIB_0_FN_MOD_BASE_IDX 3
+#define regNIC400_1_IB_0_FN_MOD 0x4ff842
+#define regNIC400_1_IB_0_FN_MOD_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
+#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
+#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf0_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF0_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf0_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf0_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
+#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
+#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf1_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF1_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf1_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf1_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
+#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
+#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf2_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF2_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf2_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf2_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
+#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
+#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf3_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF3_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf3_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf3_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
+#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
+#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf4_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF4_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf4_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf4_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
+#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
+#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf5_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF5_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf5_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf5_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
+#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
+#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf6_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF6_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf6_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf6_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
+#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
+#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf7_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF7_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf7_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf7_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
+#define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
+#define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf8_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF8_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF8_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF8_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf8_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF8_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF8_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf8_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF8_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
+#define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
+#define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf9_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF9_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF9_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF9_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf9_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF9_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF9_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf9_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF9_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
+#define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
+#define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf10_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF10_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF10_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF10_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf10_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF10_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF10_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf10_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF10_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
+#define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
+#define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf11_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF11_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF11_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF11_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf11_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF11_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF11_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf11_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF11_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
+#define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
+#define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf12_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF12_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF12_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF12_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf12_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF12_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF12_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf12_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF12_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
+#define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
+#define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf13_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF13_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF13_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF13_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf13_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF13_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF13_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf13_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF13_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
+#define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
+#define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf14_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF14_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF14_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF14_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf14_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF14_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF14_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf14_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF14_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
+#define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
+#define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf15_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF15_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF15_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF15_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf15_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF15_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF15_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf15_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF15_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf16_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf16_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF16_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF16_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF16_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF16_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf16_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF16_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF16_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf16_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF16_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf17_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf17_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF17_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF17_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF17_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF17_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf17_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF17_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF17_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf17_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF17_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf18_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf18_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF18_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF18_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF18_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF18_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf18_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF18_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF18_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf18_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF18_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf19_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf19_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF19_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF19_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF19_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF19_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf19_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF19_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF19_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf19_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF19_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf20_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf20_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF20_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF20_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF20_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF20_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf20_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF20_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF20_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf20_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF20_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf21_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf21_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF21_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF21_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF21_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF21_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf21_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF21_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF21_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf21_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF21_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf22_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf22_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF22_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF22_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF22_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF22_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf22_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF22_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF22_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf22_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF22_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf23_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS 0x00eb
+#define regBIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG 0x00ec
+#define regBIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define regBIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING 0x0108
+#define regBIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL 0x013e
+#define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL 0x013f
+#define regBIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL_BASE_IDX 2
+#define regBIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX 0x0140
+#define regBIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf23_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF23_MM_INDEX 0x0000
+#define regBIF_BX_DEV0_EPF0_VF23_MM_INDEX_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF23_MM_DATA 0x0001
+#define regBIF_BX_DEV0_EPF0_VF23_MM_DATA_BASE_IDX 0
+#define regBIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI 0x0006
+#define regBIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf23_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF23_RCC_ERR_LOG 0x0085
+#define regRCC_DEV0_EPF0_VF23_RCC_ERR_LOG_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED 0x00c4
+#define regRCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define regRCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define regRCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf23_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL 0x0403
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL 0x0407
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL 0x040b
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL 0x040f
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_PBA 0x0800
+#define regRCC_DEV0_EPF0_VF23_GFXMSIX_PBA_BASE_IDX 3
+
+
+#endif
--- /dev/null
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _nbif_6_3_1_SH_MASK_HEADER
+#define _nbif_6_3_1_SH_MASK_HEADER
+
+
+// addressBlock: nbif_bif_cfg_dev0_rc_bifcfgdecp
+//IRQ_BRIDGE_CNTL
+#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_COMMAND
+#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_STATUS
+#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_LATENCY
+#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_HEADER
+#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_BIST
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L
+//BIF_CFG_DEV0_EPF0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_PMI_CAP
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L
+//BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_LINK_CAP_16GT
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_LINK_CAP_32GT
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L
+//BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L
+//BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF0_BIST
+#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL
+#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L
+#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L
+//BIF_CFG_DEV0_EPF0_VF0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF1_BIST
+#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL
+#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L
+#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L
+//BIF_CFG_DEV0_EPF0_VF1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf2_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF2_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_HEADER
+#define BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF2_BIST
+#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL
+#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L
+#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L
+//BIF_CFG_DEV0_EPF0_VF2_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF2_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf3_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF3_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_HEADER
+#define BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF3_BIST
+#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL
+#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L
+#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L
+//BIF_CFG_DEV0_EPF0_VF3_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF3_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf4_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF4_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_HEADER
+#define BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF4_BIST
+#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL
+#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L
+#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L
+//BIF_CFG_DEV0_EPF0_VF4_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF4_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf5_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF5_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_HEADER
+#define BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF5_BIST
+#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL
+#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L
+#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L
+//BIF_CFG_DEV0_EPF0_VF5_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF5_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf6_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF6_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_HEADER
+#define BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF6_BIST
+#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL
+#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L
+#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L
+//BIF_CFG_DEV0_EPF0_VF6_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF6_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf0_vf7_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF7_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_HEADER
+#define BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF7_BIST
+#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL
+#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L
+#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L
+//BIF_CFG_DEV0_EPF0_VF7_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF7_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_COMMAND
+#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF1_STATUS
+#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_REVISION_ID
+#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_LATENCY
+#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_HEADER
+#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_BIST
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L
+//BIF_CFG_DEV0_EPF1_CAP_PTR
+#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_PMI_CAP
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_LINK_CAP
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_MASK
+#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L
+//BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+
+
+// addressBlock: nbif_bif_bx_pf_SYSPFVFDEC
+//BIF_BX_PF0_MM_INDEX
+#define BIF_BX_PF0_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_PF0_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_PF0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_PF0_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_PF0_MM_DATA
+#define BIF_BX_PF0_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MM_INDEX_HI
+#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_RSMU_INDEX
+#define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX__SHIFT 0x0
+#define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_RSMU_DATA
+#define BIF_BX_PF0_RSMU_DATA__RSMU_DATA__SHIFT 0x0
+#define BIF_BX_PF0_RSMU_DATA__RSMU_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_RSMU_INDEX_HI
+#define BIF_BX_PF0_RSMU_INDEX_HI__RSMU_INDEX_HI__SHIFT 0x0
+#define BIF_BX_PF0_RSMU_INDEX_HI__RSMU_INDEX_HI_MASK 0x000000FFL
+
+
+// addressBlock: nbif_bif_bx_SYSDEC
+//BIF_BX0_PCIE_INDEX
+#define BIF_BX0_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
+#define BIF_BX0_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL
+//BIF_BX0_PCIE_DATA
+#define BIF_BX0_PCIE_DATA__PCIE_DATA__SHIFT 0x0
+#define BIF_BX0_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL
+//BIF_BX0_PCIE_INDEX2
+#define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0
+#define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL
+//BIF_BX0_PCIE_DATA2
+#define BIF_BX0_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0
+#define BIF_BX0_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL
+//BIF_BX0_PCIE_INDEX_HI
+#define BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT 0x0
+#define BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK 0x000000FFL
+//BIF_BX0_PCIE_INDEX2_HI
+#define BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT 0x0
+#define BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK 0x000000FFL
+//BIF_BX0_SBIOS_SCRATCH_0
+#define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT 0x0
+#define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK 0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_1
+#define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT 0x0
+#define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK 0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_2
+#define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT 0x0
+#define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK 0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_3
+#define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT 0x0
+#define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_0
+#define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_1
+#define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_2
+#define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_3
+#define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_4
+#define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_5
+#define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_6
+#define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_7
+#define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_8
+#define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_9
+#define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_10
+#define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_11
+#define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_12
+#define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_13
+#define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_14
+#define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_15
+#define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL
+//BIF_BX0_BIF_RLC_INTR_CNTL
+//BIF_BX0_BIF_VCE_INTR_CNTL
+//BIF_BX0_BIF_UVD_INTR_CNTL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR1
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR2
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR3
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR4
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR5
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR6
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR7
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_CNTL
+#define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL
+//BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL
+#define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL
+#define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
+#define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_0
+#define BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT 0x0
+#define BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK 0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_1
+#define BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT 0x0
+#define BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK 0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_2
+#define BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT 0x0
+#define BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK 0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_3
+#define BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT 0x0
+#define BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK 0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_4
+#define BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT 0x0
+#define BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK 0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_5
+#define BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT 0x0
+#define BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK 0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_6
+#define BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT 0x0
+#define BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK 0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_7
+#define BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT 0x0
+#define BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK 0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_8
+#define BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT 0x0
+#define BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK 0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_9
+#define BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT 0x0
+#define BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK 0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_10
+#define BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT 0x0
+#define BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK 0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_11
+#define BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT 0x0
+#define BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK 0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_12
+#define BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT 0x0
+#define BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK 0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_13
+#define BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT 0x0
+#define BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK 0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_14
+#define BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT 0x0
+#define BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK 0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_15
+#define BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT 0x0
+#define BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK 0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_0
+#define BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT 0x0
+#define BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0_MASK 0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_1
+#define BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT 0x0
+#define BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1_MASK 0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_2
+#define BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT 0x0
+#define BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2_MASK 0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_3
+#define BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT 0x0
+#define BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3_MASK 0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_4
+#define BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT 0x0
+#define BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4_MASK 0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_5
+#define BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT 0x0
+#define BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5_MASK 0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_6
+#define BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT 0x0
+#define BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6_MASK 0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_7
+#define BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT 0x0
+#define BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7_MASK 0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_8
+#define BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT 0x0
+#define BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8_MASK 0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_9
+#define BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT 0x0
+#define BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9_MASK 0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_10
+#define BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT 0x0
+#define BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10_MASK 0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_11
+#define BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT 0x0
+#define BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11_MASK 0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_12
+#define BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT 0x0
+#define BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12_MASK 0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_13
+#define BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT 0x0
+#define BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13_MASK 0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_14
+#define BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT 0x0
+#define BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14_MASK 0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_15
+#define BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT 0x0
+#define BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15_MASK 0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_4
+#define BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT 0x0
+#define BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK 0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_5
+#define BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT 0x0
+#define BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK 0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_6
+#define BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT 0x0
+#define BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK 0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_7
+#define BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT 0x0
+#define BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK 0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_8
+#define BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT 0x0
+#define BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK 0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_9
+#define BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT 0x0
+#define BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK 0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_10
+#define BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT 0x0
+#define BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK 0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_11
+#define BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT 0x0
+#define BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK 0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_12
+#define BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT 0x0
+#define BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK 0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_13
+#define BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT 0x0
+#define BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK 0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_14
+#define BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT 0x0
+#define BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK 0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_15
+#define BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT 0x0
+#define BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dwn_dev0_BIFDEC1
+//RCC_DWN_DEV0_0_DN_PCIE_RESERVED
+#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_0_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_0_DN_PCIE_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+//RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L
+//RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L
+//RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L
+//RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L
+
+
+// addressBlock: nbif_rcc_dwnp_dev0_BIFDEC1
+//RCC_DWNP_DEV0_0_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L
+//RCC_DWNP_DEV0_0_PCIE_RX_CNTL
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L
+//RCC_DWNP_DEV0_0_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
+#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L
+//RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0
+#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_ep_dev0_BIFDEC1
+//RCC_EP_DEV0_0_EP_PCIE_SCRATCH
+#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_0_EP_PCIE_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__MFIOV_GFX_F0_FLR_DIS__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__MFIOV_GFX_F0_FLR_DIS_MASK 0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_EP_DEV0_0_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L
+//RCC_EP_DEV0_0_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L
+//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+//RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+//RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L
+//RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC
+#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2
+#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
+#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L
+//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL
+//RCC_EP_DEV0_0_EP_PCIEP_RESERVED
+#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_0_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L
+//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L
+
+
+// addressBlock: nbif_bif_bx_BIFDEC1
+//BIF_BX0_CC_BIF_BX_STRAP0
+#define BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT 0x19
+#define BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK 0xFE000000L
+//BIF_BX0_CC_BIF_BX_PINSTRAP0
+//BIF_BX0_BIF_MM_INDACCESS_CNTL
+#define BIF_BX0_BIF_MM_INDACCESS_CNTL__WRITE_DIS__SHIFT 0x0
+#define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
+#define BIF_BX0_BIF_MM_INDACCESS_CNTL__WRITE_DIS_MASK 0x00000001L
+#define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L
+//BIF_BX0_BUS_CNTL
+#define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
+#define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
+#define BIF_BX0_BUS_CNTL__SET_AZ_TC__SHIFT 0xa
+#define BIF_BX0_BUS_CNTL__SET_MC_TC__SHIFT 0xd
+#define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
+#define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
+#define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
+#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT 0x18
+#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19
+#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a
+#define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT 0x1b
+#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT 0x1c
+#define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d
+#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e
+#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f
+#define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L
+#define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L
+#define BIF_BX0_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L
+#define BIF_BX0_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L
+#define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L
+#define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L
+#define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L
+#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK 0x01000000L
+#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L
+#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L
+#define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK 0x08000000L
+#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK 0x10000000L
+#define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L
+#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L
+#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L
+//BIF_BX0_BIF_SCRATCH0
+#define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
+#define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL
+//BIF_BX0_BIF_SCRATCH1
+#define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
+#define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL
+//BIF_BX0_BX_RESET_EN
+#define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10
+#define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L
+//BIF_BX0_MM_CFGREGS_CNTL
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L
+//BIF_BX0_BX_RESET_CNTL
+#define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0
+#define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L
+//BIF_BX0_INTERRUPT_CNTL
+#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
+#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
+#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
+#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
+#define BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
+#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
+#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10
+#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11
+#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12
+#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L
+#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L
+#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L
+#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L
+#define BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L
+#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L
+#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L
+#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L
+#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L
+//BIF_BX0_INTERRUPT_CNTL2
+#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
+#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL
+//BIF_BX0_CLKREQB_PAD_CNTL
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L
+//BIF_BX0_BIF_FEATURES_CONTROL_MISC
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT 0xb
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS__SHIFT 0xe
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT 0x10
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x19
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK 0x00000800L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS_MASK 0x00004000L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK 0x01FF0000L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x02000000L
+//BIF_BX0_HDP_ATOMIC_CONTROL_MISC
+#define BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT 0x0
+#define BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK 0x000000FFL
+//BIF_BX0_BIF_DOORBELL_CNTL
+#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0
+#define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1
+#define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
+#define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
+#define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b
+#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L
+#define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L
+#define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L
+#define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L
+#define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L
+//BIF_BX0_BIF_DOORBELL_INT_CNTL
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x17
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x1f
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x00800000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x80000000L
+//BIF_BX0_BIF_FB_EN
+#define BIF_BX0_BIF_FB_EN__FB_READ_EN__SHIFT 0x0
+#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
+#define BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L
+#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L
+//BIF_BX0_BIF_INTR_CNTL
+#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0
+#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L
+//BIF_BX0_BIF_MST_TRANS_PENDING_VF
+#define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL
+//BIF_BX0_BIF_SLV_TRANS_PENDING_VF
+#define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x7FFFFFFFL
+//BIF_BX0_BACO_CNTL
+#define BIF_BX0_BACO_CNTL__BACO_EN__SHIFT 0x0
+#define BIF_BX0_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2
+#define BIF_BX0_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3
+#define BIF_BX0_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5
+#define BIF_BX0_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6
+#define BIF_BX0_BACO_CNTL__BACO_MODE__SHIFT 0x8
+#define BIF_BX0_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9
+#define BIF_BX0_BACO_CNTL__PWRGOOD_VDDSOC__SHIFT 0x10
+#define BIF_BX0_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f
+#define BIF_BX0_BACO_CNTL__BACO_EN_MASK 0x00000001L
+#define BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L
+#define BIF_BX0_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L
+#define BIF_BX0_BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L
+#define BIF_BX0_BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L
+#define BIF_BX0_BACO_CNTL__BACO_MODE_MASK 0x00000100L
+#define BIF_BX0_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L
+#define BIF_BX0_BACO_CNTL__PWRGOOD_VDDSOC_MASK 0x00010000L
+#define BIF_BX0_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L
+//BIF_BX0_BIF_BACO_EXIT_TIME0
+#define BIF_BX0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0
+#define BIF_BX0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BX0_BIF_BACO_EXIT_TIMER1
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR__SHIFT 0x19
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR_MASK 0x02000000L
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L
+//BIF_BX0_BIF_BACO_EXIT_TIMER2
+#define BIF_BX0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0
+#define BIF_BX0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL
+//BIF_BX0_BIF_BACO_EXIT_TIMER3
+#define BIF_BX0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0
+#define BIF_BX0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BX0_BIF_BACO_EXIT_TIMER4
+#define BIF_BX0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0
+#define BIF_BX0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BX0_MEM_TYPE_CNTL
+#define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0
+#define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L
+//BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL
+#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL
+#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//BIF_BX0_BIF_RB_CNTL
+#define BIF_BX0_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define BIF_BX0_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
+#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
+#define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11
+#define BIF_BX0_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL__SHIFT 0x19
+#define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT 0x1a
+#define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT 0x1d
+#define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT 0x1e
+#define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define BIF_BX0_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define BIF_BX0_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L
+#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L
+#define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L
+#define BIF_BX0_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL_MASK 0x02000000L
+#define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK 0x1C000000L
+#define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK 0x20000000L
+#define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK 0x40000000L
+#define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
+//BIF_BX0_BIF_RB_BASE
+#define BIF_BX0_BIF_RB_BASE__ADDR__SHIFT 0x0
+#define BIF_BX0_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//BIF_BX0_BIF_RB_RPTR
+#define BIF_BX0_BIF_RB_RPTR__OFFSET__SHIFT 0x2
+#define BIF_BX0_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_BX0_BIF_RB_WPTR
+#define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0
+#define BIF_BX0_BIF_RB_WPTR__OFFSET__SHIFT 0x2
+#define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L
+#define BIF_BX0_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_BX0_BIF_RB_WPTR_ADDR_HI
+#define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL
+//BIF_BX0_BIF_RB_WPTR_ADDR_LO
+#define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//BIF_BX0_MAILBOX_INDEX
+#define BIF_BX0_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0
+#define BIF_BX0_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL
+//BIF_BX0_BIF_MP1_INTR_CTRL
+#define BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT 0x0
+#define BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK 0x00000001L
+//BIF_BX0_BIF_PERSTB_PAD_CNTL
+#define BIF_BX0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0
+#define BIF_BX0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL
+//BIF_BX0_BIF_PX_EN_PAD_CNTL
+#define BIF_BX0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0
+#define BIF_BX0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x00000FFFL
+//BIF_BX0_BIF_REFPADKIN_PAD_CNTL
+#define BIF_BX0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0
+#define BIF_BX0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL
+//BIF_BX0_BIF_CLKREQB_PAD_CNTL
+#define BIF_BX0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0
+#define BIF_BX0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x7FFFFFFFL
+//BIF_BX0_BIF_PWRBRK_PAD_CNTL
+#define BIF_BX0_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT 0x0
+#define BIF_BX0_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK 0x000000FFL
+
+
+// addressBlock: nbif_rcc_dev0_BIFDEC1
+//RCC_DEV0_0_RCC_ERR_INT_CNTL
+#define RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0
+#define RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L
+//RCC_DEV0_0_RCC_BACO_CNTL_MISC
+#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0
+#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1
+#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L
+#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L
+//RCC_DEV0_0_RCC_RESET_EN
+#define RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf
+#define RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L
+//RCC_DEV0_0_RCC_VDM_SUPPORT
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L
+//RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L
+//RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L
+//RCC_DEV0_0_RCC_GPUIOV_REGION
+#define RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION__SHIFT 0x0
+#define RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION__SHIFT 0x4
+#define RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION_MASK 0x0000000FL
+#define RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION_MASK 0x000000F0L
+//RCC_DEV0_0_RCC_GPU_HOSTVM_EN
+#define RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT 0x0
+#define RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK 0x00000001L
+//RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT 0x0
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT 0x1
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK 0x00000001L
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK 0x00000002L
+//RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT 0x0
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK 0xFFFFL
+//RCC_DEV0_0_RCC_PEER_REG_RANGE0
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L
+//RCC_DEV0_0_RCC_PEER_REG_RANGE1
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L
+//RCC_DEV0_0_RCC_BUS_CNTL
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8
+#define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc
+#define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15
+#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18
+#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19
+#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c
+#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L
+#define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L
+//RCC_DEV0_0_RCC_CONFIG_CNTL
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L
+//RCC_DEV0_0_RCC_CONFIG_F0_BASE
+#define RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0
+#define RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL
+//RCC_DEV0_0_RCC_CONFIG_APER_SIZE
+#define RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0
+#define RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE
+#define RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0
+#define RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x07FFFFFFL
+//RCC_DEV0_0_RCC_XDMA_LO
+#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0
+#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f
+#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL
+#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L
+//RCC_DEV0_0_RCC_XDMA_HI
+#define RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0
+#define RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL
+//RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L
+//RCC_DEV0_0_RCC_BUSNUM_CNTL1
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL
+//RCC_DEV0_0_RCC_BUSNUM_LIST0
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0__SHIFT 0x0
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1__SHIFT 0x8
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2__SHIFT 0x10
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3__SHIFT 0x18
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L
+//RCC_DEV0_0_RCC_BUSNUM_LIST1
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4__SHIFT 0x0
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5__SHIFT 0x8
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6__SHIFT 0x10
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7__SHIFT 0x18
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L
+//RCC_DEV0_0_RCC_BUSNUM_CNTL2
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L
+//RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM
+#define RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0
+#define RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L
+//RCC_DEV0_0_RCC_HOST_BUSNUM
+#define RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0
+#define RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL
+//RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L
+//RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L
+//RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L
+//RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L
+//RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000FFL
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000FF00L
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00FF0000L
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xFF000000L
+//RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000FFL
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000FF00L
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00FF0000L
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xFF000000L
+//RCC_DEV0_0_RCC_DEV0_LINK_CNTL
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT 0x10
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT 0x11
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK 0x00010000L
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK 0x00020000L
+//RCC_DEV0_0_RCC_CMN_LINK_CNTL
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L
+//RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L
+//RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL
+#define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0
+#define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL
+//RCC_DEV0_0_RCC_MH_ARB_CNTL
+#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0
+#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1
+#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L
+#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_BIFDEC2
+//RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbif_rcc_strap_BIFDEC1
+//RCC_STRAP0_RCC_BIF_STRAP0
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT 0x1
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x14
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN__SHIFT 0x15
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GPUIOV_EN__SHIFT 0x16
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT 0x1c
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK 0x00000001L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK 0x00000002L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000078L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00100000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN_MASK 0x00200000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GPUIOV_EN_MASK 0x00400000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK 0x10000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L
+//RCC_STRAP0_RCC_BIF_STRAP1
+#define RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1
+#define RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x2
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT 0x18
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT 0x19
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT 0x1e
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT 0x1f
+#define RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L
+#define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L
+#define RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK 0x01000000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK 0x02000000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_MASK 0x40000000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK 0x80000000L
+//RCC_STRAP0_RCC_BIF_STRAP2
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SPT__SHIFT 0x1
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN__SHIFT 0x7
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_USB_PD_FUNC_DIS__SHIFT 0xc
+#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SPT_MASK 0x00000002L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN_MASK 0x00000080L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_USB_PD_FUNC_DIS_MASK 0x00001000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L
+//RCC_STRAP0_RCC_BIF_STRAP3
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L
+//RCC_STRAP0_RCC_BIF_STRAP4
+#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10
+#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L
+//RCC_STRAP0_RCC_BIF_STRAP5
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT 0x15
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN__SHIFT 0x1f
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK 0x00200000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN_MASK 0x80000000L
+//RCC_STRAP0_RCC_BIF_STRAP6
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT 0x1
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT 0x2
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL__SHIFT 0x3
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_S5_GFX_REGS_ACCESS_DIS__SHIFT 0x4
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE__SHIFT 0x5
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GFX_PARTITION_CAP_SPX_SUPPORT__SHIFT 0x6
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GFX_PARTITION_CAP_TPX_SUPPORT__SHIFT 0x7
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_MEM_PARTITION_CAP_NPS1_SUPPORT__SHIFT 0x8
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_MEM_PARTITION_CAP_NPS3_SUPPORT__SHIFT 0x9
+#define RCC_STRAP0_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6__SHIFT 0xa
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK 0x00000001L
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK 0x00000002L
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK 0x00000004L
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL_MASK 0x00000008L
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_S5_GFX_REGS_ACCESS_DIS_MASK 0x00000010L
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE_MASK 0x00000020L
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GFX_PARTITION_CAP_SPX_SUPPORT_MASK 0x00000040L
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GFX_PARTITION_CAP_TPX_SUPPORT_MASK 0x00000080L
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_MEM_PARTITION_CAP_NPS1_SUPPORT_MASK 0x00000100L
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_MEM_PARTITION_CAP_NPS3_SUPPORT_MASK 0x00000200L
+#define RCC_STRAP0_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6_MASK 0xFFFFFC00L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x11
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x13
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00010000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00020000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00080000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT 0x2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT 0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT 0x4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT 0x5
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT 0x6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK 0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK 0x00000004L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK 0x00000008L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK 0x00000010L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK 0x00000020L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK 0x0007FFC0L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP11
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK 0x0FFF0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK 0x10000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK 0x40000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP12
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK 0x00FFFFFFL
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP13
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT 0x9
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK 0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK 0x00000100L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK 0x000FFE00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK 0xFFF00000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP14
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT 0x2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT 0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT 0x4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK 0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK 0x00000004L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK 0x00000008L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK 0x00000010L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP5
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x00E00000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x0F000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0xF0000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP9
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP1
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP13
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0xFF000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP15
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT 0xc
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK 0x00000FFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK 0x00FFF000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK 0x01000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP16
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT 0xc
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK 0x00000FFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK 0x00FFF000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP17
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT 0xc
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT 0xd
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK 0x00000FFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK 0x00001000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK 0x01FFE000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK 0x00000FFFL
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP2
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP3
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x11
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00010000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00020000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP4
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP5
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0_MASK 0x38000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP8
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00780000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP9
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP2
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP20
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP21
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP3
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x11
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00010000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00020000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP4
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP5
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT 0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK 0x38000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP6
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP7
+
+
+// addressBlock: nbif_bif_bx_pf_BIFPFVFDEC1
+//BIF_BX_PF0_BIF_BME_STATUS
+#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_PF0_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_PF0_GPU_HDP_FLUSH_REQ
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_PF0_GPU_HDP_FLUSH_DONE
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_PF0_BIF_TRANS_PENDING
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_CONTROL
+#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_PF0_MAILBOX_INT_CNTL
+#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_PF0_BIF_VMHV_MAILBOX
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_BIFPFVFDEC1
+//RCC_DEV0_EPF0_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_gdc_GDCDEC
+//GDC0_SHUB_REGS_IF_CTL
+#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0
+#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS__SHIFT 0x1
+#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L
+#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS_MASK 0x00000002L
+//GDC0_A2S_QUEUE_FIFO_ARB_CNTL
+#define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT 0x0
+#define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT 0xa
+#define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE__SHIFT 0x14
+#define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE__SHIFT 0x15
+#define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY_MASK 0x000003FFL
+#define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY_MASK 0x000FFC00L
+#define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE_MASK 0x00100000L
+#define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE_MASK 0x00200000L
+//GDC0_NGDC_MGCG_CTRL
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x0
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x1
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x2
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT 0xa
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT 0xb
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT 0xc
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT 0xd
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DBG_DIS__SHIFT 0xe
+#define GDC0_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN__SHIFT 0xf
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK 0x00000001L
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK 0x00000002L
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK 0x000003FCL
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK 0x00000400L
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK 0x00000800L
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK 0x00001000L
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK 0x00002000L
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DBG_DIS_MASK 0x00004000L
+#define GDC0_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN_MASK 0x00008000L
+//GDC0_S2A_MISC_CNTL
+#define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3
+#define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT 0x8
+#define GDC0_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT 0xa
+#define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT 0xc
+#define GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT 0xf
+#define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT 0x10
+#define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L
+#define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE_MASK 0x00000300L
+#define GDC0_S2A_MISC_CNTL__RB_ARB_MODE_MASK 0x00000C00L
+#define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK 0x00003000L
+#define GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK 0x00008000L
+#define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK 0x000F0000L
+//GDC0_NGDC_PG_MISC_CTRL
+#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY__SHIFT 0xa
+#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1__SHIFT 0xd
+#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS__SHIFT 0xe
+#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2__SHIFT 0x10
+#define GDC0_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18
+#define GDC0_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f
+#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY_MASK 0x00000400L
+#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1_MASK 0x00002000L
+#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS_MASK 0x00004000L
+#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2_MASK 0x00010000L
+#define GDC0_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L
+#define GDC0_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L
+//GDC0_NGDC_PGMST_CTRL
+#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS__SHIFT 0x0
+#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN__SHIFT 0x8
+#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN__SHIFT 0xa
+#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN__SHIFT 0xe
+#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS_MASK 0x000000FFL
+#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN_MASK 0x00000100L
+#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L
+#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L
+//GDC0_NGDC_PGSLV_CTRL
+#define GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0
+#define GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5
+#define GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS__SHIFT 0xa
+#define GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL
+#define GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L
+#define GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS_MASK 0x00007C00L
+//GDC0_ATDMA_MISC_CNTL
+#define GDC0_ATDMA_MISC_CNTL__ATDMA_WRR_ARB_MODE__SHIFT 0x0
+#define GDC0_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1
+#define GDC0_ATDMA_MISC_CNTL__ATDMA_RDRSP_ARB_MODE__SHIFT 0x2
+#define GDC0_ATDMA_MISC_CNTL__ATDMA_WRR_VC6_WEIGHT__SHIFT 0x8
+#define GDC0_ATDMA_MISC_CNTL__ATDMA_WRR_VC0_WEIGHT__SHIFT 0x10
+#define GDC0_ATDMA_MISC_CNTL__ATDMA_WRR_VC1_WEIGHT__SHIFT 0x18
+#define GDC0_ATDMA_MISC_CNTL__ATDMA_WRR_ARB_MODE_MASK 0x00000001L
+#define GDC0_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L
+#define GDC0_ATDMA_MISC_CNTL__ATDMA_RDRSP_ARB_MODE_MASK 0x0000000CL
+#define GDC0_ATDMA_MISC_CNTL__ATDMA_WRR_VC6_WEIGHT_MASK 0x0000FF00L
+#define GDC0_ATDMA_MISC_CNTL__ATDMA_WRR_VC0_WEIGHT_MASK 0x00FF0000L
+#define GDC0_ATDMA_MISC_CNTL__ATDMA_WRR_VC1_WEIGHT_MASK 0xFF000000L
+
+
+// addressBlock: nbif_gdc_s2a_GDCS2A_DEC
+//GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG
+#define GDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBE_FENCE_INTR_ENABLE__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBE_FENCE_INTR_ENABLE_MASK 0x00000002L
+//GDC_S2A0_NBIF_GFX_DOORBELL_STATUS
+#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT 0x0
+#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_EN__SHIFT 0x10
+#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_ST__SHIFT 0x18
+#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK 0x0000FFFFL
+#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_EN_MASK 0x00010000L
+#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_ST_MASK 0x01000000L
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf2_bifcfgdecp
+//BIF_CFG_DEV0_EPF2_VENDOR_ID
+#define BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_DEVICE_ID
+#define BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_COMMAND
+#define BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF2_STATUS
+#define BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_REVISION_ID
+#define BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF2_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_SUB_CLASS
+#define BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_BASE_CLASS
+#define BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_CACHE_LINE
+#define BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_LATENCY
+#define BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_HEADER
+#define BIF_CFG_DEV0_EPF2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF2_BIST
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL
+#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L
+#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L
+//BIF_CFG_DEV0_EPF2_CAP_PTR
+#define BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_MIN_GRANT
+#define BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF2_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PMI_CAP
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_SBRN
+#define BIF_CFG_DEV0_EPF2_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_FLADJ
+#define BIF_CFG_DEV0_EPF2_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF2_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF2_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF2_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF2_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF2_LINK_CAP
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_LINK_CNTL
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF2_LINK_STATUS
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF2_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_LINK_CAP2
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF2_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF2_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_MASK
+#define BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_PENDING
+#define BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_MSIX_PBA
+#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L
+//BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbif_bif_cfg_dev0_epf3_bifcfgdecp
+//BIF_CFG_DEV0_EPF3_VENDOR_ID
+#define BIF_CFG_DEV0_EPF3_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_DEVICE_ID
+#define BIF_CFG_DEV0_EPF3_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_COMMAND
+#define BIF_CFG_DEV0_EPF3_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF3_STATUS
+#define BIF_CFG_DEV0_EPF3_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_REVISION_ID
+#define BIF_CFG_DEV0_EPF3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF3_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_SUB_CLASS
+#define BIF_CFG_DEV0_EPF3_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_BASE_CLASS
+#define BIF_CFG_DEV0_EPF3_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_CACHE_LINE
+#define BIF_CFG_DEV0_EPF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_LATENCY
+#define BIF_CFG_DEV0_EPF3_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_HEADER
+#define BIF_CFG_DEV0_EPF3_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF3_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF3_BIST
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL
+#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L
+#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L
+//BIF_CFG_DEV0_EPF3_CAP_PTR
+#define BIF_CFG_DEV0_EPF3_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_MIN_GRANT
+#define BIF_CFG_DEV0_EPF3_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF3_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF3_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PMI_CAP
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_SBRN
+#define BIF_CFG_DEV0_EPF3_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_FLADJ
+#define BIF_CFG_DEV0_EPF3_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF3_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF3_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF3_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF3_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF3_LINK_CAP
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_LINK_CNTL
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF3_LINK_STATUS
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF3_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_LINK_CAP2
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF3_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF3_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_MASK
+#define BIF_CFG_DEV0_EPF3_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF3_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_PENDING
+#define BIF_CFG_DEV0_EPF3_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_MSIX_PBA
+#define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L
+//BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbif_rcc_dev0_RCCPORTDEC
+//RCC_DEV0_1_RCC_VDM_SUPPORT
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L
+//RCC_DEV0_1_RCC_BUS_CNTL
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8
+#define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc
+#define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15
+#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18
+#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19
+#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c
+#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L
+#define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L
+//RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L
+//RCC_DEV0_1_RCC_DEV0_LINK_CNTL
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT 0x10
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT 0x11
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK 0x00010000L
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK 0x00020000L
+//RCC_DEV0_1_RCC_CMN_LINK_CNTL
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L
+//RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L
+//RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL
+#define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0
+#define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL
+//RCC_DEV0_1_RCC_MH_ARB_CNTL
+#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0
+#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1
+#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L
+#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL
+//RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L
+//RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L
+
+
+// addressBlock: nbif_rcc_ep_dev0_RCCPORTDEC
+//RCC_EP_DEV0_1_EP_PCIE_SCRATCH
+#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_1_EP_PCIE_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__MFIOV_GFX_F0_FLR_DIS__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__MFIOV_GFX_F0_FLR_DIS_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_EP_DEV0_1_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L
+//RCC_EP_DEV0_1_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L
+//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+//RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+//RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L
+//RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L
+//RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC
+#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2
+#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
+#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L
+//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL
+//RCC_EP_DEV0_1_EP_PCIEP_RESERVED
+#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_1_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L
+//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L
+
+
+// addressBlock: nbif_rcc_dwn_dev0_RCCPORTDEC
+//RCC_DWN_DEV0_1_DN_PCIE_RESERVED
+#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_1_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_1_DN_PCIE_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+//RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L
+//RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L
+//RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L
+//RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L
+
+
+// addressBlock: nbif_rcc_dwnp_dev0_RCCPORTDEC
+//RCC_DWNP_DEV0_1_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L
+//RCC_DWNP_DEV0_1_PCIE_RX_CNTL
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L
+//RCC_DWNP_DEV0_1_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
+#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L
+//RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0
+#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_pfc_amdgfx_RCCPFCDEC
+//RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L
+//RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_SENT_FLAG__SHIFT 0x9
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_SENT_FLAG_MASK 0x00000200L
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L
+#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L
+
+
+// addressBlock: nbif_rcc_pfc_amdgfxaz_RCCPFCDEC
+//RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L
+//RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_SENT_FLAG__SHIFT 0x9
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_SENT_FLAG_MASK 0x00000200L
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L
+
+
+// addressBlock: nbif_pciemsix_0_usb_MSIXTDEC
+//PCIEMSIX_VECT0_ADDR_LO
+#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT0_ADDR_HI
+#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT0_MSG_DATA
+#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT0_CONTROL
+#define PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT1_ADDR_LO
+#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT1_ADDR_HI
+#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT1_MSG_DATA
+#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT1_CONTROL
+#define PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT2_ADDR_LO
+#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT2_ADDR_HI
+#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT2_MSG_DATA
+#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT2_CONTROL
+#define PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT3_ADDR_LO
+#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT3_ADDR_HI
+#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT3_MSG_DATA
+#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT3_CONTROL
+#define PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT4_ADDR_LO
+#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT4_ADDR_HI
+#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT4_MSG_DATA
+#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT4_CONTROL
+#define PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT5_ADDR_LO
+#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT5_ADDR_HI
+#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT5_MSG_DATA
+#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT5_CONTROL
+#define PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT6_ADDR_LO
+#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT6_ADDR_HI
+#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT6_MSG_DATA
+#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT6_CONTROL
+#define PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT7_ADDR_LO
+#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT7_ADDR_HI
+#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT7_MSG_DATA
+#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT7_CONTROL
+#define PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT8_ADDR_LO
+#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT8_ADDR_HI
+#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT8_MSG_DATA
+#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT8_CONTROL
+#define PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT9_ADDR_LO
+#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT9_ADDR_HI
+#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT9_MSG_DATA
+#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT9_CONTROL
+#define PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT10_ADDR_LO
+#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT10_ADDR_HI
+#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT10_MSG_DATA
+#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT10_CONTROL
+#define PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT11_ADDR_LO
+#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT11_ADDR_HI
+#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT11_MSG_DATA
+#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT11_CONTROL
+#define PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT12_ADDR_LO
+#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT12_ADDR_HI
+#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT12_MSG_DATA
+#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT12_CONTROL
+#define PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT13_ADDR_LO
+#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT13_ADDR_HI
+#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT13_MSG_DATA
+#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT13_CONTROL
+#define PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT14_ADDR_LO
+#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT14_ADDR_HI
+#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT14_MSG_DATA
+#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT14_CONTROL
+#define PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT15_ADDR_LO
+#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT15_ADDR_HI
+#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT15_MSG_DATA
+#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT15_CONTROL
+#define PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT16_ADDR_LO
+#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT16_ADDR_HI
+#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT16_MSG_DATA
+#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT16_CONTROL
+#define PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT17_ADDR_LO
+#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT17_ADDR_HI
+#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT17_MSG_DATA
+#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT17_CONTROL
+#define PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT18_ADDR_LO
+#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT18_ADDR_HI
+#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT18_MSG_DATA
+#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT18_CONTROL
+#define PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT19_ADDR_LO
+#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT19_ADDR_HI
+#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT19_MSG_DATA
+#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT19_CONTROL
+#define PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT20_ADDR_LO
+#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT20_ADDR_HI
+#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT20_MSG_DATA
+#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT20_CONTROL
+#define PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT21_ADDR_LO
+#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT21_ADDR_HI
+#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT21_MSG_DATA
+#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT21_CONTROL
+#define PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT22_ADDR_LO
+#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT22_ADDR_HI
+#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT22_MSG_DATA
+#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT22_CONTROL
+#define PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT23_ADDR_LO
+#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT23_ADDR_HI
+#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT23_MSG_DATA
+#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT23_CONTROL
+#define PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT24_ADDR_LO
+#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT24_ADDR_HI
+#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT24_MSG_DATA
+#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT24_CONTROL
+#define PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT25_ADDR_LO
+#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT25_ADDR_HI
+#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT25_MSG_DATA
+#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT25_CONTROL
+#define PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT26_ADDR_LO
+#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT26_ADDR_HI
+#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT26_MSG_DATA
+#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT26_CONTROL
+#define PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT27_ADDR_LO
+#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT27_ADDR_HI
+#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT27_MSG_DATA
+#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT27_CONTROL
+#define PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT28_ADDR_LO
+#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT28_ADDR_HI
+#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT28_MSG_DATA
+#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT28_CONTROL
+#define PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT29_ADDR_LO
+#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT29_ADDR_HI
+#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT29_MSG_DATA
+#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT29_CONTROL
+#define PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT30_ADDR_LO
+#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT30_ADDR_HI
+#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT30_MSG_DATA
+#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT30_CONTROL
+#define PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT31_ADDR_LO
+#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT31_ADDR_HI
+#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT31_MSG_DATA
+#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT31_CONTROL
+#define PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT32_ADDR_LO
+#define PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT32_ADDR_HI
+#define PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT32_MSG_DATA
+#define PCIEMSIX_VECT32_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT32_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT32_CONTROL
+#define PCIEMSIX_VECT32_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT32_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT33_ADDR_LO
+#define PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT33_ADDR_HI
+#define PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT33_MSG_DATA
+#define PCIEMSIX_VECT33_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT33_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT33_CONTROL
+#define PCIEMSIX_VECT33_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT33_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT34_ADDR_LO
+#define PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT34_ADDR_HI
+#define PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT34_MSG_DATA
+#define PCIEMSIX_VECT34_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT34_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT34_CONTROL
+#define PCIEMSIX_VECT34_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT34_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT35_ADDR_LO
+#define PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT35_ADDR_HI
+#define PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT35_MSG_DATA
+#define PCIEMSIX_VECT35_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT35_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT35_CONTROL
+#define PCIEMSIX_VECT35_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT35_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT36_ADDR_LO
+#define PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT36_ADDR_HI
+#define PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT36_MSG_DATA
+#define PCIEMSIX_VECT36_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT36_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT36_CONTROL
+#define PCIEMSIX_VECT36_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT36_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT37_ADDR_LO
+#define PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT37_ADDR_HI
+#define PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT37_MSG_DATA
+#define PCIEMSIX_VECT37_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT37_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT37_CONTROL
+#define PCIEMSIX_VECT37_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT37_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT38_ADDR_LO
+#define PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT38_ADDR_HI
+#define PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT38_MSG_DATA
+#define PCIEMSIX_VECT38_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT38_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT38_CONTROL
+#define PCIEMSIX_VECT38_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT38_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT39_ADDR_LO
+#define PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT39_ADDR_HI
+#define PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT39_MSG_DATA
+#define PCIEMSIX_VECT39_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT39_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT39_CONTROL
+#define PCIEMSIX_VECT39_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT39_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT40_ADDR_LO
+#define PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT40_ADDR_HI
+#define PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT40_MSG_DATA
+#define PCIEMSIX_VECT40_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT40_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT40_CONTROL
+#define PCIEMSIX_VECT40_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT40_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT41_ADDR_LO
+#define PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT41_ADDR_HI
+#define PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT41_MSG_DATA
+#define PCIEMSIX_VECT41_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT41_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT41_CONTROL
+#define PCIEMSIX_VECT41_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT41_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT42_ADDR_LO
+#define PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT42_ADDR_HI
+#define PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT42_MSG_DATA
+#define PCIEMSIX_VECT42_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT42_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT42_CONTROL
+#define PCIEMSIX_VECT42_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT42_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT43_ADDR_LO
+#define PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT43_ADDR_HI
+#define PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT43_MSG_DATA
+#define PCIEMSIX_VECT43_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT43_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT43_CONTROL
+#define PCIEMSIX_VECT43_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT43_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT44_ADDR_LO
+#define PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT44_ADDR_HI
+#define PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT44_MSG_DATA
+#define PCIEMSIX_VECT44_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT44_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT44_CONTROL
+#define PCIEMSIX_VECT44_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT44_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT45_ADDR_LO
+#define PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT45_ADDR_HI
+#define PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT45_MSG_DATA
+#define PCIEMSIX_VECT45_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT45_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT45_CONTROL
+#define PCIEMSIX_VECT45_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT45_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT46_ADDR_LO
+#define PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT46_ADDR_HI
+#define PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT46_MSG_DATA
+#define PCIEMSIX_VECT46_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT46_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT46_CONTROL
+#define PCIEMSIX_VECT46_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT46_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT47_ADDR_LO
+#define PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT47_ADDR_HI
+#define PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT47_MSG_DATA
+#define PCIEMSIX_VECT47_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT47_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT47_CONTROL
+#define PCIEMSIX_VECT47_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT47_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT48_ADDR_LO
+#define PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT48_ADDR_HI
+#define PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT48_MSG_DATA
+#define PCIEMSIX_VECT48_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT48_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT48_CONTROL
+#define PCIEMSIX_VECT48_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT48_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT49_ADDR_LO
+#define PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT49_ADDR_HI
+#define PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT49_MSG_DATA
+#define PCIEMSIX_VECT49_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT49_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT49_CONTROL
+#define PCIEMSIX_VECT49_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT49_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT50_ADDR_LO
+#define PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT50_ADDR_HI
+#define PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT50_MSG_DATA
+#define PCIEMSIX_VECT50_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT50_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT50_CONTROL
+#define PCIEMSIX_VECT50_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT50_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT51_ADDR_LO
+#define PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT51_ADDR_HI
+#define PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT51_MSG_DATA
+#define PCIEMSIX_VECT51_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT51_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT51_CONTROL
+#define PCIEMSIX_VECT51_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT51_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT52_ADDR_LO
+#define PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT52_ADDR_HI
+#define PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT52_MSG_DATA
+#define PCIEMSIX_VECT52_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT52_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT52_CONTROL
+#define PCIEMSIX_VECT52_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT52_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT53_ADDR_LO
+#define PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT53_ADDR_HI
+#define PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT53_MSG_DATA
+#define PCIEMSIX_VECT53_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT53_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT53_CONTROL
+#define PCIEMSIX_VECT53_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT53_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT54_ADDR_LO
+#define PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT54_ADDR_HI
+#define PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT54_MSG_DATA
+#define PCIEMSIX_VECT54_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT54_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT54_CONTROL
+#define PCIEMSIX_VECT54_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT54_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT55_ADDR_LO
+#define PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT55_ADDR_HI
+#define PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT55_MSG_DATA
+#define PCIEMSIX_VECT55_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT55_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT55_CONTROL
+#define PCIEMSIX_VECT55_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT55_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT56_ADDR_LO
+#define PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT56_ADDR_HI
+#define PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT56_MSG_DATA
+#define PCIEMSIX_VECT56_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT56_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT56_CONTROL
+#define PCIEMSIX_VECT56_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT56_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT57_ADDR_LO
+#define PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT57_ADDR_HI
+#define PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT57_MSG_DATA
+#define PCIEMSIX_VECT57_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT57_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT57_CONTROL
+#define PCIEMSIX_VECT57_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT57_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT58_ADDR_LO
+#define PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT58_ADDR_HI
+#define PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT58_MSG_DATA
+#define PCIEMSIX_VECT58_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT58_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT58_CONTROL
+#define PCIEMSIX_VECT58_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT58_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT59_ADDR_LO
+#define PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT59_ADDR_HI
+#define PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT59_MSG_DATA
+#define PCIEMSIX_VECT59_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT59_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT59_CONTROL
+#define PCIEMSIX_VECT59_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT59_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT60_ADDR_LO
+#define PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT60_ADDR_HI
+#define PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT60_MSG_DATA
+#define PCIEMSIX_VECT60_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT60_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT60_CONTROL
+#define PCIEMSIX_VECT60_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT60_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT61_ADDR_LO
+#define PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT61_ADDR_HI
+#define PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT61_MSG_DATA
+#define PCIEMSIX_VECT61_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT61_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT61_CONTROL
+#define PCIEMSIX_VECT61_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT61_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT62_ADDR_LO
+#define PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT62_ADDR_HI
+#define PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT62_MSG_DATA
+#define PCIEMSIX_VECT62_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT62_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT62_CONTROL
+#define PCIEMSIX_VECT62_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT62_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT63_ADDR_LO
+#define PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT63_ADDR_HI
+#define PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT63_MSG_DATA
+#define PCIEMSIX_VECT63_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT63_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT63_CONTROL
+#define PCIEMSIX_VECT63_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT63_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT64_ADDR_LO
+#define PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT64_ADDR_HI
+#define PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT64_MSG_DATA
+#define PCIEMSIX_VECT64_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT64_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT64_CONTROL
+#define PCIEMSIX_VECT64_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT64_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT65_ADDR_LO
+#define PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT65_ADDR_HI
+#define PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT65_MSG_DATA
+#define PCIEMSIX_VECT65_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT65_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT65_CONTROL
+#define PCIEMSIX_VECT65_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT65_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT66_ADDR_LO
+#define PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT66_ADDR_HI
+#define PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT66_MSG_DATA
+#define PCIEMSIX_VECT66_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT66_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT66_CONTROL
+#define PCIEMSIX_VECT66_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT66_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT67_ADDR_LO
+#define PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT67_ADDR_HI
+#define PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT67_MSG_DATA
+#define PCIEMSIX_VECT67_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT67_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT67_CONTROL
+#define PCIEMSIX_VECT67_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT67_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT68_ADDR_LO
+#define PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT68_ADDR_HI
+#define PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT68_MSG_DATA
+#define PCIEMSIX_VECT68_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT68_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT68_CONTROL
+#define PCIEMSIX_VECT68_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT68_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT69_ADDR_LO
+#define PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT69_ADDR_HI
+#define PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT69_MSG_DATA
+#define PCIEMSIX_VECT69_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT69_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT69_CONTROL
+#define PCIEMSIX_VECT69_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT69_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT70_ADDR_LO
+#define PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT70_ADDR_HI
+#define PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT70_MSG_DATA
+#define PCIEMSIX_VECT70_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT70_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT70_CONTROL
+#define PCIEMSIX_VECT70_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT70_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT71_ADDR_LO
+#define PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT71_ADDR_HI
+#define PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT71_MSG_DATA
+#define PCIEMSIX_VECT71_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT71_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT71_CONTROL
+#define PCIEMSIX_VECT71_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT71_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT72_ADDR_LO
+#define PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT72_ADDR_HI
+#define PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT72_MSG_DATA
+#define PCIEMSIX_VECT72_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT72_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT72_CONTROL
+#define PCIEMSIX_VECT72_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT72_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT73_ADDR_LO
+#define PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT73_ADDR_HI
+#define PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT73_MSG_DATA
+#define PCIEMSIX_VECT73_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT73_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT73_CONTROL
+#define PCIEMSIX_VECT73_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT73_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT74_ADDR_LO
+#define PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT74_ADDR_HI
+#define PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT74_MSG_DATA
+#define PCIEMSIX_VECT74_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT74_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT74_CONTROL
+#define PCIEMSIX_VECT74_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT74_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT75_ADDR_LO
+#define PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT75_ADDR_HI
+#define PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT75_MSG_DATA
+#define PCIEMSIX_VECT75_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT75_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT75_CONTROL
+#define PCIEMSIX_VECT75_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT75_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT76_ADDR_LO
+#define PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT76_ADDR_HI
+#define PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT76_MSG_DATA
+#define PCIEMSIX_VECT76_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT76_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT76_CONTROL
+#define PCIEMSIX_VECT76_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT76_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT77_ADDR_LO
+#define PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT77_ADDR_HI
+#define PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT77_MSG_DATA
+#define PCIEMSIX_VECT77_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT77_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT77_CONTROL
+#define PCIEMSIX_VECT77_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT77_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT78_ADDR_LO
+#define PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT78_ADDR_HI
+#define PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT78_MSG_DATA
+#define PCIEMSIX_VECT78_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT78_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT78_CONTROL
+#define PCIEMSIX_VECT78_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT78_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT79_ADDR_LO
+#define PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT79_ADDR_HI
+#define PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT79_MSG_DATA
+#define PCIEMSIX_VECT79_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT79_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT79_CONTROL
+#define PCIEMSIX_VECT79_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT79_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT80_ADDR_LO
+#define PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT80_ADDR_HI
+#define PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT80_MSG_DATA
+#define PCIEMSIX_VECT80_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT80_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT80_CONTROL
+#define PCIEMSIX_VECT80_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT80_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT81_ADDR_LO
+#define PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT81_ADDR_HI
+#define PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT81_MSG_DATA
+#define PCIEMSIX_VECT81_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT81_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT81_CONTROL
+#define PCIEMSIX_VECT81_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT81_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT82_ADDR_LO
+#define PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT82_ADDR_HI
+#define PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT82_MSG_DATA
+#define PCIEMSIX_VECT82_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT82_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT82_CONTROL
+#define PCIEMSIX_VECT82_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT82_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT83_ADDR_LO
+#define PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT83_ADDR_HI
+#define PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT83_MSG_DATA
+#define PCIEMSIX_VECT83_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT83_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT83_CONTROL
+#define PCIEMSIX_VECT83_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT83_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT84_ADDR_LO
+#define PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT84_ADDR_HI
+#define PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT84_MSG_DATA
+#define PCIEMSIX_VECT84_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT84_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT84_CONTROL
+#define PCIEMSIX_VECT84_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT84_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT85_ADDR_LO
+#define PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT85_ADDR_HI
+#define PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT85_MSG_DATA
+#define PCIEMSIX_VECT85_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT85_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT85_CONTROL
+#define PCIEMSIX_VECT85_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT85_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT86_ADDR_LO
+#define PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT86_ADDR_HI
+#define PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT86_MSG_DATA
+#define PCIEMSIX_VECT86_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT86_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT86_CONTROL
+#define PCIEMSIX_VECT86_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT86_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT87_ADDR_LO
+#define PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT87_ADDR_HI
+#define PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT87_MSG_DATA
+#define PCIEMSIX_VECT87_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT87_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT87_CONTROL
+#define PCIEMSIX_VECT87_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT87_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT88_ADDR_LO
+#define PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT88_ADDR_HI
+#define PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT88_MSG_DATA
+#define PCIEMSIX_VECT88_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT88_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT88_CONTROL
+#define PCIEMSIX_VECT88_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT88_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT89_ADDR_LO
+#define PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT89_ADDR_HI
+#define PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT89_MSG_DATA
+#define PCIEMSIX_VECT89_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT89_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT89_CONTROL
+#define PCIEMSIX_VECT89_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT89_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT90_ADDR_LO
+#define PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT90_ADDR_HI
+#define PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT90_MSG_DATA
+#define PCIEMSIX_VECT90_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT90_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT90_CONTROL
+#define PCIEMSIX_VECT90_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT90_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT91_ADDR_LO
+#define PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT91_ADDR_HI
+#define PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT91_MSG_DATA
+#define PCIEMSIX_VECT91_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT91_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT91_CONTROL
+#define PCIEMSIX_VECT91_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT91_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT92_ADDR_LO
+#define PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT92_ADDR_HI
+#define PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT92_MSG_DATA
+#define PCIEMSIX_VECT92_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT92_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT92_CONTROL
+#define PCIEMSIX_VECT92_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT92_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT93_ADDR_LO
+#define PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT93_ADDR_HI
+#define PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT93_MSG_DATA
+#define PCIEMSIX_VECT93_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT93_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT93_CONTROL
+#define PCIEMSIX_VECT93_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT93_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT94_ADDR_LO
+#define PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT94_ADDR_HI
+#define PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT94_MSG_DATA
+#define PCIEMSIX_VECT94_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT94_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT94_CONTROL
+#define PCIEMSIX_VECT94_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT94_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT95_ADDR_LO
+#define PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT95_ADDR_HI
+#define PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT95_MSG_DATA
+#define PCIEMSIX_VECT95_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT95_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT95_CONTROL
+#define PCIEMSIX_VECT95_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT95_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT96_ADDR_LO
+#define PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT96_ADDR_HI
+#define PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT96_MSG_DATA
+#define PCIEMSIX_VECT96_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT96_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT96_CONTROL
+#define PCIEMSIX_VECT96_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT96_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT97_ADDR_LO
+#define PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT97_ADDR_HI
+#define PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT97_MSG_DATA
+#define PCIEMSIX_VECT97_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT97_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT97_CONTROL
+#define PCIEMSIX_VECT97_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT97_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT98_ADDR_LO
+#define PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT98_ADDR_HI
+#define PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT98_MSG_DATA
+#define PCIEMSIX_VECT98_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT98_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT98_CONTROL
+#define PCIEMSIX_VECT98_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT98_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT99_ADDR_LO
+#define PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT99_ADDR_HI
+#define PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT99_MSG_DATA
+#define PCIEMSIX_VECT99_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT99_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT99_CONTROL
+#define PCIEMSIX_VECT99_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT99_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT100_ADDR_LO
+#define PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT100_ADDR_HI
+#define PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT100_MSG_DATA
+#define PCIEMSIX_VECT100_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT100_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT100_CONTROL
+#define PCIEMSIX_VECT100_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT100_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT101_ADDR_LO
+#define PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT101_ADDR_HI
+#define PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT101_MSG_DATA
+#define PCIEMSIX_VECT101_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT101_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT101_CONTROL
+#define PCIEMSIX_VECT101_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT101_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT102_ADDR_LO
+#define PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT102_ADDR_HI
+#define PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT102_MSG_DATA
+#define PCIEMSIX_VECT102_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT102_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT102_CONTROL
+#define PCIEMSIX_VECT102_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT102_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT103_ADDR_LO
+#define PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT103_ADDR_HI
+#define PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT103_MSG_DATA
+#define PCIEMSIX_VECT103_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT103_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT103_CONTROL
+#define PCIEMSIX_VECT103_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT103_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT104_ADDR_LO
+#define PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT104_ADDR_HI
+#define PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT104_MSG_DATA
+#define PCIEMSIX_VECT104_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT104_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT104_CONTROL
+#define PCIEMSIX_VECT104_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT104_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT105_ADDR_LO
+#define PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT105_ADDR_HI
+#define PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT105_MSG_DATA
+#define PCIEMSIX_VECT105_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT105_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT105_CONTROL
+#define PCIEMSIX_VECT105_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT105_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT106_ADDR_LO
+#define PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT106_ADDR_HI
+#define PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT106_MSG_DATA
+#define PCIEMSIX_VECT106_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT106_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT106_CONTROL
+#define PCIEMSIX_VECT106_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT106_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT107_ADDR_LO
+#define PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT107_ADDR_HI
+#define PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT107_MSG_DATA
+#define PCIEMSIX_VECT107_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT107_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT107_CONTROL
+#define PCIEMSIX_VECT107_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT107_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT108_ADDR_LO
+#define PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT108_ADDR_HI
+#define PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT108_MSG_DATA
+#define PCIEMSIX_VECT108_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT108_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT108_CONTROL
+#define PCIEMSIX_VECT108_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT108_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT109_ADDR_LO
+#define PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT109_ADDR_HI
+#define PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT109_MSG_DATA
+#define PCIEMSIX_VECT109_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT109_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT109_CONTROL
+#define PCIEMSIX_VECT109_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT109_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT110_ADDR_LO
+#define PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT110_ADDR_HI
+#define PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT110_MSG_DATA
+#define PCIEMSIX_VECT110_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT110_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT110_CONTROL
+#define PCIEMSIX_VECT110_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT110_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT111_ADDR_LO
+#define PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT111_ADDR_HI
+#define PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT111_MSG_DATA
+#define PCIEMSIX_VECT111_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT111_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT111_CONTROL
+#define PCIEMSIX_VECT111_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT111_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT112_ADDR_LO
+#define PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT112_ADDR_HI
+#define PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT112_MSG_DATA
+#define PCIEMSIX_VECT112_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT112_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT112_CONTROL
+#define PCIEMSIX_VECT112_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT112_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT113_ADDR_LO
+#define PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT113_ADDR_HI
+#define PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT113_MSG_DATA
+#define PCIEMSIX_VECT113_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT113_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT113_CONTROL
+#define PCIEMSIX_VECT113_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT113_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT114_ADDR_LO
+#define PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT114_ADDR_HI
+#define PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT114_MSG_DATA
+#define PCIEMSIX_VECT114_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT114_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT114_CONTROL
+#define PCIEMSIX_VECT114_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT114_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT115_ADDR_LO
+#define PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT115_ADDR_HI
+#define PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT115_MSG_DATA
+#define PCIEMSIX_VECT115_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT115_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT115_CONTROL
+#define PCIEMSIX_VECT115_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT115_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT116_ADDR_LO
+#define PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT116_ADDR_HI
+#define PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT116_MSG_DATA
+#define PCIEMSIX_VECT116_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT116_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT116_CONTROL
+#define PCIEMSIX_VECT116_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT116_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT117_ADDR_LO
+#define PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT117_ADDR_HI
+#define PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT117_MSG_DATA
+#define PCIEMSIX_VECT117_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT117_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT117_CONTROL
+#define PCIEMSIX_VECT117_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT117_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT118_ADDR_LO
+#define PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT118_ADDR_HI
+#define PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT118_MSG_DATA
+#define PCIEMSIX_VECT118_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT118_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT118_CONTROL
+#define PCIEMSIX_VECT118_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT118_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT119_ADDR_LO
+#define PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT119_ADDR_HI
+#define PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT119_MSG_DATA
+#define PCIEMSIX_VECT119_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT119_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT119_CONTROL
+#define PCIEMSIX_VECT119_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT119_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT120_ADDR_LO
+#define PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT120_ADDR_HI
+#define PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT120_MSG_DATA
+#define PCIEMSIX_VECT120_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT120_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT120_CONTROL
+#define PCIEMSIX_VECT120_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT120_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT121_ADDR_LO
+#define PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT121_ADDR_HI
+#define PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT121_MSG_DATA
+#define PCIEMSIX_VECT121_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT121_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT121_CONTROL
+#define PCIEMSIX_VECT121_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT121_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT122_ADDR_LO
+#define PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT122_ADDR_HI
+#define PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT122_MSG_DATA
+#define PCIEMSIX_VECT122_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT122_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT122_CONTROL
+#define PCIEMSIX_VECT122_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT122_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT123_ADDR_LO
+#define PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT123_ADDR_HI
+#define PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT123_MSG_DATA
+#define PCIEMSIX_VECT123_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT123_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT123_CONTROL
+#define PCIEMSIX_VECT123_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT123_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT124_ADDR_LO
+#define PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT124_ADDR_HI
+#define PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT124_MSG_DATA
+#define PCIEMSIX_VECT124_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT124_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT124_CONTROL
+#define PCIEMSIX_VECT124_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT124_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT125_ADDR_LO
+#define PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT125_ADDR_HI
+#define PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT125_MSG_DATA
+#define PCIEMSIX_VECT125_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT125_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT125_CONTROL
+#define PCIEMSIX_VECT125_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT125_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT126_ADDR_LO
+#define PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT126_ADDR_HI
+#define PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT126_MSG_DATA
+#define PCIEMSIX_VECT126_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT126_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT126_CONTROL
+#define PCIEMSIX_VECT126_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT126_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT127_ADDR_LO
+#define PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT127_ADDR_HI
+#define PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT127_MSG_DATA
+#define PCIEMSIX_VECT127_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT127_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT127_CONTROL
+#define PCIEMSIX_VECT127_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT127_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT128_ADDR_LO
+#define PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT128_ADDR_HI
+#define PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT128_MSG_DATA
+#define PCIEMSIX_VECT128_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT128_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT128_CONTROL
+#define PCIEMSIX_VECT128_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT128_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT129_ADDR_LO
+#define PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT129_ADDR_HI
+#define PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT129_MSG_DATA
+#define PCIEMSIX_VECT129_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT129_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT129_CONTROL
+#define PCIEMSIX_VECT129_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT129_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT130_ADDR_LO
+#define PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT130_ADDR_HI
+#define PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT130_MSG_DATA
+#define PCIEMSIX_VECT130_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT130_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT130_CONTROL
+#define PCIEMSIX_VECT130_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT130_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT131_ADDR_LO
+#define PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT131_ADDR_HI
+#define PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT131_MSG_DATA
+#define PCIEMSIX_VECT131_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT131_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT131_CONTROL
+#define PCIEMSIX_VECT131_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT131_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT132_ADDR_LO
+#define PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT132_ADDR_HI
+#define PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT132_MSG_DATA
+#define PCIEMSIX_VECT132_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT132_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT132_CONTROL
+#define PCIEMSIX_VECT132_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT132_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT133_ADDR_LO
+#define PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT133_ADDR_HI
+#define PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT133_MSG_DATA
+#define PCIEMSIX_VECT133_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT133_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT133_CONTROL
+#define PCIEMSIX_VECT133_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT133_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT134_ADDR_LO
+#define PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT134_ADDR_HI
+#define PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT134_MSG_DATA
+#define PCIEMSIX_VECT134_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT134_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT134_CONTROL
+#define PCIEMSIX_VECT134_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT134_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT135_ADDR_LO
+#define PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT135_ADDR_HI
+#define PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT135_MSG_DATA
+#define PCIEMSIX_VECT135_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT135_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT135_CONTROL
+#define PCIEMSIX_VECT135_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT135_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT136_ADDR_LO
+#define PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT136_ADDR_HI
+#define PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT136_MSG_DATA
+#define PCIEMSIX_VECT136_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT136_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT136_CONTROL
+#define PCIEMSIX_VECT136_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT136_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT137_ADDR_LO
+#define PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT137_ADDR_HI
+#define PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT137_MSG_DATA
+#define PCIEMSIX_VECT137_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT137_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT137_CONTROL
+#define PCIEMSIX_VECT137_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT137_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT138_ADDR_LO
+#define PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT138_ADDR_HI
+#define PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT138_MSG_DATA
+#define PCIEMSIX_VECT138_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT138_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT138_CONTROL
+#define PCIEMSIX_VECT138_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT138_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT139_ADDR_LO
+#define PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT139_ADDR_HI
+#define PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT139_MSG_DATA
+#define PCIEMSIX_VECT139_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT139_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT139_CONTROL
+#define PCIEMSIX_VECT139_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT139_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT140_ADDR_LO
+#define PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT140_ADDR_HI
+#define PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT140_MSG_DATA
+#define PCIEMSIX_VECT140_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT140_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT140_CONTROL
+#define PCIEMSIX_VECT140_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT140_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT141_ADDR_LO
+#define PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT141_ADDR_HI
+#define PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT141_MSG_DATA
+#define PCIEMSIX_VECT141_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT141_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT141_CONTROL
+#define PCIEMSIX_VECT141_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT141_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT142_ADDR_LO
+#define PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT142_ADDR_HI
+#define PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT142_MSG_DATA
+#define PCIEMSIX_VECT142_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT142_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT142_CONTROL
+#define PCIEMSIX_VECT142_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT142_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT143_ADDR_LO
+#define PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT143_ADDR_HI
+#define PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT143_MSG_DATA
+#define PCIEMSIX_VECT143_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT143_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT143_CONTROL
+#define PCIEMSIX_VECT143_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT143_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT144_ADDR_LO
+#define PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT144_ADDR_HI
+#define PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT144_MSG_DATA
+#define PCIEMSIX_VECT144_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT144_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT144_CONTROL
+#define PCIEMSIX_VECT144_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT144_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT145_ADDR_LO
+#define PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT145_ADDR_HI
+#define PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT145_MSG_DATA
+#define PCIEMSIX_VECT145_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT145_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT145_CONTROL
+#define PCIEMSIX_VECT145_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT145_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT146_ADDR_LO
+#define PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT146_ADDR_HI
+#define PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT146_MSG_DATA
+#define PCIEMSIX_VECT146_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT146_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT146_CONTROL
+#define PCIEMSIX_VECT146_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT146_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT147_ADDR_LO
+#define PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT147_ADDR_HI
+#define PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT147_MSG_DATA
+#define PCIEMSIX_VECT147_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT147_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT147_CONTROL
+#define PCIEMSIX_VECT147_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT147_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT148_ADDR_LO
+#define PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT148_ADDR_HI
+#define PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT148_MSG_DATA
+#define PCIEMSIX_VECT148_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT148_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT148_CONTROL
+#define PCIEMSIX_VECT148_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT148_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT149_ADDR_LO
+#define PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT149_ADDR_HI
+#define PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT149_MSG_DATA
+#define PCIEMSIX_VECT149_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT149_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT149_CONTROL
+#define PCIEMSIX_VECT149_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT149_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT150_ADDR_LO
+#define PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT150_ADDR_HI
+#define PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT150_MSG_DATA
+#define PCIEMSIX_VECT150_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT150_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT150_CONTROL
+#define PCIEMSIX_VECT150_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT150_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT151_ADDR_LO
+#define PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT151_ADDR_HI
+#define PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT151_MSG_DATA
+#define PCIEMSIX_VECT151_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT151_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT151_CONTROL
+#define PCIEMSIX_VECT151_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT151_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT152_ADDR_LO
+#define PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT152_ADDR_HI
+#define PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT152_MSG_DATA
+#define PCIEMSIX_VECT152_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT152_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT152_CONTROL
+#define PCIEMSIX_VECT152_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT152_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT153_ADDR_LO
+#define PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT153_ADDR_HI
+#define PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT153_MSG_DATA
+#define PCIEMSIX_VECT153_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT153_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT153_CONTROL
+#define PCIEMSIX_VECT153_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT153_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT154_ADDR_LO
+#define PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT154_ADDR_HI
+#define PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT154_MSG_DATA
+#define PCIEMSIX_VECT154_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT154_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT154_CONTROL
+#define PCIEMSIX_VECT154_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT154_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT155_ADDR_LO
+#define PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT155_ADDR_HI
+#define PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT155_MSG_DATA
+#define PCIEMSIX_VECT155_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT155_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT155_CONTROL
+#define PCIEMSIX_VECT155_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT155_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT156_ADDR_LO
+#define PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT156_ADDR_HI
+#define PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT156_MSG_DATA
+#define PCIEMSIX_VECT156_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT156_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT156_CONTROL
+#define PCIEMSIX_VECT156_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT156_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT157_ADDR_LO
+#define PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT157_ADDR_HI
+#define PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT157_MSG_DATA
+#define PCIEMSIX_VECT157_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT157_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT157_CONTROL
+#define PCIEMSIX_VECT157_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT157_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT158_ADDR_LO
+#define PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT158_ADDR_HI
+#define PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT158_MSG_DATA
+#define PCIEMSIX_VECT158_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT158_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT158_CONTROL
+#define PCIEMSIX_VECT158_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT158_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT159_ADDR_LO
+#define PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT159_ADDR_HI
+#define PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT159_MSG_DATA
+#define PCIEMSIX_VECT159_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT159_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT159_CONTROL
+#define PCIEMSIX_VECT159_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT159_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT160_ADDR_LO
+#define PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT160_ADDR_HI
+#define PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT160_MSG_DATA
+#define PCIEMSIX_VECT160_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT160_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT160_CONTROL
+#define PCIEMSIX_VECT160_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT160_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT161_ADDR_LO
+#define PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT161_ADDR_HI
+#define PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT161_MSG_DATA
+#define PCIEMSIX_VECT161_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT161_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT161_CONTROL
+#define PCIEMSIX_VECT161_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT161_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT162_ADDR_LO
+#define PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT162_ADDR_HI
+#define PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT162_MSG_DATA
+#define PCIEMSIX_VECT162_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT162_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT162_CONTROL
+#define PCIEMSIX_VECT162_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT162_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT163_ADDR_LO
+#define PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT163_ADDR_HI
+#define PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT163_MSG_DATA
+#define PCIEMSIX_VECT163_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT163_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT163_CONTROL
+#define PCIEMSIX_VECT163_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT163_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT164_ADDR_LO
+#define PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT164_ADDR_HI
+#define PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT164_MSG_DATA
+#define PCIEMSIX_VECT164_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT164_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT164_CONTROL
+#define PCIEMSIX_VECT164_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT164_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT165_ADDR_LO
+#define PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT165_ADDR_HI
+#define PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT165_MSG_DATA
+#define PCIEMSIX_VECT165_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT165_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT165_CONTROL
+#define PCIEMSIX_VECT165_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT165_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT166_ADDR_LO
+#define PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT166_ADDR_HI
+#define PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT166_MSG_DATA
+#define PCIEMSIX_VECT166_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT166_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT166_CONTROL
+#define PCIEMSIX_VECT166_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT166_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT167_ADDR_LO
+#define PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT167_ADDR_HI
+#define PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT167_MSG_DATA
+#define PCIEMSIX_VECT167_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT167_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT167_CONTROL
+#define PCIEMSIX_VECT167_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT167_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT168_ADDR_LO
+#define PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT168_ADDR_HI
+#define PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT168_MSG_DATA
+#define PCIEMSIX_VECT168_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT168_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT168_CONTROL
+#define PCIEMSIX_VECT168_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT168_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT169_ADDR_LO
+#define PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT169_ADDR_HI
+#define PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT169_MSG_DATA
+#define PCIEMSIX_VECT169_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT169_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT169_CONTROL
+#define PCIEMSIX_VECT169_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT169_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT170_ADDR_LO
+#define PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT170_ADDR_HI
+#define PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT170_MSG_DATA
+#define PCIEMSIX_VECT170_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT170_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT170_CONTROL
+#define PCIEMSIX_VECT170_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT170_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT171_ADDR_LO
+#define PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT171_ADDR_HI
+#define PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT171_MSG_DATA
+#define PCIEMSIX_VECT171_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT171_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT171_CONTROL
+#define PCIEMSIX_VECT171_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT171_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT172_ADDR_LO
+#define PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT172_ADDR_HI
+#define PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT172_MSG_DATA
+#define PCIEMSIX_VECT172_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT172_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT172_CONTROL
+#define PCIEMSIX_VECT172_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT172_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT173_ADDR_LO
+#define PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT173_ADDR_HI
+#define PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT173_MSG_DATA
+#define PCIEMSIX_VECT173_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT173_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT173_CONTROL
+#define PCIEMSIX_VECT173_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT173_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT174_ADDR_LO
+#define PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT174_ADDR_HI
+#define PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT174_MSG_DATA
+#define PCIEMSIX_VECT174_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT174_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT174_CONTROL
+#define PCIEMSIX_VECT174_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT174_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT175_ADDR_LO
+#define PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT175_ADDR_HI
+#define PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT175_MSG_DATA
+#define PCIEMSIX_VECT175_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT175_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT175_CONTROL
+#define PCIEMSIX_VECT175_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT175_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT176_ADDR_LO
+#define PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT176_ADDR_HI
+#define PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT176_MSG_DATA
+#define PCIEMSIX_VECT176_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT176_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT176_CONTROL
+#define PCIEMSIX_VECT176_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT176_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT177_ADDR_LO
+#define PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT177_ADDR_HI
+#define PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT177_MSG_DATA
+#define PCIEMSIX_VECT177_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT177_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT177_CONTROL
+#define PCIEMSIX_VECT177_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT177_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT178_ADDR_LO
+#define PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT178_ADDR_HI
+#define PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT178_MSG_DATA
+#define PCIEMSIX_VECT178_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT178_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT178_CONTROL
+#define PCIEMSIX_VECT178_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT178_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT179_ADDR_LO
+#define PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT179_ADDR_HI
+#define PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT179_MSG_DATA
+#define PCIEMSIX_VECT179_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT179_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT179_CONTROL
+#define PCIEMSIX_VECT179_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT179_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT180_ADDR_LO
+#define PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT180_ADDR_HI
+#define PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT180_MSG_DATA
+#define PCIEMSIX_VECT180_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT180_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT180_CONTROL
+#define PCIEMSIX_VECT180_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT180_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT181_ADDR_LO
+#define PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT181_ADDR_HI
+#define PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT181_MSG_DATA
+#define PCIEMSIX_VECT181_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT181_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT181_CONTROL
+#define PCIEMSIX_VECT181_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT181_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT182_ADDR_LO
+#define PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT182_ADDR_HI
+#define PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT182_MSG_DATA
+#define PCIEMSIX_VECT182_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT182_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT182_CONTROL
+#define PCIEMSIX_VECT182_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT182_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT183_ADDR_LO
+#define PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT183_ADDR_HI
+#define PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT183_MSG_DATA
+#define PCIEMSIX_VECT183_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT183_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT183_CONTROL
+#define PCIEMSIX_VECT183_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT183_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT184_ADDR_LO
+#define PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT184_ADDR_HI
+#define PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT184_MSG_DATA
+#define PCIEMSIX_VECT184_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT184_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT184_CONTROL
+#define PCIEMSIX_VECT184_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT184_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT185_ADDR_LO
+#define PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT185_ADDR_HI
+#define PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT185_MSG_DATA
+#define PCIEMSIX_VECT185_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT185_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT185_CONTROL
+#define PCIEMSIX_VECT185_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT185_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT186_ADDR_LO
+#define PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT186_ADDR_HI
+#define PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT186_MSG_DATA
+#define PCIEMSIX_VECT186_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT186_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT186_CONTROL
+#define PCIEMSIX_VECT186_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT186_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT187_ADDR_LO
+#define PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT187_ADDR_HI
+#define PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT187_MSG_DATA
+#define PCIEMSIX_VECT187_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT187_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT187_CONTROL
+#define PCIEMSIX_VECT187_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT187_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT188_ADDR_LO
+#define PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT188_ADDR_HI
+#define PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT188_MSG_DATA
+#define PCIEMSIX_VECT188_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT188_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT188_CONTROL
+#define PCIEMSIX_VECT188_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT188_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT189_ADDR_LO
+#define PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT189_ADDR_HI
+#define PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT189_MSG_DATA
+#define PCIEMSIX_VECT189_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT189_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT189_CONTROL
+#define PCIEMSIX_VECT189_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT189_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT190_ADDR_LO
+#define PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT190_ADDR_HI
+#define PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT190_MSG_DATA
+#define PCIEMSIX_VECT190_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT190_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT190_CONTROL
+#define PCIEMSIX_VECT190_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT190_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT191_ADDR_LO
+#define PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT191_ADDR_HI
+#define PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT191_MSG_DATA
+#define PCIEMSIX_VECT191_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT191_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT191_CONTROL
+#define PCIEMSIX_VECT191_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT191_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT192_ADDR_LO
+#define PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT192_ADDR_HI
+#define PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT192_MSG_DATA
+#define PCIEMSIX_VECT192_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT192_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT192_CONTROL
+#define PCIEMSIX_VECT192_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT192_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT193_ADDR_LO
+#define PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT193_ADDR_HI
+#define PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT193_MSG_DATA
+#define PCIEMSIX_VECT193_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT193_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT193_CONTROL
+#define PCIEMSIX_VECT193_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT193_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT194_ADDR_LO
+#define PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT194_ADDR_HI
+#define PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT194_MSG_DATA
+#define PCIEMSIX_VECT194_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT194_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT194_CONTROL
+#define PCIEMSIX_VECT194_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT194_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT195_ADDR_LO
+#define PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT195_ADDR_HI
+#define PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT195_MSG_DATA
+#define PCIEMSIX_VECT195_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT195_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT195_CONTROL
+#define PCIEMSIX_VECT195_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT195_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT196_ADDR_LO
+#define PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT196_ADDR_HI
+#define PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT196_MSG_DATA
+#define PCIEMSIX_VECT196_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT196_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT196_CONTROL
+#define PCIEMSIX_VECT196_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT196_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT197_ADDR_LO
+#define PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT197_ADDR_HI
+#define PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT197_MSG_DATA
+#define PCIEMSIX_VECT197_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT197_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT197_CONTROL
+#define PCIEMSIX_VECT197_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT197_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT198_ADDR_LO
+#define PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT198_ADDR_HI
+#define PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT198_MSG_DATA
+#define PCIEMSIX_VECT198_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT198_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT198_CONTROL
+#define PCIEMSIX_VECT198_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT198_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT199_ADDR_LO
+#define PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT199_ADDR_HI
+#define PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT199_MSG_DATA
+#define PCIEMSIX_VECT199_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT199_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT199_CONTROL
+#define PCIEMSIX_VECT199_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT199_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT200_ADDR_LO
+#define PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT200_ADDR_HI
+#define PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT200_MSG_DATA
+#define PCIEMSIX_VECT200_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT200_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT200_CONTROL
+#define PCIEMSIX_VECT200_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT200_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT201_ADDR_LO
+#define PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT201_ADDR_HI
+#define PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT201_MSG_DATA
+#define PCIEMSIX_VECT201_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT201_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT201_CONTROL
+#define PCIEMSIX_VECT201_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT201_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT202_ADDR_LO
+#define PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT202_ADDR_HI
+#define PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT202_MSG_DATA
+#define PCIEMSIX_VECT202_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT202_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT202_CONTROL
+#define PCIEMSIX_VECT202_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT202_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT203_ADDR_LO
+#define PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT203_ADDR_HI
+#define PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT203_MSG_DATA
+#define PCIEMSIX_VECT203_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT203_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT203_CONTROL
+#define PCIEMSIX_VECT203_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT203_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT204_ADDR_LO
+#define PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT204_ADDR_HI
+#define PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT204_MSG_DATA
+#define PCIEMSIX_VECT204_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT204_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT204_CONTROL
+#define PCIEMSIX_VECT204_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT204_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT205_ADDR_LO
+#define PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT205_ADDR_HI
+#define PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT205_MSG_DATA
+#define PCIEMSIX_VECT205_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT205_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT205_CONTROL
+#define PCIEMSIX_VECT205_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT205_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT206_ADDR_LO
+#define PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT206_ADDR_HI
+#define PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT206_MSG_DATA
+#define PCIEMSIX_VECT206_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT206_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT206_CONTROL
+#define PCIEMSIX_VECT206_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT206_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT207_ADDR_LO
+#define PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT207_ADDR_HI
+#define PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT207_MSG_DATA
+#define PCIEMSIX_VECT207_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT207_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT207_CONTROL
+#define PCIEMSIX_VECT207_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT207_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT208_ADDR_LO
+#define PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT208_ADDR_HI
+#define PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT208_MSG_DATA
+#define PCIEMSIX_VECT208_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT208_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT208_CONTROL
+#define PCIEMSIX_VECT208_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT208_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT209_ADDR_LO
+#define PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT209_ADDR_HI
+#define PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT209_MSG_DATA
+#define PCIEMSIX_VECT209_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT209_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT209_CONTROL
+#define PCIEMSIX_VECT209_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT209_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT210_ADDR_LO
+#define PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT210_ADDR_HI
+#define PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT210_MSG_DATA
+#define PCIEMSIX_VECT210_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT210_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT210_CONTROL
+#define PCIEMSIX_VECT210_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT210_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT211_ADDR_LO
+#define PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT211_ADDR_HI
+#define PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT211_MSG_DATA
+#define PCIEMSIX_VECT211_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT211_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT211_CONTROL
+#define PCIEMSIX_VECT211_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT211_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT212_ADDR_LO
+#define PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT212_ADDR_HI
+#define PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT212_MSG_DATA
+#define PCIEMSIX_VECT212_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT212_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT212_CONTROL
+#define PCIEMSIX_VECT212_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT212_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT213_ADDR_LO
+#define PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT213_ADDR_HI
+#define PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT213_MSG_DATA
+#define PCIEMSIX_VECT213_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT213_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT213_CONTROL
+#define PCIEMSIX_VECT213_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT213_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT214_ADDR_LO
+#define PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT214_ADDR_HI
+#define PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT214_MSG_DATA
+#define PCIEMSIX_VECT214_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT214_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT214_CONTROL
+#define PCIEMSIX_VECT214_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT214_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT215_ADDR_LO
+#define PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT215_ADDR_HI
+#define PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT215_MSG_DATA
+#define PCIEMSIX_VECT215_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT215_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT215_CONTROL
+#define PCIEMSIX_VECT215_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT215_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT216_ADDR_LO
+#define PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT216_ADDR_HI
+#define PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT216_MSG_DATA
+#define PCIEMSIX_VECT216_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT216_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT216_CONTROL
+#define PCIEMSIX_VECT216_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT216_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT217_ADDR_LO
+#define PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT217_ADDR_HI
+#define PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT217_MSG_DATA
+#define PCIEMSIX_VECT217_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT217_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT217_CONTROL
+#define PCIEMSIX_VECT217_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT217_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT218_ADDR_LO
+#define PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT218_ADDR_HI
+#define PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT218_MSG_DATA
+#define PCIEMSIX_VECT218_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT218_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT218_CONTROL
+#define PCIEMSIX_VECT218_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT218_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT219_ADDR_LO
+#define PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT219_ADDR_HI
+#define PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT219_MSG_DATA
+#define PCIEMSIX_VECT219_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT219_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT219_CONTROL
+#define PCIEMSIX_VECT219_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT219_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT220_ADDR_LO
+#define PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT220_ADDR_HI
+#define PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT220_MSG_DATA
+#define PCIEMSIX_VECT220_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT220_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT220_CONTROL
+#define PCIEMSIX_VECT220_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT220_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT221_ADDR_LO
+#define PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT221_ADDR_HI
+#define PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT221_MSG_DATA
+#define PCIEMSIX_VECT221_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT221_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT221_CONTROL
+#define PCIEMSIX_VECT221_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT221_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT222_ADDR_LO
+#define PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT222_ADDR_HI
+#define PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT222_MSG_DATA
+#define PCIEMSIX_VECT222_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT222_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT222_CONTROL
+#define PCIEMSIX_VECT222_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT222_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT223_ADDR_LO
+#define PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT223_ADDR_HI
+#define PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT223_MSG_DATA
+#define PCIEMSIX_VECT223_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT223_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT223_CONTROL
+#define PCIEMSIX_VECT223_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT223_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT224_ADDR_LO
+#define PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT224_ADDR_HI
+#define PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT224_MSG_DATA
+#define PCIEMSIX_VECT224_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT224_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT224_CONTROL
+#define PCIEMSIX_VECT224_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT224_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT225_ADDR_LO
+#define PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT225_ADDR_HI
+#define PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT225_MSG_DATA
+#define PCIEMSIX_VECT225_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT225_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT225_CONTROL
+#define PCIEMSIX_VECT225_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT225_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT226_ADDR_LO
+#define PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT226_ADDR_HI
+#define PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT226_MSG_DATA
+#define PCIEMSIX_VECT226_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT226_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT226_CONTROL
+#define PCIEMSIX_VECT226_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT226_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT227_ADDR_LO
+#define PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT227_ADDR_HI
+#define PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT227_MSG_DATA
+#define PCIEMSIX_VECT227_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT227_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT227_CONTROL
+#define PCIEMSIX_VECT227_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT227_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT228_ADDR_LO
+#define PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT228_ADDR_HI
+#define PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT228_MSG_DATA
+#define PCIEMSIX_VECT228_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT228_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT228_CONTROL
+#define PCIEMSIX_VECT228_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT228_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT229_ADDR_LO
+#define PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT229_ADDR_HI
+#define PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT229_MSG_DATA
+#define PCIEMSIX_VECT229_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT229_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT229_CONTROL
+#define PCIEMSIX_VECT229_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT229_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT230_ADDR_LO
+#define PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT230_ADDR_HI
+#define PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT230_MSG_DATA
+#define PCIEMSIX_VECT230_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT230_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT230_CONTROL
+#define PCIEMSIX_VECT230_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT230_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT231_ADDR_LO
+#define PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT231_ADDR_HI
+#define PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT231_MSG_DATA
+#define PCIEMSIX_VECT231_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT231_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT231_CONTROL
+#define PCIEMSIX_VECT231_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT231_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT232_ADDR_LO
+#define PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT232_ADDR_HI
+#define PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT232_MSG_DATA
+#define PCIEMSIX_VECT232_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT232_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT232_CONTROL
+#define PCIEMSIX_VECT232_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT232_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT233_ADDR_LO
+#define PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT233_ADDR_HI
+#define PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT233_MSG_DATA
+#define PCIEMSIX_VECT233_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT233_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT233_CONTROL
+#define PCIEMSIX_VECT233_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT233_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT234_ADDR_LO
+#define PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT234_ADDR_HI
+#define PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT234_MSG_DATA
+#define PCIEMSIX_VECT234_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT234_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT234_CONTROL
+#define PCIEMSIX_VECT234_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT234_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT235_ADDR_LO
+#define PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT235_ADDR_HI
+#define PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT235_MSG_DATA
+#define PCIEMSIX_VECT235_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT235_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT235_CONTROL
+#define PCIEMSIX_VECT235_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT235_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT236_ADDR_LO
+#define PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT236_ADDR_HI
+#define PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT236_MSG_DATA
+#define PCIEMSIX_VECT236_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT236_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT236_CONTROL
+#define PCIEMSIX_VECT236_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT236_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT237_ADDR_LO
+#define PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT237_ADDR_HI
+#define PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT237_MSG_DATA
+#define PCIEMSIX_VECT237_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT237_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT237_CONTROL
+#define PCIEMSIX_VECT237_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT237_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT238_ADDR_LO
+#define PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT238_ADDR_HI
+#define PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT238_MSG_DATA
+#define PCIEMSIX_VECT238_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT238_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT238_CONTROL
+#define PCIEMSIX_VECT238_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT238_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT239_ADDR_LO
+#define PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT239_ADDR_HI
+#define PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT239_MSG_DATA
+#define PCIEMSIX_VECT239_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT239_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT239_CONTROL
+#define PCIEMSIX_VECT239_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT239_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT240_ADDR_LO
+#define PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT240_ADDR_HI
+#define PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT240_MSG_DATA
+#define PCIEMSIX_VECT240_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT240_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT240_CONTROL
+#define PCIEMSIX_VECT240_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT240_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT241_ADDR_LO
+#define PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT241_ADDR_HI
+#define PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT241_MSG_DATA
+#define PCIEMSIX_VECT241_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT241_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT241_CONTROL
+#define PCIEMSIX_VECT241_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT241_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT242_ADDR_LO
+#define PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT242_ADDR_HI
+#define PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT242_MSG_DATA
+#define PCIEMSIX_VECT242_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT242_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT242_CONTROL
+#define PCIEMSIX_VECT242_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT242_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT243_ADDR_LO
+#define PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT243_ADDR_HI
+#define PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT243_MSG_DATA
+#define PCIEMSIX_VECT243_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT243_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT243_CONTROL
+#define PCIEMSIX_VECT243_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT243_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT244_ADDR_LO
+#define PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT244_ADDR_HI
+#define PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT244_MSG_DATA
+#define PCIEMSIX_VECT244_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT244_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT244_CONTROL
+#define PCIEMSIX_VECT244_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT244_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT245_ADDR_LO
+#define PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT245_ADDR_HI
+#define PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT245_MSG_DATA
+#define PCIEMSIX_VECT245_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT245_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT245_CONTROL
+#define PCIEMSIX_VECT245_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT245_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT246_ADDR_LO
+#define PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT246_ADDR_HI
+#define PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT246_MSG_DATA
+#define PCIEMSIX_VECT246_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT246_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT246_CONTROL
+#define PCIEMSIX_VECT246_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT246_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT247_ADDR_LO
+#define PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT247_ADDR_HI
+#define PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT247_MSG_DATA
+#define PCIEMSIX_VECT247_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT247_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT247_CONTROL
+#define PCIEMSIX_VECT247_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT247_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT248_ADDR_LO
+#define PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT248_ADDR_HI
+#define PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT248_MSG_DATA
+#define PCIEMSIX_VECT248_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT248_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT248_CONTROL
+#define PCIEMSIX_VECT248_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT248_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT249_ADDR_LO
+#define PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT249_ADDR_HI
+#define PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT249_MSG_DATA
+#define PCIEMSIX_VECT249_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT249_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT249_CONTROL
+#define PCIEMSIX_VECT249_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT249_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT250_ADDR_LO
+#define PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT250_ADDR_HI
+#define PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT250_MSG_DATA
+#define PCIEMSIX_VECT250_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT250_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT250_CONTROL
+#define PCIEMSIX_VECT250_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT250_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT251_ADDR_LO
+#define PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT251_ADDR_HI
+#define PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT251_MSG_DATA
+#define PCIEMSIX_VECT251_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT251_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT251_CONTROL
+#define PCIEMSIX_VECT251_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT251_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT252_ADDR_LO
+#define PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT252_ADDR_HI
+#define PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT252_MSG_DATA
+#define PCIEMSIX_VECT252_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT252_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT252_CONTROL
+#define PCIEMSIX_VECT252_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT252_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT253_ADDR_LO
+#define PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT253_ADDR_HI
+#define PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT253_MSG_DATA
+#define PCIEMSIX_VECT253_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT253_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT253_CONTROL
+#define PCIEMSIX_VECT253_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT253_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT254_ADDR_LO
+#define PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT254_ADDR_HI
+#define PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT254_MSG_DATA
+#define PCIEMSIX_VECT254_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT254_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT254_CONTROL
+#define PCIEMSIX_VECT254_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT254_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT255_ADDR_LO
+#define PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT255_ADDR_HI
+#define PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT255_MSG_DATA
+#define PCIEMSIX_VECT255_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT255_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT255_CONTROL
+#define PCIEMSIX_VECT255_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT255_CONTROL__MASK_BIT_MASK 0x00000001L
+
+
+// addressBlock: nbif_rcc_pfc_usb_RCCPFCDEC
+//RCC_PFC_USB_RCC_PFC_LTR_CNTL
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L
+//RCC_PFC_USB_RCC_PFC_PME_RESTORE
+#define RCC_PFC_USB_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_USB_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+#define RCC_PFC_USB_RCC_PFC_PME_RESTORE__PME_SENT_FLAG__SHIFT 0x9
+#define RCC_PFC_USB_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L
+#define RCC_PFC_USB_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L
+#define RCC_PFC_USB_RCC_PFC_PME_RESTORE__PME_SENT_FLAG_MASK 0x00000200L
+//RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L
+//RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL
+//RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL
+//RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL
+//RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL
+//RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL
+//RCC_PFC_USB_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_USB_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_USB_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+#define RCC_PFC_USB_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L
+#define RCC_PFC_USB_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L
+
+
+// addressBlock: nbif_rcc_pfc_pd_controller_RCCPFCDEC
+//RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L
+//RCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE__PME_SENT_FLAG__SHIFT 0x9
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE__PME_SENT_FLAG_MASK 0x00000200L
+//RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L
+//RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL
+//RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL
+//RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL
+//RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL
+//RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL
+//RCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L
+
+
+// addressBlock: nbif_pciemsix_0_usb_MSIXPDEC
+//PCIEMSIX_PBA_0
+#define PCIEMSIX_PBA_0__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_PBA_0__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+//PCIEMSIX_PBA_1
+#define PCIEMSIX_PBA_1__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_PBA_1__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+//PCIEMSIX_PBA_2
+#define PCIEMSIX_PBA_2__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_PBA_2__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+//PCIEMSIX_PBA_3
+#define PCIEMSIX_PBA_3__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_PBA_3__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+//PCIEMSIX_PBA_4
+#define PCIEMSIX_PBA_4__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_PBA_4__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+//PCIEMSIX_PBA_5
+#define PCIEMSIX_PBA_5__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_PBA_5__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+//PCIEMSIX_PBA_6
+#define PCIEMSIX_PBA_6__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_PBA_6__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+//PCIEMSIX_PBA_7
+#define PCIEMSIX_PBA_7__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_PBA_7__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_shadow_reg_shadowdec
+//SHADOW_COMMAND
+#define SHADOW_COMMAND__IOEN_UP__SHIFT 0x0
+#define SHADOW_COMMAND__MEMEN_UP__SHIFT 0x1
+#define SHADOW_COMMAND__IOEN_UP_MASK 0x0001L
+#define SHADOW_COMMAND__MEMEN_UP_MASK 0x0002L
+//SHADOW_BASE_ADDR_1
+#define SHADOW_BASE_ADDR_1__BAR1_UP__SHIFT 0x0
+#define SHADOW_BASE_ADDR_1__BAR1_UP_MASK 0xFFFFFFFFL
+//SHADOW_BASE_ADDR_2
+#define SHADOW_BASE_ADDR_2__BAR2_UP__SHIFT 0x0
+#define SHADOW_BASE_ADDR_2__BAR2_UP_MASK 0xFFFFFFFFL
+//SHADOW_IRQ_BRIDGE_CNTL
+#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__SHIFT 0x2
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__SHIFT 0x3
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__SHIFT 0x4
+#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__SHIFT 0x6
+#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP_MASK 0x0004L
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP_MASK 0x0008L
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP_MASK 0x0010L
+#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP_MASK 0x0040L
+//SUC_INDEX
+#define SUC_INDEX__SUC_INDEX__SHIFT 0x0
+#define SUC_INDEX__SUC_INDEX_MASK 0xFFFFFFFFL
+//SUC_DATA
+#define SUC_DATA__SUC_DATA__SHIFT 0x0
+#define SUC_DATA__SUC_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_bif_swus_SUMDEC
+//SUM_INDEX
+#define SUM_INDEX__SUM_INDEX__SHIFT 0x0
+#define SUM_INDEX__SUM_INDEX_MASK 0xFFFFFFFFL
+//SUM_DATA
+#define SUM_DATA__SUM_DATA__SHIFT 0x0
+#define SUM_DATA__SUM_DATA_MASK 0xFFFFFFFFL
+//SUM_INDEX_HI
+#define SUM_INDEX_HI__SUM_INDEX_HI__SHIFT 0x0
+#define SUM_INDEX_HI__SUM_INDEX_HI_MASK 0x000000FFL
+
+
+// addressBlock: nbif_rcc_strap_rcc_strap_internal
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x11
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x13
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00010000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00020000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00080000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP5
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x00E00000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x0F000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0xF0000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP9
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT 0x2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT 0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT 0x4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT 0x5
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT 0x6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK 0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK 0x00000004L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK 0x00000008L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK 0x00000010L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK 0x00000020L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK 0x0007FFC0L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP11
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK 0x0FFF0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK 0x10000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK 0x40000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP12
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK 0x00FFFFFFL
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP13
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT 0x9
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK 0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK 0x00000100L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK 0x000FFE00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK 0xFFF00000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP14
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT 0x2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT 0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT 0x4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK 0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK 0x00000004L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK 0x00000008L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK 0x00000010L
+//RCC_DEV1_PORT_STRAP0
+//RCC_DEV1_PORT_STRAP1
+//RCC_DEV1_PORT_STRAP2
+//RCC_DEV1_PORT_STRAP3
+//RCC_DEV1_PORT_STRAP4
+//RCC_DEV1_PORT_STRAP5
+//RCC_DEV1_PORT_STRAP6
+//RCC_DEV1_PORT_STRAP7
+//RCC_DEV1_PORT_STRAP8
+//RCC_DEV1_PORT_STRAP9
+//RCC_DEV1_PORT_STRAP10
+//RCC_DEV1_PORT_STRAP11
+//RCC_DEV1_PORT_STRAP12
+//RCC_DEV1_PORT_STRAP13
+//RCC_DEV1_PORT_STRAP14
+//RCC_DEV2_PORT_STRAP0
+//RCC_DEV2_PORT_STRAP1
+//RCC_DEV2_PORT_STRAP2
+//RCC_DEV2_PORT_STRAP3
+//RCC_DEV2_PORT_STRAP4
+//RCC_DEV2_PORT_STRAP5
+//RCC_DEV2_PORT_STRAP6
+//RCC_DEV2_PORT_STRAP7
+//RCC_DEV2_PORT_STRAP8
+//RCC_DEV2_PORT_STRAP9
+//RCC_DEV2_PORT_STRAP10
+//RCC_DEV2_PORT_STRAP11
+//RCC_DEV2_PORT_STRAP12
+//RCC_DEV2_PORT_STRAP13
+//RCC_DEV2_PORT_STRAP14
+//RCC_STRAP1_RCC_BIF_STRAP0
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT 0x0
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT 0x1
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x14
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN__SHIFT 0x15
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GPUIOV_EN__SHIFT 0x16
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT 0x1c
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK 0x00000001L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK 0x00000002L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000078L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00100000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN_MASK 0x00200000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GPUIOV_EN_MASK 0x00400000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK 0x10000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L
+//RCC_STRAP1_RCC_BIF_STRAP1
+#define RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x0
+#define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1
+#define RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x2
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT 0x18
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT 0x19
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT 0x1e
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT 0x1f
+#define RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L
+#define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L
+#define RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK 0x01000000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK 0x02000000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_MASK 0x40000000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK 0x80000000L
+//RCC_STRAP1_RCC_BIF_STRAP2
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWUS_SPT__SHIFT 0x1
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN__SHIFT 0x7
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_USB_PD_FUNC_DIS__SHIFT 0xc
+#define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWUS_SPT_MASK 0x00000002L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN_MASK 0x00000080L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_USB_PD_FUNC_DIS_MASK 0x00001000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L
+//RCC_STRAP1_RCC_BIF_STRAP3
+#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0
+#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10
+#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L
+//RCC_STRAP1_RCC_BIF_STRAP4
+#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0
+#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10
+#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L
+//RCC_STRAP1_RCC_BIF_STRAP5
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT 0x15
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN__SHIFT 0x1f
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK 0x00200000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN_MASK 0x80000000L
+//RCC_STRAP1_RCC_BIF_STRAP6
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT 0x0
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT 0x1
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT 0x2
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL__SHIFT 0x3
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_S5_GFX_REGS_ACCESS_DIS__SHIFT 0x4
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE__SHIFT 0x5
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GFX_PARTITION_CAP_SPX_SUPPORT__SHIFT 0x6
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GFX_PARTITION_CAP_TPX_SUPPORT__SHIFT 0x7
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_MEM_PARTITION_CAP_NPS1_SUPPORT__SHIFT 0x8
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_MEM_PARTITION_CAP_NPS3_SUPPORT__SHIFT 0x9
+#define RCC_STRAP1_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6__SHIFT 0xa
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK 0x00000001L
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK 0x00000002L
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK 0x00000004L
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL_MASK 0x00000008L
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_S5_GFX_REGS_ACCESS_DIS_MASK 0x00000010L
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE_MASK 0x00000020L
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GFX_PARTITION_CAP_SPX_SUPPORT_MASK 0x00000040L
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GFX_PARTITION_CAP_TPX_SUPPORT_MASK 0x00000080L
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_MEM_PARTITION_CAP_NPS1_SUPPORT_MASK 0x00000100L
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_MEM_PARTITION_CAP_NPS3_SUPPORT_MASK 0x00000200L
+#define RCC_STRAP1_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6_MASK 0xFFFFFC00L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP1
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP2
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP3
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x11
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00010000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00020000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP4
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP5
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0_MASK 0x38000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP8
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00780000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP9
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP13
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0xFF000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP15
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT 0xc
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK 0x00000FFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK 0x00FFF000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK 0x01000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP16
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT 0xc
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK 0x00000FFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK 0x00FFF000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP17
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT 0xc
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT 0xd
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK 0x00000FFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK 0x00001000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK 0x01FFE000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK 0x00000FFFL
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP2
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP3
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x11
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00010000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00020000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP4
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP5
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT 0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK 0x38000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP6
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP7
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP20
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP21
+//RCC_DEV0_EPF2_STRAP0
+#define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__SHIFT 0x10
+#define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__SHIFT 0x14
+#define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__SHIFT 0x1c
+#define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__SHIFT 0x1d
+#define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__SHIFT 0x1e
+#define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__SHIFT 0x1f
+#define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2_MASK 0x000F0000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2_MASK 0x00F00000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2_MASK 0x10000000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2_MASK 0x20000000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2_MASK 0x40000000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2_MASK 0x80000000L
+//RCC_DEV0_EPF2_STRAP2
+#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__SHIFT 0x7
+#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__SHIFT 0x8
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F2__SHIFT 0x9
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__SHIFT 0xe
+#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__SHIFT 0x10
+#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__SHIFT 0x11
+#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__SHIFT 0x14
+#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__SHIFT 0x15
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__SHIFT 0x18
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EN_DEV0_F2__SHIFT 0x1c
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F2__SHIFT 0x1d
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F2__SHIFT 0x1e
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F2__SHIFT 0x1f
+#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK 0x00000080L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2_MASK 0x00000100L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F2_MASK 0x00003E00L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2_MASK 0x00004000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2_MASK 0x00010000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2_MASK 0x00020000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2_MASK 0x00100000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2_MASK 0x00200000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2_MASK 0x07000000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EN_DEV0_F2_MASK 0x10000000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F2_MASK 0x20000000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F2_MASK 0x40000000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F2_MASK 0x80000000L
+//RCC_DEV0_EPF2_STRAP3
+#define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__SHIFT 0x10
+#define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__SHIFT 0x11
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__SHIFT 0x12
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__SHIFT 0x13
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__SHIFT 0x14
+#define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__SHIFT 0x18
+#define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__SHIFT 0x1a
+#define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__SHIFT 0x1b
+#define RCC_DEV0_EPF2_STRAP3__STRAP_CLK_PM_EN_DEV0_F2__SHIFT 0x1d
+#define RCC_DEV0_EPF2_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F2__SHIFT 0x1e
+#define RCC_DEV0_EPF2_STRAP3__STRAP_RTR_EN_DEV0_F2__SHIFT 0x1f
+#define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2_MASK 0x00010000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2_MASK 0x00020000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2_MASK 0x00040000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2_MASK 0x00080000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2_MASK 0x00100000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2_MASK 0x01000000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2_MASK 0x04000000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2_MASK 0x08000000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_CLK_PM_EN_DEV0_F2_MASK 0x20000000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F2_MASK 0x40000000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_RTR_EN_DEV0_F2_MASK 0x80000000L
+//RCC_DEV0_EPF2_STRAP4
+#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__SHIFT 0x14
+#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__SHIFT 0x15
+#define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__SHIFT 0x16
+#define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__SHIFT 0x17
+#define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__SHIFT 0x1c
+#define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__SHIFT 0x1f
+#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2_MASK 0x00100000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2_MASK 0x00200000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2_MASK 0x00400000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2_MASK 0x0F800000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2_MASK 0x70000000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2_MASK 0x80000000L
+//RCC_DEV0_EPF2_STRAP5
+#define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP5__STRAP_USB_DBESEL_DEV0_F2__SHIFT 0x10
+#define RCC_DEV0_EPF2_STRAP5__STRAP_USB_DBESELD_DEV0_F2__SHIFT 0x14
+#define RCC_DEV0_EPF2_STRAP5__STRAP_AUX_CURRENT_DEV0_F2__SHIFT 0x1b
+#define RCC_DEV0_EPF2_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F2__SHIFT 0x1e
+#define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF2_STRAP5__STRAP_USB_DBESEL_DEV0_F2_MASK 0x000F0000L
+#define RCC_DEV0_EPF2_STRAP5__STRAP_USB_DBESELD_DEV0_F2_MASK 0x00F00000L
+#define RCC_DEV0_EPF2_STRAP5__STRAP_AUX_CURRENT_DEV0_F2_MASK 0x38000000L
+#define RCC_DEV0_EPF2_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F2_MASK 0x40000000L
+//RCC_DEV0_EPF2_STRAP6
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2_MASK 0x00000001L
+//RCC_DEV0_EPF2_STRAP7
+//RCC_DEV0_EPF2_STRAP10
+//RCC_DEV0_EPF2_STRAP11
+//RCC_DEV0_EPF2_STRAP12
+//RCC_DEV0_EPF2_STRAP13
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__SHIFT 0x8
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__SHIFT 0x10
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2_MASK 0x000000FFL
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2_MASK 0x0000FF00L
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2_MASK 0x00FF0000L
+//RCC_DEV0_EPF2_STRAP14
+#define RCC_DEV0_EPF2_STRAP14__STRAP_VENDOR_ID_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP14__STRAP_VENDOR_ID_DEV0_F2_MASK 0x0000FFFFL
+//RCC_DEV0_EPF2_STRAP20
+//RCC_DEV0_EPF3_STRAP0
+#define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__SHIFT 0x10
+#define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__SHIFT 0x14
+#define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__SHIFT 0x1c
+#define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__SHIFT 0x1d
+#define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__SHIFT 0x1e
+#define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__SHIFT 0x1f
+#define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3_MASK 0x000F0000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3_MASK 0x00F00000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3_MASK 0x10000000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3_MASK 0x20000000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3_MASK 0x40000000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3_MASK 0x80000000L
+//RCC_DEV0_EPF3_STRAP2
+#define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__SHIFT 0x7
+#define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__SHIFT 0x8
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F3__SHIFT 0x9
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__SHIFT 0xe
+#define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__SHIFT 0x10
+#define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__SHIFT 0x11
+#define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__SHIFT 0x14
+#define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__SHIFT 0x15
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__SHIFT 0x18
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EN_DEV0_F3__SHIFT 0x1c
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F3__SHIFT 0x1d
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F3__SHIFT 0x1e
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F3__SHIFT 0x1f
+#define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3_MASK 0x00000080L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3_MASK 0x00000100L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F3_MASK 0x00003E00L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3_MASK 0x00004000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3_MASK 0x00010000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3_MASK 0x00020000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3_MASK 0x00100000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3_MASK 0x00200000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3_MASK 0x07000000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EN_DEV0_F3_MASK 0x10000000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F3_MASK 0x20000000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F3_MASK 0x40000000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F3_MASK 0x80000000L
+//RCC_DEV0_EPF3_STRAP3
+#define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__SHIFT 0x10
+#define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__SHIFT 0x11
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__SHIFT 0x12
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__SHIFT 0x13
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__SHIFT 0x14
+#define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__SHIFT 0x18
+#define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__SHIFT 0x1a
+#define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__SHIFT 0x1b
+#define RCC_DEV0_EPF3_STRAP3__STRAP_CLK_PM_EN_DEV0_F3__SHIFT 0x1d
+#define RCC_DEV0_EPF3_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F3__SHIFT 0x1e
+#define RCC_DEV0_EPF3_STRAP3__STRAP_RTR_EN_DEV0_F3__SHIFT 0x1f
+#define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3_MASK 0x00010000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3_MASK 0x00020000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3_MASK 0x00040000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3_MASK 0x00080000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3_MASK 0x00100000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3_MASK 0x01000000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3_MASK 0x04000000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3_MASK 0x08000000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_CLK_PM_EN_DEV0_F3_MASK 0x20000000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F3_MASK 0x40000000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_RTR_EN_DEV0_F3_MASK 0x80000000L
+//RCC_DEV0_EPF3_STRAP4
+#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__SHIFT 0x14
+#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__SHIFT 0x15
+#define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__SHIFT 0x16
+#define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__SHIFT 0x17
+#define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__SHIFT 0x1c
+#define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3__SHIFT 0x1f
+#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3_MASK 0x00100000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3_MASK 0x00200000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3_MASK 0x00400000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3_MASK 0x0F800000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3_MASK 0x70000000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3_MASK 0x80000000L
+//RCC_DEV0_EPF3_STRAP5
+#define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP5__STRAP_AUX_CURRENT_DEV0_F3__SHIFT 0x1b
+#define RCC_DEV0_EPF3_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F3__SHIFT 0x1e
+#define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF3_STRAP5__STRAP_AUX_CURRENT_DEV0_F3_MASK 0x38000000L
+#define RCC_DEV0_EPF3_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F3_MASK 0x40000000L
+//RCC_DEV0_EPF3_STRAP6
+#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3_MASK 0x00000001L
+//RCC_DEV0_EPF3_STRAP7
+//RCC_DEV0_EPF3_STRAP10
+//RCC_DEV0_EPF3_STRAP11
+//RCC_DEV0_EPF3_STRAP12
+//RCC_DEV0_EPF3_STRAP13
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__SHIFT 0x8
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__SHIFT 0x10
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3_MASK 0x000000FFL
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3_MASK 0x0000FF00L
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3_MASK 0x00FF0000L
+//RCC_DEV0_EPF3_STRAP14
+#define RCC_DEV0_EPF3_STRAP14__STRAP_VENDOR_ID_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP14__STRAP_VENDOR_ID_DEV0_F3_MASK 0x0000FFFFL
+//RCC_DEV0_EPF3_STRAP20
+//RCC_DEV0_EPF4_STRAP0
+#define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4__SHIFT 0x1c
+#define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4__SHIFT 0x1e
+#define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4__SHIFT 0x1f
+#define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4_MASK 0x10000000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4_MASK 0x40000000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4_MASK 0x80000000L
+//RCC_DEV0_EPF4_STRAP2
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F4__SHIFT 0x9
+#define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4__SHIFT 0x10
+#define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4__SHIFT 0x11
+#define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4__SHIFT 0x14
+#define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4__SHIFT 0x15
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EN_DEV0_F4__SHIFT 0x1c
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F4__SHIFT 0x1d
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F4__SHIFT 0x1e
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F4__SHIFT 0x1f
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F4_MASK 0x00003E00L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4_MASK 0x00010000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4_MASK 0x00020000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4_MASK 0x00100000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4_MASK 0x00200000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EN_DEV0_F4_MASK 0x10000000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F4_MASK 0x20000000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F4_MASK 0x40000000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F4_MASK 0x80000000L
+//RCC_DEV0_EPF4_STRAP3
+#define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4__SHIFT 0x10
+#define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4__SHIFT 0x11
+#define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4__SHIFT 0x18
+#define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4__SHIFT 0x1a
+#define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4__SHIFT 0x1b
+#define RCC_DEV0_EPF4_STRAP3__STRAP_CLK_PM_EN_DEV0_F4__SHIFT 0x1d
+#define RCC_DEV0_EPF4_STRAP3__STRAP_RTR_EN_DEV0_F4__SHIFT 0x1f
+#define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4_MASK 0x00010000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4_MASK 0x00020000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4_MASK 0x01000000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4_MASK 0x04000000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4_MASK 0x08000000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_CLK_PM_EN_DEV0_F4_MASK 0x20000000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_RTR_EN_DEV0_F4_MASK 0x80000000L
+//RCC_DEV0_EPF4_STRAP4
+#define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4__SHIFT 0x1f
+#define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4_MASK 0x80000000L
+//RCC_DEV0_EPF4_STRAP5
+#define RCC_DEV0_EPF4_STRAP5__STRAP_AUX_CURRENT_DEV0_F4__SHIFT 0x1b
+#define RCC_DEV0_EPF4_STRAP5__STRAP_AUX_CURRENT_DEV0_F4_MASK 0x38000000L
+//RCC_DEV0_EPF4_STRAP6
+//RCC_DEV0_EPF4_STRAP7
+//RCC_DEV0_EPF4_STRAP13
+//RCC_DEV0_EPF4_STRAP14
+//RCC_DEV0_EPF5_STRAP0
+#define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5__SHIFT 0x1c
+#define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5__SHIFT 0x1e
+#define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5__SHIFT 0x1f
+#define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5_MASK 0x10000000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5_MASK 0x40000000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5_MASK 0x80000000L
+//RCC_DEV0_EPF5_STRAP2
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F5__SHIFT 0x9
+#define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5__SHIFT 0x10
+#define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5__SHIFT 0x11
+#define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5__SHIFT 0x14
+#define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5__SHIFT 0x15
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EN_DEV0_F5__SHIFT 0x1c
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F5__SHIFT 0x1d
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F5__SHIFT 0x1e
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F5__SHIFT 0x1f
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F5_MASK 0x00003E00L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5_MASK 0x00010000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5_MASK 0x00020000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5_MASK 0x00100000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5_MASK 0x00200000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EN_DEV0_F5_MASK 0x10000000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F5_MASK 0x20000000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F5_MASK 0x40000000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F5_MASK 0x80000000L
+//RCC_DEV0_EPF5_STRAP3
+#define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5__SHIFT 0x10
+#define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5__SHIFT 0x11
+#define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5__SHIFT 0x18
+#define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5__SHIFT 0x1a
+#define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5__SHIFT 0x1b
+#define RCC_DEV0_EPF5_STRAP3__STRAP_CLK_PM_EN_DEV0_F5__SHIFT 0x1d
+#define RCC_DEV0_EPF5_STRAP3__STRAP_RTR_EN_DEV0_F5__SHIFT 0x1f
+#define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5_MASK 0x00010000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5_MASK 0x00020000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5_MASK 0x01000000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5_MASK 0x04000000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5_MASK 0x08000000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_CLK_PM_EN_DEV0_F5_MASK 0x20000000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_RTR_EN_DEV0_F5_MASK 0x80000000L
+//RCC_DEV0_EPF5_STRAP4
+#define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5__SHIFT 0x1f
+#define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5_MASK 0x80000000L
+//RCC_DEV0_EPF5_STRAP5
+#define RCC_DEV0_EPF5_STRAP5__STRAP_AUX_CURRENT_DEV0_F5__SHIFT 0x1b
+#define RCC_DEV0_EPF5_STRAP5__STRAP_AUX_CURRENT_DEV0_F5_MASK 0x38000000L
+//RCC_DEV0_EPF5_STRAP6
+//RCC_DEV0_EPF5_STRAP7
+//RCC_DEV0_EPF5_STRAP13
+//RCC_DEV0_EPF5_STRAP14
+//RCC_DEV0_EPF6_STRAP0
+#define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6__SHIFT 0x1c
+#define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6__SHIFT 0x1e
+#define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6__SHIFT 0x1f
+#define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6_MASK 0x10000000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6_MASK 0x40000000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6_MASK 0x80000000L
+//RCC_DEV0_EPF6_STRAP2
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F6__SHIFT 0x9
+#define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6__SHIFT 0x10
+#define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6__SHIFT 0x11
+#define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6__SHIFT 0x14
+#define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6__SHIFT 0x15
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EN_DEV0_F6__SHIFT 0x1c
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F6__SHIFT 0x1d
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F6__SHIFT 0x1e
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F6__SHIFT 0x1f
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F6_MASK 0x00003E00L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6_MASK 0x00010000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6_MASK 0x00020000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6_MASK 0x00100000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6_MASK 0x00200000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EN_DEV0_F6_MASK 0x10000000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F6_MASK 0x20000000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F6_MASK 0x40000000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F6_MASK 0x80000000L
+//RCC_DEV0_EPF6_STRAP3
+#define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6__SHIFT 0x10
+#define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6__SHIFT 0x11
+#define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6__SHIFT 0x18
+#define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6__SHIFT 0x1a
+#define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6__SHIFT 0x1b
+#define RCC_DEV0_EPF6_STRAP3__STRAP_CLK_PM_EN_DEV0_F6__SHIFT 0x1d
+#define RCC_DEV0_EPF6_STRAP3__STRAP_RTR_EN_DEV0_F6__SHIFT 0x1f
+#define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6_MASK 0x00010000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6_MASK 0x00020000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6_MASK 0x01000000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6_MASK 0x04000000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6_MASK 0x08000000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_CLK_PM_EN_DEV0_F6_MASK 0x20000000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_RTR_EN_DEV0_F6_MASK 0x80000000L
+//RCC_DEV0_EPF6_STRAP4
+#define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6__SHIFT 0x1f
+#define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6_MASK 0x80000000L
+//RCC_DEV0_EPF6_STRAP5
+#define RCC_DEV0_EPF6_STRAP5__STRAP_AUX_CURRENT_DEV0_F6__SHIFT 0x1b
+#define RCC_DEV0_EPF6_STRAP5__STRAP_AUX_CURRENT_DEV0_F6_MASK 0x38000000L
+
+
+// addressBlock: nbif_bif_rst_bif_rst_regblk
+//HARD_RST_CTRL
+#define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0
+#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1
+#define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2
+#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3
+#define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4
+#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5
+#define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6
+#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7
+#define HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x9
+#define HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT 0xa
+#define HARD_RST_CTRL__STRAP_RST_EN__SHIFT 0x17
+#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c
+#define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d
+#define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e
+#define HARD_RST_CTRL__CORE_RST_EN__SHIFT 0x1f
+#define HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK 0x00000001L
+#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK 0x00000002L
+#define HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK 0x00000004L
+#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK 0x00000008L
+#define HARD_RST_CTRL__EP_CFG_RST_EN_MASK 0x00000010L
+#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK 0x00000020L
+#define HARD_RST_CTRL__EP_PRV_RST_EN_MASK 0x00000040L
+#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK 0x00000080L
+#define HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000200L
+#define HARD_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000400L
+#define HARD_RST_CTRL__STRAP_RST_EN_MASK 0x00800000L
+#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN_MASK 0x10000000L
+#define HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK 0x20000000L
+#define HARD_RST_CTRL__RELOAD_STRAP_EN_MASK 0x40000000L
+#define HARD_RST_CTRL__CORE_RST_EN_MASK 0x80000000L
+//RSMU_SOFT_RST_CTRL
+#define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0
+#define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1
+#define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2
+#define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3
+#define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4
+#define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5
+#define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6
+#define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7
+#define RSMU_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x9
+#define RSMU_SOFT_RST_CTRL__SION_AON_RESET_EN__SHIFT 0xa
+#define RSMU_SOFT_RST_CTRL__STRAP_RST_EN__SHIFT 0x17
+#define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c
+#define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d
+#define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e
+#define RSMU_SOFT_RST_CTRL__CORE_RST_EN__SHIFT 0x1f
+#define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN_MASK 0x00000001L
+#define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK 0x00000002L
+#define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN_MASK 0x00000004L
+#define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK 0x00000008L
+#define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN_MASK 0x00000010L
+#define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK 0x00000020L
+#define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN_MASK 0x00000040L
+#define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK 0x00000080L
+#define RSMU_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000200L
+#define RSMU_SOFT_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000400L
+#define RSMU_SOFT_RST_CTRL__STRAP_RST_EN_MASK 0x00800000L
+#define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN_MASK 0x10000000L
+#define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN_MASK 0x20000000L
+#define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN_MASK 0x40000000L
+#define RSMU_SOFT_RST_CTRL__CORE_RST_EN_MASK 0x80000000L
+//SELF_SOFT_RST
+#define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT 0x0
+#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT 0x1
+#define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT 0x2
+#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT 0x3
+#define SELF_SOFT_RST__EP0_CFG_RST__SHIFT 0x4
+#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT 0x5
+#define SELF_SOFT_RST__EP0_PRV_RST__SHIFT 0x6
+#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT 0x7
+#define SELF_SOFT_RST__HRPU_SDP_PORT_RST__SHIFT 0x18
+#define SELF_SOFT_RST__GSID_SDP_PORT_RST__SHIFT 0x19
+#define SELF_SOFT_RST__GMIU_SDP_PORT_RST__SHIFT 0x1a
+#define SELF_SOFT_RST__GMID_SDP_PORT_RST__SHIFT 0x1b
+#define SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT 0x1c
+#define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT 0x1d
+#define SELF_SOFT_RST__RELOAD_STRAP__SHIFT 0x1e
+#define SELF_SOFT_RST__CORE_RST__SHIFT 0x1f
+#define SELF_SOFT_RST__DSPT0_CFG_RST_MASK 0x00000001L
+#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK 0x00000002L
+#define SELF_SOFT_RST__DSPT0_PRV_RST_MASK 0x00000004L
+#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK 0x00000008L
+#define SELF_SOFT_RST__EP0_CFG_RST_MASK 0x00000010L
+#define SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK 0x00000020L
+#define SELF_SOFT_RST__EP0_PRV_RST_MASK 0x00000040L
+#define SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK 0x00000080L
+#define SELF_SOFT_RST__HRPU_SDP_PORT_RST_MASK 0x01000000L
+#define SELF_SOFT_RST__GSID_SDP_PORT_RST_MASK 0x02000000L
+#define SELF_SOFT_RST__GMIU_SDP_PORT_RST_MASK 0x04000000L
+#define SELF_SOFT_RST__GMID_SDP_PORT_RST_MASK 0x08000000L
+#define SELF_SOFT_RST__SWUS_SHADOW_RST_MASK 0x10000000L
+#define SELF_SOFT_RST__CORE_STICKY_RST_MASK 0x20000000L
+#define SELF_SOFT_RST__RELOAD_STRAP_MASK 0x40000000L
+#define SELF_SOFT_RST__CORE_RST_MASK 0x80000000L
+//BIF_GFX_DRV_VPU_RST
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT 0x0
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT 0x1
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT 0x2
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT 0x3
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT 0x4
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT 0x5
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT 0x6
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT 0x7
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK 0x00000001L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK 0x00000002L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK 0x00000004L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK 0x00000008L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK 0x00000010L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK 0x00000020L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK 0x00000040L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK 0x00000080L
+//BIF_RST_MISC_CTRL
+#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT 0x0
+#define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT 0x2
+#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT 0x4
+#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT 0x5
+#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT 0x6
+#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT 0x8
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT 0x9
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT 0xa
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT 0xd
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT 0xf
+#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x11
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT 0x17
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT 0x18
+#define BIF_RST_MISC_CTRL__HARD_RST_CTRL_SWUS_SHADOW_PRV_RST_EN__SHIFT 0x1a
+#define BIF_RST_MISC_CTRL__RSMU_SOFT_RST_CTRL_SWUS_SHADOW_PRV_RST_EN__SHIFT 0x1b
+#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK 0x00000001L
+#define BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK 0x0000000CL
+#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK 0x00000010L
+#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK 0x00000020L
+#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK 0x00000040L
+#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK 0x00000100L
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK 0x00000200L
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK 0x00001C00L
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK 0x00006000L
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK 0x00018000L
+#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0x000E0000L
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK 0x00800000L
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK 0x03000000L
+#define BIF_RST_MISC_CTRL__HARD_RST_CTRL_SWUS_SHADOW_PRV_RST_EN_MASK 0x04000000L
+#define BIF_RST_MISC_CTRL__RSMU_SOFT_RST_CTRL_SWUS_SHADOW_PRV_RST_EN_MASK 0x08000000L
+//BIF_RST_MISC_CTRL2
+#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_PROTECT__SHIFT 0x0
+#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_PROTECT__SHIFT 0x1
+#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_PROTECT__SHIFT 0x2
+#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT__SHIFT 0xf
+#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT 0x10
+#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT 0x11
+#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT 0x12
+#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_DIS__SHIFT 0x1e
+#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT 0x1f
+#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_PROTECT_MASK 0x00000001L
+#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_PROTECT_MASK 0x00000002L
+#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_PROTECT_MASK 0x00000004L
+#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_MASK 0x00008000L
+#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK 0x00010000L
+#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK 0x00020000L
+#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK 0x00040000L
+#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_DIS_MASK 0x40000000L
+#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK 0x80000000L
+//BIF_RST_MISC_CTRL3
+#define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT 0x0
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT 0x4
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT 0x6
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT 0x7
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT 0xa
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT 0xd
+#define BIF_RST_MISC_CTRL3__RSMU_SOFT_RST_CYCLE__SHIFT 0x10
+#define BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK 0x0000000FL
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK 0x00000030L
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK 0x00000040L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK 0x00000380L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK 0x00001C00L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK 0x0000E000L
+#define BIF_RST_MISC_CTRL3__RSMU_SOFT_RST_CYCLE_MASK 0x00FF0000L
+//DEV0_PF0_FLR_RST_CTRL
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT 0x5
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT 0x6
+#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT 0x7
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT 0x8
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT 0x9
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT 0xa
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT 0xb
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT 0xc
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT 0xd
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT 0xe
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT 0xf
+#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_FLR_EXC_EN__SHIFT 0x1b
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT 0x1f
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN_MASK 0x00000020L
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN_MASK 0x00000040L
+#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN_MASK 0x00000080L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK 0x00000100L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK 0x00000200L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK 0x00000400L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK 0x00000800L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK 0x00001000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN_MASK 0x00002000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN_MASK 0x00004000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN_MASK 0x00008000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK 0x00010000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_FLR_EXC_EN_MASK 0x08000000L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK 0x80000000L
+//DEV0_PF1_FLR_RST_CTRL
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF1_FLR_RST_CTRL__VF_VF_CFG_FLR_EXC_EN__SHIFT 0x1b
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+#define DEV0_PF1_FLR_RST_CTRL__VF_VF_CFG_FLR_EXC_EN_MASK 0x08000000L
+//DEV0_PF2_FLR_RST_CTRL
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF2_FLR_RST_CTRL__VF_VF_CFG_FLR_EXC_EN__SHIFT 0x1b
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+#define DEV0_PF2_FLR_RST_CTRL__VF_VF_CFG_FLR_EXC_EN_MASK 0x08000000L
+//DEV0_PF3_FLR_RST_CTRL
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF3_FLR_RST_CTRL__VF_VF_CFG_FLR_EXC_EN__SHIFT 0x1b
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+#define DEV0_PF3_FLR_RST_CTRL__VF_VF_CFG_FLR_EXC_EN_MASK 0x08000000L
+//DEV0_PF4_FLR_RST_CTRL
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF4_FLR_RST_CTRL__VF_VF_CFG_FLR_EXC_EN__SHIFT 0x1b
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+#define DEV0_PF4_FLR_RST_CTRL__VF_VF_CFG_FLR_EXC_EN_MASK 0x08000000L
+//DEV0_PF5_FLR_RST_CTRL
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF5_FLR_RST_CTRL__VF_VF_CFG_FLR_EXC_EN__SHIFT 0x1b
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+#define DEV0_PF5_FLR_RST_CTRL__VF_VF_CFG_FLR_EXC_EN_MASK 0x08000000L
+//DEV0_PF6_FLR_RST_CTRL
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF6_FLR_RST_CTRL__VF_VF_CFG_FLR_EXC_EN__SHIFT 0x1b
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+#define DEV0_PF6_FLR_RST_CTRL__VF_VF_CFG_FLR_EXC_EN_MASK 0x08000000L
+//BIF_INST_RESET_INTR_STS
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT 0x0
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x1
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT 0x2
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT 0x3
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT 0x4
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK 0x00000001L
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000002L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK 0x00000004L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK 0x00000008L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK 0x00000010L
+//BIF_PF_FLR_INTR_STS
+#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT 0x0
+#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT 0x1
+#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT 0x2
+#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT 0x3
+#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__SHIFT 0x4
+#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__SHIFT 0x5
+#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__SHIFT 0x6
+#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK 0x00000001L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK 0x00000002L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS_MASK 0x00000004L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS_MASK 0x00000008L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS_MASK 0x00000010L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS_MASK 0x00000020L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS_MASK 0x00000040L
+//BIF_D3HOTD0_INTR_STS
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT 0x0
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT 0x1
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT 0x2
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT 0x3
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__SHIFT 0x4
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__SHIFT 0x5
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__SHIFT 0x6
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK 0x00000001L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK 0x00000002L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS_MASK 0x00000004L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS_MASK 0x00000008L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS_MASK 0x00000010L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS_MASK 0x00000020L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS_MASK 0x00000040L
+//BIF_POWER_INTR_STS
+#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT 0x0
+#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT 0x10
+#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK 0x00000001L
+#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK 0x00010000L
+//BIF_PF_DSTATE_INTR_STS
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT 0x0
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT 0x1
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT 0x2
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT 0x3
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT 0x4
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT 0x5
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT 0x6
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT 0x7
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK 0x00000001L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK 0x00000002L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK 0x00000004L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK 0x00000008L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK 0x00000010L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK 0x00000020L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK 0x00000040L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK 0x00000080L
+//SELF_SOFT_RST_2
+#define SELF_SOFT_RST_2__DSPT3_CFG_RST__SHIFT 0x0
+#define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST__SHIFT 0x1
+#define SELF_SOFT_RST_2__DSPT3_PRV_RST__SHIFT 0x2
+#define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST__SHIFT 0x3
+#define SELF_SOFT_RST_2__EP3_CFG_RST__SHIFT 0x4
+#define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST__SHIFT 0x5
+#define SELF_SOFT_RST_2__EP3_PRV_RST__SHIFT 0x6
+#define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST__SHIFT 0x7
+#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST__SHIFT 0x18
+#define SELF_SOFT_RST_2__STRAP_RST__SHIFT 0x19
+#define SELF_SOFT_RST_2__SWUS_SHADOW_PRV_RST__SHIFT 0x1a
+#define SELF_SOFT_RST_2__NBIF_S5_RST__SHIFT 0x1e
+#define SELF_SOFT_RST_2__NBIF_S5_CDC_RST__SHIFT 0x1f
+#define SELF_SOFT_RST_2__DSPT3_CFG_RST_MASK 0x00000001L
+#define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST_MASK 0x00000002L
+#define SELF_SOFT_RST_2__DSPT3_PRV_RST_MASK 0x00000004L
+#define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST_MASK 0x00000008L
+#define SELF_SOFT_RST_2__EP3_CFG_RST_MASK 0x00000010L
+#define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST_MASK 0x00000020L
+#define SELF_SOFT_RST_2__EP3_PRV_RST_MASK 0x00000040L
+#define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST_MASK 0x00000080L
+#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST_MASK 0x01000000L
+#define SELF_SOFT_RST_2__STRAP_RST_MASK 0x02000000L
+#define SELF_SOFT_RST_2__SWUS_SHADOW_PRV_RST_MASK 0x04000000L
+#define SELF_SOFT_RST_2__NBIF_S5_RST_MASK 0x40000000L
+#define SELF_SOFT_RST_2__NBIF_S5_CDC_RST_MASK 0x80000000L
+//BIF_INST_RESET_INTR_MASK
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT 0x0
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x1
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT 0x2
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT 0x3
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT 0x4
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK 0x00000001L
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000002L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK 0x00000004L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK 0x00000008L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK 0x00000010L
+//BIF_PF_FLR_INTR_MASK
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT 0x0
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT 0x1
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT 0x2
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT 0x3
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__SHIFT 0x4
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__SHIFT 0x5
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__SHIFT 0x6
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK 0x00000001L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK 0x00000002L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK_MASK 0x00000004L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK_MASK 0x00000008L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK_MASK 0x00000010L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK_MASK 0x00000020L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK_MASK 0x00000040L
+//BIF_D3HOTD0_INTR_MASK
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT 0x0
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT 0x1
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT 0x2
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT 0x3
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__SHIFT 0x4
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__SHIFT 0x5
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__SHIFT 0x6
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK 0x00000001L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK 0x00000002L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK_MASK 0x00000004L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK_MASK 0x00000008L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK_MASK 0x00000010L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK_MASK 0x00000020L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK_MASK 0x00000040L
+//BIF_POWER_INTR_MASK
+#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT 0x0
+#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT 0x10
+#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK 0x00000001L
+#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK 0x00010000L
+//BIF_PF_DSTATE_INTR_MASK
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT 0x0
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT 0x1
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT 0x2
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT 0x3
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT 0x4
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT 0x5
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT 0x6
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT 0x7
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK 0x00000001L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK 0x00000002L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK 0x00000004L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK 0x00000008L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK 0x00000010L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK 0x00000020L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK 0x00000040L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK 0x00000080L
+//BIF_PF_FLR_RST
+#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0
+#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1
+#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2
+#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3
+#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x4
+#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x5
+#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x6
+#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L
+#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L
+#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK 0x00000004L
+#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK 0x00000008L
+#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK 0x00000010L
+#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK 0x00000020L
+#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK 0x00000040L
+//BIF_DEV0_PF0_DSTATE_VALUE
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF1_DSTATE_VALUE
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF2_DSTATE_VALUE
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF3_DSTATE_VALUE
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF4_DSTATE_VALUE
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF5_DSTATE_VALUE
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF6_DSTATE_VALUE
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE_MASK 0x00030000L
+//DEV0_PF0_D3HOTD0_RST_CTRL
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF1_D3HOTD0_RST_CTRL
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF2_D3HOTD0_RST_CTRL
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF3_D3HOTD0_RST_CTRL
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF4_D3HOTD0_RST_CTRL
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF5_D3HOTD0_RST_CTRL
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF6_D3HOTD0_RST_CTRL
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//BIF_PORT0_DSTATE_VALUE
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_USB_SHUB_RS_RESET_CNTL
+#define BIF_USB_SHUB_RS_RESET_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define BIF_USB_SHUB_RS_RESET_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define BIF_USB_SHUB_RS_RESET_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define BIF_USB_SHUB_RS_RESET_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_misc_bif_misc_regblk
+//REGS_ROM_OFFSET_CTRL
+#define REGS_ROM_OFFSET_CTRL__ROM_OFFSET__SHIFT 0x0
+#define REGS_ROM_OFFSET_CTRL__ROM_OFFSET_MASK 0x7FL
+//NBIF_STRAP_BIOS_CNTL
+#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN__SHIFT 0x0
+#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN__SHIFT 0x1
+#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN_MASK 0x00000001L
+#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN_MASK 0x00000002L
+//MISC_SCRATCH
+#define MISC_SCRATCH__MISC_SCRATCH0__SHIFT 0x0
+#define MISC_SCRATCH__MISC_SCRATCH0_MASK 0xFFFFFFFFL
+//INTR_LINE_POLARITY
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT 0x0
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK 0x000000FFL
+//INTR_LINE_ENABLE
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT 0x0
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK 0x000000FFL
+//OUTSTANDING_VC_ALLOC
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT 0x0
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT 0x2
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT 0x4
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT 0x6
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT 0x8
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT 0xa
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT 0xc
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT 0xe
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT 0x10
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT 0x18
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT 0x1a
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT 0x1c
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK 0x00000003L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK 0x0000000CL
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK 0x00000030L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK 0x000000C0L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK 0x00000300L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK 0x00000C00L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK 0x00003000L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK 0x0000C000L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK 0x000F0000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK 0x03000000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK 0x0C000000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK 0xF0000000L
+//BIFC_MISC_CTRL0
+#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT 0x0
+#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT 0x1
+#define BIFC_MISC_CTRL0__REG_ACTIVE_VLINK_L0_EN__SHIFT 0x3
+#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS__SHIFT 0x4
+#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT 0x8
+#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P__SHIFT 0x9
+#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT 0xa
+#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT 0xb
+#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT 0xc
+#define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS__SHIFT 0xd
+#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP__SHIFT 0xe
+#define BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE__SHIFT 0xf
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT 0x10
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT 0x11
+#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT 0x12
+#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT 0x13
+#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT 0x14
+#define BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN__SHIFT 0x15
+#define BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN__SHIFT 0x16
+#define BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST__SHIFT 0x17
+#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT 0x18
+#define BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST__SHIFT 0x19
+#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT 0x1a
+#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT 0x1b
+#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT 0x1c
+#define BIFC_MISC_CTRL0__DMA_ALL_RST_PROTECT_STS_SEL__SHIFT 0x1d
+#define BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST__SHIFT 0x1e
+#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT 0x1f
+#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN_MASK 0x00000001L
+#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN_MASK 0x00000006L
+#define BIFC_MISC_CTRL0__REG_ACTIVE_VLINK_L0_EN_MASK 0x00000008L
+#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS_MASK 0x000000F0L
+#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK 0x00000100L
+#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P_MASK 0x00000200L
+#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK_MASK 0x00000400L
+#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK 0x00000800L
+#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK 0x00001000L
+#define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS_MASK 0x00002000L
+#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP_MASK 0x00004000L
+#define BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE_MASK 0x00008000L
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK 0x00010000L
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK 0x00020000L
+#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK 0x00040000L
+#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK 0x00080000L
+#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK 0x00100000L
+#define BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN_MASK 0x00200000L
+#define BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN_MASK 0x00400000L
+#define BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST_MASK 0x00800000L
+#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK 0x01000000L
+#define BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST_MASK 0x02000000L
+#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK 0x04000000L
+#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK 0x08000000L
+#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK 0x10000000L
+#define BIFC_MISC_CTRL0__DMA_ALL_RST_PROTECT_STS_SEL_MASK 0x20000000L
+#define BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST_MASK 0x40000000L
+#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK 0x80000000L
+//BIFC_MISC_CTRL1
+#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT 0x0
+#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT 0x1
+#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT 0x2
+#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT 0x3
+#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT 0x4
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT 0x5
+#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT 0x6
+#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP__SHIFT 0x7
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT 0x8
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT 0xa
+#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT 0xc
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT 0xd
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT 0xe
+#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT 0xf
+#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT 0x10
+#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT 0x11
+#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT 0x12
+#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT 0x13
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT 0x14
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE__SHIFT 0x15
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE__SHIFT 0x16
+#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG__SHIFT 0x17
+#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT 0x18
+#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT 0x19
+#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT 0x1a
+#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT 0x1b
+#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT 0x1c
+#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN__SHIFT 0x1d
+#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT 0x1e
+#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK 0x00000001L
+#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK 0x00000002L
+#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK 0x00000004L
+#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK 0x00000008L
+#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK 0x00000010L
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK 0x00000020L
+#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK 0x00000040L
+#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP_MASK 0x00000080L
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK 0x00000300L
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK 0x00000C00L
+#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK 0x00001000L
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK 0x00002000L
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK 0x00004000L
+#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK 0x00008000L
+#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK 0x00010000L
+#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK 0x00020000L
+#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK 0x00040000L
+#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK 0x00080000L
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK 0x00100000L
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_MASK 0x00200000L
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE_MASK 0x00400000L
+#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG_MASK 0x00800000L
+#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK 0x01000000L
+#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK 0x02000000L
+#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK 0x04000000L
+#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK 0x08000000L
+#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK 0x10000000L
+#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN_MASK 0x20000000L
+#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK 0xC0000000L
+//BIFC_BME_ERR_LOG_LB
+#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x0
+#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x1
+#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x2
+#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x3
+#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x4
+#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x5
+#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x6
+#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x10
+#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x11
+#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x12
+#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x13
+#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x14
+#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x15
+#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x16
+#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0_MASK 0x00000001L
+#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1_MASK 0x00000002L
+#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F2_MASK 0x00000004L
+#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F3_MASK 0x00000008L
+#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F4_MASK 0x00000010L
+#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F5_MASK 0x00000020L
+#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F6_MASK 0x00000040L
+#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK 0x00010000L
+#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1_MASK 0x00020000L
+#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F2_MASK 0x00040000L
+#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F3_MASK 0x00080000L
+#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F4_MASK 0x00100000L
+#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F5_MASK 0x00200000L
+#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F6_MASK 0x00400000L
+//BIFC_LC_TIMER_CTRL
+#define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE__SHIFT 0x0
+#define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE__SHIFT 0x10
+#define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE_MASK 0x0000FFFFL
+#define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE_MASK 0xFFFF0000L
+//BIFC_RCCBIH_BME_ERR_LOG0
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x0
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x1
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x2
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x3
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x4
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x5
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x6
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x10
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x11
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x12
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x13
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x14
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x15
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x16
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00000001L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00000002L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00000004L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00000008L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F4_MASK 0x00000010L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F5_MASK 0x00000020L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F6_MASK 0x00000040L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00010000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00020000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00040000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00080000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4_MASK 0x00100000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5_MASK 0x00200000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6_MASK 0x00400000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0__SHIFT 0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0__SHIFT 0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1__SHIFT 0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1__SHIFT 0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0_MASK 0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0_MASK 0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1_MASK 0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK 0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1_MASK 0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2__SHIFT 0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2__SHIFT 0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3__SHIFT 0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3__SHIFT 0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2_MASK 0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2_MASK 0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3_MASK 0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK 0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3_MASK 0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4__SHIFT 0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4__SHIFT 0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5__SHIFT 0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5__SHIFT 0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4_MASK 0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4_MASK 0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5_MASK 0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK 0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5_MASK 0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6__SHIFT 0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6__SHIFT 0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7__SHIFT 0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7__SHIFT 0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6_MASK 0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6_MASK 0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7_MASK 0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK 0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7_MASK 0xC0000000L
+//BIFC_DMA_ATTR_CNTL2_DEV0
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0__SHIFT 0x0
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1__SHIFT 0x4
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2__SHIFT 0x8
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3__SHIFT 0xc
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4__SHIFT 0x10
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5__SHIFT 0x14
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6__SHIFT 0x18
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7__SHIFT 0x1c
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0_MASK 0x00000001L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1_MASK 0x00000010L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2_MASK 0x00000100L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3_MASK 0x00001000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4_MASK 0x00010000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5_MASK 0x00100000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6_MASK 0x01000000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7_MASK 0x10000000L
+//BIFC_MISC_CTRL2
+#define BIFC_MISC_CTRL2__DIH_INTR_STFETCH_BLOCK_IN_LINKDOWN__SHIFT 0x0
+#define BIFC_MISC_CTRL2__SLOW_GMI_UPS_RSP_CRED_REL_EN__SHIFT 0x1
+#define BIFC_MISC_CTRL2__SLFR_IGNORE_DATAERR_EN__SHIFT 0x10
+#define BIFC_MISC_CTRL2__DATAERR_OVERRIDE_SLFR_BYTEEN_EN__SHIFT 0x11
+#define BIFC_MISC_CTRL2__PH_SUPPORT__SHIFT 0x12
+#define BIFC_MISC_CTRL2__GMI_FAIL_REQ_RTS_MASK__SHIFT 0x16
+#define BIFC_MISC_CTRL2__NBIF_AERRPT_BACKPERSURE_EN__SHIFT 0x17
+#define BIFC_MISC_CTRL2__DIH_INTR_STFETCH_BLOCK_IN_LINKDOWN_MASK 0x00000001L
+#define BIFC_MISC_CTRL2__SLOW_GMI_UPS_RSP_CRED_REL_EN_MASK 0x00000002L
+#define BIFC_MISC_CTRL2__SLFR_IGNORE_DATAERR_EN_MASK 0x00010000L
+#define BIFC_MISC_CTRL2__DATAERR_OVERRIDE_SLFR_BYTEEN_EN_MASK 0x00020000L
+#define BIFC_MISC_CTRL2__PH_SUPPORT_MASK 0x003C0000L
+#define BIFC_MISC_CTRL2__GMI_FAIL_REQ_RTS_MASK_MASK 0x00400000L
+#define BIFC_MISC_CTRL2__NBIF_AERRPT_BACKPERSURE_EN_MASK 0x00800000L
+//BME_DUMMY_CNTL_0
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT 0x0
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT 0x2
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT 0x4
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT 0x6
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT 0x8
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT 0xa
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT 0xc
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT 0xe
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK 0x00000003L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK 0x0000000CL
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK 0x00000030L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK 0x000000C0L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK 0x00000300L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK 0x00000C00L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK 0x00003000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK 0x0000C000L
+//BIFC_THT_CNTL
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT 0x0
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT 0x4
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT 0x8
+#define BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x10
+#define BIFC_THT_CNTL__THT_NTB_VC0_APER0_ADSC_PUSH_DIS__SHIFT 0x18
+#define BIFC_THT_CNTL__THT_NTB_VC0_OTHAPER_ADSC_PUSH_DIS__SHIFT 0x19
+#define BIFC_THT_CNTL__THT_NTB_VC1_APER0_ADSC_PUSH_DIS__SHIFT 0x1a
+#define BIFC_THT_CNTL__THT_NTB_VC1_OTHAPER_ADSC_PUSH_DIS__SHIFT 0x1b
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0_MASK 0x0000000FL
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0_MASK 0x000000F0L
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1_MASK 0x00000F00L
+#define BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN_MASK 0x00010000L
+#define BIFC_THT_CNTL__THT_NTB_VC0_APER0_ADSC_PUSH_DIS_MASK 0x01000000L
+#define BIFC_THT_CNTL__THT_NTB_VC0_OTHAPER_ADSC_PUSH_DIS_MASK 0x02000000L
+#define BIFC_THT_CNTL__THT_NTB_VC1_APER0_ADSC_PUSH_DIS_MASK 0x04000000L
+#define BIFC_THT_CNTL__THT_NTB_VC1_OTHAPER_ADSC_PUSH_DIS_MASK 0x08000000L
+//BIFC_HSTARB_CNTL
+#define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT 0x0
+#define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN__SHIFT 0x8
+#define BIFC_HSTARB_CNTL__SLVARB_MODE_MASK 0x00000003L
+#define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN_MASK 0x00000100L
+//BIFC_GSI_CNTL
+#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT 0x0
+#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT 0x2
+#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT 0x6
+#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT 0x7
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT 0x8
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT 0x9
+#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT 0xa
+#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT 0xb
+#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT 0xd
+#define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN__SHIFT 0xf
+#define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK__SHIFT 0x10
+#define BIFC_GSI_CNTL__GSI_SMN_BURST_EN__SHIFT 0x11
+#define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN__SHIFT 0x12
+#define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE__SHIFT 0x1b
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH__SHIFT 0x1c
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH__SHIFT 0x1d
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD__SHIFT 0x1e
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL__SHIFT 0x1f
+#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK 0x00000003L
+#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK 0x0000003CL
+#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK 0x00000040L
+#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK 0x00000080L
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK 0x00000100L
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK 0x00000200L
+#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN_MASK 0x00000400L
+#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK 0x00001800L
+#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK 0x00006000L
+#define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN_MASK 0x00008000L
+#define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK_MASK 0x00010000L
+#define BIFC_GSI_CNTL__GSI_SMN_BURST_EN_MASK 0x00020000L
+#define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN_MASK 0x00040000L
+#define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE_MASK 0x08000000L
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH_MASK 0x10000000L
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH_MASK 0x20000000L
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD_MASK 0x40000000L
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL_MASK 0x80000000L
+//BIFC_PCIEFUNC_CNTL
+#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT 0x0
+#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT 0x10
+#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK 0x0000FFFFL
+#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_MASK 0x00010000L
+//BIFC_PASID_CHECK_DIS
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0__SHIFT 0x0
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1__SHIFT 0x1
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2__SHIFT 0x2
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3__SHIFT 0x3
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F4__SHIFT 0x4
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F5__SHIFT 0x5
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F6__SHIFT 0x6
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0_MASK 0x00000001L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1_MASK 0x00000002L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2_MASK 0x00000004L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3_MASK 0x00000008L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F4_MASK 0x00000010L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F5_MASK 0x00000020L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F6_MASK 0x00000040L
+//BIFC_SDP_CNTL_0
+#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT 0x0
+#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT 0x8
+#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT 0x10
+#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT 0x18
+#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK 0x000000FFL
+#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK 0x0000FF00L
+#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK 0x00FF0000L
+#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK 0xFF000000L
+//BIFC_SDP_CNTL_1
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT 0x0
+#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT 0x1
+#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT 0x2
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT 0x3
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x4
+#define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P__SHIFT 0x5
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x7
+#define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN__SHIFT 0x8
+#define BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x9
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK 0x00000001L
+#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK 0x00000002L
+#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK 0x00000004L
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK 0x00000008L
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000010L
+#define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P_MASK 0x00000020L
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000080L
+#define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN_MASK 0x00000100L
+#define BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00000200L
+//BIFC_PASID_STS
+#define BIFC_PASID_STS__PASID_STS__SHIFT 0x0
+#define BIFC_PASID_STS__PASID_STS_MASK 0x0000000FL
+//BIFC_ATHUB_ACT_CNTL
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE__SHIFT 0x0
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE__SHIFT 0x3
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS__SHIFT 0x8
+#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT 0x9
+#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT 0xa
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN__SHIFT 0xb
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE_MASK 0x00000007L
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE_MASK 0x00000038L
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS_MASK 0x00000100L
+#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER_MASK 0x00000200L
+#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER_MASK 0x00000400L
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN_MASK 0x00000800L
+//BIFC_PERF_CNTL_0
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT 0x0
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT 0x1
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT 0x8
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT 0x9
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT 0x10
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT 0x18
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK 0x00000001L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK 0x00000002L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK 0x00000100L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK 0x00000200L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK 0x007F0000L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK 0x7F000000L
+//BIFC_PERF_CNTL_1
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT 0x0
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT 0x1
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT 0x4
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT 0x5
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT 0x8
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT 0x10
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK 0x00000001L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK 0x00000002L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK 0x00000010L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK 0x00000020L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK 0x0000FF00L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK 0x01FF0000L
+//BIFC_PERF_CNT_MMIO_RD_L32BIT
+#define BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT__SHIFT 0x0
+#define BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT_MASK 0xFFFFFFFFL
+//BIFC_PERF_CNT_MMIO_WR_L32BIT
+#define BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT__SHIFT 0x0
+#define BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT_MASK 0xFFFFFFFFL
+//BIFC_PERF_CNT_DMA_RD_L32BIT
+#define BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT__SHIFT 0x0
+#define BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT_MASK 0xFFFFFFFFL
+//BIFC_PERF_CNT_DMA_WR_L32BIT
+#define BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT__SHIFT 0x0
+#define BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT_MASK 0xFFFFFFFFL
+//NBIF_REGIF_ERRSET_CTRL
+#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0
+#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L
+//BIFC_SDP_CNTL_2
+#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS__SHIFT 0x0
+#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H__SHIFT 0x8
+#define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H__SHIFT 0x10
+#define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H__SHIFT 0x18
+#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_MASK 0x000000FFL
+#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H_MASK 0x00000F00L
+#define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H_MASK 0x000F0000L
+#define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H_MASK 0x0F000000L
+//NBIF_PGMST_CTRL
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS__SHIFT 0x0
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN__SHIFT 0x8
+#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN__SHIFT 0xa
+#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN__SHIFT 0xe
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS_MASK 0x000000FFL
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN_MASK 0x00000100L
+#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L
+#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L
+//NBIF_PGSLV_CTRL
+#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS__SHIFT 0x0
+#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS_MASK 0x0000001FL
+//NBIF_PG_MISC_CTRL
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5
+#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY__SHIFT 0xa
+#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1__SHIFT 0xd
+#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS__SHIFT 0xe
+#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2__SHIFT 0x10
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18
+#define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK__SHIFT 0x1e
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY_MASK 0x00000400L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1_MASK 0x00002000L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS_MASK 0x00004000L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2_MASK 0x00010000L
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK_MASK 0x40000000L
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L
+//SMN_MST_EP_CNTL3
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK 0x00000080L
+//SMN_MST_EP_CNTL4
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK 0x00000080L
+//SMN_MST_CNTL1
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT 0x0
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT 0x10
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK 0x00000001L
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK 0x00010000L
+//SMN_MST_EP_CNTL5
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK 0x00000080L
+//BIF_SELFRING_BUFFER_VID
+#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT 0x0
+#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID__SHIFT 0x8
+#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID__SHIFT 0x10
+#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK 0x000000FFL
+#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID_MASK 0x0000FF00L
+#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID_MASK 0x00FF0000L
+//BIF_SELFRING_VECTOR_CNTL
+#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT 0x0
+#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT 0x1
+#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK 0x00000001L
+#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK 0x00000002L
+//NBIF_STRAP_WRITE_CTRL
+#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT 0x0
+#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE_MASK 0x00000001L
+//NBIF_INTX_DSTATE_MISC_CNTL
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x0
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x1
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x2
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x3
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x4
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP__SHIFT 0x5
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN__SHIFT 0x6
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x7
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00000001L
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00000002L
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00000004L
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00000008L
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00000010L
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP_MASK 0x00000020L
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN_MASK 0x00000040L
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000080L
+//NBIF_PENDING_MISC_CNTL
+#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS__SHIFT 0x0
+#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS__SHIFT 0x1
+#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS_MASK 0x00000001L
+#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS_MASK 0x00000002L
+//BIF_GMI_WRR_WEIGHT
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE__SHIFT 0x1d
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE__SHIFT 0x1e
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE__SHIFT 0x1f
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE_MASK 0x20000000L
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE_MASK 0x40000000L
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE_MASK 0x80000000L
+//BIF_GMI_WRR_WEIGHT2
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT__SHIFT 0x0
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT__SHIFT 0x8
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT__SHIFT 0x10
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT__SHIFT 0x18
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT_MASK 0x000000FFL
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT_MASK 0x0000FF00L
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT_MASK 0x00FF0000L
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT_MASK 0xFF000000L
+//BIF_GMI_WRR_WEIGHT3
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT__SHIFT 0x0
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT__SHIFT 0x8
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT__SHIFT 0x10
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT__SHIFT 0x18
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT_MASK 0x000000FFL
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT_MASK 0x0000FF00L
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT_MASK 0x00FF0000L
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT_MASK 0xFF000000L
+//NBIF_PWRBRK_REQUEST
+#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST__SHIFT 0x0
+#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST_MASK 0x00000001L
+//BIF_ATOMIC_ERR_LOG_DEV0_F0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_OPCODE_DEV0_F2__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_REQEN_LOW_DEV0_F2__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_LENGTH_DEV0_F2__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_NR_DEV0_F2__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F2__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F2__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F2__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_NR_DEV0_F2__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_OPCODE_DEV0_F2_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_REQEN_LOW_DEV0_F2_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_LENGTH_DEV0_F2_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_NR_DEV0_F2_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F2_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F2_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F2_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_NR_DEV0_F2_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_OPCODE_DEV0_F3__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_REQEN_LOW_DEV0_F3__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_LENGTH_DEV0_F3__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_NR_DEV0_F3__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F3__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F3__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F3__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_NR_DEV0_F3__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_OPCODE_DEV0_F3_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_REQEN_LOW_DEV0_F3_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_LENGTH_DEV0_F3_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_NR_DEV0_F3_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F3_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F3_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F3_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_NR_DEV0_F3_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F4
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_OPCODE_DEV0_F4__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_REQEN_LOW_DEV0_F4__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_LENGTH_DEV0_F4__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_NR_DEV0_F4__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_OPCODE_DEV0_F4__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F4__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_LENGTH_DEV0_F4__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_NR_DEV0_F4__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_OPCODE_DEV0_F4_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_REQEN_LOW_DEV0_F4_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_LENGTH_DEV0_F4_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_NR_DEV0_F4_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_OPCODE_DEV0_F4_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F4_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_LENGTH_DEV0_F4_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_NR_DEV0_F4_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F5
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_OPCODE_DEV0_F5__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_REQEN_LOW_DEV0_F5__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_LENGTH_DEV0_F5__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_NR_DEV0_F5__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_OPCODE_DEV0_F5__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F5__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_LENGTH_DEV0_F5__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_NR_DEV0_F5__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_OPCODE_DEV0_F5_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_REQEN_LOW_DEV0_F5_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_LENGTH_DEV0_F5_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_NR_DEV0_F5_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_OPCODE_DEV0_F5_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F5_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_LENGTH_DEV0_F5_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_NR_DEV0_F5_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F6
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_OPCODE_DEV0_F6__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_REQEN_LOW_DEV0_F6__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_LENGTH_DEV0_F6__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_NR_DEV0_F6__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_OPCODE_DEV0_F6__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F6__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_LENGTH_DEV0_F6__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_NR_DEV0_F6__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_OPCODE_DEV0_F6_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_REQEN_LOW_DEV0_F6_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_LENGTH_DEV0_F6_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_NR_DEV0_F6_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_OPCODE_DEV0_F6_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F6_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_LENGTH_DEV0_F6_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_NR_DEV0_F6_MASK 0x00080000L
+//BIF_DMA_MP4_ERR_LOG
+#define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR__SHIFT 0x0
+#define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT 0x1
+#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR__SHIFT 0x10
+#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT 0x11
+#define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR_MASK 0x00000001L
+#define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK 0x00000002L
+#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR_MASK 0x00010000L
+#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK 0x00020000L
+//BIF_PASID_ERR_LOG
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0__SHIFT 0x0
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1__SHIFT 0x1
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F2__SHIFT 0x2
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F3__SHIFT 0x3
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F4__SHIFT 0x4
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F5__SHIFT 0x5
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F6__SHIFT 0x6
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0_MASK 0x00000001L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1_MASK 0x00000002L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F2_MASK 0x00000004L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F3_MASK 0x00000008L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F4_MASK 0x00000010L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F5_MASK 0x00000020L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F6_MASK 0x00000040L
+//BIF_PASID_ERR_CLR
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0__SHIFT 0x0
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1__SHIFT 0x1
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2__SHIFT 0x2
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3__SHIFT 0x3
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F4__SHIFT 0x4
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F5__SHIFT 0x5
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F6__SHIFT 0x6
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0_MASK 0x00000001L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1_MASK 0x00000002L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2_MASK 0x00000004L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3_MASK 0x00000008L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F4_MASK 0x00000010L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F5_MASK 0x00000020L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F6_MASK 0x00000040L
+//NBIF_VWIRE_CTRL
+#define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS__SHIFT 0x0
+#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT 0x4
+#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT 0x8
+#define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS__SHIFT 0x10
+#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT 0x14
+#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT 0x1a
+#define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS_MASK 0x00000001L
+#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK 0x000000F0L
+#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK 0x00000100L
+#define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS_MASK 0x00010000L
+#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK 0x00F00000L
+#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK 0x0C000000L
+//NBIF_SMN_VWR_VCHG_DIS_CTRL
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT 0x3
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT 0x4
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT 0x5
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT 0x6
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS__SHIFT 0x7
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS__SHIFT 0x8
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS__SHIFT 0x9
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS_MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS_MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS_MASK 0x00000004L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS_MASK 0x00000008L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS_MASK 0x00000010L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS_MASK 0x00000020L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS_MASK 0x00000040L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS_MASK 0x00000080L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS_MASK 0x00000100L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS_MASK 0x00000200L
+//NBIF_SMN_VWR_VCHG_RST_CTRL0
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT 0x3
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT 0x4
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT 0x5
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT 0x6
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV__SHIFT 0x7
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV__SHIFT 0x8
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV__SHIFT 0x9
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV_MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV_MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV_MASK 0x00000004L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV_MASK 0x00000008L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV_MASK 0x00000010L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV_MASK 0x00000020L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV_MASK 0x00000040L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV_MASK 0x00000080L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV_MASK 0x00000100L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV_MASK 0x00000200L
+//NBIF_SMN_VWR_VCHG_TRIG
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT 0x3
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT 0x4
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT 0x5
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT 0x6
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG__SHIFT 0x7
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG__SHIFT 0x8
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG__SHIFT 0x9
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG_MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG_MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG_MASK 0x00000004L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG_MASK 0x00000008L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG_MASK 0x00000010L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG_MASK 0x00000020L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG_MASK 0x00000040L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG_MASK 0x00000080L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG_MASK 0x00000100L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG_MASK 0x00000200L
+//NBIF_SMN_VWR_WTRIG_CNTL
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT 0x0
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT 0x1
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT 0x2
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT 0x3
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT 0x4
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT 0x5
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT 0x6
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS__SHIFT 0x7
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS__SHIFT 0x8
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS__SHIFT 0x9
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS_MASK 0x00000001L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS_MASK 0x00000002L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS_MASK 0x00000004L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS_MASK 0x00000008L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS_MASK 0x00000010L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS_MASK 0x00000020L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS_MASK 0x00000040L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS_MASK 0x00000080L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS_MASK 0x00000100L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS_MASK 0x00000200L
+//NBIF_SMN_VWR_VCHG_DIS_CTRL_1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT 0x3
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT 0x4
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT 0x5
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT 0x6
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV__SHIFT 0x7
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV__SHIFT 0x8
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV__SHIFT 0x9
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV_MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV_MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV_MASK 0x00000004L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV_MASK 0x00000008L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV_MASK 0x00000010L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV_MASK 0x00000020L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV_MASK 0x00000040L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV_MASK 0x00000080L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV_MASK 0x00000100L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV_MASK 0x00000200L
+//NBIF_MGCG_CTRL_LCLK
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT 0x0
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT 0x1
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT 0x2
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT 0xa
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT 0xb
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK__SHIFT 0xc
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT 0xd
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DBG_DIS_LCLK__SHIFT 0xe
+#define NBIF_MGCG_CTRL_LCLK__NBIF_SRAM_FGCG_EN_LCLK__SHIFT 0xf
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK 0x00000001L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK 0x00000002L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK 0x000003FCL
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK 0x00000400L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK 0x00000800L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK 0x00001000L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK 0x00002000L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DBG_DIS_LCLK_MASK 0x00004000L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_SRAM_FGCG_EN_LCLK_MASK 0x00008000L
+//NBIF_DS_CTRL_LCLK
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT 0x0
+#define NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1
+#define NBIF_DS_CTRL_LCLK__USB_LCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT 0x10
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK 0x00000001L
+#define NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L
+#define NBIF_DS_CTRL_LCLK__USB_LCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK 0xFFFF0000L
+//SMN_MST_CNTL0
+#define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT 0x0
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT 0x8
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT 0x9
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT 0xa
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT 0xb
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT 0x10
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT 0x14
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT 0x18
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT 0x1c
+#define SMN_MST_CNTL0__SMN_ARB_MODE_MASK 0x00000003L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK 0x00000100L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK 0x00000200L
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK 0x00000400L
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK 0x00000800L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK 0x00010000L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK 0x00100000L
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK 0x01000000L
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK 0x10000000L
+//SMN_MST_EP_CNTL1
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK 0x00000080L
+//SMN_MST_EP_CNTL2
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK 0x00000080L
+//NBIF_SDP_VWR_VCHG_DIS_CTRL
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT 0x18
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK 0x01000000L
+//NBIF_SDP_VWR_VCHG_RST_CTRL0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT 0x18
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK 0x01000000L
+//NBIF_SDP_VWR_VCHG_RST_CTRL1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT 0x18
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK 0x01000000L
+//NBIF_SDP_VWR_VCHG_TRIG
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT 0x18
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK 0x01000000L
+//NBIF_SHUB_TODET_CTRL
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN__SHIFT 0x0
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN__SHIFT 0x1
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT__SHIFT 0x8
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT__SHIFT 0x10
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN_MASK 0x00000001L
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN_MASK 0x00000002L
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT_MASK 0x00000700L
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT_MASK 0xFFFF0000L
+//NBIF_SHUB_TODET_CLIENT_CTRL
+#define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN__SHIFT 0x0
+#define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN_MASK 0xFFFFFFFFL
+//NBIF_SHUB_TODET_CLIENT_STATUS
+#define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS__SHIFT 0x0
+#define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS_MASK 0xFFFFFFFFL
+//NBIF_SHUB_TODET_SYNCFLOOD_CTRL
+#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN__SHIFT 0x0
+#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN_MASK 0xFFFFFFFFL
+//NBIF_SHUB_TODET_CLIENT_CTRL2
+#define NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2__SHIFT 0x0
+#define NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2_MASK 0xFFFFFFFFL
+//NBIF_SHUB_TODET_CLIENT_STATUS2
+#define NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2__SHIFT 0x0
+#define NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2_MASK 0xFFFFFFFFL
+//NBIF_SHUB_TODET_SYNCFLOOD_CTRL2
+#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2__SHIFT 0x0
+#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2_MASK 0xFFFFFFFFL
+//BIFC_BME_ERR_LOG_HB
+//BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC
+#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0
+#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4
+#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL
+#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L
+//BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC
+#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0
+#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4
+#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL
+#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L
+//BIFC_GMI_SDP_REQ_POOLCRED_ALLOC
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L
+//BIFC_GMI_SDP_DAT_POOLCRED_ALLOC
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L
+//BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L
+//BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L
+//DISCON_HYSTERESIS_HEAD_CTRL
+#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H__SHIFT 0x0
+#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H__SHIFT 0x8
+#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H_MASK 0x0000000FL
+#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H_MASK 0x00000F00L
+//BIFC_EARLY_WAKEUP_CNTL
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0x0
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0x1
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0x2
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000001L
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00000002L
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00000004L
+//BIFC_PERF_CNT_MMIO_RD_H16BIT
+#define BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT__SHIFT 0x0
+#define BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT_MASK 0x0000FFFFL
+//BIFC_PERF_CNT_MMIO_WR_H16BIT
+#define BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT__SHIFT 0x0
+#define BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT_MASK 0x0000FFFFL
+//BIFC_PERF_CNT_DMA_RD_H16BIT
+#define BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT__SHIFT 0x0
+#define BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT_MASK 0x0000FFFFL
+//BIFC_PERF_CNT_DMA_WR_H16BIT
+#define BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT__SHIFT 0x0
+#define BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT_MASK 0x0000FFFFL
+//NBIF_PERF_COM_COUNT_ENABLE
+#define NBIF_PERF_COM_COUNT_ENABLE__NBIF_COM_COUNT_ENABLE__SHIFT 0x0
+#define NBIF_PERF_COM_COUNT_ENABLE__START_COUNT_NOPULS__SHIFT 0x3
+#define NBIF_PERF_COM_COUNT_ENABLE__LEGACY_OUT_REALTIME_SEL__SHIFT 0x4
+#define NBIF_PERF_COM_COUNT_ENABLE__NBIF_COM_COUNT_ENABLE_MASK 0x00000001L
+#define NBIF_PERF_COM_COUNT_ENABLE__START_COUNT_NOPULS_MASK 0x00000008L
+#define NBIF_PERF_COM_COUNT_ENABLE__LEGACY_OUT_REALTIME_SEL_MASK 0x00000010L
+//NBIF_BX_PERF_CNT_FSM
+#define NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_SHADOW_TGL_DELAY_COUNT__SHIFT 0x0
+#define NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_COUNT__SHIFT 0x4
+#define NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_EN__SHIFT 0x8
+#define NBIF_BX_PERF_CNT_FSM__BX_PRE_FLD_GLOBAL_SHADOW_WR__SHIFT 0x9
+#define NBIF_BX_PERF_CNT_FSM__BX_PERF_CNT_DONE__SHIFT 0xa
+#define NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_SHADOW_TGL_DELAY_COUNT_MASK 0x0000000FL
+#define NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_COUNT_MASK 0x000000F0L
+#define NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_EN_MASK 0x00000100L
+#define NBIF_BX_PERF_CNT_FSM__BX_PRE_FLD_GLOBAL_SHADOW_WR_MASK 0x00000200L
+#define NBIF_BX_PERF_CNT_FSM__BX_PERF_CNT_DONE_MASK 0x00000400L
+//NBIF_COM_COUNT_VALUE
+#define NBIF_COM_COUNT_VALUE__NBIF_COM_COUNT_VALUE__SHIFT 0x0
+#define NBIF_COM_COUNT_VALUE__NBIF_COM_COUNT_VALUE_MASK 0xFFFFFFFFL
+//BIFC_A2S_SDP_PORT_CTRL
+#define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0
+#define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H__SHIFT 0x8
+#define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_DIS__SHIFT 0xc
+#define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x000000FFL
+#define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H_MASK 0x00000F00L
+#define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_DIS_MASK 0x00001000L
+//BIFC_A2S_CNTL_SW0
+#define BIFC_A2S_CNTL_SW0__RDRSP_ERRMAP__SHIFT 0x0
+#define BIFC_A2S_CNTL_SW0__RDRSP_SEL_MODE__SHIFT 0x2
+#define BIFC_A2S_CNTL_SW0__STATIC_VC_ENABLE__SHIFT 0x5
+#define BIFC_A2S_CNTL_SW0__STATIC_VC_VALUE__SHIFT 0x6
+#define BIFC_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT 0x9
+#define BIFC_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa
+#define BIFC_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb
+#define BIFC_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc
+#define BIFC_A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT 0x10
+#define BIFC_A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT 0x18
+#define BIFC_A2S_CNTL_SW0__RDRSP_ERRMAP_MASK 0x00000003L
+#define BIFC_A2S_CNTL_SW0__RDRSP_SEL_MODE_MASK 0x0000001CL
+#define BIFC_A2S_CNTL_SW0__STATIC_VC_ENABLE_MASK 0x00000020L
+#define BIFC_A2S_CNTL_SW0__STATIC_VC_VALUE_MASK 0x000001C0L
+#define BIFC_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK 0x00000200L
+#define BIFC_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L
+#define BIFC_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L
+#define BIFC_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L
+#define BIFC_A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK 0x00FF0000L
+#define BIFC_A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK 0xFF000000L
+//BIFC_A2S_MISC_CNTL
+#define BIFC_A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT 0x0
+#define BIFC_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT 0x2
+#define BIFC_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE__SHIFT 0x3
+#define BIFC_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN__SHIFT 0x4
+#define BIFC_A2S_MISC_CNTL__RSP_REORDER_DIS__SHIFT 0x5
+#define BIFC_A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT 0x6
+#define BIFC_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x7
+#define BIFC_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x8
+#define BIFC_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0x9
+#define BIFC_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0xa
+#define BIFC_A2S_MISC_CNTL__WR_TAG_SET_MIN__SHIFT 0x10
+#define BIFC_A2S_MISC_CNTL__RD_TAG_SET_MIN__SHIFT 0x15
+#define BIFC_A2S_MISC_CNTL__WRR_LRG_MODE__SHIFT 0x1a
+#define BIFC_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE__SHIFT 0x1b
+#define BIFC_A2S_MISC_CNTL__BYPASS_OVERRIDE_EN__SHIFT 0x1c
+#define BIFC_A2S_MISC_CNTL__BYPASS_OVERRIDE_VALUE__SHIFT 0x1d
+#define BIFC_A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK 0x00000003L
+#define BIFC_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS_MASK 0x00000004L
+#define BIFC_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE_MASK 0x00000008L
+#define BIFC_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN_MASK 0x00000010L
+#define BIFC_A2S_MISC_CNTL__RSP_REORDER_DIS_MASK 0x00000020L
+#define BIFC_A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK 0x00000040L
+#define BIFC_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000080L
+#define BIFC_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000100L
+#define BIFC_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY_MASK 0x00000200L
+#define BIFC_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000400L
+#define BIFC_A2S_MISC_CNTL__WR_TAG_SET_MIN_MASK 0x001F0000L
+#define BIFC_A2S_MISC_CNTL__RD_TAG_SET_MIN_MASK 0x03E00000L
+#define BIFC_A2S_MISC_CNTL__WRR_LRG_MODE_MASK 0x04000000L
+#define BIFC_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE_MASK 0x08000000L
+#define BIFC_A2S_MISC_CNTL__BYPASS_OVERRIDE_EN_MASK 0x10000000L
+#define BIFC_A2S_MISC_CNTL__BYPASS_OVERRIDE_VALUE_MASK 0x20000000L
+//BIFC_A2S_TAG_ALLOC_0
+#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT 0x0
+#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT 0x8
+#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT 0x10
+#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK 0x000000FFL
+#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK 0x0000FF00L
+#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK 0x00FF0000L
+//BIFC_A2S_TAG_ALLOC_1
+#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT 0x0
+#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT 0x10
+#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT 0x18
+#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK 0x000000FFL
+#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK 0x00FF0000L
+#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK 0xFF000000L
+
+
+// addressBlock: nbif_bif_ras_bif_ras_regblk
+//BIFL_RAS_CENTRAL_CNTL
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_HST_STALL_DIS__SHIFT 0x1b
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_STALL_DIS__SHIFT 0x1c
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS__SHIFT 0x1d
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS__SHIFT 0x1e
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS__SHIFT 0x1f
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_HST_STALL_DIS_MASK 0x08000000L
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_STALL_DIS_MASK 0x10000000L
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS_MASK 0x20000000L
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS_MASK 0x40000000L
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS_MASK 0x80000000L
+//BIFL_RAS_CENTRAL_STATUS
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det__SHIFT 0x0
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det__SHIFT 0x1
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det__SHIFT 0x2
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det__SHIFT 0x3
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv__SHIFT 0x1d
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv__SHIFT 0x1e
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv__SHIFT 0x1f
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det_MASK 0x00000001L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det_MASK 0x00000002L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det_MASK 0x00000004L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det_MASK 0x00000008L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv_MASK 0x20000000L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv_MASK 0x40000000L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv_MASK 0x80000000L
+//BIFL_RAS_LEAF0_CTRL
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0
+#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3
+#define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x4
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8
+#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa
+#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10
+#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11
+#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12
+#define BIFL_RAS_LEAF0_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14
+#define BIFL_RAS_LEAF0_CTRL__UCP_EN__SHIFT 0x15
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L
+#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L
+#define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK 0x00000010L
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L
+#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L
+#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L
+#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L
+#define BIFL_RAS_LEAF0_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L
+#define BIFL_RAS_LEAF0_CTRL__UCP_EN_MASK 0x00200000L
+//BIFL_RAS_LEAF1_CTRL
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0
+#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3
+#define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x4
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8
+#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa
+#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10
+#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11
+#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12
+#define BIFL_RAS_LEAF1_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14
+#define BIFL_RAS_LEAF1_CTRL__UCP_EN__SHIFT 0x15
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L
+#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L
+#define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK 0x00000010L
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L
+#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L
+#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L
+#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L
+#define BIFL_RAS_LEAF1_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L
+#define BIFL_RAS_LEAF1_CTRL__UCP_EN_MASK 0x00200000L
+//BIFL_RAS_LEAF2_CTRL
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0
+#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3
+#define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x4
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8
+#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa
+#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10
+#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11
+#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12
+#define BIFL_RAS_LEAF2_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14
+#define BIFL_RAS_LEAF2_CTRL__UCP_EN__SHIFT 0x15
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L
+#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L
+#define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK 0x00000010L
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L
+#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L
+#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L
+#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L
+#define BIFL_RAS_LEAF2_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L
+#define BIFL_RAS_LEAF2_CTRL__UCP_EN_MASK 0x00200000L
+//BIFL_RAS_LEAF3_CTRL
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0
+#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3
+#define BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT 0x4
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8
+#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa
+#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10
+#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11
+#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12
+#define BIFL_RAS_LEAF3_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14
+#define BIFL_RAS_LEAF3_CTRL__UCP_EN__SHIFT 0x15
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L
+#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L
+#define BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN_MASK 0x00000010L
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L
+#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L
+#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L
+#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L
+#define BIFL_RAS_LEAF3_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L
+#define BIFL_RAS_LEAF3_CTRL__UCP_EN_MASK 0x00200000L
+//BIFL_RAS_LEAF0_STATUS
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV__SHIFT 0x0
+#define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET__SHIFT 0x1
+#define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET__SHIFT 0x2
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV_MASK 0x00000001L
+#define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET_MASK 0x00000002L
+#define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET_MASK 0x00000004L
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//BIFL_RAS_LEAF1_STATUS
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV__SHIFT 0x0
+#define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET__SHIFT 0x1
+#define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET__SHIFT 0x2
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV_MASK 0x00000001L
+#define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET_MASK 0x00000002L
+#define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET_MASK 0x00000004L
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//BIFL_RAS_LEAF2_STATUS
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV__SHIFT 0x0
+#define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET__SHIFT 0x1
+#define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET__SHIFT 0x2
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV_MASK 0x00000001L
+#define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET_MASK 0x00000002L
+#define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET_MASK 0x00000004L
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//BIFL_RAS_LEAF3_STATUS
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV__SHIFT 0x0
+#define BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET__SHIFT 0x1
+#define BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET__SHIFT 0x2
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV_MASK 0x00000001L
+#define BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET_MASK 0x00000002L
+#define BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET_MASK 0x00000004L
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//BIFL_IOHUB_RAS_IH_CNTL
+#define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN__SHIFT 0x0
+#define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN_MASK 0x00000001L
+//BIFL_RAS_VWR_FROM_IOHUB
+#define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG__SHIFT 0x0
+#define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG_MASK 0x00000001L
+
+
+// addressBlock: nbif_rcc_dwn_dev0_BIFDEC1
+//RCC_DWN_DEV0_2_DN_PCIE_RESERVED
+#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_2_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_2_DN_PCIE_CNTL
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+//RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8
+#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L
+//RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L
+//RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L
+//RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L
+
+
+// addressBlock: nbif_rcc_dwnp_dev0_BIFDEC1
+//RCC_DWNP_DEV0_2_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L
+//RCC_DWNP_DEV0_2_PCIE_RX_CNTL
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L
+//RCC_DWNP_DEV0_2_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
+#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L
+//RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0
+#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_ep_dev0_BIFDEC1
+//RCC_EP_DEV0_2_EP_PCIE_SCRATCH
+#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_2_EP_PCIE_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__MFIOV_GFX_F0_FLR_DIS__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__MFIOV_GFX_F0_FLR_DIS_MASK 0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_EP_DEV0_2_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L
+//RCC_EP_DEV0_2_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L
+//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+//RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+//RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L
+//RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC
+#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2
+#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
+#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L
+//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL
+//RCC_EP_DEV0_2_EP_PCIEP_RESERVED
+#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_2_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L
+//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L
+
+
+// addressBlock: nbif_rcc_dev0_BIFDEC1
+//RCC_DEV0_1_RCC_ERR_INT_CNTL
+#define RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0
+#define RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L
+//RCC_DEV0_1_RCC_BACO_CNTL_MISC
+#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0
+#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1
+#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L
+#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L
+//RCC_DEV0_1_RCC_RESET_EN
+#define RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf
+#define RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L
+//RCC_DEV0_2_RCC_VDM_SUPPORT
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L
+//RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L
+//RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L
+//RCC_DEV0_1_RCC_GPUIOV_REGION
+#define RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION__SHIFT 0x0
+#define RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION__SHIFT 0x4
+#define RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION_MASK 0x0000000FL
+#define RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION_MASK 0x000000F0L
+//RCC_DEV0_1_RCC_GPU_HOSTVM_EN
+#define RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT 0x0
+#define RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK 0x00000001L
+//RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT 0x0
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT 0x1
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK 0x00000001L
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK 0x00000002L
+//RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT 0x0
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK 0xFFFFL
+//RCC_DEV0_1_RCC_PEER_REG_RANGE0
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L
+//RCC_DEV0_1_RCC_PEER_REG_RANGE1
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L
+//RCC_DEV0_2_RCC_BUS_CNTL
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8
+#define RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc
+#define RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15
+#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18
+#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19
+#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c
+#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L
+#define RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L
+//RCC_DEV0_1_RCC_CONFIG_CNTL
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L
+//RCC_DEV0_1_RCC_CONFIG_F0_BASE
+#define RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0
+#define RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL
+//RCC_DEV0_1_RCC_CONFIG_APER_SIZE
+#define RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0
+#define RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE
+#define RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0
+#define RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x07FFFFFFL
+//RCC_DEV0_1_RCC_XDMA_LO
+#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0
+#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f
+#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL
+#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L
+//RCC_DEV0_1_RCC_XDMA_HI
+#define RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0
+#define RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL
+//RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L
+//RCC_DEV0_1_RCC_BUSNUM_CNTL1
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL
+//RCC_DEV0_1_RCC_BUSNUM_LIST0
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0__SHIFT 0x0
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1__SHIFT 0x8
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2__SHIFT 0x10
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3__SHIFT 0x18
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L
+//RCC_DEV0_1_RCC_BUSNUM_LIST1
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4__SHIFT 0x0
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5__SHIFT 0x8
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6__SHIFT 0x10
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7__SHIFT 0x18
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L
+//RCC_DEV0_1_RCC_BUSNUM_CNTL2
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L
+//RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM
+#define RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0
+#define RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L
+//RCC_DEV0_1_RCC_HOST_BUSNUM
+#define RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0
+#define RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL
+//RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L
+//RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L
+//RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L
+//RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L
+//RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000FFL
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000FF00L
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00FF0000L
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xFF000000L
+//RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000FFL
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000FF00L
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00FF0000L
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xFF000000L
+//RCC_DEV0_2_RCC_DEV0_LINK_CNTL
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT 0x10
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT 0x11
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK 0x00010000L
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK 0x00020000L
+//RCC_DEV0_2_RCC_CMN_LINK_CNTL
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L
+//RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE
+#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0
+#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8
+#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL
+#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L
+//RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL
+#define RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0
+#define RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL
+//RCC_DEV0_2_RCC_MH_ARB_CNTL
+#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0
+#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1
+#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L
+#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL
+
+
+// addressBlock: nbif_bif_bx_SYSDEC
+//BIF_BX1_PCIE_INDEX
+#define BIF_BX1_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
+#define BIF_BX1_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL
+//BIF_BX1_PCIE_DATA
+#define BIF_BX1_PCIE_DATA__PCIE_DATA__SHIFT 0x0
+#define BIF_BX1_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL
+//BIF_BX1_PCIE_INDEX2
+#define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0
+#define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL
+//BIF_BX1_PCIE_DATA2
+#define BIF_BX1_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0
+#define BIF_BX1_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL
+//BIF_BX1_PCIE_INDEX_HI
+#define BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT 0x0
+#define BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK 0x000000FFL
+//BIF_BX1_PCIE_INDEX2_HI
+#define BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT 0x0
+#define BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK 0x000000FFL
+//BIF_BX1_SBIOS_SCRATCH_0
+#define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT 0x0
+#define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK 0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_1
+#define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT 0x0
+#define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK 0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_2
+#define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT 0x0
+#define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK 0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_3
+#define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT 0x0
+#define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_0
+#define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_1
+#define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_2
+#define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_3
+#define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_4
+#define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_5
+#define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_6
+#define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_7
+#define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_8
+#define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_9
+#define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_10
+#define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_11
+#define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_12
+#define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_13
+#define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_14
+#define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_15
+#define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL
+//BIF_BX1_BIF_RLC_INTR_CNTL
+//BIF_BX1_BIF_VCE_INTR_CNTL
+//BIF_BX1_BIF_UVD_INTR_CNTL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR1
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR2
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR3
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR4
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR5
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR6
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR7
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_CNTL
+#define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL
+//BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL
+#define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL
+#define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
+#define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_0
+#define BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT 0x0
+#define BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK 0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_1
+#define BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT 0x0
+#define BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK 0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_2
+#define BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT 0x0
+#define BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK 0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_3
+#define BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT 0x0
+#define BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK 0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_4
+#define BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT 0x0
+#define BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK 0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_5
+#define BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT 0x0
+#define BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK 0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_6
+#define BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT 0x0
+#define BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK 0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_7
+#define BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT 0x0
+#define BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK 0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_8
+#define BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT 0x0
+#define BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK 0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_9
+#define BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT 0x0
+#define BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK 0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_10
+#define BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT 0x0
+#define BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK 0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_11
+#define BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT 0x0
+#define BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK 0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_12
+#define BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT 0x0
+#define BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK 0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_13
+#define BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT 0x0
+#define BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK 0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_14
+#define BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT 0x0
+#define BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK 0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_15
+#define BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT 0x0
+#define BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK 0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_0
+#define BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT 0x0
+#define BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0_MASK 0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_1
+#define BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT 0x0
+#define BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1_MASK 0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_2
+#define BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT 0x0
+#define BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2_MASK 0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_3
+#define BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT 0x0
+#define BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3_MASK 0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_4
+#define BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT 0x0
+#define BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4_MASK 0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_5
+#define BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT 0x0
+#define BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5_MASK 0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_6
+#define BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT 0x0
+#define BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6_MASK 0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_7
+#define BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT 0x0
+#define BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7_MASK 0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_8
+#define BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT 0x0
+#define BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8_MASK 0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_9
+#define BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT 0x0
+#define BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9_MASK 0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_10
+#define BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT 0x0
+#define BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10_MASK 0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_11
+#define BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT 0x0
+#define BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11_MASK 0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_12
+#define BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT 0x0
+#define BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12_MASK 0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_13
+#define BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT 0x0
+#define BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13_MASK 0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_14
+#define BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT 0x0
+#define BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14_MASK 0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_15
+#define BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT 0x0
+#define BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15_MASK 0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_4
+#define BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT 0x0
+#define BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK 0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_5
+#define BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT 0x0
+#define BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK 0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_6
+#define BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT 0x0
+#define BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK 0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_7
+#define BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT 0x0
+#define BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK 0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_8
+#define BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT 0x0
+#define BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK 0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_9
+#define BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT 0x0
+#define BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK 0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_10
+#define BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT 0x0
+#define BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK 0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_11
+#define BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT 0x0
+#define BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK 0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_12
+#define BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT 0x0
+#define BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK 0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_13
+#define BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT 0x0
+#define BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK 0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_14
+#define BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT 0x0
+#define BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK 0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_15
+#define BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT 0x0
+#define BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_bif_bx_pf_SYSPFVFDEC
+//BIF_BX_PF1_MM_INDEX
+#define BIF_BX_PF1_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_PF1_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_PF1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_PF1_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_PF1_MM_DATA
+#define BIF_BX_PF1_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MM_INDEX_HI
+#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_RSMU_INDEX
+#define BIF_BX_PF1_RSMU_INDEX__RSMU_INDEX__SHIFT 0x0
+#define BIF_BX_PF1_RSMU_INDEX__RSMU_INDEX_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_RSMU_DATA
+#define BIF_BX_PF1_RSMU_DATA__RSMU_DATA__SHIFT 0x0
+#define BIF_BX_PF1_RSMU_DATA__RSMU_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_bif_bx_BIFDEC1
+//BIF_BX1_CC_BIF_BX_STRAP0
+#define BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT 0x19
+#define BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK 0xFE000000L
+//BIF_BX1_CC_BIF_BX_PINSTRAP0
+//BIF_BX1_BIF_MM_INDACCESS_CNTL
+#define BIF_BX1_BIF_MM_INDACCESS_CNTL__WRITE_DIS__SHIFT 0x0
+#define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
+#define BIF_BX1_BIF_MM_INDACCESS_CNTL__WRITE_DIS_MASK 0x00000001L
+#define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L
+//BIF_BX1_BUS_CNTL
+#define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
+#define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
+#define BIF_BX1_BUS_CNTL__SET_AZ_TC__SHIFT 0xa
+#define BIF_BX1_BUS_CNTL__SET_MC_TC__SHIFT 0xd
+#define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
+#define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
+#define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
+#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT 0x18
+#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19
+#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a
+#define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT 0x1b
+#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT 0x1c
+#define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d
+#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e
+#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f
+#define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L
+#define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L
+#define BIF_BX1_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L
+#define BIF_BX1_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L
+#define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L
+#define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L
+#define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L
+#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK 0x01000000L
+#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L
+#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L
+#define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK 0x08000000L
+#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK 0x10000000L
+#define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L
+#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L
+#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L
+//BIF_BX1_BIF_SCRATCH0
+#define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
+#define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL
+//BIF_BX1_BIF_SCRATCH1
+#define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
+#define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL
+//BIF_BX1_BX_RESET_EN
+#define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10
+#define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L
+//BIF_BX1_MM_CFGREGS_CNTL
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L
+//BIF_BX1_BX_RESET_CNTL
+#define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0
+#define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L
+//BIF_BX1_INTERRUPT_CNTL
+#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
+#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
+#define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
+#define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
+#define BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
+#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
+#define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10
+#define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11
+#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12
+#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L
+#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L
+#define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L
+#define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L
+#define BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L
+#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L
+#define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L
+#define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L
+#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L
+//BIF_BX1_INTERRUPT_CNTL2
+#define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
+#define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL
+//BIF_BX1_CLKREQB_PAD_CNTL
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L
+//BIF_BX1_BIF_FEATURES_CONTROL_MISC
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT 0xb
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS__SHIFT 0xe
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT 0x10
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x19
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK 0x00000800L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS_MASK 0x00004000L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK 0x01FF0000L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x02000000L
+//BIF_BX1_HDP_ATOMIC_CONTROL_MISC
+#define BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT 0x0
+#define BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK 0x000000FFL
+//BIF_BX1_BIF_DOORBELL_CNTL
+#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0
+#define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1
+#define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
+#define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
+#define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b
+#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L
+#define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L
+#define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L
+#define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L
+#define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L
+//BIF_BX1_BIF_DOORBELL_INT_CNTL
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x17
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x1f
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x00800000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x80000000L
+//BIF_BX1_BIF_FB_EN
+#define BIF_BX1_BIF_FB_EN__FB_READ_EN__SHIFT 0x0
+#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
+#define BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L
+#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L
+//BIF_BX1_BIF_INTR_CNTL
+#define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0
+#define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L
+//BIF_BX1_BIF_MST_TRANS_PENDING_VF
+#define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL
+//BIF_BX1_BIF_SLV_TRANS_PENDING_VF
+#define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x7FFFFFFFL
+//BIF_BX1_BACO_CNTL
+#define BIF_BX1_BACO_CNTL__BACO_EN__SHIFT 0x0
+#define BIF_BX1_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2
+#define BIF_BX1_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3
+#define BIF_BX1_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5
+#define BIF_BX1_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6
+#define BIF_BX1_BACO_CNTL__BACO_MODE__SHIFT 0x8
+#define BIF_BX1_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9
+#define BIF_BX1_BACO_CNTL__PWRGOOD_VDDSOC__SHIFT 0x10
+#define BIF_BX1_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f
+#define BIF_BX1_BACO_CNTL__BACO_EN_MASK 0x00000001L
+#define BIF_BX1_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L
+#define BIF_BX1_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L
+#define BIF_BX1_BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L
+#define BIF_BX1_BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L
+#define BIF_BX1_BACO_CNTL__BACO_MODE_MASK 0x00000100L
+#define BIF_BX1_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L
+#define BIF_BX1_BACO_CNTL__PWRGOOD_VDDSOC_MASK 0x00010000L
+#define BIF_BX1_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L
+//BIF_BX1_BIF_BACO_EXIT_TIME0
+#define BIF_BX1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0
+#define BIF_BX1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BX1_BIF_BACO_EXIT_TIMER1
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR__SHIFT 0x19
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR_MASK 0x02000000L
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L
+//BIF_BX1_BIF_BACO_EXIT_TIMER2
+#define BIF_BX1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0
+#define BIF_BX1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL
+//BIF_BX1_BIF_BACO_EXIT_TIMER3
+#define BIF_BX1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0
+#define BIF_BX1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BX1_BIF_BACO_EXIT_TIMER4
+#define BIF_BX1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0
+#define BIF_BX1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BX1_MEM_TYPE_CNTL
+#define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0
+#define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L
+//BIF_BX1_VF_REGWR_EN
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0__SHIFT 0x0
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1__SHIFT 0x1
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2__SHIFT 0x2
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3__SHIFT 0x3
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4__SHIFT 0x4
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5__SHIFT 0x5
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6__SHIFT 0x6
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7__SHIFT 0x7
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8__SHIFT 0x8
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9__SHIFT 0x9
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10__SHIFT 0xa
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11__SHIFT 0xb
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12__SHIFT 0xc
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13__SHIFT 0xd
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14__SHIFT 0xe
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15__SHIFT 0xf
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16__SHIFT 0x10
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17__SHIFT 0x11
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18__SHIFT 0x12
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19__SHIFT 0x13
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20__SHIFT 0x14
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21__SHIFT 0x15
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22__SHIFT 0x16
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23__SHIFT 0x17
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24__SHIFT 0x18
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25__SHIFT 0x19
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26__SHIFT 0x1a
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27__SHIFT 0x1b
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28__SHIFT 0x1c
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29__SHIFT 0x1d
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30__SHIFT 0x1e
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0_MASK 0x00000001L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1_MASK 0x00000002L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2_MASK 0x00000004L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3_MASK 0x00000008L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4_MASK 0x00000010L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5_MASK 0x00000020L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6_MASK 0x00000040L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7_MASK 0x00000080L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8_MASK 0x00000100L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9_MASK 0x00000200L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10_MASK 0x00000400L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11_MASK 0x00000800L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12_MASK 0x00001000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13_MASK 0x00002000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14_MASK 0x00004000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15_MASK 0x00008000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16_MASK 0x00010000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17_MASK 0x00020000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18_MASK 0x00040000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19_MASK 0x00080000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20_MASK 0x00100000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21_MASK 0x00200000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22_MASK 0x00400000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23_MASK 0x00800000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24_MASK 0x01000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25_MASK 0x02000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26_MASK 0x04000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27_MASK 0x08000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28_MASK 0x10000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29_MASK 0x20000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30_MASK 0x40000000L
+//BIF_BX1_VF_DOORBELL_EN
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0__SHIFT 0x0
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1__SHIFT 0x1
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2__SHIFT 0x2
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3__SHIFT 0x3
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4__SHIFT 0x4
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5__SHIFT 0x5
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6__SHIFT 0x6
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7__SHIFT 0x7
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8__SHIFT 0x8
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9__SHIFT 0x9
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10__SHIFT 0xa
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11__SHIFT 0xb
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12__SHIFT 0xc
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13__SHIFT 0xd
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14__SHIFT 0xe
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15__SHIFT 0xf
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16__SHIFT 0x10
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17__SHIFT 0x11
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18__SHIFT 0x12
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19__SHIFT 0x13
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20__SHIFT 0x14
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21__SHIFT 0x15
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22__SHIFT 0x16
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23__SHIFT 0x17
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24__SHIFT 0x18
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25__SHIFT 0x19
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26__SHIFT 0x1a
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27__SHIFT 0x1b
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28__SHIFT 0x1c
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29__SHIFT 0x1d
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30__SHIFT 0x1e
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS__SHIFT 0x1f
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0_MASK 0x00000001L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1_MASK 0x00000002L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2_MASK 0x00000004L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3_MASK 0x00000008L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4_MASK 0x00000010L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5_MASK 0x00000020L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6_MASK 0x00000040L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7_MASK 0x00000080L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8_MASK 0x00000100L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9_MASK 0x00000200L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10_MASK 0x00000400L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11_MASK 0x00000800L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12_MASK 0x00001000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13_MASK 0x00002000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14_MASK 0x00004000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15_MASK 0x00008000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16_MASK 0x00010000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17_MASK 0x00020000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18_MASK 0x00040000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19_MASK 0x00080000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20_MASK 0x00100000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21_MASK 0x00200000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22_MASK 0x00400000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23_MASK 0x00800000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24_MASK 0x01000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25_MASK 0x02000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26_MASK 0x04000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27_MASK 0x08000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28_MASK 0x10000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29_MASK 0x20000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30_MASK 0x40000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS_MASK 0x80000000L
+//BIF_BX1_VF_FB_EN
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF0__SHIFT 0x0
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF1__SHIFT 0x1
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF2__SHIFT 0x2
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF3__SHIFT 0x3
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF4__SHIFT 0x4
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF5__SHIFT 0x5
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF6__SHIFT 0x6
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF7__SHIFT 0x7
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF8__SHIFT 0x8
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF9__SHIFT 0x9
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF10__SHIFT 0xa
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF11__SHIFT 0xb
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF12__SHIFT 0xc
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF13__SHIFT 0xd
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF14__SHIFT 0xe
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF15__SHIFT 0xf
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF16__SHIFT 0x10
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF17__SHIFT 0x11
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF18__SHIFT 0x12
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF19__SHIFT 0x13
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF20__SHIFT 0x14
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF21__SHIFT 0x15
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF22__SHIFT 0x16
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF23__SHIFT 0x17
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF24__SHIFT 0x18
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF25__SHIFT 0x19
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF26__SHIFT 0x1a
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF27__SHIFT 0x1b
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF28__SHIFT 0x1c
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF29__SHIFT 0x1d
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF30__SHIFT 0x1e
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF0_MASK 0x00000001L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF1_MASK 0x00000002L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF2_MASK 0x00000004L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF3_MASK 0x00000008L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF4_MASK 0x00000010L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF5_MASK 0x00000020L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF6_MASK 0x00000040L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF7_MASK 0x00000080L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF8_MASK 0x00000100L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF9_MASK 0x00000200L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF10_MASK 0x00000400L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF11_MASK 0x00000800L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF12_MASK 0x00001000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF13_MASK 0x00002000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF14_MASK 0x00004000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF15_MASK 0x00008000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF16_MASK 0x00010000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF17_MASK 0x00020000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF18_MASK 0x00040000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF19_MASK 0x00080000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF20_MASK 0x00100000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF21_MASK 0x00200000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF22_MASK 0x00400000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF23_MASK 0x00800000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF24_MASK 0x01000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF25_MASK 0x02000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF26_MASK 0x04000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF27_MASK 0x08000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF28_MASK 0x10000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF29_MASK 0x20000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF30_MASK 0x40000000L
+//BIF_BX1_VF_REGWR_STATUS
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0__SHIFT 0x0
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1__SHIFT 0x1
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2__SHIFT 0x2
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3__SHIFT 0x3
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4__SHIFT 0x4
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5__SHIFT 0x5
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6__SHIFT 0x6
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7__SHIFT 0x7
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8__SHIFT 0x8
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9__SHIFT 0x9
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10__SHIFT 0xa
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11__SHIFT 0xb
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12__SHIFT 0xc
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13__SHIFT 0xd
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14__SHIFT 0xe
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15__SHIFT 0xf
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16__SHIFT 0x10
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17__SHIFT 0x11
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18__SHIFT 0x12
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19__SHIFT 0x13
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20__SHIFT 0x14
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21__SHIFT 0x15
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22__SHIFT 0x16
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23__SHIFT 0x17
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24__SHIFT 0x18
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25__SHIFT 0x19
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26__SHIFT 0x1a
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27__SHIFT 0x1b
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28__SHIFT 0x1c
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29__SHIFT 0x1d
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30__SHIFT 0x1e
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0_MASK 0x00000001L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1_MASK 0x00000002L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2_MASK 0x00000004L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3_MASK 0x00000008L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4_MASK 0x00000010L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5_MASK 0x00000020L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6_MASK 0x00000040L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7_MASK 0x00000080L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8_MASK 0x00000100L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9_MASK 0x00000200L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10_MASK 0x00000400L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11_MASK 0x00000800L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12_MASK 0x00001000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13_MASK 0x00002000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14_MASK 0x00004000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15_MASK 0x00008000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16_MASK 0x00010000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17_MASK 0x00020000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18_MASK 0x00040000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19_MASK 0x00080000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20_MASK 0x00100000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21_MASK 0x00200000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22_MASK 0x00400000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23_MASK 0x00800000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24_MASK 0x01000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25_MASK 0x02000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26_MASK 0x04000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27_MASK 0x08000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28_MASK 0x10000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29_MASK 0x20000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30_MASK 0x40000000L
+//BIF_BX1_VF_DOORBELL_STATUS
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0__SHIFT 0x0
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1__SHIFT 0x1
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2__SHIFT 0x2
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3__SHIFT 0x3
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4__SHIFT 0x4
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5__SHIFT 0x5
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6__SHIFT 0x6
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7__SHIFT 0x7
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8__SHIFT 0x8
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9__SHIFT 0x9
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10__SHIFT 0xa
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11__SHIFT 0xb
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12__SHIFT 0xc
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13__SHIFT 0xd
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14__SHIFT 0xe
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15__SHIFT 0xf
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16__SHIFT 0x10
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17__SHIFT 0x11
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18__SHIFT 0x12
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19__SHIFT 0x13
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20__SHIFT 0x14
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21__SHIFT 0x15
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22__SHIFT 0x16
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23__SHIFT 0x17
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24__SHIFT 0x18
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25__SHIFT 0x19
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26__SHIFT 0x1a
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27__SHIFT 0x1b
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28__SHIFT 0x1c
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29__SHIFT 0x1d
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30__SHIFT 0x1e
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0_MASK 0x00000001L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1_MASK 0x00000002L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2_MASK 0x00000004L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3_MASK 0x00000008L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4_MASK 0x00000010L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5_MASK 0x00000020L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6_MASK 0x00000040L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7_MASK 0x00000080L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8_MASK 0x00000100L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9_MASK 0x00000200L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10_MASK 0x00000400L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11_MASK 0x00000800L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12_MASK 0x00001000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13_MASK 0x00002000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14_MASK 0x00004000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15_MASK 0x00008000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16_MASK 0x00010000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17_MASK 0x00020000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18_MASK 0x00040000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19_MASK 0x00080000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20_MASK 0x00100000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21_MASK 0x00200000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22_MASK 0x00400000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23_MASK 0x00800000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24_MASK 0x01000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25_MASK 0x02000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26_MASK 0x04000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27_MASK 0x08000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28_MASK 0x10000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29_MASK 0x20000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30_MASK 0x40000000L
+//BIF_BX1_VF_FB_STATUS
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0__SHIFT 0x0
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1__SHIFT 0x1
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2__SHIFT 0x2
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3__SHIFT 0x3
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4__SHIFT 0x4
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5__SHIFT 0x5
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6__SHIFT 0x6
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7__SHIFT 0x7
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8__SHIFT 0x8
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9__SHIFT 0x9
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10__SHIFT 0xa
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11__SHIFT 0xb
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12__SHIFT 0xc
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13__SHIFT 0xd
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14__SHIFT 0xe
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15__SHIFT 0xf
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16__SHIFT 0x10
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17__SHIFT 0x11
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18__SHIFT 0x12
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19__SHIFT 0x13
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20__SHIFT 0x14
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21__SHIFT 0x15
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22__SHIFT 0x16
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23__SHIFT 0x17
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24__SHIFT 0x18
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25__SHIFT 0x19
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26__SHIFT 0x1a
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27__SHIFT 0x1b
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28__SHIFT 0x1c
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29__SHIFT 0x1d
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30__SHIFT 0x1e
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0_MASK 0x00000001L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1_MASK 0x00000002L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2_MASK 0x00000004L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3_MASK 0x00000008L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4_MASK 0x00000010L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5_MASK 0x00000020L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6_MASK 0x00000040L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7_MASK 0x00000080L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8_MASK 0x00000100L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9_MASK 0x00000200L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10_MASK 0x00000400L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11_MASK 0x00000800L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12_MASK 0x00001000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13_MASK 0x00002000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14_MASK 0x00004000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15_MASK 0x00008000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16_MASK 0x00010000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17_MASK 0x00020000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18_MASK 0x00040000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19_MASK 0x00080000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20_MASK 0x00100000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21_MASK 0x00200000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22_MASK 0x00400000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23_MASK 0x00800000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24_MASK 0x01000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25_MASK 0x02000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26_MASK 0x04000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27_MASK 0x08000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28_MASK 0x10000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29_MASK 0x20000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30_MASK 0x40000000L
+//BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL
+#define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL
+#define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//BIF_BX1_BIF_RB_CNTL
+#define BIF_BX1_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define BIF_BX1_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
+#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
+#define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11
+#define BIF_BX1_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL__SHIFT 0x19
+#define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT 0x1a
+#define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT 0x1d
+#define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT 0x1e
+#define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define BIF_BX1_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define BIF_BX1_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L
+#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L
+#define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L
+#define BIF_BX1_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL_MASK 0x02000000L
+#define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK 0x1C000000L
+#define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK 0x20000000L
+#define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK 0x40000000L
+#define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
+//BIF_BX1_BIF_RB_BASE
+#define BIF_BX1_BIF_RB_BASE__ADDR__SHIFT 0x0
+#define BIF_BX1_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//BIF_BX1_BIF_RB_RPTR
+#define BIF_BX1_BIF_RB_RPTR__OFFSET__SHIFT 0x2
+#define BIF_BX1_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_BX1_BIF_RB_WPTR
+#define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0
+#define BIF_BX1_BIF_RB_WPTR__OFFSET__SHIFT 0x2
+#define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L
+#define BIF_BX1_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_BX1_BIF_RB_WPTR_ADDR_HI
+#define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL
+//BIF_BX1_BIF_RB_WPTR_ADDR_LO
+#define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//BIF_BX1_MAILBOX_INDEX
+#define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0
+#define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL
+//BIF_BX1_BIF_MP1_INTR_CTRL
+#define BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT 0x0
+#define BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK 0x00000001L
+//BIF_BX1_BIF_PERSTB_PAD_CNTL
+#define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0
+#define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL
+//BIF_BX1_BIF_PX_EN_PAD_CNTL
+#define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0
+#define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x00000FFFL
+//BIF_BX1_BIF_REFPADKIN_PAD_CNTL
+#define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0
+#define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL
+//BIF_BX1_BIF_CLKREQB_PAD_CNTL
+#define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0
+#define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x7FFFFFFFL
+//BIF_BX1_BIF_PWRBRK_PAD_CNTL
+#define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT 0x0
+#define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK 0x000000FFL
+//BIF_BX1_BIF_WAKEB_PAD_CNTL
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL__SHIFT 0x0
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN__SHIFT 0x1
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPD__SHIFT 0x2
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPU__SHIFT 0x3
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN__SHIFT 0x4
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0__SHIFT 0x5
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1__SHIFT 0x6
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED__SHIFT 0x7
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL_MASK 0x00000001L
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN_MASK 0x00000002L
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPD_MASK 0x00000004L
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPU_MASK 0x00000008L
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN_MASK 0x00000010L
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0_MASK 0x00000020L
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1_MASK 0x00000040L
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED_MASK 0x00000080L
+//BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD__SHIFT 0x0
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU__SHIFT 0x1
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN__SHIFT 0x2
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0__SHIFT 0x3
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1__SHIFT 0x4
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL__SHIFT 0x5
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD_MASK 0x00000001L
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU_MASK 0x00000002L
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN_MASK 0x00000004L
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0_MASK 0x00000008L
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1_MASK 0x00000010L
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL_MASK 0x00000020L
+//BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL
+#define BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID__SHIFT 0x0
+#define BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH__SHIFT 0x1
+#define BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID_MASK 0x00000001L
+#define BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH_MASK 0xFFFFFFFEL
+//BIF_BX1_BIF_S5_MEM_POWER_CTRL0
+#define BIF_BX1_BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0__SHIFT 0x0
+#define BIF_BX1_BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0_MASK 0xFFFFFFFFL
+//BIF_BX1_BIF_S5_MEM_POWER_CTRL1
+#define BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32__SHIFT 0x0
+#define BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL__SHIFT 0xa
+#define BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32_MASK 0x000003FFL
+#define BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL_MASK 0x00000400L
+//BIF_BX1_BIF_S5_DUMMY_REGS
+#define BIF_BX1_BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS__SHIFT 0x0
+#define BIF_BX1_BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_bif_bx_pf_BIFPFVFDEC1
+//BIF_BX_PF1_BIF_BME_STATUS
+#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_PF1_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_PF1_GPU_HDP_FLUSH_REQ
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_PF1_GPU_HDP_FLUSH_DONE
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_PF1_BIF_TRANS_PENDING
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_CONTROL
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_PF1_MAILBOX_INT_CNTL
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_PF1_BIF_VMHV_MAILBOX
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_rcc_strap_BIFDEC1:1
+//RCC_STRAP2_RCC_BIF_STRAP0
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT 0x0
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT 0x1
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x14
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN__SHIFT 0x15
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GPUIOV_EN__SHIFT 0x16
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT 0x1c
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK 0x00000001L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK 0x00000002L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000078L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00100000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN_MASK 0x00200000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GPUIOV_EN_MASK 0x00400000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK 0x10000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L
+//RCC_STRAP2_RCC_BIF_STRAP1
+#define RCC_STRAP2_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x0
+#define RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1
+#define RCC_STRAP2_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x2
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT 0x18
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT 0x19
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT 0x1e
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT 0x1f
+#define RCC_STRAP2_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L
+#define RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L
+#define RCC_STRAP2_RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK 0x01000000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK 0x02000000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_MASK 0x40000000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK 0x80000000L
+//RCC_STRAP2_RCC_BIF_STRAP2
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWUS_SPT__SHIFT 0x1
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN__SHIFT 0x7
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_USB_PD_FUNC_DIS__SHIFT 0xc
+#define RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWUS_SPT_MASK 0x00000002L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN_MASK 0x00000080L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_USB_PD_FUNC_DIS_MASK 0x00001000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L
+//RCC_STRAP2_RCC_BIF_STRAP3
+#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0
+#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10
+#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L
+//RCC_STRAP2_RCC_BIF_STRAP4
+#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0
+#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10
+#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L
+//RCC_STRAP2_RCC_BIF_STRAP5
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT 0x15
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN__SHIFT 0x1f
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK 0x00200000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN_MASK 0x80000000L
+//RCC_STRAP2_RCC_BIF_STRAP6
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT 0x0
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT 0x1
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT 0x2
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL__SHIFT 0x3
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_S5_GFX_REGS_ACCESS_DIS__SHIFT 0x4
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE__SHIFT 0x5
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GFX_PARTITION_CAP_SPX_SUPPORT__SHIFT 0x6
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GFX_PARTITION_CAP_TPX_SUPPORT__SHIFT 0x7
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_MEM_PARTITION_CAP_NPS1_SUPPORT__SHIFT 0x8
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_MEM_PARTITION_CAP_NPS3_SUPPORT__SHIFT 0x9
+#define RCC_STRAP2_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6__SHIFT 0xa
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK 0x00000001L
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK 0x00000002L
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK 0x00000004L
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL_MASK 0x00000008L
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_S5_GFX_REGS_ACCESS_DIS_MASK 0x00000010L
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE_MASK 0x00000020L
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GFX_PARTITION_CAP_SPX_SUPPORT_MASK 0x00000040L
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GFX_PARTITION_CAP_TPX_SUPPORT_MASK 0x00000080L
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_MEM_PARTITION_CAP_NPS1_SUPPORT_MASK 0x00000100L
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_MEM_PARTITION_CAP_NPS3_SUPPORT_MASK 0x00000200L
+#define RCC_STRAP2_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6_MASK 0xFFFFFC00L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x11
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x12
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x13
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00010000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00020000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00040000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00080000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0_MASK 0x00100000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT 0x1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT 0x2
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT 0x3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT 0x4
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT 0x5
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT 0x6
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK 0x00000001L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK 0x00000002L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK 0x00000004L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK 0x00000008L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK 0x00000010L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK 0x00000020L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK 0x0007FFC0L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP11
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK 0x0FFF0000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK 0x10000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK 0x20000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK 0x40000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP12
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK 0x00FFFFFFL
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP13
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT 0x9
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK 0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK 0x00000100L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK 0x000FFE00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK 0xFFF00000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP14
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT 0x1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT 0x2
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT 0x3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT 0x4
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK 0x00000001L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK 0x00000002L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK 0x00000004L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK 0x00000008L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK 0x00000010L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP2
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP4
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP5
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK 0x40000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP6
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x15
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK 0x00100000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x00E00000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x0F000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0xF0000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP7
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP9
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP1
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP13
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0xFF000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP15
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT 0xc
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK 0x00000FFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK 0x00FFF000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK 0x01000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP16
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT 0xc
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK 0x00000FFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK 0x00FFF000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP17
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT 0xc
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT 0xd
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK 0x00000FFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK 0x00001000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK 0x01FFE000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK 0x00000FFFL
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP2
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP3
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x11
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00010000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00020000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP4
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP5
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0_MASK 0x38000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP8
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00780000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP9
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP2
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK 0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP20
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP21
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP3
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x11
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00010000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00020000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP4
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP5
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT 0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK 0x38000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP6
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP7
+
+
+// addressBlock: nbif_gdc_dma_sion_SIONDEC
+//GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0
+#define GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1
+#define GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0
+#define GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1
+#define GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0
+#define GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1
+#define GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0
+#define GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1
+#define GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL0_Req_BurstTarget_REG0
+#define GDC_DMA_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL0_Req_BurstTarget_REG1
+#define GDC_DMA_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL0_Req_TimeSlot_REG0
+#define GDC_DMA_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL0_Req_TimeSlot_REG1
+#define GDC_DMA_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0
+#define GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1
+#define GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0
+#define GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1
+#define GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0
+#define GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1
+#define GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0
+#define GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1
+#define GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_Req_BurstTarget_REG0
+#define GDC_DMA_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_Req_BurstTarget_REG1
+#define GDC_DMA_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_Req_TimeSlot_REG0
+#define GDC_DMA_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_Req_TimeSlot_REG1
+#define GDC_DMA_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0
+#define GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1
+#define GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0
+#define GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1
+#define GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0
+#define GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1
+#define GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0
+#define GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1
+#define GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_Req_BurstTarget_REG0
+#define GDC_DMA_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_Req_BurstTarget_REG1
+#define GDC_DMA_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_Req_TimeSlot_REG0
+#define GDC_DMA_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_Req_TimeSlot_REG1
+#define GDC_DMA_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0
+#define GDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1
+#define GDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0
+#define GDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1
+#define GDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0
+#define GDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1
+#define GDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0
+#define GDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1
+#define GDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL3_Req_BurstTarget_REG0
+#define GDC_DMA_SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL3_Req_BurstTarget_REG1
+#define GDC_DMA_SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL3_Req_TimeSlot_REG0
+#define GDC_DMA_SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL3_Req_TimeSlot_REG1
+#define GDC_DMA_SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_DMA_SION_CNTL_REG0
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK 0x00000400L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK 0x00000800L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK 0x00001000L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK 0x00002000L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK 0x00004000L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK 0x00008000L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK 0x00010000L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK 0x00020000L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK 0x00040000L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK 0x00080000L
+//GDC_DMA_SION_CNTL_REG1
+#define GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0
+#define GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_CG_OFF_HYSTERESIS__SHIFT 0x8
+#define GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_LIVELOCK_WATCHDOG_THRESHOLD_MASK 0x000000FFL
+#define GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_CG_OFF_HYSTERESIS_MASK 0x0000FF00L
+
+
+// addressBlock: nbif_gdc_hst_sion_SIONDEC
+//GDC_HST_SION_CL0_RdRsp_BurstTarget_REG0
+#define GDC_HST_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define GDC_HST_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL0_RdRsp_BurstTarget_REG1
+#define GDC_HST_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define GDC_HST_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL0_RdRsp_TimeSlot_REG0
+#define GDC_HST_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define GDC_HST_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL0_RdRsp_TimeSlot_REG1
+#define GDC_HST_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define GDC_HST_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL0_WrRsp_BurstTarget_REG0
+#define GDC_HST_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define GDC_HST_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL0_WrRsp_BurstTarget_REG1
+#define GDC_HST_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define GDC_HST_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL0_WrRsp_TimeSlot_REG0
+#define GDC_HST_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define GDC_HST_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL0_WrRsp_TimeSlot_REG1
+#define GDC_HST_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define GDC_HST_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL0_Req_BurstTarget_REG0
+#define GDC_HST_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define GDC_HST_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL0_Req_BurstTarget_REG1
+#define GDC_HST_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define GDC_HST_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL0_Req_TimeSlot_REG0
+#define GDC_HST_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define GDC_HST_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL0_Req_TimeSlot_REG1
+#define GDC_HST_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define GDC_HST_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0
+#define GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1
+#define GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0
+#define GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1
+#define GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0
+#define GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1
+#define GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0
+#define GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1
+#define GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL1_RdRsp_BurstTarget_REG0
+#define GDC_HST_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define GDC_HST_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL1_RdRsp_BurstTarget_REG1
+#define GDC_HST_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define GDC_HST_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL1_RdRsp_TimeSlot_REG0
+#define GDC_HST_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define GDC_HST_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL1_RdRsp_TimeSlot_REG1
+#define GDC_HST_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define GDC_HST_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL1_WrRsp_BurstTarget_REG0
+#define GDC_HST_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define GDC_HST_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL1_WrRsp_BurstTarget_REG1
+#define GDC_HST_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define GDC_HST_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL1_WrRsp_TimeSlot_REG0
+#define GDC_HST_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define GDC_HST_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL1_WrRsp_TimeSlot_REG1
+#define GDC_HST_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define GDC_HST_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL1_Req_BurstTarget_REG0
+#define GDC_HST_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define GDC_HST_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL1_Req_BurstTarget_REG1
+#define GDC_HST_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define GDC_HST_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL1_Req_TimeSlot_REG0
+#define GDC_HST_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define GDC_HST_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL1_Req_TimeSlot_REG1
+#define GDC_HST_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define GDC_HST_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0
+#define GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1
+#define GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0
+#define GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1
+#define GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0
+#define GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1
+#define GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0
+#define GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1
+#define GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//GDC_HST_SION_CNTL_REG0
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK 0x00000400L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK 0x00000800L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK 0x00001000L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK 0x00002000L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK 0x00004000L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK 0x00008000L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK 0x00010000L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK 0x00020000L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK 0x00040000L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK 0x00080000L
+//GDC_HST_SION_CNTL_REG1
+#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0
+#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_CG_OFF_HYSTERESIS__SHIFT 0x8
+#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVE_ACTIVE__SHIFT 0x10
+#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVELOCK_WATCHDOG_THRESHOLD_MASK 0x000000FFL
+#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_CG_OFF_HYSTERESIS_MASK 0x0000FF00L
+#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVE_ACTIVE_MASK 0xFFFF0000L
+
+
+// addressBlock: nbif_gdc_GDCDEC
+//GDC1_SHUB_REGS_IF_CTL
+#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0
+#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS__SHIFT 0x1
+#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L
+#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS_MASK 0x00000002L
+//GDC1_A2S_QUEUE_FIFO_ARB_CNTL
+#define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT 0x0
+#define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT 0xa
+#define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE__SHIFT 0x14
+#define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE__SHIFT 0x15
+#define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY_MASK 0x000003FFL
+#define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY_MASK 0x000FFC00L
+#define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE_MASK 0x00100000L
+#define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE_MASK 0x00200000L
+//GDC1_NGDC_MGCG_CTRL
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x0
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x1
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x2
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT 0xa
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT 0xb
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT 0xc
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT 0xd
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DBG_DIS__SHIFT 0xe
+#define GDC1_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN__SHIFT 0xf
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK 0x00000001L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK 0x00000002L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK 0x000003FCL
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK 0x00000400L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK 0x00000800L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK 0x00001000L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK 0x00002000L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DBG_DIS_MASK 0x00004000L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN_MASK 0x00008000L
+//GDC1_S2A_MISC_CNTL
+#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3
+#define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT 0x8
+#define GDC1_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT 0xa
+#define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT 0xc
+#define GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT 0xf
+#define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT 0x10
+#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L
+#define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE_MASK 0x00000300L
+#define GDC1_S2A_MISC_CNTL__RB_ARB_MODE_MASK 0x00000C00L
+#define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK 0x00003000L
+#define GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK 0x00008000L
+#define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK 0x000F0000L
+//GDC1_NGDC_EARLY_WAKEUP_CTRL
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0x0
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0x1
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0x2
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000001L
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00000002L
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00000004L
+//GDC1_NGDC_PG_MISC_CTRL
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY__SHIFT 0xa
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1__SHIFT 0xd
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS__SHIFT 0xe
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2__SHIFT 0x10
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY_MASK 0x00000400L
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1_MASK 0x00002000L
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS_MASK 0x00004000L
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2_MASK 0x00010000L
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L
+//GDC1_NGDC_PGMST_CTRL
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS__SHIFT 0x0
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN__SHIFT 0x8
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN__SHIFT 0xa
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN__SHIFT 0xe
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS_MASK 0x000000FFL
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN_MASK 0x00000100L
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L
+//GDC1_NGDC_PGSLV_CTRL
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS__SHIFT 0xa
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS_MASK 0x00007C00L
+//GDC1_ATDMA_MISC_CNTL
+#define GDC1_ATDMA_MISC_CNTL__ATDMA_WRR_ARB_MODE__SHIFT 0x0
+#define GDC1_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1
+#define GDC1_ATDMA_MISC_CNTL__ATDMA_RDRSP_ARB_MODE__SHIFT 0x2
+#define GDC1_ATDMA_MISC_CNTL__ATDMA_WRR_VC6_WEIGHT__SHIFT 0x8
+#define GDC1_ATDMA_MISC_CNTL__ATDMA_WRR_VC0_WEIGHT__SHIFT 0x10
+#define GDC1_ATDMA_MISC_CNTL__ATDMA_WRR_VC1_WEIGHT__SHIFT 0x18
+#define GDC1_ATDMA_MISC_CNTL__ATDMA_WRR_ARB_MODE_MASK 0x00000001L
+#define GDC1_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L
+#define GDC1_ATDMA_MISC_CNTL__ATDMA_RDRSP_ARB_MODE_MASK 0x0000000CL
+#define GDC1_ATDMA_MISC_CNTL__ATDMA_WRR_VC6_WEIGHT_MASK 0x0000FF00L
+#define GDC1_ATDMA_MISC_CNTL__ATDMA_WRR_VC0_WEIGHT_MASK 0x00FF0000L
+#define GDC1_ATDMA_MISC_CNTL__ATDMA_WRR_VC1_WEIGHT_MASK 0xFF000000L
+
+
+// addressBlock: nbif_gdc_ras_gdc_ras_regblk
+//GDCSOC_ERR_RSP_CNTL
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_BYPASS__SHIFT 0x0
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_ACCUM_SEL__SHIFT 0x1
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_EN__SHIFT 0x2
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_DATA__SHIFT 0x3
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_STATUS_ACCUM_EN__SHIFT 0x4
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_DATASTATUS_ACCUM_EN__SHIFT 0x5
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_BYPASS_MASK 0x00000001L
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_ACCUM_SEL_MASK 0x00000002L
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_EN_MASK 0x00000004L
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_DATA_MASK 0x00000008L
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_STATUS_ACCUM_EN_MASK 0x00000010L
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_DATASTATUS_ACCUM_EN_MASK 0x00000020L
+//GDCSOC_RAS_CENTRAL_STATUS
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det__SHIFT 0x0
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det__SHIFT 0x1
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det__SHIFT 0x2
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det__SHIFT 0x3
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det_MASK 0x00000001L
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det_MASK 0x00000002L
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det_MASK 0x00000004L
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det_MASK 0x00000008L
+//GDCSOC_RAS_LEAF0_CTRL
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_UCP_EN__SHIFT 0x15
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_UCP_EN_MASK 0x00200000L
+//GDCSOC_RAS_LEAF1_CTRL
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_UCP_EN__SHIFT 0x15
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_UCP_EN_MASK 0x00200000L
+//GDCSOC_RAS_LEAF2_CTRL
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_INTR_EN__SHIFT 0x10
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_UCP_EN__SHIFT 0x15
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_UCP_EN_MASK 0x00200000L
+//GDCSOC_RAS_LEAF3_CTRL
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_UCP_EN__SHIFT 0x15
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_UCP_EN_MASK 0x00200000L
+//GDCSOC_RAS_LEAF4_CTRL
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_UCP_EN__SHIFT 0x15
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_UCP_EN_MASK 0x00200000L
+//GDCSOC_RAS_LEAF2_MISC_CTRL
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_DROP_EN__SHIFT 0x0
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_DROP_EN__SHIFT 0x1
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS__SHIFT 0x8
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS__SHIFT 0x9
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_REQ__SHIFT 0xb
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_EN_DMA_REQ_CHAIN_CHK__SHIFT 0xc
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_RSP__SHIFT 0xd
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID_EN__SHIFT 0x10
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_CONST_EN__SHIFT 0x11
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_DROP_EN_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_DROP_EN_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_REQ_MASK 0x00000800L
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_EN_DMA_REQ_CHAIN_CHK_MASK 0x00001000L
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_RSP_MASK 0x00002000L
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID_EN_MASK 0x00010000L
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_CONST_EN_MASK 0x00020000L
+//GDCSOC_RAS_LEAF2_MISC_CTRL2
+#define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID__SHIFT 0x0
+#define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG__SHIFT 0xb
+#define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_OFFSET__SHIFT 0x15
+#define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID_MASK 0x000007FFL
+#define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_MASK 0x001FF800L
+#define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_OFFSET_MASK 0x7FE00000L
+//GDCSOC_RAS_LEAF0_STATUS
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCSOC_RAS_LEAF1_STATUS
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCSOC_RAS_LEAF2_STATUS
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCSOC_RAS_LEAF3_STATUS
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCSOC_RAS_LEAF4_STATUS
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+
+
+// addressBlock: nbif_gdc_rst_GDCRST_DEC
+//SHUB_PF_FLR_RST
+#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0
+#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1
+#define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2
+#define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3
+#define SHUB_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x4
+#define SHUB_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x5
+#define SHUB_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x6
+#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L
+#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L
+#define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK 0x00000004L
+#define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK 0x00000008L
+#define SHUB_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK 0x00000010L
+#define SHUB_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK 0x00000020L
+#define SHUB_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK 0x00000040L
+//SHUB_GFX_DRV_VPU_RST
+#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST__SHIFT 0x0
+#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST_MASK 0x00000001L
+//SHUB_LINK_RESET
+#define SHUB_LINK_RESET__LINK_P0_RESET__SHIFT 0x0
+#define SHUB_LINK_RESET__LINK_P1_RESET__SHIFT 0x1
+#define SHUB_LINK_RESET__LINK_P2_RESET__SHIFT 0x2
+#define SHUB_LINK_RESET__LINK_P3_RESET__SHIFT 0x3
+#define SHUB_LINK_RESET__LINK_P0_RESET_MASK 0x00000001L
+#define SHUB_LINK_RESET__LINK_P1_RESET_MASK 0x00000002L
+#define SHUB_LINK_RESET__LINK_P2_RESET_MASK 0x00000004L
+#define SHUB_LINK_RESET__LINK_P3_RESET_MASK 0x00000008L
+//SHUB_HARD_RST_CTRL
+#define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT 0x0
+#define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT 0x1
+#define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT 0x2
+#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3
+#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4
+#define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT 0x5
+#define SHUB_HARD_RST_CTRL__COR_RESET_EN_MASK 0x00000001L
+#define SHUB_HARD_RST_CTRL__REG_RESET_EN_MASK 0x00000002L
+#define SHUB_HARD_RST_CTRL__STY_RESET_EN_MASK 0x00000004L
+#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L
+#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L
+#define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000020L
+//SHUB_SOFT_RST_CTRL
+#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT 0x0
+#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT 0x1
+#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT 0x2
+#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3
+#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4
+#define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN__SHIFT 0x5
+#define SHUB_SOFT_RST_CTRL__COR_RESET_EN_MASK 0x00000001L
+#define SHUB_SOFT_RST_CTRL__REG_RESET_EN_MASK 0x00000002L
+#define SHUB_SOFT_RST_CTRL__STY_RESET_EN_MASK 0x00000004L
+#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L
+#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L
+#define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000020L
+//SHUB_SDP_PORT_RST
+#define SHUB_SDP_PORT_RST__A2S_SDP_PORT_RST__SHIFT 0x0
+#define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST__SHIFT 0x1
+#define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST__SHIFT 0x2
+#define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST__SHIFT 0x3
+#define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST__SHIFT 0x4
+#define SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST__SHIFT 0x6
+#define SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST__SHIFT 0x7
+#define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST__SHIFT 0x8
+#define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST__SHIFT 0x9
+#define SHUB_SDP_PORT_RST__MPDMATF_DMA_SDP_PORT_RST__SHIFT 0xa
+#define SHUB_SDP_PORT_RST__MPDMAPM_DMA_SDP_PORT_RST__SHIFT 0xb
+#define SHUB_SDP_PORT_RST__MPDMATF_HST_SDP_PORT_RST__SHIFT 0xc
+#define SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST__SHIFT 0xd
+#define SHUB_SDP_PORT_RST__SION_AON_RST__SHIFT 0x18
+#define SHUB_SDP_PORT_RST__A2S_SDP_PORT_RST_MASK 0x00000001L
+#define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST_MASK 0x00000002L
+#define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST_MASK 0x00000004L
+#define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST_MASK 0x00000008L
+#define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST_MASK 0x00000010L
+#define SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST_MASK 0x00000040L
+#define SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST_MASK 0x00000080L
+#define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST_MASK 0x00000100L
+#define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST_MASK 0x00000200L
+#define SHUB_SDP_PORT_RST__MPDMATF_DMA_SDP_PORT_RST_MASK 0x00000400L
+#define SHUB_SDP_PORT_RST__MPDMAPM_DMA_SDP_PORT_RST_MASK 0x00000800L
+#define SHUB_SDP_PORT_RST__MPDMATF_HST_SDP_PORT_RST_MASK 0x00001000L
+#define SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST_MASK 0x00002000L
+#define SHUB_SDP_PORT_RST__SION_AON_RST_MASK 0x01000000L
+//SHUB_RST_MISC_TRL
+#define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_ATOMIC__SHIFT 0x0
+#define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_CYCLE__SHIFT 0x10
+#define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_ATOMIC_MASK 0x00000001L
+#define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_CYCLE_MASK 0x00FF0000L
+
+
+// addressBlock: nbif_gdc_s2a_GDCS2A_DEC
+//GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE__SHIFT 0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID__SHIFT 0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_DROP_EN__SHIFT 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE_MASK 0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID_MASK 0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_DROP_EN_MASK 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE__SHIFT 0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID__SHIFT 0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_DROP_EN__SHIFT 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE_MASK 0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID_MASK 0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_DROP_EN_MASK 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE__SHIFT 0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID__SHIFT 0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_DROP_EN__SHIFT 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE_MASK 0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID_MASK 0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_DROP_EN_MASK 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE__SHIFT 0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID__SHIFT 0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_DROP_EN__SHIFT 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE_MASK 0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID_MASK 0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_DROP_EN_MASK 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE__SHIFT 0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID__SHIFT 0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_DROP_EN__SHIFT 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE_MASK 0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID_MASK 0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_DROP_EN_MASK 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE__SHIFT 0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID__SHIFT 0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_DROP_EN__SHIFT 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE_MASK 0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID_MASK 0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_DROP_EN_MASK 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE__SHIFT 0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID__SHIFT 0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_DROP_EN__SHIFT 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE_MASK 0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID_MASK 0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_DROP_EN_MASK 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE__SHIFT 0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID__SHIFT 0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_DROP_EN__SHIFT 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE_MASK 0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID_MASK 0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_DROP_EN_MASK 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE__SHIFT 0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID__SHIFT 0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_DROP_EN__SHIFT 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE_MASK 0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID_MASK 0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_DROP_EN_MASK 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE__SHIFT 0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID__SHIFT 0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_DROP_EN__SHIFT 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE_MASK 0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID_MASK 0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_DROP_EN_MASK 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE__SHIFT 0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID__SHIFT 0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_DROP_EN__SHIFT 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE_MASK 0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID_MASK 0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_DROP_EN_MASK 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE__SHIFT 0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID__SHIFT 0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_DROP_EN__SHIFT 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE_MASK 0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID_MASK 0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_DROP_EN_MASK 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE__SHIFT 0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID__SHIFT 0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_DROP_EN__SHIFT 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE_MASK 0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID_MASK 0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_DROP_EN_MASK 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE__SHIFT 0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID__SHIFT 0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_DROP_EN__SHIFT 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE_MASK 0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID_MASK 0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_DROP_EN_MASK 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE__SHIFT 0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID__SHIFT 0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_DROP_EN__SHIFT 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE_MASK 0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID_MASK 0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_DROP_EN_MASK 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE__SHIFT 0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID__SHIFT 0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_DROP_EN__SHIFT 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE_MASK 0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID_MASK 0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_DROP_EN_MASK 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG
+#define GDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT 0x0
+#define GDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBE_FENCE_INTR_ENABLE__SHIFT 0x1
+#define GDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK 0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBE_FENCE_INTR_ENABLE_MASK 0x00000002L
+//GDC_S2A1_NBIF_GFX_DOORBELL_STATUS
+#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT 0x0
+#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_EN__SHIFT 0x10
+#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_ST__SHIFT 0x18
+#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK 0x0000FFFFL
+#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_EN_MASK 0x00010000L
+#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_ST_MASK 0x01000000L
+
+
+// addressBlock: nbif_gdc_a2s_GDCA2S_DEC
+//A2S_CNTL_SW0
+#define A2S_CNTL_SW0__STATIC_VC_ENABLE__SHIFT 0x0
+#define A2S_CNTL_SW0__STATIC_VC_VALUE__SHIFT 0x1
+#define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT 0x9
+#define A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa
+#define A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb
+#define A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc
+#define A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT 0x10
+#define A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT 0x18
+#define A2S_CNTL_SW0__STATIC_VC_ENABLE_MASK 0x00000001L
+#define A2S_CNTL_SW0__STATIC_VC_VALUE_MASK 0x0000000EL
+#define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK 0x00000200L
+#define A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L
+#define A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L
+#define A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L
+#define A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK 0x00FF0000L
+#define A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK 0xFF000000L
+//A2S_CNTL_SW1
+#define A2S_CNTL_SW1__STATIC_VC_ENABLE__SHIFT 0x0
+#define A2S_CNTL_SW1__STATIC_VC_VALUE__SHIFT 0x1
+#define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT 0x9
+#define A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa
+#define A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb
+#define A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc
+#define A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT 0x10
+#define A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT 0x18
+#define A2S_CNTL_SW1__STATIC_VC_ENABLE_MASK 0x00000001L
+#define A2S_CNTL_SW1__STATIC_VC_VALUE_MASK 0x0000000EL
+#define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS_MASK 0x00000200L
+#define A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L
+#define A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L
+#define A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L
+#define A2S_CNTL_SW1__WRR_RD_WEIGHT_MASK 0x00FF0000L
+#define A2S_CNTL_SW1__WRR_WR_WEIGHT_MASK 0xFF000000L
+//A2S_MISC_CNTL
+#define A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT 0x0
+#define A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT 0x6
+#define A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0x9
+#define A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK 0x00000003L
+#define A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK 0x00000040L
+#define A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY_MASK 0x00000200L
+//A2S_TAG_ALLOC_0
+#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT 0x0
+#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT 0x8
+#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT 0x10
+#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK 0x000000FFL
+#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK 0x0000FF00L
+#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK 0x00FF0000L
+//A2S_TAG_ALLOC_1
+#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT 0x0
+#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT 0x10
+#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT 0x18
+#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK 0x000000FFL
+#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK 0x00FF0000L
+#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK 0xFF000000L
+
+
+// addressBlock: nbif_syshub_mmreg_syshubdirect
+//HST_CLK0_SW0_CL0_CNTL
+#define HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//HST_CLK0_SW1_CL0_CNTL
+#define HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//DMA_CLK0_SW0_CL0_CNTL
+#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//NIC400_1_ASIB_0_FN_MOD
+#define NIC400_1_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define NIC400_1_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define NIC400_1_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define NIC400_1_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//NIC400_1_IB_0_FN_MOD
+#define NIC400_1_IB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define NIC400_1_IB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define NIC400_1_IB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define NIC400_1_IB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf0_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF0_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF0_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf0_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF0_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf0_BIFDEC2
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF0_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf1_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF1_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF1_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf1_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF1_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf1_BIFDEC2
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF1_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf2_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF2_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF2_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf2_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF2_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf2_BIFDEC2
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF2_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf3_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF3_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF3_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf3_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF3_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf3_BIFDEC2
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF3_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf4_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF4_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF4_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf4_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF4_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf4_BIFDEC2
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF4_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf5_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF5_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF5_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf5_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF5_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf5_BIFDEC2
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF5_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf6_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF6_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF6_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf6_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF6_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf6_BIFDEC2
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF6_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf7_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF7_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF7_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf7_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF7_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf7_BIFDEC2
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF7_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf8_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF8_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF8_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF8_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf8_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF8_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf8_BIFDEC2
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF8_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf9_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF9_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF9_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF9_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf9_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF9_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf9_BIFDEC2
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF9_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf10_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF10_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF10_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF10_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf10_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF10_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf10_BIFDEC2
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF10_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf11_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF11_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF11_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF11_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf11_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF11_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf11_BIFDEC2
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF11_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf12_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF12_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF12_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF12_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf12_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF12_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf12_BIFDEC2
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF12_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf13_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF13_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF13_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF13_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf13_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF13_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf13_BIFDEC2
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF13_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf14_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF14_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF14_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF14_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf14_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF14_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf14_BIFDEC2
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF14_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf15_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF15_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF15_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF15_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf15_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF15_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf15_BIFDEC2
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF15_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf16_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf16_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF16_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF16_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF16_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF16_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF16_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF16_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf16_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF16_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF16_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF16_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF16_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf16_BIFDEC2
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF16_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf17_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf17_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF17_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF17_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF17_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF17_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF17_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF17_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf17_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF17_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF17_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF17_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF17_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf17_BIFDEC2
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF17_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf18_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf18_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF18_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF18_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF18_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF18_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF18_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF18_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf18_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF18_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF18_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF18_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF18_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf18_BIFDEC2
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF18_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf19_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf19_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF19_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF19_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF19_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF19_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF19_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF19_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf19_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF19_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF19_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF19_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF19_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf19_BIFDEC2
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF19_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf20_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf20_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF20_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF20_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF20_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF20_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF20_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF20_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf20_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF20_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF20_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF20_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF20_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf20_BIFDEC2
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF20_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf21_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf21_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF21_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF21_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF21_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF21_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF21_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF21_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf21_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF21_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF21_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF21_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF21_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf21_BIFDEC2
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF21_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf22_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf22_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF22_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF22_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF22_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF22_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF22_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF22_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf22_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF22_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF22_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF22_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF22_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf22_BIFDEC2
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF22_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf23_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbif_bif_bx_dev0_epf0_vf23_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF23_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF23_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF23_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF23_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF23_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF23_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf23_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF23_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF23_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF23_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF23_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbif_rcc_dev0_epf0_vf23_BIFDEC2
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF23_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+
+
+#endif
git.samba.org / sfrench / cifs-2.6.git / commitdiff