drm/i915/vrr: Generate VRR "safe window" for DSB

Looks like TRANS_CHICKEN bit 31 means something totally different
depending on the platform:
TGL: generate VRR "safe window" for DSB
ADL/DG2: make TRANS_SET_CONTEXT_LATENCY effective with VRR

So far we've only set this on ADL/DG2, but when using DSB+VRR
we also need to set it on TGL.

And a quick test on MTL says it doesn't need this bit for either
of those purposes, even though it's still documented as valid
in bspec.

Cc: stable@vger.kernel.org
Fixes: 34d8311f4a1c ("drm/i915/dsb: Re-instate DSB for LUT updates")
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9927
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240306040806.21697-2-ville.syrjala@linux.intel.com
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
(cherry picked from commit 810e4519a1b34b5a0ff0eab32e5b184f533c5ee9)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5d905f932cb4b3f6bdcc65a249570f510046c162..eb5bd0743902065d9b4bcac060d1fd340d448069 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -187,10 +187,11 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
        enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
        /*
-        * TRANS_SET_CONTEXT_LATENCY with VRR enabled
-        * requires this chicken bit on ADL/DG2.
+        * This bit seems to have two meanings depending on the platform:
+        * TGL: generate VRR "safe window" for DSB vblank waits
+        * ADL/DG2: make TRANS_SET_CONTEXT_LATENCY effective with VRR
         */
-       if (DISPLAY_VER(dev_priv) == 13)
+       if (IS_DISPLAY_VER(dev_priv, 12, 13))
                intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
                             0, PIPE_VBLANK_WITH_DELAY);
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e00557e1a57f0cc69ed71dd3dc0e29b8c06cebb1..3b2e49ce29ba03d055f32aab83ea8f048b49c3a9 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4599,7 +4599,7 @@
 #define MTL_CHICKEN_TRANS(trans)       _MMIO_TRANS((trans), \
                                                    _MTL_CHICKEN_TRANS_A, \
                                                    _MTL_CHICKEN_TRANS_B)
-#define   PIPE_VBLANK_WITH_DELAY       REG_BIT(31) /* ADL/DG2 */
+#define   PIPE_VBLANK_WITH_DELAY       REG_BIT(31) /* tgl+ */
 #define   SKL_UNMASK_VBL_TO_PIPE_IN_SRD        REG_BIT(30) /* skl+ */
 #define   HSW_FRAME_START_DELAY_MASK   REG_GENMASK(28, 27)
 #define   HSW_FRAME_START_DELAY(x)     REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)