IB/mlx5: Use cache line size to select CQE stride
authorDaniel Jurgens <danielj@mellanox.com>
Thu, 27 Oct 2016 13:36:41 +0000 (16:36 +0300)
committerDoug Ledford <dledford@redhat.com>
Thu, 17 Nov 2016 01:03:44 +0000 (20:03 -0500)
commit16b0e0695a73b68d8ca40288c8f9614ef208917b
tree33cc55e4a4a7ac46c66cabfdf8be6379b60b39bd
parentefd7f40082a0dfd112eb87ff2124467a5739216f
IB/mlx5: Use cache line size to select CQE stride

When creating kernel CQs use 128B CQE stride if the
cache line size is 128B, 64B otherwise.  This prevents
multiple CQEs from residing in a 128B cache line,
which can cause retries when there are concurrent
read and writes in one cache line.

Tested with IPoIB on PPC64, saw ~5% throughput
improvement.

Fixes: e126ba97dba9 ('mlx5: Add driver for Mellanox Connect-IB adapters')
Signed-off-by: Daniel Jurgens <danielj@mellanox.com>
Signed-off-by: Maor Gottlieb <maorg@mellanox.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>
Signed-off-by: Doug Ledford <dledford@redhat.com>
drivers/infiniband/hw/mlx5/cq.c