Merge branches 'clk-counted', 'clk-imx', 'clk-amlogic', 'clk-binding' and 'clk-rockchip' into clk-next
* clk-counted:
clk: bcm: rpi: Assign ->num before accessing ->hws
clk: bcm: dvp: Assign ->num before accessing ->hws
* clk-imx:
clk: imx: imx8mp: Convert to platform remove callback returning void
clk: imx: imx8mp: Switch to RUNTIME_PM_OPS()
clk: imx: add i.MX95 BLK CTL clk driver
dt-bindings: clock: support i.MX95 Display Master CSR module
dt-bindings: clock: support i.MX95 BLK CTL module
dt-bindings: clock: add i.MX95 clock header
clk: imx: imx8mp: Add pm_runtime support for power saving
* clk-amlogic:
clk: meson: s4: fix module autoloading
clk: meson: fix module license to GPL only
clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF
clk: meson: add vclk driver
clk: meson: pll: print out pll name when unable to lock it
clk: meson: s4: pll: determine maximum register in regmap config
clk: meson: s4: peripherals: determine maximum register in regmap config
clk: meson: a1: pll: determine maximum register in regmap config
clk: meson: a1: peripherals: determine maximum register in regmap config
* clk-binding:
dt-bindings: clock: fixed: Define a preferred node name
* clk-rockchip:
clk: rockchip: rk3568: Add PLL rate for 724 MHz
clk: rockchip: Remove an unused field in struct rockchip_mmc_clock
clk: rockchip: rk3588: Add reset line for HDMI Receiver
clk: rockchip: rk3568: Add missing USB480M_PHY mux
dt-bindings: reset: Define reset id used for HDMI Receiver
dt-bindings: clock: rockchip: add USB480M_PHY mux