arch/arm64/kernel/cpufeature.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Contains CPU feature definitions
   4  *
   5  * Copyright (C) 2015 ARM Ltd.
   6  *
   7  * A note for the weary kernel hacker: the code here is confusing and hard to
   8  * follow! That's partly because it's solving a nasty problem, but also because
   9  * there's a little bit of over-abstraction that tends to obscure what's going
  10  * on behind a maze of helper functions and macros.
  11  *
  12  * The basic problem is that hardware folks have started gluing together CPUs
  13  * with distinct architectural features; in some cases even creating SoCs where
  14  * user-visible instructions are available only on a subset of the available
  15  * cores. We try to address this by snapshotting the feature registers of the
  16  * boot CPU and comparing these with the feature registers of each secondary
  17  * CPU when bringing them up. If there is a mismatch, then we update the
  18  * snapshot state to indicate the lowest-common denominator of the feature,
  19  * known as the "safe" value. This snapshot state can be queried to view the
  20  * "sanitised" value of a feature register.
  21  *
  22  * The sanitised register values are used to decide which capabilities we
  23  * have in the system. These may be in the form of traditional "hwcaps"
  24  * advertised to userspace or internal "cpucaps" which are used to configure
  25  * things like alternative patching and static keys. While a feature mismatch
  26  * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
  27  * may prevent a CPU from being onlined at all.
  28  *
  29  * Some implementation details worth remembering:
  30  *
  31  * - Mismatched features are *always* sanitised to a "safe" value, which
  32  *   usually indicates that the feature is not supported.
  33  *
  34  * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
  35  *   warning when onlining an offending CPU and the kernel will be tainted
  36  *   with TAINT_CPU_OUT_OF_SPEC.
  37  *
  38  * - Features marked as FTR_VISIBLE have their sanitised value visible to
  39  *   userspace. FTR_VISIBLE features in registers that are only visible
  40  *   to EL0 by trapping *must* have a corresponding HWCAP so that late
  41  *   onlining of CPUs cannot lead to features disappearing at runtime.
  42  *
  43  * - A "feature" is typically a 4-bit register field. A "capability" is the
  44  *   high-level description derived from the sanitised field value.
  45  *
  46  * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
  47  *   scheme for fields in ID registers") to understand when feature fields
  48  *   may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly).
  49  *
  50  * - KVM exposes its own view of the feature registers to guest operating
  51  *   systems regardless of FTR_VISIBLE. This is typically driven from the
  52  *   sanitised register values to allow virtual CPUs to be migrated between
  53  *   arbitrary physical CPUs, but some features not present on the host are
  54  *   also advertised and emulated. Look at sys_reg_descs[] for the gory
  55  *   details.
  56  *
  57  * - If the arm64_ftr_bits[] for a register has a missing field, then this
  58  *   field is treated as STRICT RES0, including for read_sanitised_ftr_reg().
  59  *   This is stronger than FTR_HIDDEN and can be used to hide features from
  60  *   KVM guests.
  61  */
  62
  63 #define pr_fmt(fmt) "CPU features: " fmt
  64
  65 #include <linux/bsearch.h>
  66 #include <linux/cpumask.h>
  67 #include <linux/crash_dump.h>
  68 #include <linux/kstrtox.h>
  69 #include <linux/sort.h>
  70 #include <linux/stop_machine.h>
  71 #include <linux/sysfs.h>
  72 #include <linux/types.h>
  73 #include <linux/minmax.h>
  74 #include <linux/mm.h>
  75 #include <linux/cpu.h>
  76 #include <linux/kasan.h>
  77 #include <linux/percpu.h>
  78
  79 #include <asm/cpu.h>
  80 #include <asm/cpufeature.h>
  81 #include <asm/cpu_ops.h>
  82 #include <asm/fpsimd.h>
  83 #include <asm/hwcap.h>
  84 #include <asm/insn.h>
  85 #include <asm/kvm_host.h>
  86 #include <asm/mmu_context.h>
  87 #include <asm/mte.h>
  88 #include <asm/processor.h>
  89 #include <asm/smp.h>
  90 #include <asm/sysreg.h>
  91 #include <asm/traps.h>
  92 #include <asm/vectors.h>
  93 #include <asm/virt.h>
  94
  95 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
  96 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly;
  97
  98 #ifdef CONFIG_COMPAT
  99 #define COMPAT_ELF_HWCAP_DEFAULT        \
 100                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
 101                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
 102                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
 103                                  COMPAT_HWCAP_LPAE)
 104 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
 105 unsigned int compat_elf_hwcap2 __read_mostly;
 106 #endif
 107
 108 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS);
 109 EXPORT_SYMBOL(system_cpucaps);
 110 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS];
 111
 112 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS);
 113
 114 bool arm64_use_ng_mappings = false;
 115 EXPORT_SYMBOL(arm64_use_ng_mappings);
 116
 117 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors;
 118
 119 /*
 120  * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs
 121  * support it?
 122  */
 123 static bool __read_mostly allow_mismatched_32bit_el0;
 124
 125 /*
 126  * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have
 127  * seen at least one CPU capable of 32-bit EL0.
 128  */
 129 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
 130
 131 /*
 132  * Mask of CPUs supporting 32-bit EL0.
 133  * Only valid if arm64_mismatched_32bit_el0 is enabled.
 134  */
 135 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly;
 136
 137 void dump_cpu_features(void)
 138 {
 139         /* file-wide pr_fmt adds "CPU features: " prefix */
 140         pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps);
 141 }
 142
 143 #define ARM64_CPUID_FIELDS(reg, field, min_value)                       \
 144                 .sys_reg = SYS_##reg,                                                   \
 145                 .field_pos = reg##_##field##_SHIFT,                                             \
 146                 .field_width = reg##_##field##_WIDTH,                                           \
 147                 .sign = reg##_##field##_SIGNED,                                                 \
 148                 .min_field_value = reg##_##field##_##min_value,
 149
 150 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 151         {                                               \
 152                 .sign = SIGNED,                         \
 153                 .visible = VISIBLE,                     \
 154                 .strict = STRICT,                       \
 155                 .type = TYPE,                           \
 156                 .shift = SHIFT,                         \
 157                 .width = WIDTH,                         \
 158                 .safe_val = SAFE_VAL,                   \
 159         }
 160
 161 /* Define a feature with unsigned values */
 162 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 163         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 164
 165 /* Define a feature with a signed value */
 166 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 167         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 168
 169 #define ARM64_FTR_END                                   \
 170         {                                               \
 171                 .width = 0,                             \
 172         }
 173
 174 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
 175
 176 static bool __system_matches_cap(unsigned int n);
 177
 178 /*
 179  * NOTE: Any changes to the visibility of features should be kept in
 180  * sync with the documentation of the CPU feature register ABI.
 181  */
 182 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 183         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0),
 184         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0),
 185         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0),
 186         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0),
 187         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0),
 188         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0),
 189         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0),
 190         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0),
 191         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0),
 192         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0),
 193         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0),
 194         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0),
 195         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0),
 196         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0),
 197         ARM64_FTR_END,
 198 };
 199
 200 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 201         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0),
 202         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0),
 203         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0),
 204         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0),
 205         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0),
 206         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0),
 207         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 208                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0),
 209         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 210                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0),
 211         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0),
 212         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0),
 213         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0),
 214         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 215                        FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0),
 216         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 217                        FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0),
 218         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0),
 219         ARM64_FTR_END,
 220 };
 221
 222 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
 223         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0),
 224         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0),
 225         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0),
 226         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),
 227         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0),
 228         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 229                        FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0),
 230         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 231                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0),
 232         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0),
 233         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0),
 234         ARM64_FTR_END,
 235 };
 236
 237 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 238         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0),
 239         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0),
 240         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0),
 241         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0),
 242         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0),
 243         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0),
 244         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 245                                    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0),
 246         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0),
 247         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0),
 248         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI),
 249         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI),
 250         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0),
 251         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0),
 252         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY),
 253         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY),
 254         ARM64_FTR_END,
 255 };
 256
 257 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
 258         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 259                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0),
 260         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0),
 261         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0),
 262         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),
 263                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI),
 264         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI),
 265         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI),
 266                                     FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0),
 267         ARM64_FTR_END,
 268 };
 269
 270 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
 271         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 272                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0),
 273         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 274                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0),
 275         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 276                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0),
 277         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 278                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0),
 279         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 280                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0),
 281         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 282                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0),
 283         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 284                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0),
 285         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 286                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0),
 287         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 288                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0),
 289         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 290                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0),
 291         ARM64_FTR_END,
 292 };
 293
 294 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = {
 295         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 296                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0),
 297         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 298                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0),
 299         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 300                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0),
 301         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 302                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0),
 303         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 304                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0),
 305         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 306                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0),
 307         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 308                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0),
 309         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 310                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0),
 311         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 312                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0),
 313         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 314                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0),
 315         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 316                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0),
 317         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 318                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0),
 319         ARM64_FTR_END,
 320 };
 321
 322 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 323         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0),
 324         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0),
 325         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0),
 326         /*
 327          * Page size not being supported at Stage-2 is not fatal. You
 328          * just give up KVM if PAGE_SIZE isn't supported there. Go fix
 329          * your favourite nesting hypervisor.
 330          *
 331          * There is a small corner case where the hypervisor explicitly
 332          * advertises a given granule size at Stage-2 (value 2) on some
 333          * vCPUs, and uses the fallback to Stage-1 (value 0) for other
 334          * vCPUs. Although this is not forbidden by the architecture, it
 335          * indicates that the hypervisor is being silly (or buggy).
 336          *
 337          * We make no effort to cope with this and pretend that if these
 338          * fields are inconsistent across vCPUs, then it isn't worth
 339          * trying to bring KVM up.
 340          */
 341         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1),
 342         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1),
 343         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1),
 344         /*
 345          * We already refuse to boot CPUs that don't support our configured
 346          * page size, so we can only detect mismatches for a page size other
 347          * than the one we're currently using. Unfortunately, SoCs like this
 348          * exist in the wild so, even though we don't like it, we'll have to go
 349          * along with it and treat them as non-strict.
 350          */
 351         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI),
 352         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI),
 353         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI),
 354
 355         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0),
 356         /* Linux shouldn't care about secure memory */
 357         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0),
 358         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0),
 359         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0),
 360         /*
 361          * Differing PARange is fine as long as all peripherals and memory are mapped
 362          * within the minimum PARange of all CPUs
 363          */
 364         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0),
 365         ARM64_FTR_END,
 366 };
 367
 368 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 369         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0),
 370         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0),
 371         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0),
 372         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0),
 373         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0),
 374         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0),
 375         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0),
 376         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0),
 377         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0),
 378         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0),
 379         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0),
 380         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0),
 381         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0),
 382         ARM64_FTR_END,
 383 };
 384
 385 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 386         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0),
 387         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0),
 388         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0),
 389         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0),
 390         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0),
 391         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0),
 392         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0),
 393         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0),
 394         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0),
 395         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0),
 396         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0),
 397         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0),
 398         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0),
 399         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0),
 400         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0),
 401         ARM64_FTR_END,
 402 };
 403
 404 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = {
 405         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0),
 406         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0),
 407         ARM64_FTR_END,
 408 };
 409
 410 static const struct arm64_ftr_bits ftr_ctr[] = {
 411         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
 412         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1),
 413         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1),
 414         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0),
 415         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0),
 416         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1),
 417         /*
 418          * Linux can handle differing I-cache policies. Userspace JITs will
 419          * make use of *minLine.
 420          * If we have differing I-cache policies, report it as the weakest - VIPT.
 421          */
 422         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT),        /* L1Ip */
 423         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0),
 424         ARM64_FTR_END,
 425 };
 426
 427 static struct arm64_ftr_override __ro_after_init no_override = { };
 428
 429 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 430         .name           = "SYS_CTR_EL0",
 431         .ftr_bits       = ftr_ctr,
 432         .override       = &no_override,
 433 };
 434
 435 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 436         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf),
 437         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0),
 438         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0),
 439         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0),
 440         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0),
 441         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf),
 442         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0),
 443         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0),
 444         ARM64_FTR_END,
 445 };
 446
 447 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 448         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0),
 449         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0),
 450         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0),
 451         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0),
 452         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0),
 453         /*
 454          * We can instantiate multiple PMU instances with different levels
 455          * of support.
 456          */
 457         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0),
 458         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6),
 459         ARM64_FTR_END,
 460 };
 461
 462 static const struct arm64_ftr_bits ftr_mvfr0[] = {
 463         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0),
 464         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0),
 465         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0),
 466         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0),
 467         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0),
 468         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0),
 469         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0),
 470         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0),
 471         ARM64_FTR_END,
 472 };
 473
 474 static const struct arm64_ftr_bits ftr_mvfr1[] = {
 475         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0),
 476         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0),
 477         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0),
 478         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0),
 479         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0),
 480         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0),
 481         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0),
 482         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0),
 483         ARM64_FTR_END,
 484 };
 485
 486 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 487         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0),
 488         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0),
 489         ARM64_FTR_END,
 490 };
 491
 492 static const struct arm64_ftr_bits ftr_dczid[] = {
 493         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1),
 494         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0),
 495         ARM64_FTR_END,
 496 };
 497
 498 static const struct arm64_ftr_bits ftr_gmid[] = {
 499         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0),
 500         ARM64_FTR_END,
 501 };
 502
 503 static const struct arm64_ftr_bits ftr_id_isar0[] = {
 504         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0),
 505         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0),
 506         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0),
 507         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0),
 508         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0),
 509         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0),
 510         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0),
 511         ARM64_FTR_END,
 512 };
 513
 514 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 515         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0),
 516         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0),
 517         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0),
 518         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0),
 519         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0),
 520         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0),
 521         ARM64_FTR_END,
 522 };
 523
 524 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 525         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0),
 526         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0),
 527         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0),
 528         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0),
 529         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0),
 530         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0),
 531         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0),
 532
 533         /*
 534          * SpecSEI = 1 indicates that the PE might generate an SError on an
 535          * external abort on speculative read. It is safe to assume that an
 536          * SError might be generated than it will not be. Hence it has been
 537          * classified as FTR_HIGHER_SAFE.
 538          */
 539         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0),
 540         ARM64_FTR_END,
 541 };
 542
 543 static const struct arm64_ftr_bits ftr_id_isar4[] = {
 544         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0),
 545         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0),
 546         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0),
 547         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0),
 548         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0),
 549         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0),
 550         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0),
 551         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0),
 552         ARM64_FTR_END,
 553 };
 554
 555 static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
 556         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0),
 557         ARM64_FTR_END,
 558 };
 559
 560 static const struct arm64_ftr_bits ftr_id_isar6[] = {
 561         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0),
 562         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0),
 563         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0),
 564         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0),
 565         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0),
 566         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0),
 567         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0),
 568         ARM64_FTR_END,
 569 };
 570
 571 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 572         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0),
 573         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0),
 574         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0),
 575         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0),
 576         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0),
 577         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0),
 578         ARM64_FTR_END,
 579 };
 580
 581 static const struct arm64_ftr_bits ftr_id_pfr1[] = {
 582         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0),
 583         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0),
 584         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0),
 585         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0),
 586         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0),
 587         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0),
 588         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0),
 589         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0),
 590         ARM64_FTR_END,
 591 };
 592
 593 static const struct arm64_ftr_bits ftr_id_pfr2[] = {
 594         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0),
 595         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0),
 596         ARM64_FTR_END,
 597 };
 598
 599 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 600         /* [31:28] TraceFilt */
 601         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0),
 602         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0),
 603         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0),
 604         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0),
 605         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0),
 606         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0),
 607         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0),
 608         ARM64_FTR_END,
 609 };
 610
 611 static const struct arm64_ftr_bits ftr_id_dfr1[] = {
 612         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0),
 613         ARM64_FTR_END,
 614 };
 615
 616 /*
 617  * Common ftr bits for a 32bit register with all hidden, strict
 618  * attributes, with 4bit feature fields and a default safe value of
 619  * 0. Covers the following 32bit registers:
 620  * id_isar[1-3], id_mmfr[1-3]
 621  */
 622 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 623         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 624         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 625         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 626         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 627         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 628         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 629         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 630         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 631         ARM64_FTR_END,
 632 };
 633
 634 /* Table for a single 32bit feature value */
 635 static const struct arm64_ftr_bits ftr_single32[] = {
 636         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
 637         ARM64_FTR_END,
 638 };
 639
 640 static const struct arm64_ftr_bits ftr_raz[] = {
 641         ARM64_FTR_END,
 642 };
 643
 644 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) {      \
 645                 .sys_id = id,                                   \
 646                 .reg =  &(struct arm64_ftr_reg){                \
 647                         .name = id_str,                         \
 648                         .override = (ovr),                      \
 649                         .ftr_bits = &((table)[0]),              \
 650         }}
 651
 652 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr)  \
 653         __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr)
 654
 655 #define ARM64_FTR_REG(id, table)                \
 656         __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override)
 657
 658 struct arm64_ftr_override id_aa64mmfr0_override;
 659 struct arm64_ftr_override id_aa64mmfr1_override;
 660 struct arm64_ftr_override id_aa64mmfr2_override;
 661 struct arm64_ftr_override id_aa64pfr0_override;
 662 struct arm64_ftr_override id_aa64pfr1_override;
 663 struct arm64_ftr_override id_aa64zfr0_override;
 664 struct arm64_ftr_override id_aa64smfr0_override;
 665 struct arm64_ftr_override id_aa64isar1_override;
 666 struct arm64_ftr_override id_aa64isar2_override;
 667
 668 struct arm64_ftr_override arm64_sw_feature_override;
 669
 670 static const struct __ftr_reg_entry {
 671         u32                     sys_id;
 672         struct arm64_ftr_reg    *reg;
 673 } arm64_ftr_regs[] = {
 674
 675         /* Op1 = 0, CRn = 0, CRm = 1 */
 676         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 677         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
 678         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 679         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 680         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 681         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 682         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 683
 684         /* Op1 = 0, CRn = 0, CRm = 2 */
 685         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
 686         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 687         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 688         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 689         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
 690         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 691         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 692         ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
 693
 694         /* Op1 = 0, CRn = 0, CRm = 3 */
 695         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0),
 696         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1),
 697         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 698         ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
 699         ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
 700         ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
 701
 702         /* Op1 = 0, CRn = 0, CRm = 4 */
 703         ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0,
 704                                &id_aa64pfr0_override),
 705         ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1,
 706                                &id_aa64pfr1_override),
 707         ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0,
 708                                &id_aa64zfr0_override),
 709         ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0,
 710                                &id_aa64smfr0_override),
 711
 712         /* Op1 = 0, CRn = 0, CRm = 5 */
 713         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 714         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
 715
 716         /* Op1 = 0, CRn = 0, CRm = 6 */
 717         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 718         ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1,
 719                                &id_aa64isar1_override),
 720         ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2,
 721                                &id_aa64isar2_override),
 722
 723         /* Op1 = 0, CRn = 0, CRm = 7 */
 724         ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0,
 725                                &id_aa64mmfr0_override),
 726         ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1,
 727                                &id_aa64mmfr1_override),
 728         ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2,
 729                                &id_aa64mmfr2_override),
 730         ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3),
 731
 732         /* Op1 = 1, CRn = 0, CRm = 0 */
 733         ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
 734
 735         /* Op1 = 3, CRn = 0, CRm = 0 */
 736         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
 737         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 738
 739         /* Op1 = 3, CRn = 14, CRm = 0 */
 740         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
 741 };
 742
 743 static int search_cmp_ftr_reg(const void *id, const void *regp)
 744 {
 745         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 746 }
 747
 748 /*
 749  * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using
 750  * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 751  * ascending order of sys_id, we use binary search to find a matching
 752  * entry.
 753  *
 754  * returns - Upon success,  matching ftr_reg entry for id.
 755  *         - NULL on failure. It is upto the caller to decide
 756  *           the impact of a failure.
 757  */
 758 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
 759 {
 760         const struct __ftr_reg_entry *ret;
 761
 762         ret = bsearch((const void *)(unsigned long)sys_id,
 763                         arm64_ftr_regs,
 764                         ARRAY_SIZE(arm64_ftr_regs),
 765                         sizeof(arm64_ftr_regs[0]),
 766                         search_cmp_ftr_reg);
 767         if (ret)
 768                 return ret->reg;
 769         return NULL;
 770 }
 771
 772 /*
 773  * get_arm64_ftr_reg - Looks up a feature register entry using
 774  * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn().
 775  *
 776  * returns - Upon success,  matching ftr_reg entry for id.
 777  *         - NULL on failure but with an WARN_ON().
 778  */
 779 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 780 {
 781         struct arm64_ftr_reg *reg;
 782
 783         reg = get_arm64_ftr_reg_nowarn(sys_id);
 784
 785         /*
 786          * Requesting a non-existent register search is an error. Warn
 787          * and let the caller handle it.
 788          */
 789         WARN_ON(!reg);
 790         return reg;
 791 }
 792
 793 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 794                                s64 ftr_val)
 795 {
 796         u64 mask = arm64_ftr_mask(ftrp);
 797
 798         reg &= ~mask;
 799         reg |= (ftr_val << ftrp->shift) & mask;
 800         return reg;
 801 }
 802
 803 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 804                                 s64 cur)
 805 {
 806         s64 ret = 0;
 807
 808         switch (ftrp->type) {
 809         case FTR_EXACT:
 810                 ret = ftrp->safe_val;
 811                 break;
 812         case FTR_LOWER_SAFE:
 813                 ret = min(new, cur);
 814                 break;
 815         case FTR_HIGHER_OR_ZERO_SAFE:
 816                 if (!cur || !new)
 817                         break;
 818                 fallthrough;
 819         case FTR_HIGHER_SAFE:
 820                 ret = max(new, cur);
 821                 break;
 822         default:
 823                 BUG();
 824         }
 825
 826         return ret;
 827 }
 828
 829 static void __init sort_ftr_regs(void)
 830 {
 831         unsigned int i;
 832
 833         for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) {
 834                 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg;
 835                 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits;
 836                 unsigned int j = 0;
 837
 838                 /*
 839                  * Features here must be sorted in descending order with respect
 840                  * to their shift values and should not overlap with each other.
 841                  */
 842                 for (; ftr_bits->width != 0; ftr_bits++, j++) {
 843                         unsigned int width = ftr_reg->ftr_bits[j].width;
 844                         unsigned int shift = ftr_reg->ftr_bits[j].shift;
 845                         unsigned int prev_shift;
 846
 847                         WARN((shift  + width) > 64,
 848                                 "%s has invalid feature at shift %d\n",
 849                                 ftr_reg->name, shift);
 850
 851                         /*
 852                          * Skip the first feature. There is nothing to
 853                          * compare against for now.
 854                          */
 855                         if (j == 0)
 856                                 continue;
 857
 858                         prev_shift = ftr_reg->ftr_bits[j - 1].shift;
 859                         WARN((shift + width) > prev_shift,
 860                                 "%s has feature overlap at shift %d\n",
 861                                 ftr_reg->name, shift);
 862                 }
 863
 864                 /*
 865                  * Skip the first register. There is nothing to
 866                  * compare against for now.
 867                  */
 868                 if (i == 0)
 869                         continue;
 870                 /*
 871                  * Registers here must be sorted in ascending order with respect
 872                  * to sys_id for subsequent binary search in get_arm64_ftr_reg()
 873                  * to work correctly.
 874                  */
 875                 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id);
 876         }
 877 }
 878
 879 /*
 880  * Initialise the CPU feature register from Boot CPU values.
 881  * Also initiliases the strict_mask for the register.
 882  * Any bits that are not covered by an arm64_ftr_bits entry are considered
 883  * RES0 for the system-wide value, and must strictly match.
 884  */
 885 static void init_cpu_ftr_reg(u32 sys_reg, u64 new)
 886 {
 887         u64 val = 0;
 888         u64 strict_mask = ~0x0ULL;
 889         u64 user_mask = 0;
 890         u64 valid_mask = 0;
 891
 892         const struct arm64_ftr_bits *ftrp;
 893         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 894
 895         if (!reg)
 896                 return;
 897
 898         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 899                 u64 ftr_mask = arm64_ftr_mask(ftrp);
 900                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 901                 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val);
 902
 903                 if ((ftr_mask & reg->override->mask) == ftr_mask) {
 904                         s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new);
 905                         char *str = NULL;
 906
 907                         if (ftr_ovr != tmp) {
 908                                 /* Unsafe, remove the override */
 909                                 reg->override->mask &= ~ftr_mask;
 910                                 reg->override->val &= ~ftr_mask;
 911                                 tmp = ftr_ovr;
 912                                 str = "ignoring override";
 913                         } else if (ftr_new != tmp) {
 914                                 /* Override was valid */
 915                                 ftr_new = tmp;
 916                                 str = "forced";
 917                         } else if (ftr_ovr == tmp) {
 918                                 /* Override was the safe value */
 919                                 str = "already set";
 920                         }
 921
 922                         if (str)
 923                                 pr_warn("%s[%d:%d]: %s to %llx\n",
 924                                         reg->name,
 925                                         ftrp->shift + ftrp->width - 1,
 926                                         ftrp->shift, str, tmp);
 927                 } else if ((ftr_mask & reg->override->val) == ftr_mask) {
 928                         reg->override->val &= ~ftr_mask;
 929                         pr_warn("%s[%d:%d]: impossible override, ignored\n",
 930                                 reg->name,
 931                                 ftrp->shift + ftrp->width - 1,
 932                                 ftrp->shift);
 933                 }
 934
 935                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 936
 937                 valid_mask |= ftr_mask;
 938                 if (!ftrp->strict)
 939                         strict_mask &= ~ftr_mask;
 940                 if (ftrp->visible)
 941                         user_mask |= ftr_mask;
 942                 else
 943                         reg->user_val = arm64_ftr_set_value(ftrp,
 944                                                             reg->user_val,
 945                                                             ftrp->safe_val);
 946         }
 947
 948         val &= valid_mask;
 949
 950         reg->sys_val = val;
 951         reg->strict_mask = strict_mask;
 952         reg->user_mask = user_mask;
 953 }
 954
 955 extern const struct arm64_cpu_capabilities arm64_errata[];
 956 static const struct arm64_cpu_capabilities arm64_features[];
 957
 958 static void __init
 959 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
 960 {
 961         for (; caps->matches; caps++) {
 962                 if (WARN(caps->capability >= ARM64_NCAPS,
 963                         "Invalid capability %d\n", caps->capability))
 964                         continue;
 965                 if (WARN(cpucap_ptrs[caps->capability],
 966                         "Duplicate entry for capability %d\n",
 967                         caps->capability))
 968                         continue;
 969                 cpucap_ptrs[caps->capability] = caps;
 970         }
 971 }
 972
 973 static void __init init_cpucap_indirect_list(void)
 974 {
 975         init_cpucap_indirect_list_from_array(arm64_features);
 976         init_cpucap_indirect_list_from_array(arm64_errata);
 977 }
 978
 979 static void __init setup_boot_cpu_capabilities(void);
 980
 981 static void init_32bit_cpu_features(struct cpuinfo_32bit *info)
 982 {
 983         init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 984         init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);
 985         init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 986         init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 987         init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 988         init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 989         init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 990         init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 991         init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
 992         init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 993         init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 994         init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 995         init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 996         init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4);
 997         init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
 998         init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 999         init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
1000         init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
1001         init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
1002         init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
1003         init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
1004 }
1005
1006 #ifdef CONFIG_ARM64_PSEUDO_NMI
1007 static bool enable_pseudo_nmi;
1008
1009 static int __init early_enable_pseudo_nmi(char *p)
1010 {
1011         return kstrtobool(p, &enable_pseudo_nmi);
1012 }
1013 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1014
1015 static __init void detect_system_supports_pseudo_nmi(void)
1016 {
1017         struct device_node *np;
1018
1019         if (!enable_pseudo_nmi)
1020                 return;
1021
1022         /*
1023          * Detect broken MediaTek firmware that doesn't properly save and
1024          * restore GIC priorities.
1025          */
1026         np = of_find_compatible_node(NULL, NULL, "arm,gic-v3");
1027         if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) {
1028                 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n");
1029                 enable_pseudo_nmi = false;
1030         }
1031         of_node_put(np);
1032 }
1033 #else /* CONFIG_ARM64_PSEUDO_NMI */
1034 static inline void detect_system_supports_pseudo_nmi(void) { }
1035 #endif
1036
1037 void __init init_cpu_features(struct cpuinfo_arm64 *info)
1038 {
1039         /* Before we start using the tables, make sure it is sorted */
1040         sort_ftr_regs();
1041
1042         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
1043         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
1044         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
1045         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
1046         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
1047         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
1048         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
1049         init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
1050         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
1051         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
1052         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
1053         init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3);
1054         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
1055         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
1056         init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
1057         init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0);
1058
1059         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
1060                 init_32bit_cpu_features(&info->aarch32);
1061
1062         if (IS_ENABLED(CONFIG_ARM64_SVE) &&
1063             id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) {
1064                 unsigned long cpacr = cpacr_save_enable_kernel_sve();
1065
1066                 vec_init_vq_map(ARM64_VEC_SVE);
1067
1068                 cpacr_restore(cpacr);
1069         }
1070
1071         if (IS_ENABLED(CONFIG_ARM64_SME) &&
1072             id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) {
1073                 unsigned long cpacr = cpacr_save_enable_kernel_sme();
1074
1075                 /*
1076                  * We mask out SMPS since even if the hardware
1077                  * supports priorities the kernel does not at present
1078                  * and we block access to them.
1079                  */
1080                 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS;
1081                 vec_init_vq_map(ARM64_VEC_SME);
1082
1083                 cpacr_restore(cpacr);
1084         }
1085
1086         if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
1087                 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);
1088 }
1089
1090 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
1091 {
1092         const struct arm64_ftr_bits *ftrp;
1093
1094         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
1095                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
1096                 s64 ftr_new = arm64_ftr_value(ftrp, new);
1097
1098                 if (ftr_cur == ftr_new)
1099                         continue;
1100                 /* Find a safe value */
1101                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
1102                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
1103         }
1104
1105 }
1106
1107 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
1108 {
1109         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1110
1111         if (!regp)
1112                 return 0;
1113
1114         update_cpu_ftr_reg(regp, val);
1115         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
1116                 return 0;
1117         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
1118                         regp->name, boot, cpu, val);
1119         return 1;
1120 }
1121
1122 static void relax_cpu_ftr_reg(u32 sys_id, int field)
1123 {
1124         const struct arm64_ftr_bits *ftrp;
1125         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1126
1127         if (!regp)
1128                 return;
1129
1130         for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
1131                 if (ftrp->shift == field) {
1132                         regp->strict_mask &= ~arm64_ftr_mask(ftrp);
1133                         break;
1134                 }
1135         }
1136
1137         /* Bogus field? */
1138         WARN_ON(!ftrp->width);
1139 }
1140
1141 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info,
1142                                          struct cpuinfo_arm64 *boot)
1143 {
1144         static bool boot_cpu_32bit_regs_overridden = false;
1145
1146         if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden)
1147                 return;
1148
1149         if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0))
1150                 return;
1151
1152         boot->aarch32 = info->aarch32;
1153         init_32bit_cpu_features(&boot->aarch32);
1154         boot_cpu_32bit_regs_overridden = true;
1155 }
1156
1157 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info,
1158                                      struct cpuinfo_32bit *boot)
1159 {
1160         int taint = 0;
1161         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1162
1163         /*
1164          * If we don't have AArch32 at EL1, then relax the strictness of
1165          * EL1-dependent register fields to avoid spurious sanity check fails.
1166          */
1167         if (!id_aa64pfr0_32bit_el1(pfr0)) {
1168                 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT);
1169                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT);
1170                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT);
1171                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT);
1172                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT);
1173                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT);
1174         }
1175
1176         taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
1177                                       info->reg_id_dfr0, boot->reg_id_dfr0);
1178         taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu,
1179                                       info->reg_id_dfr1, boot->reg_id_dfr1);
1180         taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
1181                                       info->reg_id_isar0, boot->reg_id_isar0);
1182         taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
1183                                       info->reg_id_isar1, boot->reg_id_isar1);
1184         taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
1185                                       info->reg_id_isar2, boot->reg_id_isar2);
1186         taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
1187                                       info->reg_id_isar3, boot->reg_id_isar3);
1188         taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
1189                                       info->reg_id_isar4, boot->reg_id_isar4);
1190         taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
1191                                       info->reg_id_isar5, boot->reg_id_isar5);
1192         taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
1193                                       info->reg_id_isar6, boot->reg_id_isar6);
1194
1195         /*
1196          * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
1197          * ACTLR formats could differ across CPUs and therefore would have to
1198          * be trapped for virtualization anyway.
1199          */
1200         taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
1201                                       info->reg_id_mmfr0, boot->reg_id_mmfr0);
1202         taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
1203                                       info->reg_id_mmfr1, boot->reg_id_mmfr1);
1204         taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
1205                                       info->reg_id_mmfr2, boot->reg_id_mmfr2);
1206         taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
1207                                       info->reg_id_mmfr3, boot->reg_id_mmfr3);
1208         taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
1209                                       info->reg_id_mmfr4, boot->reg_id_mmfr4);
1210         taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
1211                                       info->reg_id_mmfr5, boot->reg_id_mmfr5);
1212         taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
1213                                       info->reg_id_pfr0, boot->reg_id_pfr0);
1214         taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
1215                                       info->reg_id_pfr1, boot->reg_id_pfr1);
1216         taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
1217                                       info->reg_id_pfr2, boot->reg_id_pfr2);
1218         taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
1219                                       info->reg_mvfr0, boot->reg_mvfr0);
1220         taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
1221                                       info->reg_mvfr1, boot->reg_mvfr1);
1222         taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
1223                                       info->reg_mvfr2, boot->reg_mvfr2);
1224
1225         return taint;
1226 }
1227
1228 /*
1229  * Update system wide CPU feature registers with the values from a
1230  * non-boot CPU. Also performs SANITY checks to make sure that there
1231  * aren't any insane variations from that of the boot CPU.
1232  */
1233 void update_cpu_features(int cpu,
1234                          struct cpuinfo_arm64 *info,
1235                          struct cpuinfo_arm64 *boot)
1236 {
1237         int taint = 0;
1238
1239         /*
1240          * The kernel can handle differing I-cache policies, but otherwise
1241          * caches should look identical. Userspace JITs will make use of
1242          * *minLine.
1243          */
1244         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
1245                                       info->reg_ctr, boot->reg_ctr);
1246
1247         /*
1248          * Userspace may perform DC ZVA instructions. Mismatched block sizes
1249          * could result in too much or too little memory being zeroed if a
1250          * process is preempted and migrated between CPUs.
1251          */
1252         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
1253                                       info->reg_dczid, boot->reg_dczid);
1254
1255         /* If different, timekeeping will be broken (especially with KVM) */
1256         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
1257                                       info->reg_cntfrq, boot->reg_cntfrq);
1258
1259         /*
1260          * The kernel uses self-hosted debug features and expects CPUs to
1261          * support identical debug features. We presently need CTX_CMPs, WRPs,
1262          * and BRPs to be identical.
1263          * ID_AA64DFR1 is currently RES0.
1264          */
1265         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
1266                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
1267         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
1268                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
1269         /*
1270          * Even in big.LITTLE, processors should be identical instruction-set
1271          * wise.
1272          */
1273         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
1274                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
1275         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
1276                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
1277         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
1278                                       info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
1279
1280         /*
1281          * Differing PARange support is fine as long as all peripherals and
1282          * memory are mapped within the minimum PARange of all CPUs.
1283          * Linux should not care about secure memory.
1284          */
1285         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
1286                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
1287         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
1288                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
1289         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
1290                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
1291         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu,
1292                                       info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3);
1293
1294         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
1295                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
1296         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
1297                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
1298
1299         taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
1300                                       info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
1301
1302         taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu,
1303                                       info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0);
1304
1305         /* Probe vector lengths */
1306         if (IS_ENABLED(CONFIG_ARM64_SVE) &&
1307             id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) {
1308                 if (!system_capabilities_finalized()) {
1309                         unsigned long cpacr = cpacr_save_enable_kernel_sve();
1310
1311                         vec_update_vq_map(ARM64_VEC_SVE);
1312
1313                         cpacr_restore(cpacr);
1314                 }
1315         }
1316
1317         if (IS_ENABLED(CONFIG_ARM64_SME) &&
1318             id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) {
1319                 unsigned long cpacr = cpacr_save_enable_kernel_sme();
1320
1321                 /*
1322                  * We mask out SMPS since even if the hardware
1323                  * supports priorities the kernel does not at present
1324                  * and we block access to them.
1325                  */
1326                 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS;
1327
1328                 /* Probe vector lengths */
1329                 if (!system_capabilities_finalized())
1330                         vec_update_vq_map(ARM64_VEC_SME);
1331
1332                 cpacr_restore(cpacr);
1333         }
1334
1335         /*
1336          * The kernel uses the LDGM/STGM instructions and the number of tags
1337          * they read/write depends on the GMID_EL1.BS field. Check that the
1338          * value is the same on all CPUs.
1339          */
1340         if (IS_ENABLED(CONFIG_ARM64_MTE) &&
1341             id_aa64pfr1_mte(info->reg_id_aa64pfr1)) {
1342                 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,
1343                                               info->reg_gmid, boot->reg_gmid);
1344         }
1345
1346         /*
1347          * If we don't have AArch32 at all then skip the checks entirely
1348          * as the register values may be UNKNOWN and we're not going to be
1349          * using them for anything.
1350          *
1351          * This relies on a sanitised view of the AArch64 ID registers
1352          * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
1353          */
1354         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
1355                 lazy_init_32bit_cpu_features(info, boot);
1356                 taint |= update_32bit_cpu_features(cpu, &info->aarch32,
1357                                                    &boot->aarch32);
1358         }
1359
1360         /*
1361          * Mismatched CPU features are a recipe for disaster. Don't even
1362          * pretend to support them.
1363          */
1364         if (taint) {
1365                 pr_warn_once("Unsupported CPU feature variation detected.\n");
1366                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1367         }
1368 }
1369
1370 u64 read_sanitised_ftr_reg(u32 id)
1371 {
1372         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
1373
1374         if (!regp)
1375                 return 0;
1376         return regp->sys_val;
1377 }
1378 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
1379
1380 #define read_sysreg_case(r)     \
1381         case r:         val = read_sysreg_s(r); break;
1382
1383 /*
1384  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
1385  * Read the system register on the current CPU
1386  */
1387 u64 __read_sysreg_by_encoding(u32 sys_id)
1388 {
1389         struct arm64_ftr_reg *regp;
1390         u64 val;
1391
1392         switch (sys_id) {
1393         read_sysreg_case(SYS_ID_PFR0_EL1);
1394         read_sysreg_case(SYS_ID_PFR1_EL1);
1395         read_sysreg_case(SYS_ID_PFR2_EL1);
1396         read_sysreg_case(SYS_ID_DFR0_EL1);
1397         read_sysreg_case(SYS_ID_DFR1_EL1);
1398         read_sysreg_case(SYS_ID_MMFR0_EL1);
1399         read_sysreg_case(SYS_ID_MMFR1_EL1);
1400         read_sysreg_case(SYS_ID_MMFR2_EL1);
1401         read_sysreg_case(SYS_ID_MMFR3_EL1);
1402         read_sysreg_case(SYS_ID_MMFR4_EL1);
1403         read_sysreg_case(SYS_ID_MMFR5_EL1);
1404         read_sysreg_case(SYS_ID_ISAR0_EL1);
1405         read_sysreg_case(SYS_ID_ISAR1_EL1);
1406         read_sysreg_case(SYS_ID_ISAR2_EL1);
1407         read_sysreg_case(SYS_ID_ISAR3_EL1);
1408         read_sysreg_case(SYS_ID_ISAR4_EL1);
1409         read_sysreg_case(SYS_ID_ISAR5_EL1);
1410         read_sysreg_case(SYS_ID_ISAR6_EL1);
1411         read_sysreg_case(SYS_MVFR0_EL1);
1412         read_sysreg_case(SYS_MVFR1_EL1);
1413         read_sysreg_case(SYS_MVFR2_EL1);
1414
1415         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1416         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
1417         read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
1418         read_sysreg_case(SYS_ID_AA64SMFR0_EL1);
1419         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1420         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1421         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1422         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1423         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1424         read_sysreg_case(SYS_ID_AA64MMFR3_EL1);
1425         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1426         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1427         read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
1428
1429         read_sysreg_case(SYS_CNTFRQ_EL0);
1430         read_sysreg_case(SYS_CTR_EL0);
1431         read_sysreg_case(SYS_DCZID_EL0);
1432
1433         default:
1434                 BUG();
1435                 return 0;
1436         }
1437
1438         regp  = get_arm64_ftr_reg(sys_id);
1439         if (regp) {
1440                 val &= ~regp->override->mask;
1441                 val |= (regp->override->val & regp->override->mask);
1442         }
1443
1444         return val;
1445 }
1446
1447 #include <linux/irqchip/arm-gic-v3.h>
1448
1449 static bool
1450 has_always(const struct arm64_cpu_capabilities *entry, int scope)
1451 {
1452         return true;
1453 }
1454
1455 static bool
1456 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1457 {
1458         int val = cpuid_feature_extract_field_width(reg, entry->field_pos,
1459                                                     entry->field_width,
1460                                                     entry->sign);
1461
1462         return val >= entry->min_field_value;
1463 }
1464
1465 static u64
1466 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope)
1467 {
1468         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1469         if (scope == SCOPE_SYSTEM)
1470                 return read_sanitised_ftr_reg(entry->sys_reg);
1471         else
1472                 return __read_sysreg_by_encoding(entry->sys_reg);
1473 }
1474
1475 static bool
1476 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1477 {
1478         int mask;
1479         struct arm64_ftr_reg *regp;
1480         u64 val = read_scoped_sysreg(entry, scope);
1481
1482         regp = get_arm64_ftr_reg(entry->sys_reg);
1483         if (!regp)
1484                 return false;
1485
1486         mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask,
1487                                                           entry->field_pos,
1488                                                           entry->field_width);
1489         if (!mask)
1490                 return false;
1491
1492         return feature_matches(val, entry);
1493 }
1494
1495 static bool
1496 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1497 {
1498         u64 val = read_scoped_sysreg(entry, scope);
1499         return feature_matches(val, entry);
1500 }
1501
1502 const struct cpumask *system_32bit_el0_cpumask(void)
1503 {
1504         if (!system_supports_32bit_el0())
1505                 return cpu_none_mask;
1506
1507         if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
1508                 return cpu_32bit_el0_mask;
1509
1510         return cpu_possible_mask;
1511 }
1512
1513 static int __init parse_32bit_el0_param(char *str)
1514 {
1515         allow_mismatched_32bit_el0 = true;
1516         return 0;
1517 }
1518 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param);
1519
1520 static ssize_t aarch32_el0_show(struct device *dev,
1521                                 struct device_attribute *attr, char *buf)
1522 {
1523         const struct cpumask *mask = system_32bit_el0_cpumask();
1524
1525         return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask));
1526 }
1527 static const DEVICE_ATTR_RO(aarch32_el0);
1528
1529 static int __init aarch32_el0_sysfs_init(void)
1530 {
1531         struct device *dev_root;
1532         int ret = 0;
1533
1534         if (!allow_mismatched_32bit_el0)
1535                 return 0;
1536
1537         dev_root = bus_get_dev_root(&cpu_subsys);
1538         if (dev_root) {
1539                 ret = device_create_file(dev_root, &dev_attr_aarch32_el0);
1540                 put_device(dev_root);
1541         }
1542         return ret;
1543 }
1544 device_initcall(aarch32_el0_sysfs_init);
1545
1546 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope)
1547 {
1548         if (!has_cpuid_feature(entry, scope))
1549                 return allow_mismatched_32bit_el0;
1550
1551         if (scope == SCOPE_SYSTEM)
1552                 pr_info("detected: 32-bit EL0 Support\n");
1553
1554         return true;
1555 }
1556
1557 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
1558 {
1559         bool has_sre;
1560
1561         if (!has_cpuid_feature(entry, scope))
1562                 return false;
1563
1564         has_sre = gic_enable_sre();
1565         if (!has_sre)
1566                 pr_warn_once("%s present but disabled by higher exception level\n",
1567                              entry->desc);
1568
1569         return has_sre;
1570 }
1571
1572 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
1573                           int scope)
1574 {
1575         u64 ctr;
1576
1577         if (scope == SCOPE_SYSTEM)
1578                 ctr = arm64_ftr_reg_ctrel0.sys_val;
1579         else
1580                 ctr = read_cpuid_effective_cachetype();
1581
1582         return ctr & BIT(CTR_EL0_IDC_SHIFT);
1583 }
1584
1585 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1586 {
1587         /*
1588          * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1589          * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1590          * to the CTR_EL0 on this CPU and emulate it with the real/safe
1591          * value.
1592          */
1593         if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT)))
1594                 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1595 }
1596
1597 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
1598                           int scope)
1599 {
1600         u64 ctr;
1601
1602         if (scope == SCOPE_SYSTEM)
1603                 ctr = arm64_ftr_reg_ctrel0.sys_val;
1604         else
1605                 ctr = read_cpuid_cachetype();
1606
1607         return ctr & BIT(CTR_EL0_DIC_SHIFT);
1608 }
1609
1610 static bool __maybe_unused
1611 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1612 {
1613         /*
1614          * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1615          * may share TLB entries with a CPU stuck in the crashed
1616          * kernel.
1617          */
1618         if (is_kdump_kernel())
1619                 return false;
1620
1621         if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP))
1622                 return false;
1623
1624         return has_cpuid_feature(entry, scope);
1625 }
1626
1627 static bool __meltdown_safe = true;
1628 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1629
1630 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1631                                 int scope)
1632 {
1633         /* List of CPUs that are not vulnerable and don't need KPTI */
1634         static const struct midr_range kpti_safe_list[] = {
1635                 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1636                 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1637                 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1638                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1639                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1640                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1641                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1642                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1643                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1644                 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1645                 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1646                 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD),
1647                 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
1648                 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
1649                 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
1650                 { /* sentinel */ }
1651         };
1652         char const *str = "kpti command line option";
1653         bool meltdown_safe;
1654
1655         meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1656
1657         /* Defer to CPU feature registers */
1658         if (has_cpuid_feature(entry, scope))
1659                 meltdown_safe = true;
1660
1661         if (!meltdown_safe)
1662                 __meltdown_safe = false;
1663
1664         /*
1665          * For reasons that aren't entirely clear, enabling KPTI on Cavium
1666          * ThunderX leads to apparent I-cache corruption of kernel text, which
1667          * ends as well as you might imagine. Don't even try. We cannot rely
1668          * on the cpus_have_*cap() helpers here to detect the CPU erratum
1669          * because cpucap detection order may change. However, since we know
1670          * affected CPUs are always in a homogeneous configuration, it is
1671          * safe to rely on this_cpu_has_cap() here.
1672          */
1673         if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1674                 str = "ARM64_WORKAROUND_CAVIUM_27456";
1675                 __kpti_forced = -1;
1676         }
1677
1678         /* Useful for KASLR robustness */
1679         if (kaslr_enabled() && kaslr_requires_kpti()) {
1680                 if (!__kpti_forced) {
1681                         str = "KASLR";
1682                         __kpti_forced = 1;
1683                 }
1684         }
1685
1686         if (cpu_mitigations_off() && !__kpti_forced) {
1687                 str = "mitigations=off";
1688                 __kpti_forced = -1;
1689         }
1690
1691         if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1692                 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1693                 return false;
1694         }
1695
1696         /* Forced? */
1697         if (__kpti_forced) {
1698                 pr_info_once("kernel page table isolation forced %s by %s\n",
1699                              __kpti_forced > 0 ? "ON" : "OFF", str);
1700                 return __kpti_forced > 0;
1701         }
1702
1703         return !meltdown_safe;
1704 }
1705
1706 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2)
1707 static bool has_lpa2_at_stage1(u64 mmfr0)
1708 {
1709         unsigned int tgran;
1710
1711         tgran = cpuid_feature_extract_unsigned_field(mmfr0,
1712                                         ID_AA64MMFR0_EL1_TGRAN_SHIFT);
1713         return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2;
1714 }
1715
1716 static bool has_lpa2_at_stage2(u64 mmfr0)
1717 {
1718         unsigned int tgran;
1719
1720         tgran = cpuid_feature_extract_unsigned_field(mmfr0,
1721                                         ID_AA64MMFR0_EL1_TGRAN_2_SHIFT);
1722         return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2;
1723 }
1724
1725 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope)
1726 {
1727         u64 mmfr0;
1728
1729         mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
1730         return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0);
1731 }
1732 #else
1733 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope)
1734 {
1735         return false;
1736 }
1737 #endif
1738
1739 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1740 #define KPTI_NG_TEMP_VA         (-(1UL << PMD_SHIFT))
1741
1742 extern
1743 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt,
1744                              phys_addr_t size, pgprot_t prot,
1745                              phys_addr_t (*pgtable_alloc)(int), int flags);
1746
1747 static phys_addr_t __initdata kpti_ng_temp_alloc;
1748
1749 static phys_addr_t __init kpti_ng_pgd_alloc(int shift)
1750 {
1751         kpti_ng_temp_alloc -= PAGE_SIZE;
1752         return kpti_ng_temp_alloc;
1753 }
1754
1755 static int __init __kpti_install_ng_mappings(void *__unused)
1756 {
1757         typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long);
1758         extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1759         kpti_remap_fn *remap_fn;
1760
1761         int cpu = smp_processor_id();
1762         int levels = CONFIG_PGTABLE_LEVELS;
1763         int order = order_base_2(levels);
1764         u64 kpti_ng_temp_pgd_pa = 0;
1765         pgd_t *kpti_ng_temp_pgd;
1766         u64 alloc = 0;
1767
1768         if (levels == 5 && !pgtable_l5_enabled())
1769                 levels = 4;
1770         else if (levels == 4 && !pgtable_l4_enabled())
1771                 levels = 3;
1772
1773         remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1774
1775         if (!cpu) {
1776                 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order);
1777                 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE);
1778                 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd);
1779
1780                 //
1781                 // Create a minimal page table hierarchy that permits us to map
1782                 // the swapper page tables temporarily as we traverse them.
1783                 //
1784                 // The physical pages are laid out as follows:
1785                 //
1786                 // +--------+-/-------+-/------ +-/------ +-\\\--------+
1787                 // :  PTE[] : | PMD[] : | PUD[] : | P4D[] : ||| PGD[]  :
1788                 // +--------+-\-------+-\------ +-\------ +-///--------+
1789                 //      ^
1790                 // The first page is mapped into this hierarchy at a PMD_SHIFT
1791                 // aligned virtual address, so that we can manipulate the PTE
1792                 // level entries while the mapping is active. The first entry
1793                 // covers the PTE[] page itself, the remaining entries are free
1794                 // to be used as a ad-hoc fixmap.
1795                 //
1796                 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc),
1797                                         KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL,
1798                                         kpti_ng_pgd_alloc, 0);
1799         }
1800
1801         cpu_install_idmap();
1802         remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA);
1803         cpu_uninstall_idmap();
1804
1805         if (!cpu) {
1806                 free_pages(alloc, order);
1807                 arm64_use_ng_mappings = true;
1808         }
1809
1810         return 0;
1811 }
1812
1813 static void __init kpti_install_ng_mappings(void)
1814 {
1815         /* Check whether KPTI is going to be used */
1816         if (!arm64_kernel_unmapped_at_el0())
1817                 return;
1818
1819         /*
1820          * We don't need to rewrite the page-tables if either we've done
1821          * it already or we have KASLR enabled and therefore have not
1822          * created any global mappings at all.
1823          */
1824         if (arm64_use_ng_mappings)
1825                 return;
1826
1827         stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask);
1828 }
1829
1830 #else
1831 static inline void kpti_install_ng_mappings(void)
1832 {
1833 }
1834 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1835
1836 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap)
1837 {
1838         if (__this_cpu_read(this_cpu_vector) == vectors) {
1839                 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);
1840
1841                 __this_cpu_write(this_cpu_vector, v);
1842         }
1843
1844 }
1845
1846 static int __init parse_kpti(char *str)
1847 {
1848         bool enabled;
1849         int ret = kstrtobool(str, &enabled);
1850
1851         if (ret)
1852                 return ret;
1853
1854         __kpti_forced = enabled ? 1 : -1;
1855         return 0;
1856 }
1857 early_param("kpti", parse_kpti);
1858
1859 #ifdef CONFIG_ARM64_HW_AFDBM
1860 static struct cpumask dbm_cpus __read_mostly;
1861
1862 static inline void __cpu_enable_hw_dbm(void)
1863 {
1864         u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1865
1866         write_sysreg(tcr, tcr_el1);
1867         isb();
1868         local_flush_tlb_all();
1869 }
1870
1871 static bool cpu_has_broken_dbm(void)
1872 {
1873         /* List of CPUs which have broken DBM support. */
1874         static const struct midr_range cpus[] = {
1875 #ifdef CONFIG_ARM64_ERRATUM_1024718
1876                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1877                 /* Kryo4xx Silver (rdpe => r1p0) */
1878                 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
1879 #endif
1880 #ifdef CONFIG_ARM64_ERRATUM_2051678
1881                 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2),
1882 #endif
1883                 {},
1884         };
1885
1886         return is_midr_in_range_list(read_cpuid_id(), cpus);
1887 }
1888
1889 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1890 {
1891         return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1892                !cpu_has_broken_dbm();
1893 }
1894
1895 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1896 {
1897         if (cpu_can_use_dbm(cap)) {
1898                 __cpu_enable_hw_dbm();
1899                 cpumask_set_cpu(smp_processor_id(), &dbm_cpus);
1900         }
1901 }
1902
1903 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1904                        int __unused)
1905 {
1906         /*
1907          * DBM is a non-conflicting feature. i.e, the kernel can safely
1908          * run a mix of CPUs with and without the feature. So, we
1909          * unconditionally enable the capability to allow any late CPU
1910          * to use the feature. We only enable the control bits on the
1911          * CPU, if it is supported.
1912          */
1913
1914         return true;
1915 }
1916
1917 #endif
1918
1919 #ifdef CONFIG_ARM64_AMU_EXTN
1920
1921 /*
1922  * The "amu_cpus" cpumask only signals that the CPU implementation for the
1923  * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1924  * information regarding all the events that it supports. When a CPU bit is
1925  * set in the cpumask, the user of this feature can only rely on the presence
1926  * of the 4 fixed counters for that CPU. But this does not guarantee that the
1927  * counters are enabled or access to these counters is enabled by code
1928  * executed at higher exception levels (firmware).
1929  */
1930 static struct cpumask amu_cpus __read_mostly;
1931
1932 bool cpu_has_amu_feat(int cpu)
1933 {
1934         return cpumask_test_cpu(cpu, &amu_cpus);
1935 }
1936
1937 int get_cpu_with_amu_feat(void)
1938 {
1939         return cpumask_any(&amu_cpus);
1940 }
1941
1942 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1943 {
1944         if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1945                 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
1946
1947                 /* 0 reference values signal broken/disabled counters */
1948                 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168))
1949                         update_freq_counters_refs();
1950         }
1951 }
1952
1953 static bool has_amu(const struct arm64_cpu_capabilities *cap,
1954                     int __unused)
1955 {
1956         /*
1957          * The AMU extension is a non-conflicting feature: the kernel can
1958          * safely run a mix of CPUs with and without support for the
1959          * activity monitors extension. Therefore, unconditionally enable
1960          * the capability to allow any late CPU to use the feature.
1961          *
1962          * With this feature unconditionally enabled, the cpu_enable
1963          * function will be called for all CPUs that match the criteria,
1964          * including secondary and hotplugged, marking this feature as
1965          * present on that respective CPU. The enable function will also
1966          * print a detection message.
1967          */
1968
1969         return true;
1970 }
1971 #else
1972 int get_cpu_with_amu_feat(void)
1973 {
1974         return nr_cpu_ids;
1975 }
1976 #endif
1977
1978 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1979 {
1980         return is_kernel_in_hyp_mode();
1981 }
1982
1983 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1984 {
1985         /*
1986          * Copy register values that aren't redirected by hardware.
1987          *
1988          * Before code patching, we only set tpidr_el1, all CPUs need to copy
1989          * this value to tpidr_el2 before we patch the code. Once we've done
1990          * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1991          * do anything here.
1992          */
1993         if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1994                 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1995 }
1996
1997 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap,
1998                                     int scope)
1999 {
2000         if (kvm_get_mode() != KVM_MODE_NV)
2001                 return false;
2002
2003         if (!has_cpuid_feature(cap, scope)) {
2004                 pr_warn("unavailable: %s\n", cap->desc);
2005                 return false;
2006         }
2007
2008         return true;
2009 }
2010
2011 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry,
2012                           int __unused)
2013 {
2014         return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE);
2015 }
2016
2017 #ifdef CONFIG_ARM64_PAN
2018 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
2019 {
2020         /*
2021          * We modify PSTATE. This won't work from irq context as the PSTATE
2022          * is discarded once we return from the exception.
2023          */
2024         WARN_ON_ONCE(in_interrupt());
2025
2026         sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
2027         set_pstate_pan(1);
2028 }
2029 #endif /* CONFIG_ARM64_PAN */
2030
2031 #ifdef CONFIG_ARM64_RAS_EXTN
2032 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
2033 {
2034         /* Firmware may have left a deferred SError in this register. */
2035         write_sysreg_s(0, SYS_DISR_EL1);
2036 }
2037 #endif /* CONFIG_ARM64_RAS_EXTN */
2038
2039 #ifdef CONFIG_ARM64_PTR_AUTH
2040 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope)
2041 {
2042         int boot_val, sec_val;
2043
2044         /* We don't expect to be called with SCOPE_SYSTEM */
2045         WARN_ON(scope == SCOPE_SYSTEM);
2046         /*
2047          * The ptr-auth feature levels are not intercompatible with lower
2048          * levels. Hence we must match ptr-auth feature level of the secondary
2049          * CPUs with that of the boot CPU. The level of boot cpu is fetched
2050          * from the sanitised register whereas direct register read is done for
2051          * the secondary CPUs.
2052          * The sanitised feature state is guaranteed to match that of the
2053          * boot CPU as a mismatched secondary CPU is parked before it gets
2054          * a chance to update the state, with the capability.
2055          */
2056         boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg),
2057                                                entry->field_pos, entry->sign);
2058         if (scope & SCOPE_BOOT_CPU)
2059                 return boot_val >= entry->min_field_value;
2060         /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */
2061         sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg),
2062                                               entry->field_pos, entry->sign);
2063         return (sec_val >= entry->min_field_value) && (sec_val == boot_val);
2064 }
2065
2066 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry,
2067                                      int scope)
2068 {
2069         bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope);
2070         bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope);
2071         bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope);
2072
2073         return apa || apa3 || api;
2074 }
2075
2076 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
2077                              int __unused)
2078 {
2079         bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
2080         bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5);
2081         bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3);
2082
2083         return gpa || gpa3 || gpi;
2084 }
2085 #endif /* CONFIG_ARM64_PTR_AUTH */
2086
2087 #ifdef CONFIG_ARM64_E0PD
2088 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
2089 {
2090         if (this_cpu_has_cap(ARM64_HAS_E0PD))
2091                 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
2092 }
2093 #endif /* CONFIG_ARM64_E0PD */
2094
2095 #ifdef CONFIG_ARM64_PSEUDO_NMI
2096 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
2097                                    int scope)
2098 {
2099         /*
2100          * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU
2101          * feature, so will be detected earlier.
2102          */
2103         BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS);
2104         if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS))
2105                 return false;
2106
2107         return enable_pseudo_nmi;
2108 }
2109
2110 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry,
2111                                       int scope)
2112 {
2113         /*
2114          * If we're not using priority masking then we won't be poking PMR_EL1,
2115          * and there's no need to relax synchronization of writes to it, and
2116          * ICC_CTLR_EL1 might not be accessible and we must avoid reads from
2117          * that.
2118          *
2119          * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU
2120          * feature, so will be detected earlier.
2121          */
2122         BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING);
2123         if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING))
2124                 return false;
2125
2126         /*
2127          * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a
2128          * hint for interrupt distribution, a DSB is not necessary when
2129          * unmasking IRQs via PMR, and we can relax the barrier to a NOP.
2130          *
2131          * Linux itself doesn't use 1:N distribution, so has no need to
2132          * set PMHE. The only reason to have it set is if EL3 requires it
2133          * (and we can't change it).
2134          */
2135         return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0;
2136 }
2137 #endif
2138
2139 #ifdef CONFIG_ARM64_BTI
2140 static void bti_enable(const struct arm64_cpu_capabilities *__unused)
2141 {
2142         /*
2143          * Use of X16/X17 for tail-calls and trampolines that jump to
2144          * function entry points using BR is a requirement for
2145          * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI.
2146          * So, be strict and forbid other BRs using other registers to
2147          * jump onto a PACIxSP instruction:
2148          */
2149         sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1);
2150         isb();
2151 }
2152 #endif /* CONFIG_ARM64_BTI */
2153
2154 #ifdef CONFIG_ARM64_MTE
2155 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
2156 {
2157         sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0);
2158
2159         mte_cpu_setup();
2160
2161         /*
2162          * Clear the tags in the zero page. This needs to be done via the
2163          * linear map which has the Tagged attribute.
2164          */
2165         if (try_page_mte_tagging(ZERO_PAGE(0))) {
2166                 mte_clear_page_tags(lm_alias(empty_zero_page));
2167                 set_page_mte_tagged(ZERO_PAGE(0));
2168         }
2169
2170         kasan_init_hw_tags_cpu();
2171 }
2172 #endif /* CONFIG_ARM64_MTE */
2173
2174 static void user_feature_fixup(void)
2175 {
2176         if (cpus_have_cap(ARM64_WORKAROUND_2658417)) {
2177                 struct arm64_ftr_reg *regp;
2178
2179                 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1);
2180                 if (regp)
2181                         regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK;
2182         }
2183 }
2184
2185 static void elf_hwcap_fixup(void)
2186 {
2187 #ifdef CONFIG_COMPAT
2188         if (cpus_have_cap(ARM64_WORKAROUND_1742098))
2189                 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES;
2190 #endif /* CONFIG_COMPAT */
2191 }
2192
2193 #ifdef CONFIG_KVM
2194 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused)
2195 {
2196         return kvm_get_mode() == KVM_MODE_PROTECTED;
2197 }
2198 #endif /* CONFIG_KVM */
2199
2200 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused)
2201 {
2202         sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP);
2203 }
2204
2205 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused)
2206 {
2207         set_pstate_dit(1);
2208 }
2209
2210 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused)
2211 {
2212         sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn);
2213 }
2214
2215 /* Internal helper functions to match cpu capability type */
2216 static bool
2217 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
2218 {
2219         return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
2220 }
2221
2222 static bool
2223 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
2224 {
2225         return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
2226 }
2227
2228 static bool
2229 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
2230 {
2231         return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
2232 }
2233
2234 static const struct arm64_cpu_capabilities arm64_features[] = {
2235         {
2236                 .capability = ARM64_ALWAYS_BOOT,
2237                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2238                 .matches = has_always,
2239         },
2240         {
2241                 .capability = ARM64_ALWAYS_SYSTEM,
2242                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2243                 .matches = has_always,
2244         },
2245         {
2246                 .desc = "GIC system register CPU interface",
2247                 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS,
2248                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2249                 .matches = has_useable_gicv3_cpuif,
2250                 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP)
2251         },
2252         {
2253                 .desc = "Enhanced Counter Virtualization",
2254                 .capability = ARM64_HAS_ECV,
2255                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2256                 .matches = has_cpuid_feature,
2257                 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP)
2258         },
2259         {
2260                 .desc = "Enhanced Counter Virtualization (CNTPOFF)",
2261                 .capability = ARM64_HAS_ECV_CNTPOFF,
2262                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2263                 .matches = has_cpuid_feature,
2264                 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF)
2265         },
2266 #ifdef CONFIG_ARM64_PAN
2267         {
2268                 .desc = "Privileged Access Never",
2269                 .capability = ARM64_HAS_PAN,
2270                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2271                 .matches = has_cpuid_feature,
2272                 .cpu_enable = cpu_enable_pan,
2273                 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP)
2274         },
2275 #endif /* CONFIG_ARM64_PAN */
2276 #ifdef CONFIG_ARM64_EPAN
2277         {
2278                 .desc = "Enhanced Privileged Access Never",
2279                 .capability = ARM64_HAS_EPAN,
2280                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2281                 .matches = has_cpuid_feature,
2282                 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3)
2283         },
2284 #endif /* CONFIG_ARM64_EPAN */
2285 #ifdef CONFIG_ARM64_LSE_ATOMICS
2286         {
2287                 .desc = "LSE atomic instructions",
2288                 .capability = ARM64_HAS_LSE_ATOMICS,
2289                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2290                 .matches = has_cpuid_feature,
2291                 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP)
2292         },
2293 #endif /* CONFIG_ARM64_LSE_ATOMICS */
2294         {
2295                 .desc = "Virtualization Host Extensions",
2296                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
2297                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2298                 .matches = runs_at_el2,
2299                 .cpu_enable = cpu_copy_el2regs,
2300         },
2301         {
2302                 .desc = "Nested Virtualization Support",
2303                 .capability = ARM64_HAS_NESTED_VIRT,
2304                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2305                 .matches = has_nested_virt_support,
2306                 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2)
2307         },
2308         {
2309                 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE,
2310                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2311                 .matches = has_32bit_el0,
2312                 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32)
2313         },
2314 #ifdef CONFIG_KVM
2315         {
2316                 .desc = "32-bit EL1 Support",
2317                 .capability = ARM64_HAS_32BIT_EL1,
2318                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2319                 .matches = has_cpuid_feature,
2320                 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32)
2321         },
2322         {
2323                 .desc = "Protected KVM",
2324                 .capability = ARM64_KVM_PROTECTED_MODE,
2325                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2326                 .matches = is_kvm_protected_mode,
2327         },
2328         {
2329                 .desc = "HCRX_EL2 register",
2330                 .capability = ARM64_HAS_HCX,
2331                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2332                 .matches = has_cpuid_feature,
2333                 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP)
2334         },
2335 #endif
2336         {
2337                 .desc = "Kernel page table isolation (KPTI)",
2338                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
2339                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2340                 .cpu_enable = cpu_enable_kpti,
2341                 .matches = unmap_kernel_at_el0,
2342                 /*
2343                  * The ID feature fields below are used to indicate that
2344                  * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
2345                  * more details.
2346                  */
2347                 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP)
2348         },
2349         {
2350                 .capability = ARM64_HAS_FPSIMD,
2351                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2352                 .matches = has_cpuid_feature,
2353                 .cpu_enable = cpu_enable_fpsimd,
2354                 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP)
2355         },
2356 #ifdef CONFIG_ARM64_PMEM
2357         {
2358                 .desc = "Data cache clean to Point of Persistence",
2359                 .capability = ARM64_HAS_DCPOP,
2360                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2361                 .matches = has_cpuid_feature,
2362                 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP)
2363         },
2364         {
2365                 .desc = "Data cache clean to Point of Deep Persistence",
2366                 .capability = ARM64_HAS_DCPODP,
2367                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2368                 .matches = has_cpuid_feature,
2369                 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2)
2370         },
2371 #endif
2372 #ifdef CONFIG_ARM64_SVE
2373         {
2374                 .desc = "Scalable Vector Extension",
2375                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2376                 .capability = ARM64_SVE,
2377                 .cpu_enable = cpu_enable_sve,
2378                 .matches = has_cpuid_feature,
2379                 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP)
2380         },
2381 #endif /* CONFIG_ARM64_SVE */
2382 #ifdef CONFIG_ARM64_RAS_EXTN
2383         {
2384                 .desc = "RAS Extension Support",
2385                 .capability = ARM64_HAS_RAS_EXTN,
2386                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2387                 .matches = has_cpuid_feature,
2388                 .cpu_enable = cpu_clear_disr,
2389                 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP)
2390         },
2391 #endif /* CONFIG_ARM64_RAS_EXTN */
2392 #ifdef CONFIG_ARM64_AMU_EXTN
2393         {
2394                 .desc = "Activity Monitors Unit (AMU)",
2395                 .capability = ARM64_HAS_AMU_EXTN,
2396                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2397                 .matches = has_amu,
2398                 .cpu_enable = cpu_amu_enable,
2399                 .cpus = &amu_cpus,
2400                 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP)
2401         },
2402 #endif /* CONFIG_ARM64_AMU_EXTN */
2403         {
2404                 .desc = "Data cache clean to the PoU not required for I/D coherence",
2405                 .capability = ARM64_HAS_CACHE_IDC,
2406                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2407                 .matches = has_cache_idc,
2408                 .cpu_enable = cpu_emulate_effective_ctr,
2409         },
2410         {
2411                 .desc = "Instruction cache invalidation not required for I/D coherence",
2412                 .capability = ARM64_HAS_CACHE_DIC,
2413                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2414                 .matches = has_cache_dic,
2415         },
2416         {
2417                 .desc = "Stage-2 Force Write-Back",
2418                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2419                 .capability = ARM64_HAS_STAGE2_FWB,
2420                 .matches = has_cpuid_feature,
2421                 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP)
2422         },
2423         {
2424                 .desc = "ARMv8.4 Translation Table Level",
2425                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2426                 .capability = ARM64_HAS_ARMv8_4_TTL,
2427                 .matches = has_cpuid_feature,
2428                 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP)
2429         },
2430         {
2431                 .desc = "TLB range maintenance instructions",
2432                 .capability = ARM64_HAS_TLB_RANGE,
2433                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2434                 .matches = has_cpuid_feature,
2435                 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE)
2436         },
2437 #ifdef CONFIG_ARM64_HW_AFDBM
2438         {
2439                 .desc = "Hardware dirty bit management",
2440                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2441                 .capability = ARM64_HW_DBM,
2442                 .matches = has_hw_dbm,
2443                 .cpu_enable = cpu_enable_hw_dbm,
2444                 .cpus = &dbm_cpus,
2445                 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM)
2446         },
2447 #endif
2448         {
2449                 .desc = "CRC32 instructions",
2450                 .capability = ARM64_HAS_CRC32,
2451                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2452                 .matches = has_cpuid_feature,
2453                 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP)
2454         },
2455         {
2456                 .desc = "Speculative Store Bypassing Safe (SSBS)",
2457                 .capability = ARM64_SSBS,
2458                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2459                 .matches = has_cpuid_feature,
2460                 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP)
2461         },
2462 #ifdef CONFIG_ARM64_CNP
2463         {
2464                 .desc = "Common not Private translations",
2465                 .capability = ARM64_HAS_CNP,
2466                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2467                 .matches = has_useable_cnp,
2468                 .cpu_enable = cpu_enable_cnp,
2469                 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP)
2470         },
2471 #endif
2472         {
2473                 .desc = "Speculation barrier (SB)",
2474                 .capability = ARM64_HAS_SB,
2475                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2476                 .matches = has_cpuid_feature,
2477                 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP)
2478         },
2479 #ifdef CONFIG_ARM64_PTR_AUTH
2480         {
2481                 .desc = "Address authentication (architected QARMA5 algorithm)",
2482                 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5,
2483                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2484                 .matches = has_address_auth_cpucap,
2485                 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth)
2486         },
2487         {
2488                 .desc = "Address authentication (architected QARMA3 algorithm)",
2489                 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3,
2490                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2491                 .matches = has_address_auth_cpucap,
2492                 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth)
2493         },
2494         {
2495                 .desc = "Address authentication (IMP DEF algorithm)",
2496                 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
2497                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2498                 .matches = has_address_auth_cpucap,
2499                 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth)
2500         },
2501         {
2502                 .capability = ARM64_HAS_ADDRESS_AUTH,
2503                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2504                 .matches = has_address_auth_metacap,
2505         },
2506         {
2507                 .desc = "Generic authentication (architected QARMA5 algorithm)",
2508                 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5,
2509                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2510                 .matches = has_cpuid_feature,
2511                 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP)
2512         },
2513         {
2514                 .desc = "Generic authentication (architected QARMA3 algorithm)",
2515                 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3,
2516                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2517                 .matches = has_cpuid_feature,
2518                 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP)
2519         },
2520         {
2521                 .desc = "Generic authentication (IMP DEF algorithm)",
2522                 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
2523                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2524                 .matches = has_cpuid_feature,
2525                 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP)
2526         },
2527         {
2528                 .capability = ARM64_HAS_GENERIC_AUTH,
2529                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2530                 .matches = has_generic_auth,
2531         },
2532 #endif /* CONFIG_ARM64_PTR_AUTH */
2533 #ifdef CONFIG_ARM64_PSEUDO_NMI
2534         {
2535                 /*
2536                  * Depends on having GICv3
2537                  */
2538                 .desc = "IRQ priority masking",
2539                 .capability = ARM64_HAS_GIC_PRIO_MASKING,
2540                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2541                 .matches = can_use_gic_priorities,
2542         },
2543         {
2544                 /*
2545                  * Depends on ARM64_HAS_GIC_PRIO_MASKING
2546                  */
2547                 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC,
2548                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2549                 .matches = has_gic_prio_relaxed_sync,
2550         },
2551 #endif
2552 #ifdef CONFIG_ARM64_E0PD
2553         {
2554                 .desc = "E0PD",
2555                 .capability = ARM64_HAS_E0PD,
2556                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2557                 .cpu_enable = cpu_enable_e0pd,
2558                 .matches = has_cpuid_feature,
2559                 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP)
2560         },
2561 #endif
2562         {
2563                 .desc = "Random Number Generator",
2564                 .capability = ARM64_HAS_RNG,
2565                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2566                 .matches = has_cpuid_feature,
2567                 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP)
2568         },
2569 #ifdef CONFIG_ARM64_BTI
2570         {
2571                 .desc = "Branch Target Identification",
2572                 .capability = ARM64_BTI,
2573 #ifdef CONFIG_ARM64_BTI_KERNEL
2574                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2575 #else
2576                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2577 #endif
2578                 .matches = has_cpuid_feature,
2579                 .cpu_enable = bti_enable,
2580                 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP)
2581         },
2582 #endif
2583 #ifdef CONFIG_ARM64_MTE
2584         {
2585                 .desc = "Memory Tagging Extension",
2586                 .capability = ARM64_MTE,
2587                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2588                 .matches = has_cpuid_feature,
2589                 .cpu_enable = cpu_enable_mte,
2590                 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2)
2591         },
2592         {
2593                 .desc = "Asymmetric MTE Tag Check Fault",
2594                 .capability = ARM64_MTE_ASYMM,
2595                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2596                 .matches = has_cpuid_feature,
2597                 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3)
2598         },
2599 #endif /* CONFIG_ARM64_MTE */
2600         {
2601                 .desc = "RCpc load-acquire (LDAPR)",
2602                 .capability = ARM64_HAS_LDAPR,
2603                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2604                 .matches = has_cpuid_feature,
2605                 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP)
2606         },
2607         {
2608                 .desc = "Fine Grained Traps",
2609                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2610                 .capability = ARM64_HAS_FGT,
2611                 .matches = has_cpuid_feature,
2612                 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP)
2613         },
2614 #ifdef CONFIG_ARM64_SME
2615         {
2616                 .desc = "Scalable Matrix Extension",
2617                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2618                 .capability = ARM64_SME,
2619                 .matches = has_cpuid_feature,
2620                 .cpu_enable = cpu_enable_sme,
2621                 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP)
2622         },
2623         /* FA64 should be sorted after the base SME capability */
2624         {
2625                 .desc = "FA64",
2626                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2627                 .capability = ARM64_SME_FA64,
2628                 .matches = has_cpuid_feature,
2629                 .cpu_enable = cpu_enable_fa64,
2630                 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP)
2631         },
2632         {
2633                 .desc = "SME2",
2634                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2635                 .capability = ARM64_SME2,
2636                 .matches = has_cpuid_feature,
2637                 .cpu_enable = cpu_enable_sme2,
2638                 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2)
2639         },
2640 #endif /* CONFIG_ARM64_SME */
2641         {
2642                 .desc = "WFx with timeout",
2643                 .capability = ARM64_HAS_WFXT,
2644                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2645                 .matches = has_cpuid_feature,
2646                 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP)
2647         },
2648         {
2649                 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality",
2650                 .capability = ARM64_HAS_TIDCP1,
2651                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2652                 .matches = has_cpuid_feature,
2653                 .cpu_enable = cpu_trap_el0_impdef,
2654                 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP)
2655         },
2656         {
2657                 .desc = "Data independent timing control (DIT)",
2658                 .capability = ARM64_HAS_DIT,
2659                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2660                 .matches = has_cpuid_feature,
2661                 .cpu_enable = cpu_enable_dit,
2662                 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP)
2663         },
2664         {
2665                 .desc = "Memory Copy and Memory Set instructions",
2666                 .capability = ARM64_HAS_MOPS,
2667                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2668                 .matches = has_cpuid_feature,
2669                 .cpu_enable = cpu_enable_mops,
2670                 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP)
2671         },
2672         {
2673                 .capability = ARM64_HAS_TCR2,
2674                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2675                 .matches = has_cpuid_feature,
2676                 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP)
2677         },
2678         {
2679                 .desc = "Stage-1 Permission Indirection Extension (S1PIE)",
2680                 .capability = ARM64_HAS_S1PIE,
2681                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2682                 .matches = has_cpuid_feature,
2683                 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP)
2684         },
2685         {
2686                 .desc = "VHE for hypervisor only",
2687                 .capability = ARM64_KVM_HVHE,
2688                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2689                 .matches = hvhe_possible,
2690         },
2691         {
2692                 .desc = "Enhanced Virtualization Traps",
2693                 .capability = ARM64_HAS_EVT,
2694                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2695                 .matches = has_cpuid_feature,
2696                 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP)
2697         },
2698         {
2699                 .desc = "52-bit Virtual Addressing for KVM (LPA2)",
2700                 .capability = ARM64_HAS_LPA2,
2701                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2702                 .matches = has_lpa2,
2703         },
2704 #ifdef CONFIG_ARM64_VA_BITS_52
2705         {
2706                 .desc = "52-bit Virtual Addressing (LVA)",
2707                 .capability = ARM64_HAS_VA52,
2708                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2709                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2710                 .sign = FTR_UNSIGNED,
2711                 .field_width = 4,
2712                 .field_pos = ID_AA64MMFR2_EL1_VARange_SHIFT,
2713                 .matches = has_cpuid_feature,
2714                 .min_field_value = ID_AA64MMFR2_EL1_VARange_52,
2715         },
2716 #endif
2717         {},
2718 };
2719
2720 #define HWCAP_CPUID_MATCH(reg, field, min_value)                        \
2721                 .matches = has_user_cpuid_feature,                      \
2722                 ARM64_CPUID_FIELDS(reg, field, min_value)
2723
2724 #define __HWCAP_CAP(name, cap_type, cap)                                        \
2725                 .desc = name,                                                   \
2726                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,                            \
2727                 .hwcap_type = cap_type,                                         \
2728                 .hwcap = cap,                                                   \
2729
2730 #define HWCAP_CAP(reg, field, min_value, cap_type, cap)         \
2731         {                                                                       \
2732                 __HWCAP_CAP(#cap, cap_type, cap)                                \
2733                 HWCAP_CPUID_MATCH(reg, field, min_value)                \
2734         }
2735
2736 #define HWCAP_MULTI_CAP(list, cap_type, cap)                                    \
2737         {                                                                       \
2738                 __HWCAP_CAP(#cap, cap_type, cap)                                \
2739                 .matches = cpucap_multi_entry_cap_matches,                      \
2740                 .match_list = list,                                             \
2741         }
2742
2743 #define HWCAP_CAP_MATCH(match, cap_type, cap)                                   \
2744         {                                                                       \
2745                 __HWCAP_CAP(#cap, cap_type, cap)                                \
2746                 .matches = match,                                               \
2747         }
2748
2749 #ifdef CONFIG_ARM64_PTR_AUTH
2750 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
2751         {
2752                 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth)
2753         },
2754         {
2755                 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth)
2756         },
2757         {
2758                 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth)
2759         },
2760         {},
2761 };
2762
2763 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
2764         {
2765                 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP)
2766         },
2767         {
2768                 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP)
2769         },
2770         {
2771                 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP)
2772         },
2773         {},
2774 };
2775 #endif
2776
2777 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
2778         HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL),
2779         HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES),
2780         HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1),
2781         HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2),
2782         HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512),
2783         HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32),
2784         HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
2785         HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128),
2786         HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
2787         HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3),
2788         HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3),
2789         HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4),
2790         HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
2791         HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
2792         HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
2793         HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
2794         HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG),
2795         HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP),
2796         HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP),
2797         HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2798         HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2799         HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT),
2800         HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
2801         HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
2802         HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2803         HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2804         HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2805         HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
2806         HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3),
2807         HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT),
2808         HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB),
2809         HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16),
2810         HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16),
2811         HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH),
2812         HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2813         HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT),
2814 #ifdef CONFIG_ARM64_SVE
2815         HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE),
2816         HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1),
2817         HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2818         HWCAP_CAP(ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2819         HWCAP_CAP(ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2820         HWCAP_CAP(ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
2821         HWCAP_CAP(ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16),
2822         HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
2823         HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16),
2824         HWCAP_CAP(ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2825         HWCAP_CAP(ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
2826         HWCAP_CAP(ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2827         HWCAP_CAP(ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2828         HWCAP_CAP(ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
2829 #endif
2830         HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS),
2831 #ifdef CONFIG_ARM64_BTI
2832         HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI),
2833 #endif
2834 #ifdef CONFIG_ARM64_PTR_AUTH
2835         HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2836         HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
2837 #endif
2838 #ifdef CONFIG_ARM64_MTE
2839         HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE),
2840         HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3),
2841 #endif /* CONFIG_ARM64_MTE */
2842         HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV),
2843         HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP),
2844         HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC),
2845         HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM),
2846         HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES),
2847         HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
2848         HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS),
2849         HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC),
2850 #ifdef CONFIG_ARM64_SME
2851         HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME),
2852         HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
2853         HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1),
2854         HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2),
2855         HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64),
2856         HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64),
2857         HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32),
2858         HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16),
2859         HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16),
2860         HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32),
2861         HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32),
2862         HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32),
2863         HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32),
2864         HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32),
2865 #endif /* CONFIG_ARM64_SME */
2866         {},
2867 };
2868
2869 #ifdef CONFIG_COMPAT
2870 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
2871 {
2872         /*
2873          * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
2874          * in line with that of arm32 as in vfp_init(). We make sure that the
2875          * check is future proof, by making sure value is non-zero.
2876          */
2877         u32 mvfr1;
2878
2879         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
2880         if (scope == SCOPE_SYSTEM)
2881                 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
2882         else
2883                 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
2884
2885         return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) &&
2886                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) &&
2887                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT);
2888 }
2889 #endif
2890
2891 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
2892 #ifdef CONFIG_COMPAT
2893         HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2894         HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2895         /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
2896         HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2897         HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
2898         HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP),
2899         HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP),
2900         HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2901         HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2902         HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2903         HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2904         HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
2905         HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP),
2906         HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM),
2907         HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB),
2908         HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16),
2909         HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM),
2910         HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS),
2911 #endif
2912         {},
2913 };
2914
2915 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2916 {
2917         switch (cap->hwcap_type) {
2918         case CAP_HWCAP:
2919                 cpu_set_feature(cap->hwcap);
2920                 break;
2921 #ifdef CONFIG_COMPAT
2922         case CAP_COMPAT_HWCAP:
2923                 compat_elf_hwcap |= (u32)cap->hwcap;
2924                 break;
2925         case CAP_COMPAT_HWCAP2:
2926                 compat_elf_hwcap2 |= (u32)cap->hwcap;
2927                 break;
2928 #endif
2929         default:
2930                 WARN_ON(1);
2931                 break;
2932         }
2933 }
2934
2935 /* Check if we have a particular HWCAP enabled */
2936 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2937 {
2938         bool rc;
2939
2940         switch (cap->hwcap_type) {
2941         case CAP_HWCAP:
2942                 rc = cpu_have_feature(cap->hwcap);
2943                 break;
2944 #ifdef CONFIG_COMPAT
2945         case CAP_COMPAT_HWCAP:
2946                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
2947                 break;
2948         case CAP_COMPAT_HWCAP2:
2949                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
2950                 break;
2951 #endif
2952         default:
2953                 WARN_ON(1);
2954                 rc = false;
2955         }
2956
2957         return rc;
2958 }
2959
2960 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
2961 {
2962         /* We support emulation of accesses to CPU ID feature registers */
2963         cpu_set_named_feature(CPUID);
2964         for (; hwcaps->matches; hwcaps++)
2965                 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
2966                         cap_set_elf_hwcap(hwcaps);
2967 }
2968
2969 static void update_cpu_capabilities(u16 scope_mask)
2970 {
2971         int i;
2972         const struct arm64_cpu_capabilities *caps;
2973
2974         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2975         for (i = 0; i < ARM64_NCAPS; i++) {
2976                 caps = cpucap_ptrs[i];
2977                 if (!caps || !(caps->type & scope_mask) ||
2978                     cpus_have_cap(caps->capability) ||
2979                     !caps->matches(caps, cpucap_default_scope(caps)))
2980                         continue;
2981
2982                 if (caps->desc && !caps->cpus)
2983                         pr_info("detected: %s\n", caps->desc);
2984
2985                 __set_bit(caps->capability, system_cpucaps);
2986
2987                 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
2988                         set_bit(caps->capability, boot_cpucaps);
2989         }
2990 }
2991
2992 /*
2993  * Enable all the available capabilities on this CPU. The capabilities
2994  * with BOOT_CPU scope are handled separately and hence skipped here.
2995  */
2996 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
2997 {
2998         int i;
2999         u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
3000
3001         for_each_available_cap(i) {
3002                 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i];
3003
3004                 if (WARN_ON(!cap))
3005                         continue;
3006
3007                 if (!(cap->type & non_boot_scope))
3008                         continue;
3009
3010                 if (cap->cpu_enable)
3011                         cap->cpu_enable(cap);
3012         }
3013         return 0;
3014 }
3015
3016 /*
3017  * Run through the enabled capabilities and enable() it on all active
3018  * CPUs
3019  */
3020 static void __init enable_cpu_capabilities(u16 scope_mask)
3021 {
3022         int i;
3023         const struct arm64_cpu_capabilities *caps;
3024         bool boot_scope;
3025
3026         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
3027         boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
3028
3029         for (i = 0; i < ARM64_NCAPS; i++) {
3030                 unsigned int num;
3031
3032                 caps = cpucap_ptrs[i];
3033                 if (!caps || !(caps->type & scope_mask))
3034                         continue;
3035                 num = caps->capability;
3036                 if (!cpus_have_cap(num))
3037                         continue;
3038
3039                 if (boot_scope && caps->cpu_enable)
3040                         /*
3041                          * Capabilities with SCOPE_BOOT_CPU scope are finalised
3042                          * before any secondary CPU boots. Thus, each secondary
3043                          * will enable the capability as appropriate via
3044                          * check_local_cpu_capabilities(). The only exception is
3045                          * the boot CPU, for which the capability must be
3046                          * enabled here. This approach avoids costly
3047                          * stop_machine() calls for this case.
3048                          */
3049                         caps->cpu_enable(caps);
3050         }
3051
3052         /*
3053          * For all non-boot scope capabilities, use stop_machine()
3054          * as it schedules the work allowing us to modify PSTATE,
3055          * instead of on_each_cpu() which uses an IPI, giving us a
3056          * PSTATE that disappears when we return.
3057          */
3058         if (!boot_scope)
3059                 stop_machine(cpu_enable_non_boot_scope_capabilities,
3060                              NULL, cpu_online_mask);
3061 }
3062
3063 /*
3064  * Run through the list of capabilities to check for conflicts.
3065  * If the system has already detected a capability, take necessary
3066  * action on this CPU.
3067  */
3068 static void verify_local_cpu_caps(u16 scope_mask)
3069 {
3070         int i;
3071         bool cpu_has_cap, system_has_cap;
3072         const struct arm64_cpu_capabilities *caps;
3073
3074         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
3075
3076         for (i = 0; i < ARM64_NCAPS; i++) {
3077                 caps = cpucap_ptrs[i];
3078                 if (!caps || !(caps->type & scope_mask))
3079                         continue;
3080
3081                 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
3082                 system_has_cap = cpus_have_cap(caps->capability);
3083
3084                 if (system_has_cap) {
3085                         /*
3086                          * Check if the new CPU misses an advertised feature,
3087                          * which is not safe to miss.
3088                          */
3089                         if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
3090                                 break;
3091                         /*
3092                          * We have to issue cpu_enable() irrespective of
3093                          * whether the CPU has it or not, as it is enabeld
3094                          * system wide. It is upto the call back to take
3095                          * appropriate action on this CPU.
3096                          */
3097                         if (caps->cpu_enable)
3098                                 caps->cpu_enable(caps);
3099                 } else {
3100                         /*
3101                          * Check if the CPU has this capability if it isn't
3102                          * safe to have when the system doesn't.
3103                          */
3104                         if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
3105                                 break;
3106                 }
3107         }
3108
3109         if (i < ARM64_NCAPS) {
3110                 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
3111                         smp_processor_id(), caps->capability,
3112                         caps->desc, system_has_cap, cpu_has_cap);
3113
3114                 if (cpucap_panic_on_conflict(caps))
3115                         cpu_panic_kernel();
3116                 else
3117                         cpu_die_early();
3118         }
3119 }
3120
3121 /*
3122  * Check for CPU features that are used in early boot
3123  * based on the Boot CPU value.
3124  */
3125 static void check_early_cpu_features(void)
3126 {
3127         verify_cpu_asid_bits();
3128
3129         verify_local_cpu_caps(SCOPE_BOOT_CPU);
3130 }
3131
3132 static void
3133 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
3134 {
3135
3136         for (; caps->matches; caps++)
3137                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
3138                         pr_crit("CPU%d: missing HWCAP: %s\n",
3139                                         smp_processor_id(), caps->desc);
3140                         cpu_die_early();
3141                 }
3142 }
3143
3144 static void verify_local_elf_hwcaps(void)
3145 {
3146         __verify_local_elf_hwcaps(arm64_elf_hwcaps);
3147
3148         if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1)))
3149                 __verify_local_elf_hwcaps(compat_elf_hwcaps);
3150 }
3151
3152 static void verify_sve_features(void)
3153 {
3154         unsigned long cpacr = cpacr_save_enable_kernel_sve();
3155
3156         if (vec_verify_vq_map(ARM64_VEC_SVE)) {
3157                 pr_crit("CPU%d: SVE: vector length support mismatch\n",
3158                         smp_processor_id());
3159                 cpu_die_early();
3160         }
3161
3162         cpacr_restore(cpacr);
3163 }
3164
3165 static void verify_sme_features(void)
3166 {
3167         unsigned long cpacr = cpacr_save_enable_kernel_sme();
3168
3169         if (vec_verify_vq_map(ARM64_VEC_SME)) {
3170                 pr_crit("CPU%d: SME: vector length support mismatch\n",
3171                         smp_processor_id());
3172                 cpu_die_early();
3173         }
3174
3175         cpacr_restore(cpacr);
3176 }
3177
3178 static void verify_hyp_capabilities(void)
3179 {
3180         u64 safe_mmfr1, mmfr0, mmfr1;
3181         int parange, ipa_max;
3182         unsigned int safe_vmid_bits, vmid_bits;
3183
3184         if (!IS_ENABLED(CONFIG_KVM))
3185                 return;
3186
3187         safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
3188         mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
3189         mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
3190
3191         /* Verify VMID bits */
3192         safe_vmid_bits = get_vmid_bits(safe_mmfr1);
3193         vmid_bits = get_vmid_bits(mmfr1);
3194         if (vmid_bits < safe_vmid_bits) {
3195                 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
3196                 cpu_die_early();
3197         }
3198
3199         /* Verify IPA range */
3200         parange = cpuid_feature_extract_unsigned_field(mmfr0,
3201                                 ID_AA64MMFR0_EL1_PARANGE_SHIFT);
3202         ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
3203         if (ipa_max < get_kvm_ipa_limit()) {
3204                 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
3205                 cpu_die_early();
3206         }
3207 }
3208
3209 /*
3210  * Run through the enabled system capabilities and enable() it on this CPU.
3211  * The capabilities were decided based on the available CPUs at the boot time.
3212  * Any new CPU should match the system wide status of the capability. If the
3213  * new CPU doesn't have a capability which the system now has enabled, we
3214  * cannot do anything to fix it up and could cause unexpected failures. So
3215  * we park the CPU.
3216  */
3217 static void verify_local_cpu_capabilities(void)
3218 {
3219         /*
3220          * The capabilities with SCOPE_BOOT_CPU are checked from
3221          * check_early_cpu_features(), as they need to be verified
3222          * on all secondary CPUs.
3223          */
3224         verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
3225         verify_local_elf_hwcaps();
3226
3227         if (system_supports_sve())
3228                 verify_sve_features();
3229
3230         if (system_supports_sme())
3231                 verify_sme_features();
3232
3233         if (is_hyp_mode_available())
3234                 verify_hyp_capabilities();
3235 }
3236
3237 void check_local_cpu_capabilities(void)
3238 {
3239         /*
3240          * All secondary CPUs should conform to the early CPU features
3241          * in use by the kernel based on boot CPU.
3242          */
3243         check_early_cpu_features();
3244
3245         /*
3246          * If we haven't finalised the system capabilities, this CPU gets
3247          * a chance to update the errata work arounds and local features.
3248          * Otherwise, this CPU should verify that it has all the system
3249          * advertised capabilities.
3250          */
3251         if (!system_capabilities_finalized())
3252                 update_cpu_capabilities(SCOPE_LOCAL_CPU);
3253         else
3254                 verify_local_cpu_capabilities();
3255 }
3256
3257 bool this_cpu_has_cap(unsigned int n)
3258 {
3259         if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
3260                 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n];
3261
3262                 if (cap)
3263                         return cap->matches(cap, SCOPE_LOCAL_CPU);
3264         }
3265
3266         return false;
3267 }
3268 EXPORT_SYMBOL_GPL(this_cpu_has_cap);
3269
3270 /*
3271  * This helper function is used in a narrow window when,
3272  * - The system wide safe registers are set with all the SMP CPUs and,
3273  * - The SYSTEM_FEATURE system_cpucaps may not have been set.
3274  */
3275 static bool __maybe_unused __system_matches_cap(unsigned int n)
3276 {
3277         if (n < ARM64_NCAPS) {
3278                 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n];
3279
3280                 if (cap)
3281                         return cap->matches(cap, SCOPE_SYSTEM);
3282         }
3283         return false;
3284 }
3285
3286 void cpu_set_feature(unsigned int num)
3287 {
3288         set_bit(num, elf_hwcap);
3289 }
3290
3291 bool cpu_have_feature(unsigned int num)
3292 {
3293         return test_bit(num, elf_hwcap);
3294 }
3295 EXPORT_SYMBOL_GPL(cpu_have_feature);
3296
3297 unsigned long cpu_get_elf_hwcap(void)
3298 {
3299         /*
3300          * We currently only populate the first 32 bits of AT_HWCAP. Please
3301          * note that for userspace compatibility we guarantee that bits 62
3302          * and 63 will always be returned as 0.
3303          */
3304         return elf_hwcap[0];
3305 }
3306
3307 unsigned long cpu_get_elf_hwcap2(void)
3308 {
3309         return elf_hwcap[1];
3310 }
3311
3312 static void __init setup_boot_cpu_capabilities(void)
3313 {
3314         /*
3315          * The boot CPU's feature register values have been recorded. Detect
3316          * boot cpucaps and local cpucaps for the boot CPU, then enable and
3317          * patch alternatives for the available boot cpucaps.
3318          */
3319         update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
3320         enable_cpu_capabilities(SCOPE_BOOT_CPU);
3321         apply_boot_alternatives();
3322 }
3323
3324 void __init setup_boot_cpu_features(void)
3325 {
3326         /*
3327          * Initialize the indirect array of CPU capabilities pointers before we
3328          * handle the boot CPU.
3329          */
3330         init_cpucap_indirect_list();
3331
3332         /*
3333          * Detect broken pseudo-NMI. Must be called _before_ the call to
3334          * setup_boot_cpu_capabilities() since it interacts with
3335          * can_use_gic_priorities().
3336          */
3337         detect_system_supports_pseudo_nmi();
3338
3339         setup_boot_cpu_capabilities();
3340 }
3341
3342 static void __init setup_system_capabilities(void)
3343 {
3344         /*
3345          * The system-wide safe feature register values have been finalized.
3346          * Detect, enable, and patch alternatives for the available system
3347          * cpucaps.
3348          */
3349         update_cpu_capabilities(SCOPE_SYSTEM);
3350         enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
3351         apply_alternatives_all();
3352
3353         /*
3354          * Log any cpucaps with a cpumask as these aren't logged by
3355          * update_cpu_capabilities().
3356          */
3357         for (int i = 0; i < ARM64_NCAPS; i++) {
3358                 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i];
3359
3360                 if (caps && caps->cpus && caps->desc &&
3361                         cpumask_any(caps->cpus) < nr_cpu_ids)
3362                         pr_info("detected: %s on CPU%*pbl\n",
3363                                 caps->desc, cpumask_pr_args(caps->cpus));
3364         }
3365
3366         /*
3367          * TTBR0 PAN doesn't have its own cpucap, so log it manually.
3368          */
3369         if (system_uses_ttbr0_pan())
3370                 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
3371 }
3372
3373 void __init setup_system_features(void)
3374 {
3375         setup_system_capabilities();
3376
3377         kpti_install_ng_mappings();
3378
3379         sve_setup();
3380         sme_setup();
3381
3382         /*
3383          * Check for sane CTR_EL0.CWG value.
3384          */
3385         if (!cache_type_cwg())
3386                 pr_warn("No Cache Writeback Granule information, assuming %d\n",
3387                         ARCH_DMA_MINALIGN);
3388 }
3389
3390 void __init setup_user_features(void)
3391 {
3392         user_feature_fixup();
3393
3394         setup_elf_hwcaps(arm64_elf_hwcaps);
3395
3396         if (system_supports_32bit_el0()) {
3397                 setup_elf_hwcaps(compat_elf_hwcaps);
3398                 elf_hwcap_fixup();
3399         }
3400
3401         minsigstksz_setup();
3402 }
3403
3404 static int enable_mismatched_32bit_el0(unsigned int cpu)
3405 {
3406         /*
3407          * The first 32-bit-capable CPU we detected and so can no longer
3408          * be offlined by userspace. -1 indicates we haven't yet onlined
3409          * a 32-bit-capable CPU.
3410          */
3411         static int lucky_winner = -1;
3412
3413         struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
3414         bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0);
3415
3416         if (cpu_32bit) {
3417                 cpumask_set_cpu(cpu, cpu_32bit_el0_mask);
3418                 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0);
3419         }
3420
3421         if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit)
3422                 return 0;
3423
3424         if (lucky_winner >= 0)
3425                 return 0;
3426
3427         /*
3428          * We've detected a mismatch. We need to keep one of our CPUs with
3429          * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting
3430          * every CPU in the system for a 32-bit task.
3431          */
3432         lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask,
3433                                                          cpu_active_mask);
3434         get_cpu_device(lucky_winner)->offline_disabled = true;
3435         setup_elf_hwcaps(compat_elf_hwcaps);
3436         elf_hwcap_fixup();
3437         pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n",
3438                 cpu, lucky_winner);
3439         return 0;
3440 }
3441
3442 static int __init init_32bit_el0_mask(void)
3443 {
3444         if (!allow_mismatched_32bit_el0)
3445                 return 0;
3446
3447         if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL))
3448                 return -ENOMEM;
3449
3450         return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
3451                                  "arm64/mismatched_32bit_el0:online",
3452                                  enable_mismatched_32bit_el0, NULL);
3453 }
3454 subsys_initcall_sync(init_32bit_el0_mask);
3455
3456 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
3457 {
3458         cpu_enable_swapper_cnp();
3459 }
3460
3461 /*
3462  * We emulate only the following system register space.
3463  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7]
3464  * See Table C5-6 System instruction encodings for System register accesses,
3465  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
3466  */
3467 static inline bool __attribute_const__ is_emulated(u32 id)
3468 {
3469         return (sys_reg_Op0(id) == 0x3 &&
3470                 sys_reg_CRn(id) == 0x0 &&
3471                 sys_reg_Op1(id) == 0x0 &&
3472                 (sys_reg_CRm(id) == 0 ||
3473                  ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7))));
3474 }
3475
3476 /*
3477  * With CRm == 0, reg should be one of :
3478  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
3479  */
3480 static inline int emulate_id_reg(u32 id, u64 *valp)
3481 {
3482         switch (id) {
3483         case SYS_MIDR_EL1:
3484                 *valp = read_cpuid_id();
3485                 break;
3486         case SYS_MPIDR_EL1:
3487                 *valp = SYS_MPIDR_SAFE_VAL;
3488                 break;
3489         case SYS_REVIDR_EL1:
3490                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
3491                 *valp = 0;
3492                 break;
3493         default:
3494                 return -EINVAL;
3495         }
3496
3497         return 0;
3498 }
3499
3500 static int emulate_sys_reg(u32 id, u64 *valp)
3501 {
3502         struct arm64_ftr_reg *regp;
3503
3504         if (!is_emulated(id))
3505                 return -EINVAL;
3506
3507         if (sys_reg_CRm(id) == 0)
3508                 return emulate_id_reg(id, valp);
3509
3510         regp = get_arm64_ftr_reg_nowarn(id);
3511         if (regp)
3512                 *valp = arm64_ftr_reg_user_value(regp);
3513         else
3514                 /*
3515                  * The untracked registers are either IMPLEMENTATION DEFINED
3516                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
3517                  */
3518                 *valp = 0;
3519         return 0;
3520 }
3521
3522 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
3523 {
3524         int rc;
3525         u64 val;
3526
3527         rc = emulate_sys_reg(sys_reg, &val);
3528         if (!rc) {
3529                 pt_regs_write_reg(regs, rt, val);
3530                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
3531         }
3532         return rc;
3533 }
3534
3535 bool try_emulate_mrs(struct pt_regs *regs, u32 insn)
3536 {
3537         u32 sys_reg, rt;
3538
3539         if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn))
3540                 return false;
3541
3542         /*
3543          * sys_reg values are defined as used in mrs/msr instruction.
3544          * shift the imm value to get the encoding.
3545          */
3546         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
3547         rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
3548         return do_emulate_mrs(regs, sys_reg, rt) == 0;
3549 }
3550
3551 enum mitigation_state arm64_get_meltdown_state(void)
3552 {
3553         if (__meltdown_safe)
3554                 return SPECTRE_UNAFFECTED;
3555
3556         if (arm64_kernel_unmapped_at_el0())
3557                 return SPECTRE_MITIGATED;
3558
3559         return SPECTRE_VULNERABLE;
3560 }
3561
3562 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
3563                           char *buf)
3564 {
3565         switch (arm64_get_meltdown_state()) {
3566         case SPECTRE_UNAFFECTED:
3567                 return sprintf(buf, "Not affected\n");
3568
3569         case SPECTRE_MITIGATED:
3570                 return sprintf(buf, "Mitigation: PTI\n");
3571
3572         default:
3573                 return sprintf(buf, "Vulnerable\n");
3574         }
3575 }