1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copied from arch/arm64/kernel/cpufeature.c
5 * Copyright (C) 2015 ARM Ltd.
6 * Copyright (C) 2017 SiFive
9 #include <linux/acpi.h>
10 #include <linux/bitmap.h>
11 #include <linux/cpu.h>
12 #include <linux/cpuhotplug.h>
13 #include <linux/ctype.h>
14 #include <linux/log2.h>
15 #include <linux/memory.h>
16 #include <linux/module.h>
19 #include <asm/alternative.h>
20 #include <asm/cacheflush.h>
21 #include <asm/cpufeature.h>
22 #include <asm/hwcap.h>
23 #include <asm/patch.h>
24 #include <asm/processor.h>
25 #include <asm/vector.h>
27 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
29 unsigned long elf_hwcap __read_mostly;
32 static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
34 /* Per-cpu ISA extensions. */
35 struct riscv_isainfo hart_isa[NR_CPUS];
38 * riscv_isa_extension_base() - Get base extension word
40 * @isa_bitmap: ISA bitmap to use
41 * Return: base extension word as unsigned long value
43 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
45 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap)
51 EXPORT_SYMBOL_GPL(riscv_isa_extension_base);
54 * __riscv_isa_extension_available() - Check whether given extension
57 * @isa_bitmap: ISA bitmap to use
58 * @bit: bit position of the desired extension
59 * Return: true or false
61 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
63 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned int bit)
65 const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa;
67 if (bit >= RISCV_ISA_EXT_MAX)
70 return test_bit(bit, bmap) ? true : false;
72 EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
74 static bool riscv_isa_extension_check(int id)
77 case RISCV_ISA_EXT_ZICBOM:
78 if (!riscv_cbom_block_size) {
79 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n");
81 } else if (!is_power_of_2(riscv_cbom_block_size)) {
82 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n");
86 case RISCV_ISA_EXT_ZICBOZ:
87 if (!riscv_cboz_block_size) {
88 pr_err("Zicboz detected in ISA string, disabling as no cboz-block-size found\n");
90 } else if (!is_power_of_2(riscv_cboz_block_size)) {
91 pr_err("Zicboz disabled as cboz-block-size present, but is not a power-of-2\n");
95 case RISCV_ISA_EXT_INVALID:
102 #define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size) { \
104 .property = #_name, \
106 .subset_ext_ids = _subset_exts, \
107 .subset_ext_size = _subset_exts_size \
110 #define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0)
112 /* Used to declare pure "lasso" extension (Zk for instance) */
113 #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \
114 _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, ARRAY_SIZE(_bundled_exts))
116 /* Used to declare extensions that are a superset of other extensions (Zvbb for instance) */
117 #define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \
118 _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts))
120 static const unsigned int riscv_zk_bundled_exts[] = {
130 static const unsigned int riscv_zkn_bundled_exts[] = {
139 static const unsigned int riscv_zks_bundled_exts[] = {
146 #define RISCV_ISA_EXT_ZVKN \
147 RISCV_ISA_EXT_ZVKNED, \
148 RISCV_ISA_EXT_ZVKNHB, \
149 RISCV_ISA_EXT_ZVKB, \
152 static const unsigned int riscv_zvkn_bundled_exts[] = {
156 static const unsigned int riscv_zvknc_bundled_exts[] = {
161 static const unsigned int riscv_zvkng_bundled_exts[] = {
166 #define RISCV_ISA_EXT_ZVKS \
167 RISCV_ISA_EXT_ZVKSED, \
168 RISCV_ISA_EXT_ZVKSH, \
169 RISCV_ISA_EXT_ZVKB, \
172 static const unsigned int riscv_zvks_bundled_exts[] = {
176 static const unsigned int riscv_zvksc_bundled_exts[] = {
181 static const unsigned int riscv_zvksg_bundled_exts[] = {
186 static const unsigned int riscv_zvbb_exts[] = {
191 * The canonical order of ISA extension names in the ISA string is defined in
192 * chapter 27 of the unprivileged specification.
194 * Ordinarily, for in-kernel data structures, this order is unimportant but
195 * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo.
197 * The specification uses vague wording, such as should, when it comes to
198 * ordering, so for our purposes the following rules apply:
200 * 1. All multi-letter extensions must be separated from other extensions by an
203 * 2. Additional standard extensions (starting with 'Z') must be sorted after
204 * single-letter extensions and before any higher-privileged extensions.
206 * 3. The first letter following the 'Z' conventionally indicates the most
207 * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
208 * If multiple 'Z' extensions are named, they must be ordered first by
209 * category, then alphabetically within a category.
211 * 3. Standard supervisor-level extensions (starting with 'S') must be listed
212 * after standard unprivileged extensions. If multiple supervisor-level
213 * extensions are listed, they must be ordered alphabetically.
215 * 4. Standard machine-level extensions (starting with 'Zxm') must be listed
216 * after any lower-privileged, standard extensions. If multiple
217 * machine-level extensions are listed, they must be ordered
220 * 5. Non-standard extensions (starting with 'X') must be listed after all
221 * standard extensions. If multiple non-standard extensions are listed, they
222 * must be ordered alphabetically.
224 * An example string following the order is:
225 * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux
227 * New entries to this struct should follow the ordering rules described above.
229 const struct riscv_isa_ext_data riscv_isa_ext[] = {
230 __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i),
231 __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m),
232 __RISCV_ISA_EXT_DATA(a, RISCV_ISA_EXT_a),
233 __RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f),
234 __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
235 __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
236 __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c),
237 __RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v),
238 __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
239 __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
240 __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
241 __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
242 __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
243 __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
244 __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
245 __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL),
246 __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
247 __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
248 __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
249 __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
250 __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
251 __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
252 __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
253 __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
254 __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
255 __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB),
256 __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC),
257 __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX),
258 __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
259 __RISCV_ISA_EXT_BUNDLE(zk, riscv_zk_bundled_exts),
260 __RISCV_ISA_EXT_BUNDLE(zkn, riscv_zkn_bundled_exts),
261 __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND),
262 __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE),
263 __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH),
264 __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR),
265 __RISCV_ISA_EXT_BUNDLE(zks, riscv_zks_bundled_exts),
266 __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT),
267 __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED),
268 __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH),
269 __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
270 __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
271 __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
272 __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
273 __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
274 __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
275 __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG),
276 __RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts),
277 __RISCV_ISA_EXT_BUNDLE(zvknc, riscv_zvknc_bundled_exts),
278 __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED),
279 __RISCV_ISA_EXT_BUNDLE(zvkng, riscv_zvkng_bundled_exts),
280 __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA),
281 __RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB),
282 __RISCV_ISA_EXT_BUNDLE(zvks, riscv_zvks_bundled_exts),
283 __RISCV_ISA_EXT_BUNDLE(zvksc, riscv_zvksc_bundled_exts),
284 __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED),
285 __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH),
286 __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts),
287 __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT),
288 __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
289 __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
290 __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
291 __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
292 __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
293 __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
294 __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
295 __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
296 __RISCV_ISA_EXT_DATA(xandespmu, RISCV_ISA_EXT_XANDESPMU),
299 const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
301 static void __init match_isa_ext(const struct riscv_isa_ext_data *ext, const char *name,
302 const char *name_end, struct riscv_isainfo *isainfo)
304 if ((name_end - name == strlen(ext->name)) &&
305 !strncasecmp(name, ext->name, name_end - name)) {
307 * If this is a bundle, enable all the ISA extensions that
308 * comprise the bundle.
310 if (ext->subset_ext_size) {
311 for (int i = 0; i < ext->subset_ext_size; i++) {
312 if (riscv_isa_extension_check(ext->subset_ext_ids[i]))
313 set_bit(ext->subset_ext_ids[i], isainfo->isa);
318 * This is valid even for bundle extensions which uses the RISCV_ISA_EXT_INVALID id
319 * (rejected by riscv_isa_extension_check()).
321 if (riscv_isa_extension_check(ext->id))
322 set_bit(ext->id, isainfo->isa);
326 static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct riscv_isainfo *isainfo,
327 unsigned long *isa2hwcap, const char *isa)
330 * For all possible cpus, we have already validated in
331 * the boot process that they at least contain "rv" and
332 * whichever of "32"/"64" this kernel supports, and so this
333 * section can be skipped.
338 const char *ext = isa++;
339 const char *ext_end = isa;
340 bool ext_long = false, ext_err = false;
345 * Workaround for invalid single-letter 's' & 'u' (QEMU).
346 * No need to set the bit in riscv_isa as 's' & 'u' are
347 * not valid ISA extensions. It works unless the first
348 * multi-letter extension in the ISA string begins with
349 * "Su" and is not prefixed with an underscore.
351 if (ext[-1] != '_' && ext[1] == 'u') {
363 * Before attempting to parse the extension itself, we find its end.
364 * As multi-letter extensions must be split from other multi-letter
365 * extensions with an "_", the end of a multi-letter extension will
366 * either be the null character or the "_" at the start of the next
367 * multi-letter extension.
369 * Next, as the extensions version is currently ignored, we
370 * eliminate that portion. This is done by parsing backwards from
371 * the end of the extension, removing any numbers. This may be a
372 * major or minor number however, so the process is repeated if a
373 * minor number was found.
375 * ext_end is intended to represent the first character *after* the
376 * name portion of an extension, but will be decremented to the last
377 * character itself while eliminating the extensions version number.
378 * A simple re-increment solves this problem.
381 for (; *isa && *isa != '_'; ++isa)
382 if (unlikely(!isalnum(*isa)))
386 if (unlikely(ext_err))
389 if (!isdigit(ext_end[-1]))
392 while (isdigit(*--ext_end))
395 if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) {
400 while (isdigit(*--ext_end))
407 * Things are a little easier for single-letter extensions, as they
408 * are parsed forwards.
410 * After checking that our starting position is valid, we need to
411 * ensure that, when isa was incremented at the start of the loop,
412 * that it arrived at the start of the next extension.
414 * If we are already on a non-digit, there is nothing to do. Either
415 * we have a multi-letter extension's _, or the start of an
418 * Otherwise we have found the current extension's major version
419 * number. Parse past it, and a subsequent p/minor version number
420 * if present. The `p` extension must not appear immediately after
421 * a number, so there is no fear of missing it.
424 if (unlikely(!isalpha(*ext))) {
432 while (isdigit(*++isa))
435 if (tolower(*isa) != 'p')
438 if (!isdigit(*++isa)) {
443 while (isdigit(*++isa))
450 * The parser expects that at the start of an iteration isa points to the
451 * first character of the next extension. As we stop parsing an extension
452 * on meeting a non-alphanumeric character, an extra increment is needed
453 * where the succeeding extension is a multi-letter prefixed with an "_".
458 if (unlikely(ext_err))
461 int nr = tolower(*ext) - 'a';
463 if (riscv_isa_extension_check(nr)) {
464 *this_hwcap |= isa2hwcap[nr];
465 set_bit(nr, isainfo->isa);
468 for (int i = 0; i < riscv_isa_ext_count; i++)
469 match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo);
474 static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap)
476 struct device_node *node;
479 struct acpi_table_header *rhct;
483 if (!acpi_disabled) {
484 status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
485 if (ACPI_FAILURE(status))
489 for_each_possible_cpu(cpu) {
490 struct riscv_isainfo *isainfo = &hart_isa[cpu];
491 unsigned long this_hwcap = 0;
494 node = of_cpu_device_node_get(cpu);
496 pr_warn("Unable to find cpu node\n");
500 rc = of_property_read_string(node, "riscv,isa", &isa);
503 pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
507 rc = acpi_get_riscv_isa(rhct, cpu, &isa);
509 pr_warn("Unable to get ISA for the hart - %d\n", cpu);
514 riscv_parse_isa_string(&this_hwcap, isainfo, isa2hwcap, isa);
517 * These ones were as they were part of the base ISA when the
518 * port & dt-bindings were upstreamed, and so can be set
519 * unconditionally where `i` is in riscv,isa on DT systems.
522 set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
523 set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
524 set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa);
525 set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa);
529 * All "okay" hart should have same isa. Set HWCAP based on
530 * common capabilities of every "okay" hart, in case they don't
534 elf_hwcap &= this_hwcap;
536 elf_hwcap = this_hwcap;
538 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
539 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
541 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
544 if (!acpi_disabled && rhct)
545 acpi_put_table((struct acpi_table_header *)rhct);
548 static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap)
552 for_each_possible_cpu(cpu) {
553 unsigned long this_hwcap = 0;
554 struct device_node *cpu_node;
555 struct riscv_isainfo *isainfo = &hart_isa[cpu];
557 cpu_node = of_cpu_device_node_get(cpu);
559 pr_warn("Unable to find cpu node\n");
563 if (!of_property_present(cpu_node, "riscv,isa-extensions")) {
564 of_node_put(cpu_node);
568 for (int i = 0; i < riscv_isa_ext_count; i++) {
569 const struct riscv_isa_ext_data *ext = &riscv_isa_ext[i];
571 if (of_property_match_string(cpu_node, "riscv,isa-extensions",
575 if (ext->subset_ext_size) {
576 for (int j = 0; j < ext->subset_ext_size; j++) {
577 if (riscv_isa_extension_check(ext->subset_ext_ids[i]))
578 set_bit(ext->subset_ext_ids[j], isainfo->isa);
582 if (riscv_isa_extension_check(ext->id)) {
583 set_bit(ext->id, isainfo->isa);
585 /* Only single letter extensions get set in hwcap */
586 if (strnlen(riscv_isa_ext[i].name, 2) == 1)
587 this_hwcap |= isa2hwcap[riscv_isa_ext[i].id];
591 of_node_put(cpu_node);
594 * All "okay" harts should have same isa. Set HWCAP based on
595 * common capabilities of every "okay" hart, in case they don't.
598 elf_hwcap &= this_hwcap;
600 elf_hwcap = this_hwcap;
602 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
603 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
605 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
608 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
614 #ifdef CONFIG_RISCV_ISA_FALLBACK
615 bool __initdata riscv_isa_fallback = true;
617 bool __initdata riscv_isa_fallback;
618 static int __init riscv_isa_fallback_setup(char *__unused)
620 riscv_isa_fallback = true;
623 early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
626 void __init riscv_fill_hwcap(void)
628 char print_str[NUM_ALPHA_EXTS + 1];
629 unsigned long isa2hwcap[26] = {0};
632 isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;
633 isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M;
634 isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A;
635 isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;
636 isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;
637 isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;
638 isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V;
640 if (!acpi_disabled) {
641 riscv_fill_hwcap_from_isa_string(isa2hwcap);
643 int ret = riscv_fill_hwcap_from_ext_list(isa2hwcap);
645 if (ret && riscv_isa_fallback) {
646 pr_info("Falling back to deprecated \"riscv,isa\"\n");
647 riscv_fill_hwcap_from_isa_string(isa2hwcap);
652 * We don't support systems with F but without D, so mask those out
655 if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
656 pr_info("This kernel does not support systems with F but not D\n");
657 elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
660 if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
661 riscv_v_setup_vsize();
663 * ISA string in device tree might have 'v' flag, but
664 * CONFIG_RISCV_ISA_V is disabled in kernel.
665 * Clear V flag in elf_hwcap if CONFIG_RISCV_ISA_V is disabled.
667 if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
668 elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
671 memset(print_str, 0, sizeof(print_str));
672 for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
673 if (riscv_isa[0] & BIT_MASK(i))
674 print_str[j++] = (char)('a' + i);
675 pr_info("riscv: base ISA extensions %s\n", print_str);
677 memset(print_str, 0, sizeof(print_str));
678 for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
679 if (elf_hwcap & BIT_MASK(i))
680 print_str[j++] = (char)('a' + i);
681 pr_info("riscv: ELF capabilities %s\n", print_str);
684 unsigned long riscv_get_elf_hwcap(void)
688 hwcap = (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1));
690 if (!riscv_v_vstate_ctrl_user_allowed())
691 hwcap &= ~COMPAT_HWCAP_ISA_V;
696 void riscv_user_isa_enable(void)
698 if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ))
699 csr_set(CSR_SENVCFG, ENVCFG_CBZE);
702 #ifdef CONFIG_RISCV_ALTERNATIVE
704 * Alternative patch sites consider 48 bits when determining when to patch
705 * the old instruction sequence with the new. These bits are broken into a
706 * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the
707 * patch site is for an erratum, identified by the 32-bit patch ID. When
708 * the vendor ID is zero, the patch site is for a cpufeature. cpufeatures
709 * further break down patch ID into two 16-bit numbers. The lower 16 bits
710 * are the cpufeature ID and the upper 16 bits are used for a value specific
711 * to the cpufeature and patch site. If the upper 16 bits are zero, then it
712 * implies no specific value is specified. cpufeatures that want to control
713 * patching on a per-site basis will provide non-zero values and implement
714 * checks here. The checks return true when patching should be done, and
717 static bool riscv_cpufeature_patch_check(u16 id, u16 value)
723 case RISCV_ISA_EXT_ZICBOZ:
725 * Zicboz alternative applications provide the maximum
726 * supported block size order, or zero when it doesn't
727 * matter. If the current block size exceeds the maximum,
728 * then the alternative cannot be applied.
730 return riscv_cboz_block_size <= (1U << value);
736 void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
737 struct alt_entry *end,
740 struct alt_entry *alt;
741 void *oldptr, *altptr;
744 if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
747 for (alt = begin; alt < end; alt++) {
748 if (alt->vendor_id != 0)
751 id = PATCH_ID_CPUFEATURE_ID(alt->patch_id);
753 if (id >= RISCV_ISA_EXT_MAX) {
754 WARN(1, "This extension id:%d is not in ISA extension list", id);
758 if (!__riscv_isa_extension_available(NULL, id))
761 value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id);
762 if (!riscv_cpufeature_patch_check(id, value))
765 oldptr = ALT_OLD_PTR(alt);
766 altptr = ALT_ALT_PTR(alt);
768 mutex_lock(&text_mutex);
769 patch_text_nosync(oldptr, altptr, alt->alt_len);
770 riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr);
771 mutex_unlock(&text_mutex);