x86/cpu: Add several Intel server CPU model numbers
authorTony Luck <tony.luck@intel.com>
Thu, 3 Nov 2022 20:33:10 +0000 (13:33 -0700)
committerBorislav Petkov <bp@suse.de>
Fri, 4 Nov 2022 20:12:22 +0000 (21:12 +0100)
These servers are all on the public versions of the roadmap. The model
numbers for Grand Ridge, Granite Rapids, and Sierra Forest were included
in the September 2022 edition of the Instruction Set Extensions document.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Dave Hansen <dave.hansen@linux.intel.com>
Link: https://lore.kernel.org/r/20221103203310.5058-1-tony.luck@intel.com
arch/x86/include/asm/intel-family.h

index 5d75fe22934217bf6d01084b5da943803099798c..347707d459c67f2dc85427b04e78b733ff4201f6 100644 (file)
 
 #define INTEL_FAM6_SAPPHIRERAPIDS_X    0x8F    /* Golden Cove */
 
+#define INTEL_FAM6_EMERALDRAPIDS_X     0xCF
+
+#define INTEL_FAM6_GRANITERAPIDS_X     0xAD
+#define INTEL_FAM6_GRANITERAPIDS_D     0xAE
+
 #define INTEL_FAM6_ALDERLAKE           0x97    /* Golden Cove / Gracemont */
 #define INTEL_FAM6_ALDERLAKE_L         0x9A    /* Golden Cove / Gracemont */
 #define INTEL_FAM6_ALDERLAKE_N         0xBE
 #define INTEL_FAM6_METEORLAKE          0xAC
 #define INTEL_FAM6_METEORLAKE_L                0xAA
 
-/* "Small Core" Processors (Atom) */
+/* "Small Core" Processors (Atom/E-Core) */
 
 #define INTEL_FAM6_ATOM_BONNELL                0x1C /* Diamondville, Pineview */
 #define INTEL_FAM6_ATOM_BONNELL_MID    0x26 /* Silverthorne, Lincroft */
 #define INTEL_FAM6_ATOM_TREMONT                0x96 /* Elkhart Lake */
 #define INTEL_FAM6_ATOM_TREMONT_L      0x9C /* Jasper Lake */
 
+#define INTEL_FAM6_SIERRAFOREST_X      0xAF
+
+#define INTEL_FAM6_GRANDRIDGE          0xB6
+
 /* Xeon Phi */
 
 #define INTEL_FAM6_XEON_PHI_KNL                0x57 /* Knights Landing */