Documentation/devicetree/bindings/riscv/cpus.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: RISC-V CPUs
   8
   9 maintainers:
  10   - Paul Walmsley <paul.walmsley@sifive.com>
  11   - Palmer Dabbelt <palmer@sifive.com>
  12   - Conor Dooley <conor@kernel.org>
  13
  14 description: |
  15   This document uses some terminology common to the RISC-V community
  16   that is not widely used, the definitions of which are listed here:
  17
  18   hart: A hardware execution context, which contains all the state
  19   mandated by the RISC-V ISA: a PC and some registers.  This
  20   terminology is designed to disambiguate software's view of execution
  21   contexts from any particular microarchitectural implementation
  22   strategy.  For example, an Intel laptop containing one socket with
  23   two cores, each of which has two hyperthreads, could be described as
  24   having four harts.
  25
  26 allOf:
  27   - $ref: /schemas/cpu.yaml#
  28   - $ref: extensions.yaml
  29
  30 properties:
  31   compatible:
  32     oneOf:
  33       - items:
  34           - enum:
  35               - amd,mbv32
  36               - andestech,ax45mp
  37               - canaan,k210
  38               - sifive,bullet0
  39               - sifive,e5
  40               - sifive,e7
  41               - sifive,e71
  42               - sifive,rocket0
  43               - sifive,s7
  44               - sifive,u5
  45               - sifive,u54
  46               - sifive,u7
  47               - sifive,u74
  48               - sifive,u74-mc
  49               - thead,c906
  50               - thead,c910
  51               - thead,c920
  52           - const: riscv
  53       - items:
  54           - enum:
  55               - sifive,e51
  56               - sifive,u54-mc
  57           - const: sifive,rocket0
  58           - const: riscv
  59       - const: riscv    # Simulator only
  60     description:
  61       Identifies that the hart uses the RISC-V instruction set
  62       and identifies the type of the hart.
  63
  64   mmu-type:
  65     description:
  66       Identifies the largest MMU address translation mode supported by
  67       this hart.  These values originate from the RISC-V Privileged
  68       Specification document, available from
  69       https://riscv.org/specifications/
  70     $ref: /schemas/types.yaml#/definitions/string
  71     enum:
  72       - riscv,sv32
  73       - riscv,sv39
  74       - riscv,sv48
  75       - riscv,sv57
  76       - riscv,none
  77
  78   reg:
  79     description:
  80       The hart ID of this CPU node.
  81
  82   riscv,cbom-block-size:
  83     $ref: /schemas/types.yaml#/definitions/uint32
  84     description:
  85       The blocksize in bytes for the Zicbom cache operations.
  86
  87   riscv,cbop-block-size:
  88     $ref: /schemas/types.yaml#/definitions/uint32
  89     description:
  90       The blocksize in bytes for the Zicbop cache operations.
  91
  92   riscv,cboz-block-size:
  93     $ref: /schemas/types.yaml#/definitions/uint32
  94     description:
  95       The blocksize in bytes for the Zicboz cache operations.
  96
  97   # RISC-V has multiple properties for cache op block sizes as the sizes
  98   # differ between individual CBO extensions
  99   cache-op-block-size: false
 100   # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
 101   timebase-frequency: false
 102
 103   interrupt-controller:
 104     type: object
 105     additionalProperties: false
 106     description: Describes the CPU's local interrupt controller
 107
 108     properties:
 109       '#interrupt-cells':
 110         const: 1
 111
 112       compatible:
 113         oneOf:
 114           - items:
 115               - const: andestech,cpu-intc
 116               - const: riscv,cpu-intc
 117           - const: riscv,cpu-intc
 118
 119       interrupt-controller: true
 120
 121     required:
 122       - '#interrupt-cells'
 123       - compatible
 124       - interrupt-controller
 125
 126   cpu-idle-states:
 127     $ref: /schemas/types.yaml#/definitions/phandle-array
 128     items:
 129       maxItems: 1
 130     description: |
 131       List of phandles to idle state nodes supported
 132       by this hart (see ./idle-states.yaml).
 133
 134   capacity-dmips-mhz:
 135     description:
 136       u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
 137       DMIPS/MHz, relative to highest capacity-dmips-mhz
 138       in the system.
 139
 140 anyOf:
 141   - required:
 142       - riscv,isa
 143   - required:
 144       - riscv,isa-base
 145
 146 dependencies:
 147   riscv,isa-base: [ "riscv,isa-extensions" ]
 148   riscv,isa-extensions: [ "riscv,isa-base" ]
 149
 150 required:
 151   - interrupt-controller
 152
 153 unevaluatedProperties: false
 154
 155 examples:
 156   - |
 157     // Example 1: SiFive Freedom U540G Development Kit
 158     cpus {
 159         #address-cells = <1>;
 160         #size-cells = <0>;
 161         timebase-frequency = <1000000>;
 162         cpu@0 {
 163                 clock-frequency = <0>;
 164                 compatible = "sifive,rocket0", "riscv";
 165                 device_type = "cpu";
 166                 i-cache-block-size = <64>;
 167                 i-cache-sets = <128>;
 168                 i-cache-size = <16384>;
 169                 reg = <0>;
 170                 riscv,isa-base = "rv64i";
 171                 riscv,isa-extensions = "i", "m", "a", "c";
 172
 173                 cpu_intc0: interrupt-controller {
 174                         #interrupt-cells = <1>;
 175                         compatible = "riscv,cpu-intc";
 176                         interrupt-controller;
 177                 };
 178         };
 179         cpu@1 {
 180                 clock-frequency = <0>;
 181                 compatible = "sifive,rocket0", "riscv";
 182                 d-cache-block-size = <64>;
 183                 d-cache-sets = <64>;
 184                 d-cache-size = <32768>;
 185                 d-tlb-sets = <1>;
 186                 d-tlb-size = <32>;
 187                 device_type = "cpu";
 188                 i-cache-block-size = <64>;
 189                 i-cache-sets = <64>;
 190                 i-cache-size = <32768>;
 191                 i-tlb-sets = <1>;
 192                 i-tlb-size = <32>;
 193                 mmu-type = "riscv,sv39";
 194                 reg = <1>;
 195                 tlb-split;
 196                 riscv,isa-base = "rv64i";
 197                 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
 198
 199                 cpu_intc1: interrupt-controller {
 200                         #interrupt-cells = <1>;
 201                         compatible = "riscv,cpu-intc";
 202                         interrupt-controller;
 203                 };
 204         };
 205     };
 206
 207   - |
 208     // Example 2: Spike ISA Simulator with 1 Hart
 209     cpus {
 210         #address-cells = <1>;
 211         #size-cells = <0>;
 212         cpu@0 {
 213                 device_type = "cpu";
 214                 reg = <0>;
 215                 compatible = "riscv";
 216                 mmu-type = "riscv,sv48";
 217                 riscv,isa-base = "rv64i";
 218                 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
 219
 220                 interrupt-controller {
 221                         #interrupt-cells = <1>;
 222                         interrupt-controller;
 223                         compatible = "riscv,cpu-intc";
 224                 };
 225         };
 226     };
 227 ...