Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel...
authorLinus Torvalds <torvalds@linux-foundation.org>
Fri, 22 Mar 2024 17:41:13 +0000 (10:41 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Fri, 22 Mar 2024 17:41:13 +0000 (10:41 -0700)
Pull RISC-V updates from Palmer Dabbelt:

 - Support for various vector-accelerated crypto routines

 - Hibernation is now enabled for portable kernel builds

 - mmap_rnd_bits_max is larger on systems with larger VAs

 - Support for fast GUP

 - Support for membarrier-based instruction cache synchronization

 - Support for the Andes hart-level interrupt controller and PMU

 - Some cleanups around unaligned access speed probing and Kconfig
   settings

 - Support for ACPI LPI and CPPC

 - Various cleanus related to barriers

 - A handful of fixes

* tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (66 commits)
  riscv: Fix syscall wrapper for >word-size arguments
  crypto: riscv - add vector crypto accelerated AES-CBC-CTS
  crypto: riscv - parallelize AES-CBC decryption
  riscv: Only flush the mm icache when setting an exec pte
  riscv: Use kcalloc() instead of kzalloc()
  riscv/barrier: Add missing space after ','
  riscv/barrier: Consolidate fence definitions
  riscv/barrier: Define RISCV_FULL_BARRIER
  riscv/barrier: Define __{mb,rmb,wmb}
  RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ
  cpufreq: Move CPPC configs to common Kconfig and add RISC-V
  ACPI: RISC-V: Add CPPC driver
  ACPI: Enable ACPI_PROCESSOR for RISC-V
  ACPI: RISC-V: Add LPI driver
  cpuidle: RISC-V: Move few functions to arch/riscv
  riscv: Introduce set_compat_task() in asm/compat.h
  riscv: Introduce is_compat_thread() into compat.h
  riscv: add compile-time test into is_compat_task()
  riscv: Replace direct thread flag check with is_compat_task()
  riscv: Improve arch_get_mmap_end() macro
  ...

26 files changed:
1  2 
Documentation/devicetree/bindings/riscv/cpus.yaml
MAINTAINERS
arch/riscv/Kconfig
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
arch/riscv/include/asm/bitops.h
arch/riscv/include/asm/cpufeature.h
arch/riscv/include/asm/hwcap.h
arch/riscv/include/asm/pgtable.h
arch/riscv/include/asm/suspend.h
arch/riscv/include/asm/tlb.h
arch/riscv/kernel/Makefile
arch/riscv/kernel/cpufeature.c
arch/riscv/kernel/smpboot.c
arch/riscv/kernel/suspend.c
arch/riscv/lib/csum.c
arch/riscv/mm/init.c
crypto/Kconfig
drivers/acpi/Kconfig
drivers/cpufreq/Kconfig.arm
drivers/perf/Kconfig
drivers/perf/riscv_pmu_sbi.c
include/linux/mm.h
init/Kconfig
kernel/sched/core.c
kernel/sched/membarrier.c
mm/mmap.c

diff --cc MAINTAINERS
Simple merge
index 92b1dbf55176fa1ec989a6b6567e3418a496ed13,8ebafe337eac9880970ff877065c3f7161375313..be09c8836d56be91d24a768cbe3a2411423716f6
@@@ -35,9 -38,10 +38,10 @@@ config RISC
        select ARCH_HAS_SET_MEMORY if MMU
        select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
        select ARCH_HAS_STRICT_MODULE_RWX if MMU && !XIP_KERNEL
+       select ARCH_HAS_SYNC_CORE_BEFORE_USERMODE
        select ARCH_HAS_SYSCALL_WRAPPER
        select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
 -      select ARCH_HAS_UBSAN_SANITIZE_ALL
 +      select ARCH_HAS_UBSAN
        select ARCH_HAS_VDSO_DATA
        select ARCH_KEEP_MEMBLOCK if ACPI
        select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
index 329d8244a9b3fd516104808db5a959acfb469b22,c4c2173dfe996aeabba1375c8c0f8bec069ec537..880606b0469a83bc97d864da9235ce29b5807970
@@@ -37,9 -47,7 +47,7 @@@
  
  static __always_inline unsigned long variable__ffs(unsigned long word)
  {
-       int num;
 -      asm_volatile_goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
 +      asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
                                      RISCV_ISA_EXT_ZBB, 1)
                          : : : : legacy);
  
@@@ -93,9 -76,7 +76,7 @@@ legacy
  
  static __always_inline unsigned long variable__fls(unsigned long word)
  {
-       int num;
 -      asm_volatile_goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
 +      asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
                                      RISCV_ISA_EXT_ZBB, 1)
                          : : : : legacy);
  
@@@ -149,12 -105,7 +105,7 @@@ legacy
  
  static __always_inline int variable_ffs(int x)
  {
-       int r;
-       if (!x)
-               return 0;
 -      asm_volatile_goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
 +      asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
                                      RISCV_ISA_EXT_ZBB, 1)
                          : : : : legacy);
  
@@@ -204,12 -137,7 +137,7 @@@ legacy
  
  static __always_inline int variable_fls(unsigned int x)
  {
-       int r;
-       if (!x)
-               return 0;
 -      asm_volatile_goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
 +      asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
                                      RISCV_ISA_EXT_ZBB, 1)
                          : : : : legacy);
  
Simple merge
index 1f2d2599c655d20be6df7516382e20a7e3956301,bae7eac76c180c3b988dd277319207d11892a4a1..e17d0078a65116810cda686225c78e0ff420a603
  #define RISCV_ISA_EXT_ZFA             71
  #define RISCV_ISA_EXT_ZTSO            72
  #define RISCV_ISA_EXT_ZACAS           73
+ #define RISCV_ISA_EXT_XANDESPMU               74
  
 +#define RISCV_ISA_EXT_XLINUXENVCFG    127
 +
  #define RISCV_ISA_EXT_MAX             128
  #define RISCV_ISA_EXT_INVALID         U32_MAX
  
Simple merge
Simple merge
Simple merge
Simple merge
index 79a5a35fab964d3b54db97b5504f45f68dface11,afeae3ff43dc1f880594708444121b823ba8d7ce..3ed2359eae353f863561c02983e4e5e5bf27603d
  #include <asm/cacheflush.h>
  #include <asm/cpufeature.h>
  #include <asm/hwcap.h>
- #include <asm/hwprobe.h>
  #include <asm/patch.h>
  #include <asm/processor.h>
 +#include <asm/sbi.h>
  #include <asm/vector.h>
  
- #include "copy-unaligned.h"
  #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
  
- #define MISALIGNED_ACCESS_JIFFIES_LG2 1
- #define MISALIGNED_BUFFER_SIZE 0x4000
- #define MISALIGNED_BUFFER_ORDER get_order(MISALIGNED_BUFFER_SIZE)
- #define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80)
  unsigned long elf_hwcap __read_mostly;
  
  /* Host ISA bitmap */
Simple merge
Simple merge
Simple merge
Simple merge
diff --cc crypto/Kconfig
Simple merge
Simple merge
Simple merge
index 54ff5cc17ccdb459bfa430331060abfd68ea6da2,564e813d8c69b2195b84eb54cd43490733fe21de..7526a9e714fa985d79d20b77003483a81f7b60a7
@@@ -86,16 -86,20 +86,30 @@@ config RISCV_PMU_SB
          full perf feature support i.e. counter overflow, privilege mode
          filtering, counter configuration.
  
 +config STARFIVE_STARLINK_PMU
 +      depends on ARCH_STARFIVE || COMPILE_TEST
 +      depends on 64BIT
 +      bool "StarFive StarLink PMU"
 +      help
 +         Provide support for StarLink Performance Monitor Unit.
 +         StarLink Performance Monitor Unit integrates one or more cores with
 +         an L3 memory system. The L3 cache events are added into perf event
 +         subsystem, allowing monitoring of various L3 cache perf events.
 +
+ config ANDES_CUSTOM_PMU
+       bool "Andes custom PMU support"
+       depends on ARCH_RENESAS && RISCV_ALTERNATIVE && RISCV_PMU_SBI
+       default y
+       help
+         The Andes cores implement the PMU overflow extension very
+         similar to the standard Sscofpmf and Smcntrpmf extension.
+         This will patch the overflow and pending CSRs and handle the
+         non-standard behaviour via the regular SBI PMU driver and
+         interface.
+         If you don't know what to do here, say "Y".
  config ARM_PMU_ACPI
        depends on ARM_PMU && ACPI
        def_bool y
Simple merge
Simple merge
diff --cc init/Kconfig
Simple merge
Simple merge
Simple merge
diff --cc mm/mmap.c
Simple merge